1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/delay.h> 36 #include "cxgb4.h" 37 #include "t4_regs.h" 38 #include "t4_values.h" 39 #include "t4fw_api.h" 40 41 /** 42 * t4_wait_op_done_val - wait until an operation is completed 43 * @adapter: the adapter performing the operation 44 * @reg: the register to check for completion 45 * @mask: a single-bit field within @reg that indicates completion 46 * @polarity: the value of the field when the operation is completed 47 * @attempts: number of check iterations 48 * @delay: delay in usecs between iterations 49 * @valp: where to store the value of the register at completion time 50 * 51 * Wait until an operation is completed by checking a bit in a register 52 * up to @attempts times. If @valp is not NULL the value of the register 53 * at the time it indicated completion is stored there. Returns 0 if the 54 * operation completes and -EAGAIN otherwise. 55 */ 56 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 57 int polarity, int attempts, int delay, u32 *valp) 58 { 59 while (1) { 60 u32 val = t4_read_reg(adapter, reg); 61 62 if (!!(val & mask) == polarity) { 63 if (valp) 64 *valp = val; 65 return 0; 66 } 67 if (--attempts == 0) 68 return -EAGAIN; 69 if (delay) 70 udelay(delay); 71 } 72 } 73 74 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 75 int polarity, int attempts, int delay) 76 { 77 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 78 delay, NULL); 79 } 80 81 /** 82 * t4_set_reg_field - set a register field to a value 83 * @adapter: the adapter to program 84 * @addr: the register address 85 * @mask: specifies the portion of the register to modify 86 * @val: the new value for the register field 87 * 88 * Sets a register field specified by the supplied mask to the 89 * given value. 90 */ 91 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 92 u32 val) 93 { 94 u32 v = t4_read_reg(adapter, addr) & ~mask; 95 96 t4_write_reg(adapter, addr, v | val); 97 (void) t4_read_reg(adapter, addr); /* flush */ 98 } 99 100 /** 101 * t4_read_indirect - read indirectly addressed registers 102 * @adap: the adapter 103 * @addr_reg: register holding the indirect address 104 * @data_reg: register holding the value of the indirect register 105 * @vals: where the read register values are stored 106 * @nregs: how many indirect registers to read 107 * @start_idx: index of first indirect register to read 108 * 109 * Reads registers that are accessed indirectly through an address/data 110 * register pair. 111 */ 112 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 113 unsigned int data_reg, u32 *vals, 114 unsigned int nregs, unsigned int start_idx) 115 { 116 while (nregs--) { 117 t4_write_reg(adap, addr_reg, start_idx); 118 *vals++ = t4_read_reg(adap, data_reg); 119 start_idx++; 120 } 121 } 122 123 /** 124 * t4_write_indirect - write indirectly addressed registers 125 * @adap: the adapter 126 * @addr_reg: register holding the indirect addresses 127 * @data_reg: register holding the value for the indirect registers 128 * @vals: values to write 129 * @nregs: how many indirect registers to write 130 * @start_idx: address of first indirect register to write 131 * 132 * Writes a sequential block of registers that are accessed indirectly 133 * through an address/data register pair. 134 */ 135 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 136 unsigned int data_reg, const u32 *vals, 137 unsigned int nregs, unsigned int start_idx) 138 { 139 while (nregs--) { 140 t4_write_reg(adap, addr_reg, start_idx++); 141 t4_write_reg(adap, data_reg, *vals++); 142 } 143 } 144 145 /* 146 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 147 * mechanism. This guarantees that we get the real value even if we're 148 * operating within a Virtual Machine and the Hypervisor is trapping our 149 * Configuration Space accesses. 150 */ 151 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) 152 { 153 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg); 154 155 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 156 req |= ENABLE_F; 157 else 158 req |= T6_ENABLE_F; 159 160 if (is_t4(adap->params.chip)) 161 req |= LOCALCFG_F; 162 163 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req); 164 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A); 165 166 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 167 * Configuration Space read. (None of the other fields matter when 168 * ENABLE is 0 so a simple register write is easier than a 169 * read-modify-write via t4_set_reg_field().) 170 */ 171 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); 172 } 173 174 /* 175 * t4_report_fw_error - report firmware error 176 * @adap: the adapter 177 * 178 * The adapter firmware can indicate error conditions to the host. 179 * If the firmware has indicated an error, print out the reason for 180 * the firmware error. 181 */ 182 static void t4_report_fw_error(struct adapter *adap) 183 { 184 static const char *const reason[] = { 185 "Crash", /* PCIE_FW_EVAL_CRASH */ 186 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 187 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 188 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 189 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 190 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 191 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 192 "Reserved", /* reserved */ 193 }; 194 u32 pcie_fw; 195 196 pcie_fw = t4_read_reg(adap, PCIE_FW_A); 197 if (pcie_fw & PCIE_FW_ERR_F) 198 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n", 199 reason[PCIE_FW_EVAL_G(pcie_fw)]); 200 } 201 202 /* 203 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 204 */ 205 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 206 u32 mbox_addr) 207 { 208 for ( ; nflit; nflit--, mbox_addr += 8) 209 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 210 } 211 212 /* 213 * Handle a FW assertion reported in a mailbox. 214 */ 215 static void fw_asrt(struct adapter *adap, u32 mbox_addr) 216 { 217 struct fw_debug_cmd asrt; 218 219 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr); 220 dev_alert(adap->pdev_dev, 221 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 222 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line), 223 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y)); 224 } 225 226 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg) 227 { 228 dev_err(adap->pdev_dev, 229 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox, 230 (unsigned long long)t4_read_reg64(adap, data_reg), 231 (unsigned long long)t4_read_reg64(adap, data_reg + 8), 232 (unsigned long long)t4_read_reg64(adap, data_reg + 16), 233 (unsigned long long)t4_read_reg64(adap, data_reg + 24), 234 (unsigned long long)t4_read_reg64(adap, data_reg + 32), 235 (unsigned long long)t4_read_reg64(adap, data_reg + 40), 236 (unsigned long long)t4_read_reg64(adap, data_reg + 48), 237 (unsigned long long)t4_read_reg64(adap, data_reg + 56)); 238 } 239 240 /** 241 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 242 * @adap: the adapter 243 * @mbox: index of the mailbox to use 244 * @cmd: the command to write 245 * @size: command length in bytes 246 * @rpl: where to optionally store the reply 247 * @sleep_ok: if true we may sleep while awaiting command completion 248 * @timeout: time to wait for command to finish before timing out 249 * 250 * Sends the given command to FW through the selected mailbox and waits 251 * for the FW to execute the command. If @rpl is not %NULL it is used to 252 * store the FW's reply to the command. The command and its optional 253 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms 254 * to respond. @sleep_ok determines whether we may sleep while awaiting 255 * the response. If sleeping is allowed we use progressive backoff 256 * otherwise we spin. 257 * 258 * The return value is 0 on success or a negative errno on failure. A 259 * failure can happen either because we are not able to execute the 260 * command or FW executes it but signals an error. In the latter case 261 * the return value is the error code indicated by FW (negated). 262 */ 263 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 264 int size, void *rpl, bool sleep_ok, int timeout) 265 { 266 static const int delay[] = { 267 1, 1, 3, 5, 10, 10, 20, 50, 100, 200 268 }; 269 270 u32 v; 271 u64 res; 272 int i, ms, delay_idx; 273 const __be64 *p = cmd; 274 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A); 275 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A); 276 277 if ((size & 15) || size > MBOX_LEN) 278 return -EINVAL; 279 280 /* 281 * If the device is off-line, as in EEH, commands will time out. 282 * Fail them early so we don't waste time waiting. 283 */ 284 if (adap->pdev->error_state != pci_channel_io_normal) 285 return -EIO; 286 287 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); 288 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++) 289 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); 290 291 if (v != MBOX_OWNER_DRV) 292 return v ? -EBUSY : -ETIMEDOUT; 293 294 for (i = 0; i < size; i += 8) 295 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++)); 296 297 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); 298 t4_read_reg(adap, ctl_reg); /* flush write */ 299 300 delay_idx = 0; 301 ms = delay[0]; 302 303 for (i = 0; i < timeout; i += ms) { 304 if (sleep_ok) { 305 ms = delay[delay_idx]; /* last element may repeat */ 306 if (delay_idx < ARRAY_SIZE(delay) - 1) 307 delay_idx++; 308 msleep(ms); 309 } else 310 mdelay(ms); 311 312 v = t4_read_reg(adap, ctl_reg); 313 if (MBOWNER_G(v) == MBOX_OWNER_DRV) { 314 if (!(v & MBMSGVALID_F)) { 315 t4_write_reg(adap, ctl_reg, 0); 316 continue; 317 } 318 319 res = t4_read_reg64(adap, data_reg); 320 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) { 321 fw_asrt(adap, data_reg); 322 res = FW_CMD_RETVAL_V(EIO); 323 } else if (rpl) { 324 get_mbox_rpl(adap, rpl, size / 8, data_reg); 325 } 326 327 if (FW_CMD_RETVAL_G((int)res)) 328 dump_mbox(adap, mbox, data_reg); 329 t4_write_reg(adap, ctl_reg, 0); 330 return -FW_CMD_RETVAL_G((int)res); 331 } 332 } 333 334 dump_mbox(adap, mbox, data_reg); 335 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", 336 *(const u8 *)cmd, mbox); 337 t4_report_fw_error(adap); 338 return -ETIMEDOUT; 339 } 340 341 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 342 void *rpl, bool sleep_ok) 343 { 344 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok, 345 FW_CMD_MAX_TIMEOUT); 346 } 347 348 static int t4_edc_err_read(struct adapter *adap, int idx) 349 { 350 u32 edc_ecc_err_addr_reg; 351 u32 rdata_reg; 352 353 if (is_t4(adap->params.chip)) { 354 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 355 return 0; 356 } 357 if (idx != 0 && idx != 1) { 358 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 359 return 0; 360 } 361 362 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx); 363 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx); 364 365 CH_WARN(adap, 366 "edc%d err addr 0x%x: 0x%x.\n", 367 idx, edc_ecc_err_addr_reg, 368 t4_read_reg(adap, edc_ecc_err_addr_reg)); 369 CH_WARN(adap, 370 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 371 rdata_reg, 372 (unsigned long long)t4_read_reg64(adap, rdata_reg), 373 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8), 374 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16), 375 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24), 376 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32), 377 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40), 378 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48), 379 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56), 380 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64)); 381 382 return 0; 383 } 384 385 /** 386 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window 387 * @adap: the adapter 388 * @win: PCI-E Memory Window to use 389 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 390 * @addr: address within indicated memory type 391 * @len: amount of memory to transfer 392 * @hbuf: host memory buffer 393 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0) 394 * 395 * Reads/writes an [almost] arbitrary memory region in the firmware: the 396 * firmware memory address and host buffer must be aligned on 32-bit 397 * boudaries; the length may be arbitrary. The memory is transferred as 398 * a raw byte sequence from/to the firmware's memory. If this memory 399 * contains data structures which contain multi-byte integers, it's the 400 * caller's responsibility to perform appropriate byte order conversions. 401 */ 402 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, 403 u32 len, void *hbuf, int dir) 404 { 405 u32 pos, offset, resid, memoffset; 406 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base; 407 u32 *buf; 408 409 /* Argument sanity checks ... 410 */ 411 if (addr & 0x3 || (uintptr_t)hbuf & 0x3) 412 return -EINVAL; 413 buf = (u32 *)hbuf; 414 415 /* It's convenient to be able to handle lengths which aren't a 416 * multiple of 32-bits because we often end up transferring files to 417 * the firmware. So we'll handle that by normalizing the length here 418 * and then handling any residual transfer at the end. 419 */ 420 resid = len & 0x3; 421 len -= resid; 422 423 /* Offset into the region of memory which is being accessed 424 * MEM_EDC0 = 0 425 * MEM_EDC1 = 1 426 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller 427 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5) 428 */ 429 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A)); 430 if (mtype != MEM_MC1) 431 memoffset = (mtype * (edc_size * 1024 * 1024)); 432 else { 433 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap, 434 MA_EXT_MEMORY0_BAR_A)); 435 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; 436 } 437 438 /* Determine the PCIE_MEM_ACCESS_OFFSET */ 439 addr = addr + memoffset; 440 441 /* Each PCI-E Memory Window is programmed with a window size -- or 442 * "aperture" -- which controls the granularity of its mapping onto 443 * adapter memory. We need to grab that aperture in order to know 444 * how to use the specified window. The window is also programmed 445 * with the base address of the Memory Window in BAR0's address 446 * space. For T4 this is an absolute PCI-E Bus Address. For T5 447 * the address is relative to BAR0. 448 */ 449 mem_reg = t4_read_reg(adap, 450 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 451 win)); 452 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X); 453 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X; 454 if (is_t4(adap->params.chip)) 455 mem_base -= adap->t4_bar0; 456 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf); 457 458 /* Calculate our initial PCI-E Memory Window Position and Offset into 459 * that Window. 460 */ 461 pos = addr & ~(mem_aperture-1); 462 offset = addr - pos; 463 464 /* Set up initial PCI-E Memory Window to cover the start of our 465 * transfer. (Read it back to ensure that changes propagate before we 466 * attempt to use the new value.) 467 */ 468 t4_write_reg(adap, 469 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win), 470 pos | win_pf); 471 t4_read_reg(adap, 472 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win)); 473 474 /* Transfer data to/from the adapter as long as there's an integral 475 * number of 32-bit transfers to complete. 476 * 477 * A note on Endianness issues: 478 * 479 * The "register" reads and writes below from/to the PCI-E Memory 480 * Window invoke the standard adapter Big-Endian to PCI-E Link 481 * Little-Endian "swizzel." As a result, if we have the following 482 * data in adapter memory: 483 * 484 * Memory: ... | b0 | b1 | b2 | b3 | ... 485 * Address: i+0 i+1 i+2 i+3 486 * 487 * Then a read of the adapter memory via the PCI-E Memory Window 488 * will yield: 489 * 490 * x = readl(i) 491 * 31 0 492 * [ b3 | b2 | b1 | b0 ] 493 * 494 * If this value is stored into local memory on a Little-Endian system 495 * it will show up correctly in local memory as: 496 * 497 * ( ..., b0, b1, b2, b3, ... ) 498 * 499 * But on a Big-Endian system, the store will show up in memory 500 * incorrectly swizzled as: 501 * 502 * ( ..., b3, b2, b1, b0, ... ) 503 * 504 * So we need to account for this in the reads and writes to the 505 * PCI-E Memory Window below by undoing the register read/write 506 * swizzels. 507 */ 508 while (len > 0) { 509 if (dir == T4_MEMORY_READ) 510 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap, 511 mem_base + offset)); 512 else 513 t4_write_reg(adap, mem_base + offset, 514 (__force u32)cpu_to_le32(*buf++)); 515 offset += sizeof(__be32); 516 len -= sizeof(__be32); 517 518 /* If we've reached the end of our current window aperture, 519 * move the PCI-E Memory Window on to the next. Note that 520 * doing this here after "len" may be 0 allows us to set up 521 * the PCI-E Memory Window for a possible final residual 522 * transfer below ... 523 */ 524 if (offset == mem_aperture) { 525 pos += mem_aperture; 526 offset = 0; 527 t4_write_reg(adap, 528 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 529 win), pos | win_pf); 530 t4_read_reg(adap, 531 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 532 win)); 533 } 534 } 535 536 /* If the original transfer had a length which wasn't a multiple of 537 * 32-bits, now's where we need to finish off the transfer of the 538 * residual amount. The PCI-E Memory Window has already been moved 539 * above (if necessary) to cover this final transfer. 540 */ 541 if (resid) { 542 union { 543 u32 word; 544 char byte[4]; 545 } last; 546 unsigned char *bp; 547 int i; 548 549 if (dir == T4_MEMORY_READ) { 550 last.word = le32_to_cpu( 551 (__force __le32)t4_read_reg(adap, 552 mem_base + offset)); 553 for (bp = (unsigned char *)buf, i = resid; i < 4; i++) 554 bp[i] = last.byte[i]; 555 } else { 556 last.word = *buf; 557 for (i = resid; i < 4; i++) 558 last.byte[i] = 0; 559 t4_write_reg(adap, mem_base + offset, 560 (__force u32)cpu_to_le32(last.word)); 561 } 562 } 563 564 return 0; 565 } 566 567 /* Return the specified PCI-E Configuration Space register from our Physical 568 * Function. We try first via a Firmware LDST Command since we prefer to let 569 * the firmware own all of these registers, but if that fails we go for it 570 * directly ourselves. 571 */ 572 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg) 573 { 574 u32 val, ldst_addrspace; 575 576 /* If fw_attach != 0, construct and send the Firmware LDST Command to 577 * retrieve the specified PCI-E Configuration Space register. 578 */ 579 struct fw_ldst_cmd ldst_cmd; 580 int ret; 581 582 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 583 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE); 584 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 585 FW_CMD_REQUEST_F | 586 FW_CMD_READ_F | 587 ldst_addrspace); 588 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 589 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1); 590 ldst_cmd.u.pcie.ctrl_to_fn = 591 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf)); 592 ldst_cmd.u.pcie.r = reg; 593 594 /* If the LDST Command succeeds, return the result, otherwise 595 * fall through to reading it directly ourselves ... 596 */ 597 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 598 &ldst_cmd); 599 if (ret == 0) 600 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]); 601 else 602 /* Read the desired Configuration Space register via the PCI-E 603 * Backdoor mechanism. 604 */ 605 t4_hw_pci_read_cfg4(adap, reg, &val); 606 return val; 607 } 608 609 /* Get the window based on base passed to it. 610 * Window aperture is currently unhandled, but there is no use case for it 611 * right now 612 */ 613 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask, 614 u32 memwin_base) 615 { 616 u32 ret; 617 618 if (is_t4(adap->params.chip)) { 619 u32 bar0; 620 621 /* Truncation intentional: we only read the bottom 32-bits of 622 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor 623 * mechanism to read BAR0 instead of using 624 * pci_resource_start() because we could be operating from 625 * within a Virtual Machine which is trapping our accesses to 626 * our Configuration Space and we need to set up the PCI-E 627 * Memory Window decoders with the actual addresses which will 628 * be coming across the PCI-E link. 629 */ 630 bar0 = t4_read_pcie_cfg4(adap, pci_base); 631 bar0 &= pci_mask; 632 adap->t4_bar0 = bar0; 633 634 ret = bar0 + memwin_base; 635 } else { 636 /* For T5, only relative offset inside the PCIe BAR is passed */ 637 ret = memwin_base; 638 } 639 return ret; 640 } 641 642 /* Get the default utility window (win0) used by everyone */ 643 u32 t4_get_util_window(struct adapter *adap) 644 { 645 return t4_get_window(adap, PCI_BASE_ADDRESS_0, 646 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE); 647 } 648 649 /* Set up memory window for accessing adapter memory ranges. (Read 650 * back MA register to ensure that changes propagate before we attempt 651 * to use the new values.) 652 */ 653 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window) 654 { 655 t4_write_reg(adap, 656 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window), 657 memwin_base | BIR_V(0) | 658 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X)); 659 t4_read_reg(adap, 660 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window)); 661 } 662 663 /** 664 * t4_get_regs_len - return the size of the chips register set 665 * @adapter: the adapter 666 * 667 * Returns the size of the chip's BAR0 register space. 668 */ 669 unsigned int t4_get_regs_len(struct adapter *adapter) 670 { 671 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); 672 673 switch (chip_version) { 674 case CHELSIO_T4: 675 return T4_REGMAP_SIZE; 676 677 case CHELSIO_T5: 678 case CHELSIO_T6: 679 return T5_REGMAP_SIZE; 680 } 681 682 dev_err(adapter->pdev_dev, 683 "Unsupported chip version %d\n", chip_version); 684 return 0; 685 } 686 687 /** 688 * t4_get_regs - read chip registers into provided buffer 689 * @adap: the adapter 690 * @buf: register buffer 691 * @buf_size: size (in bytes) of register buffer 692 * 693 * If the provided register buffer isn't large enough for the chip's 694 * full register range, the register dump will be truncated to the 695 * register buffer's size. 696 */ 697 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) 698 { 699 static const unsigned int t4_reg_ranges[] = { 700 0x1008, 0x1108, 701 0x1180, 0x11b4, 702 0x11fc, 0x123c, 703 0x1300, 0x173c, 704 0x1800, 0x18fc, 705 0x3000, 0x305c, 706 0x3068, 0x30d8, 707 0x30e0, 0x5924, 708 0x5960, 0x59d4, 709 0x5a00, 0x5af8, 710 0x6000, 0x6098, 711 0x6100, 0x6150, 712 0x6200, 0x6208, 713 0x6240, 0x6248, 714 0x6280, 0x6338, 715 0x6370, 0x638c, 716 0x6400, 0x643c, 717 0x6500, 0x6524, 718 0x6a00, 0x6a38, 719 0x6a60, 0x6a78, 720 0x6b00, 0x6b84, 721 0x6bf0, 0x6c84, 722 0x6cf0, 0x6d84, 723 0x6df0, 0x6e84, 724 0x6ef0, 0x6f84, 725 0x6ff0, 0x7084, 726 0x70f0, 0x7184, 727 0x71f0, 0x7284, 728 0x72f0, 0x7384, 729 0x73f0, 0x7450, 730 0x7500, 0x7530, 731 0x7600, 0x761c, 732 0x7680, 0x76cc, 733 0x7700, 0x7798, 734 0x77c0, 0x77fc, 735 0x7900, 0x79fc, 736 0x7b00, 0x7c38, 737 0x7d00, 0x7efc, 738 0x8dc0, 0x8e1c, 739 0x8e30, 0x8e78, 740 0x8ea0, 0x8f6c, 741 0x8fc0, 0x9074, 742 0x90fc, 0x90fc, 743 0x9400, 0x9458, 744 0x9600, 0x96bc, 745 0x9800, 0x9808, 746 0x9820, 0x983c, 747 0x9850, 0x9864, 748 0x9c00, 0x9c6c, 749 0x9c80, 0x9cec, 750 0x9d00, 0x9d6c, 751 0x9d80, 0x9dec, 752 0x9e00, 0x9e6c, 753 0x9e80, 0x9eec, 754 0x9f00, 0x9f6c, 755 0x9f80, 0x9fec, 756 0xd004, 0xd03c, 757 0xdfc0, 0xdfe0, 758 0xe000, 0xea7c, 759 0xf000, 0x11110, 760 0x11118, 0x11190, 761 0x19040, 0x1906c, 762 0x19078, 0x19080, 763 0x1908c, 0x19124, 764 0x19150, 0x191b0, 765 0x191d0, 0x191e8, 766 0x19238, 0x1924c, 767 0x193f8, 0x19474, 768 0x19490, 0x194f8, 769 0x19800, 0x19f4c, 770 0x1a000, 0x1a06c, 771 0x1a0b0, 0x1a120, 772 0x1a128, 0x1a138, 773 0x1a190, 0x1a1c4, 774 0x1a1fc, 0x1a1fc, 775 0x1e040, 0x1e04c, 776 0x1e284, 0x1e28c, 777 0x1e2c0, 0x1e2c0, 778 0x1e2e0, 0x1e2e0, 779 0x1e300, 0x1e384, 780 0x1e3c0, 0x1e3c8, 781 0x1e440, 0x1e44c, 782 0x1e684, 0x1e68c, 783 0x1e6c0, 0x1e6c0, 784 0x1e6e0, 0x1e6e0, 785 0x1e700, 0x1e784, 786 0x1e7c0, 0x1e7c8, 787 0x1e840, 0x1e84c, 788 0x1ea84, 0x1ea8c, 789 0x1eac0, 0x1eac0, 790 0x1eae0, 0x1eae0, 791 0x1eb00, 0x1eb84, 792 0x1ebc0, 0x1ebc8, 793 0x1ec40, 0x1ec4c, 794 0x1ee84, 0x1ee8c, 795 0x1eec0, 0x1eec0, 796 0x1eee0, 0x1eee0, 797 0x1ef00, 0x1ef84, 798 0x1efc0, 0x1efc8, 799 0x1f040, 0x1f04c, 800 0x1f284, 0x1f28c, 801 0x1f2c0, 0x1f2c0, 802 0x1f2e0, 0x1f2e0, 803 0x1f300, 0x1f384, 804 0x1f3c0, 0x1f3c8, 805 0x1f440, 0x1f44c, 806 0x1f684, 0x1f68c, 807 0x1f6c0, 0x1f6c0, 808 0x1f6e0, 0x1f6e0, 809 0x1f700, 0x1f784, 810 0x1f7c0, 0x1f7c8, 811 0x1f840, 0x1f84c, 812 0x1fa84, 0x1fa8c, 813 0x1fac0, 0x1fac0, 814 0x1fae0, 0x1fae0, 815 0x1fb00, 0x1fb84, 816 0x1fbc0, 0x1fbc8, 817 0x1fc40, 0x1fc4c, 818 0x1fe84, 0x1fe8c, 819 0x1fec0, 0x1fec0, 820 0x1fee0, 0x1fee0, 821 0x1ff00, 0x1ff84, 822 0x1ffc0, 0x1ffc8, 823 0x20000, 0x2002c, 824 0x20100, 0x2013c, 825 0x20190, 0x201c8, 826 0x20200, 0x20318, 827 0x20400, 0x20528, 828 0x20540, 0x20614, 829 0x21000, 0x21040, 830 0x2104c, 0x21060, 831 0x210c0, 0x210ec, 832 0x21200, 0x21268, 833 0x21270, 0x21284, 834 0x212fc, 0x21388, 835 0x21400, 0x21404, 836 0x21500, 0x21518, 837 0x2152c, 0x2153c, 838 0x21550, 0x21554, 839 0x21600, 0x21600, 840 0x21608, 0x21628, 841 0x21630, 0x2163c, 842 0x21700, 0x2171c, 843 0x21780, 0x2178c, 844 0x21800, 0x21c38, 845 0x21c80, 0x21d7c, 846 0x21e00, 0x21e04, 847 0x22000, 0x2202c, 848 0x22100, 0x2213c, 849 0x22190, 0x221c8, 850 0x22200, 0x22318, 851 0x22400, 0x22528, 852 0x22540, 0x22614, 853 0x23000, 0x23040, 854 0x2304c, 0x23060, 855 0x230c0, 0x230ec, 856 0x23200, 0x23268, 857 0x23270, 0x23284, 858 0x232fc, 0x23388, 859 0x23400, 0x23404, 860 0x23500, 0x23518, 861 0x2352c, 0x2353c, 862 0x23550, 0x23554, 863 0x23600, 0x23600, 864 0x23608, 0x23628, 865 0x23630, 0x2363c, 866 0x23700, 0x2371c, 867 0x23780, 0x2378c, 868 0x23800, 0x23c38, 869 0x23c80, 0x23d7c, 870 0x23e00, 0x23e04, 871 0x24000, 0x2402c, 872 0x24100, 0x2413c, 873 0x24190, 0x241c8, 874 0x24200, 0x24318, 875 0x24400, 0x24528, 876 0x24540, 0x24614, 877 0x25000, 0x25040, 878 0x2504c, 0x25060, 879 0x250c0, 0x250ec, 880 0x25200, 0x25268, 881 0x25270, 0x25284, 882 0x252fc, 0x25388, 883 0x25400, 0x25404, 884 0x25500, 0x25518, 885 0x2552c, 0x2553c, 886 0x25550, 0x25554, 887 0x25600, 0x25600, 888 0x25608, 0x25628, 889 0x25630, 0x2563c, 890 0x25700, 0x2571c, 891 0x25780, 0x2578c, 892 0x25800, 0x25c38, 893 0x25c80, 0x25d7c, 894 0x25e00, 0x25e04, 895 0x26000, 0x2602c, 896 0x26100, 0x2613c, 897 0x26190, 0x261c8, 898 0x26200, 0x26318, 899 0x26400, 0x26528, 900 0x26540, 0x26614, 901 0x27000, 0x27040, 902 0x2704c, 0x27060, 903 0x270c0, 0x270ec, 904 0x27200, 0x27268, 905 0x27270, 0x27284, 906 0x272fc, 0x27388, 907 0x27400, 0x27404, 908 0x27500, 0x27518, 909 0x2752c, 0x2753c, 910 0x27550, 0x27554, 911 0x27600, 0x27600, 912 0x27608, 0x27628, 913 0x27630, 0x2763c, 914 0x27700, 0x2771c, 915 0x27780, 0x2778c, 916 0x27800, 0x27c38, 917 0x27c80, 0x27d7c, 918 0x27e00, 0x27e04, 919 }; 920 921 static const unsigned int t5_reg_ranges[] = { 922 0x1008, 0x1148, 923 0x1180, 0x11b4, 924 0x11fc, 0x123c, 925 0x1280, 0x173c, 926 0x1800, 0x18fc, 927 0x3000, 0x3028, 928 0x3068, 0x30d8, 929 0x30e0, 0x30fc, 930 0x3140, 0x357c, 931 0x35a8, 0x35cc, 932 0x35ec, 0x35ec, 933 0x3600, 0x5624, 934 0x56cc, 0x575c, 935 0x580c, 0x5814, 936 0x5890, 0x58bc, 937 0x5940, 0x59dc, 938 0x59fc, 0x5a18, 939 0x5a60, 0x5a9c, 940 0x5b94, 0x5bfc, 941 0x6000, 0x6040, 942 0x6058, 0x614c, 943 0x7700, 0x7798, 944 0x77c0, 0x78fc, 945 0x7b00, 0x7c54, 946 0x7d00, 0x7efc, 947 0x8dc0, 0x8de0, 948 0x8df8, 0x8e84, 949 0x8ea0, 0x8f84, 950 0x8fc0, 0x90f8, 951 0x9400, 0x9470, 952 0x9600, 0x96f4, 953 0x9800, 0x9808, 954 0x9820, 0x983c, 955 0x9850, 0x9864, 956 0x9c00, 0x9c6c, 957 0x9c80, 0x9cec, 958 0x9d00, 0x9d6c, 959 0x9d80, 0x9dec, 960 0x9e00, 0x9e6c, 961 0x9e80, 0x9eec, 962 0x9f00, 0x9f6c, 963 0x9f80, 0xa020, 964 0xd004, 0xd03c, 965 0xdfc0, 0xdfe0, 966 0xe000, 0x11088, 967 0x1109c, 0x11110, 968 0x11118, 0x1117c, 969 0x11190, 0x11204, 970 0x19040, 0x1906c, 971 0x19078, 0x19080, 972 0x1908c, 0x19124, 973 0x19150, 0x191b0, 974 0x191d0, 0x191e8, 975 0x19238, 0x19290, 976 0x193f8, 0x19474, 977 0x19490, 0x194cc, 978 0x194f0, 0x194f8, 979 0x19c00, 0x19c60, 980 0x19c94, 0x19e10, 981 0x19e50, 0x19f34, 982 0x19f40, 0x19f50, 983 0x19f90, 0x19fe4, 984 0x1a000, 0x1a06c, 985 0x1a0b0, 0x1a120, 986 0x1a128, 0x1a138, 987 0x1a190, 0x1a1c4, 988 0x1a1fc, 0x1a1fc, 989 0x1e008, 0x1e00c, 990 0x1e040, 0x1e04c, 991 0x1e284, 0x1e290, 992 0x1e2c0, 0x1e2c0, 993 0x1e2e0, 0x1e2e0, 994 0x1e300, 0x1e384, 995 0x1e3c0, 0x1e3c8, 996 0x1e408, 0x1e40c, 997 0x1e440, 0x1e44c, 998 0x1e684, 0x1e690, 999 0x1e6c0, 0x1e6c0, 1000 0x1e6e0, 0x1e6e0, 1001 0x1e700, 0x1e784, 1002 0x1e7c0, 0x1e7c8, 1003 0x1e808, 0x1e80c, 1004 0x1e840, 0x1e84c, 1005 0x1ea84, 0x1ea90, 1006 0x1eac0, 0x1eac0, 1007 0x1eae0, 0x1eae0, 1008 0x1eb00, 0x1eb84, 1009 0x1ebc0, 0x1ebc8, 1010 0x1ec08, 0x1ec0c, 1011 0x1ec40, 0x1ec4c, 1012 0x1ee84, 0x1ee90, 1013 0x1eec0, 0x1eec0, 1014 0x1eee0, 0x1eee0, 1015 0x1ef00, 0x1ef84, 1016 0x1efc0, 0x1efc8, 1017 0x1f008, 0x1f00c, 1018 0x1f040, 0x1f04c, 1019 0x1f284, 0x1f290, 1020 0x1f2c0, 0x1f2c0, 1021 0x1f2e0, 0x1f2e0, 1022 0x1f300, 0x1f384, 1023 0x1f3c0, 0x1f3c8, 1024 0x1f408, 0x1f40c, 1025 0x1f440, 0x1f44c, 1026 0x1f684, 0x1f690, 1027 0x1f6c0, 0x1f6c0, 1028 0x1f6e0, 0x1f6e0, 1029 0x1f700, 0x1f784, 1030 0x1f7c0, 0x1f7c8, 1031 0x1f808, 0x1f80c, 1032 0x1f840, 0x1f84c, 1033 0x1fa84, 0x1fa90, 1034 0x1fac0, 0x1fac0, 1035 0x1fae0, 0x1fae0, 1036 0x1fb00, 0x1fb84, 1037 0x1fbc0, 0x1fbc8, 1038 0x1fc08, 0x1fc0c, 1039 0x1fc40, 0x1fc4c, 1040 0x1fe84, 0x1fe90, 1041 0x1fec0, 0x1fec0, 1042 0x1fee0, 0x1fee0, 1043 0x1ff00, 0x1ff84, 1044 0x1ffc0, 0x1ffc8, 1045 0x30000, 0x30030, 1046 0x30100, 0x30144, 1047 0x30190, 0x301d0, 1048 0x30200, 0x30318, 1049 0x30400, 0x3052c, 1050 0x30540, 0x3061c, 1051 0x30800, 0x30834, 1052 0x308c0, 0x30908, 1053 0x30910, 0x309ac, 1054 0x30a00, 0x30a2c, 1055 0x30a44, 0x30a50, 1056 0x30a74, 0x30c24, 1057 0x30d00, 0x30d00, 1058 0x30d08, 0x30d14, 1059 0x30d1c, 0x30d20, 1060 0x30d3c, 0x30d50, 1061 0x31200, 0x3120c, 1062 0x31220, 0x31220, 1063 0x31240, 0x31240, 1064 0x31600, 0x3160c, 1065 0x31a00, 0x31a1c, 1066 0x31e00, 0x31e20, 1067 0x31e38, 0x31e3c, 1068 0x31e80, 0x31e80, 1069 0x31e88, 0x31ea8, 1070 0x31eb0, 0x31eb4, 1071 0x31ec8, 0x31ed4, 1072 0x31fb8, 0x32004, 1073 0x32200, 0x32200, 1074 0x32208, 0x32240, 1075 0x32248, 0x32280, 1076 0x32288, 0x322c0, 1077 0x322c8, 0x322fc, 1078 0x32600, 0x32630, 1079 0x32a00, 0x32abc, 1080 0x32b00, 0x32b70, 1081 0x33000, 0x33048, 1082 0x33060, 0x3309c, 1083 0x330f0, 0x33148, 1084 0x33160, 0x3319c, 1085 0x331f0, 0x332e4, 1086 0x332f8, 0x333e4, 1087 0x333f8, 0x33448, 1088 0x33460, 0x3349c, 1089 0x334f0, 0x33548, 1090 0x33560, 0x3359c, 1091 0x335f0, 0x336e4, 1092 0x336f8, 0x337e4, 1093 0x337f8, 0x337fc, 1094 0x33814, 0x33814, 1095 0x3382c, 0x3382c, 1096 0x33880, 0x3388c, 1097 0x338e8, 0x338ec, 1098 0x33900, 0x33948, 1099 0x33960, 0x3399c, 1100 0x339f0, 0x33ae4, 1101 0x33af8, 0x33b10, 1102 0x33b28, 0x33b28, 1103 0x33b3c, 0x33b50, 1104 0x33bf0, 0x33c10, 1105 0x33c28, 0x33c28, 1106 0x33c3c, 0x33c50, 1107 0x33cf0, 0x33cfc, 1108 0x34000, 0x34030, 1109 0x34100, 0x34144, 1110 0x34190, 0x341d0, 1111 0x34200, 0x34318, 1112 0x34400, 0x3452c, 1113 0x34540, 0x3461c, 1114 0x34800, 0x34834, 1115 0x348c0, 0x34908, 1116 0x34910, 0x349ac, 1117 0x34a00, 0x34a2c, 1118 0x34a44, 0x34a50, 1119 0x34a74, 0x34c24, 1120 0x34d00, 0x34d00, 1121 0x34d08, 0x34d14, 1122 0x34d1c, 0x34d20, 1123 0x34d3c, 0x34d50, 1124 0x35200, 0x3520c, 1125 0x35220, 0x35220, 1126 0x35240, 0x35240, 1127 0x35600, 0x3560c, 1128 0x35a00, 0x35a1c, 1129 0x35e00, 0x35e20, 1130 0x35e38, 0x35e3c, 1131 0x35e80, 0x35e80, 1132 0x35e88, 0x35ea8, 1133 0x35eb0, 0x35eb4, 1134 0x35ec8, 0x35ed4, 1135 0x35fb8, 0x36004, 1136 0x36200, 0x36200, 1137 0x36208, 0x36240, 1138 0x36248, 0x36280, 1139 0x36288, 0x362c0, 1140 0x362c8, 0x362fc, 1141 0x36600, 0x36630, 1142 0x36a00, 0x36abc, 1143 0x36b00, 0x36b70, 1144 0x37000, 0x37048, 1145 0x37060, 0x3709c, 1146 0x370f0, 0x37148, 1147 0x37160, 0x3719c, 1148 0x371f0, 0x372e4, 1149 0x372f8, 0x373e4, 1150 0x373f8, 0x37448, 1151 0x37460, 0x3749c, 1152 0x374f0, 0x37548, 1153 0x37560, 0x3759c, 1154 0x375f0, 0x376e4, 1155 0x376f8, 0x377e4, 1156 0x377f8, 0x377fc, 1157 0x37814, 0x37814, 1158 0x3782c, 0x3782c, 1159 0x37880, 0x3788c, 1160 0x378e8, 0x378ec, 1161 0x37900, 0x37948, 1162 0x37960, 0x3799c, 1163 0x379f0, 0x37ae4, 1164 0x37af8, 0x37b10, 1165 0x37b28, 0x37b28, 1166 0x37b3c, 0x37b50, 1167 0x37bf0, 0x37c10, 1168 0x37c28, 0x37c28, 1169 0x37c3c, 0x37c50, 1170 0x37cf0, 0x37cfc, 1171 0x38000, 0x38030, 1172 0x38100, 0x38144, 1173 0x38190, 0x381d0, 1174 0x38200, 0x38318, 1175 0x38400, 0x3852c, 1176 0x38540, 0x3861c, 1177 0x38800, 0x38834, 1178 0x388c0, 0x38908, 1179 0x38910, 0x389ac, 1180 0x38a00, 0x38a2c, 1181 0x38a44, 0x38a50, 1182 0x38a74, 0x38c24, 1183 0x38d00, 0x38d00, 1184 0x38d08, 0x38d14, 1185 0x38d1c, 0x38d20, 1186 0x38d3c, 0x38d50, 1187 0x39200, 0x3920c, 1188 0x39220, 0x39220, 1189 0x39240, 0x39240, 1190 0x39600, 0x3960c, 1191 0x39a00, 0x39a1c, 1192 0x39e00, 0x39e20, 1193 0x39e38, 0x39e3c, 1194 0x39e80, 0x39e80, 1195 0x39e88, 0x39ea8, 1196 0x39eb0, 0x39eb4, 1197 0x39ec8, 0x39ed4, 1198 0x39fb8, 0x3a004, 1199 0x3a200, 0x3a200, 1200 0x3a208, 0x3a240, 1201 0x3a248, 0x3a280, 1202 0x3a288, 0x3a2c0, 1203 0x3a2c8, 0x3a2fc, 1204 0x3a600, 0x3a630, 1205 0x3aa00, 0x3aabc, 1206 0x3ab00, 0x3ab70, 1207 0x3b000, 0x3b048, 1208 0x3b060, 0x3b09c, 1209 0x3b0f0, 0x3b148, 1210 0x3b160, 0x3b19c, 1211 0x3b1f0, 0x3b2e4, 1212 0x3b2f8, 0x3b3e4, 1213 0x3b3f8, 0x3b448, 1214 0x3b460, 0x3b49c, 1215 0x3b4f0, 0x3b548, 1216 0x3b560, 0x3b59c, 1217 0x3b5f0, 0x3b6e4, 1218 0x3b6f8, 0x3b7e4, 1219 0x3b7f8, 0x3b7fc, 1220 0x3b814, 0x3b814, 1221 0x3b82c, 0x3b82c, 1222 0x3b880, 0x3b88c, 1223 0x3b8e8, 0x3b8ec, 1224 0x3b900, 0x3b948, 1225 0x3b960, 0x3b99c, 1226 0x3b9f0, 0x3bae4, 1227 0x3baf8, 0x3bb10, 1228 0x3bb28, 0x3bb28, 1229 0x3bb3c, 0x3bb50, 1230 0x3bbf0, 0x3bc10, 1231 0x3bc28, 0x3bc28, 1232 0x3bc3c, 0x3bc50, 1233 0x3bcf0, 0x3bcfc, 1234 0x3c000, 0x3c030, 1235 0x3c100, 0x3c144, 1236 0x3c190, 0x3c1d0, 1237 0x3c200, 0x3c318, 1238 0x3c400, 0x3c52c, 1239 0x3c540, 0x3c61c, 1240 0x3c800, 0x3c834, 1241 0x3c8c0, 0x3c908, 1242 0x3c910, 0x3c9ac, 1243 0x3ca00, 0x3ca2c, 1244 0x3ca44, 0x3ca50, 1245 0x3ca74, 0x3cc24, 1246 0x3cd00, 0x3cd00, 1247 0x3cd08, 0x3cd14, 1248 0x3cd1c, 0x3cd20, 1249 0x3cd3c, 0x3cd50, 1250 0x3d200, 0x3d20c, 1251 0x3d220, 0x3d220, 1252 0x3d240, 0x3d240, 1253 0x3d600, 0x3d60c, 1254 0x3da00, 0x3da1c, 1255 0x3de00, 0x3de20, 1256 0x3de38, 0x3de3c, 1257 0x3de80, 0x3de80, 1258 0x3de88, 0x3dea8, 1259 0x3deb0, 0x3deb4, 1260 0x3dec8, 0x3ded4, 1261 0x3dfb8, 0x3e004, 1262 0x3e200, 0x3e200, 1263 0x3e208, 0x3e240, 1264 0x3e248, 0x3e280, 1265 0x3e288, 0x3e2c0, 1266 0x3e2c8, 0x3e2fc, 1267 0x3e600, 0x3e630, 1268 0x3ea00, 0x3eabc, 1269 0x3eb00, 0x3eb70, 1270 0x3f000, 0x3f048, 1271 0x3f060, 0x3f09c, 1272 0x3f0f0, 0x3f148, 1273 0x3f160, 0x3f19c, 1274 0x3f1f0, 0x3f2e4, 1275 0x3f2f8, 0x3f3e4, 1276 0x3f3f8, 0x3f448, 1277 0x3f460, 0x3f49c, 1278 0x3f4f0, 0x3f548, 1279 0x3f560, 0x3f59c, 1280 0x3f5f0, 0x3f6e4, 1281 0x3f6f8, 0x3f7e4, 1282 0x3f7f8, 0x3f7fc, 1283 0x3f814, 0x3f814, 1284 0x3f82c, 0x3f82c, 1285 0x3f880, 0x3f88c, 1286 0x3f8e8, 0x3f8ec, 1287 0x3f900, 0x3f948, 1288 0x3f960, 0x3f99c, 1289 0x3f9f0, 0x3fae4, 1290 0x3faf8, 0x3fb10, 1291 0x3fb28, 0x3fb28, 1292 0x3fb3c, 0x3fb50, 1293 0x3fbf0, 0x3fc10, 1294 0x3fc28, 0x3fc28, 1295 0x3fc3c, 0x3fc50, 1296 0x3fcf0, 0x3fcfc, 1297 0x40000, 0x4000c, 1298 0x40040, 0x40068, 1299 0x4007c, 0x40144, 1300 0x40180, 0x4018c, 1301 0x40200, 0x40298, 1302 0x402ac, 0x4033c, 1303 0x403f8, 0x403fc, 1304 0x41304, 0x413c4, 1305 0x41400, 0x4141c, 1306 0x41480, 0x414d0, 1307 0x44000, 0x44078, 1308 0x440c0, 0x44278, 1309 0x442c0, 0x44478, 1310 0x444c0, 0x44678, 1311 0x446c0, 0x44878, 1312 0x448c0, 0x449fc, 1313 0x45000, 0x45068, 1314 0x45080, 0x45084, 1315 0x450a0, 0x450b0, 1316 0x45200, 0x45268, 1317 0x45280, 0x45284, 1318 0x452a0, 0x452b0, 1319 0x460c0, 0x460e4, 1320 0x47000, 0x4708c, 1321 0x47200, 0x47250, 1322 0x47400, 0x47420, 1323 0x47600, 0x47618, 1324 0x47800, 0x47814, 1325 0x48000, 0x4800c, 1326 0x48040, 0x48068, 1327 0x4807c, 0x48144, 1328 0x48180, 0x4818c, 1329 0x48200, 0x48298, 1330 0x482ac, 0x4833c, 1331 0x483f8, 0x483fc, 1332 0x49304, 0x493c4, 1333 0x49400, 0x4941c, 1334 0x49480, 0x494d0, 1335 0x4c000, 0x4c078, 1336 0x4c0c0, 0x4c278, 1337 0x4c2c0, 0x4c478, 1338 0x4c4c0, 0x4c678, 1339 0x4c6c0, 0x4c878, 1340 0x4c8c0, 0x4c9fc, 1341 0x4d000, 0x4d068, 1342 0x4d080, 0x4d084, 1343 0x4d0a0, 0x4d0b0, 1344 0x4d200, 0x4d268, 1345 0x4d280, 0x4d284, 1346 0x4d2a0, 0x4d2b0, 1347 0x4e0c0, 0x4e0e4, 1348 0x4f000, 0x4f08c, 1349 0x4f200, 0x4f250, 1350 0x4f400, 0x4f420, 1351 0x4f600, 0x4f618, 1352 0x4f800, 0x4f814, 1353 0x50000, 0x500cc, 1354 0x50400, 0x50400, 1355 0x50800, 0x508cc, 1356 0x50c00, 0x50c00, 1357 0x51000, 0x5101c, 1358 0x51300, 0x51308, 1359 }; 1360 1361 static const unsigned int t6_reg_ranges[] = { 1362 0x1008, 0x1124, 1363 0x1138, 0x114c, 1364 0x1180, 0x11b4, 1365 0x11fc, 0x1254, 1366 0x1280, 0x133c, 1367 0x1800, 0x18fc, 1368 0x3000, 0x302c, 1369 0x3060, 0x30d8, 1370 0x30e0, 0x30fc, 1371 0x3140, 0x357c, 1372 0x35a8, 0x35cc, 1373 0x35ec, 0x35ec, 1374 0x3600, 0x5624, 1375 0x56cc, 0x575c, 1376 0x580c, 0x5814, 1377 0x5890, 0x58bc, 1378 0x5940, 0x595c, 1379 0x5980, 0x598c, 1380 0x59b0, 0x59dc, 1381 0x59fc, 0x5a18, 1382 0x5a60, 0x5a6c, 1383 0x5a80, 0x5a9c, 1384 0x5b94, 0x5bfc, 1385 0x5c10, 0x5ec0, 1386 0x5ec8, 0x5ecc, 1387 0x6000, 0x6040, 1388 0x6058, 0x619c, 1389 0x7700, 0x7798, 1390 0x77c0, 0x7880, 1391 0x78cc, 0x78fc, 1392 0x7b00, 0x7c54, 1393 0x7d00, 0x7efc, 1394 0x8dc0, 0x8de4, 1395 0x8df8, 0x8e84, 1396 0x8ea0, 0x8f88, 1397 0x8fb8, 0x9124, 1398 0x9400, 0x9470, 1399 0x9600, 0x971c, 1400 0x9800, 0x9808, 1401 0x9820, 0x983c, 1402 0x9850, 0x9864, 1403 0x9c00, 0x9c6c, 1404 0x9c80, 0x9cec, 1405 0x9d00, 0x9d6c, 1406 0x9d80, 0x9dec, 1407 0x9e00, 0x9e6c, 1408 0x9e80, 0x9eec, 1409 0x9f00, 0x9f6c, 1410 0x9f80, 0xa020, 1411 0xd004, 0xd03c, 1412 0xd100, 0xd118, 1413 0xd200, 0xd31c, 1414 0xdfc0, 0xdfe0, 1415 0xe000, 0xf008, 1416 0x11000, 0x11014, 1417 0x11048, 0x1117c, 1418 0x11190, 0x11270, 1419 0x11300, 0x1130c, 1420 0x12000, 0x1206c, 1421 0x19040, 0x1906c, 1422 0x19078, 0x19080, 1423 0x1908c, 0x19124, 1424 0x19150, 0x191b0, 1425 0x191d0, 0x191e8, 1426 0x19238, 0x192bc, 1427 0x193f8, 0x19474, 1428 0x19490, 0x194cc, 1429 0x194f0, 0x194f8, 1430 0x19c00, 0x19c80, 1431 0x19c94, 0x19cbc, 1432 0x19ce4, 0x19d28, 1433 0x19d50, 0x19d78, 1434 0x19d94, 0x19dc8, 1435 0x19df0, 0x19e10, 1436 0x19e50, 0x19e6c, 1437 0x19ea0, 0x19f34, 1438 0x19f40, 0x19f50, 1439 0x19f90, 0x19fac, 1440 0x19fc4, 0x19fe4, 1441 0x1a000, 0x1a06c, 1442 0x1a0b0, 0x1a120, 1443 0x1a128, 0x1a138, 1444 0x1a190, 0x1a1c4, 1445 0x1a1fc, 0x1a1fc, 1446 0x1e008, 0x1e00c, 1447 0x1e040, 0x1e04c, 1448 0x1e284, 0x1e290, 1449 0x1e2c0, 0x1e2c0, 1450 0x1e2e0, 0x1e2e0, 1451 0x1e300, 0x1e384, 1452 0x1e3c0, 0x1e3c8, 1453 0x1e408, 0x1e40c, 1454 0x1e440, 0x1e44c, 1455 0x1e684, 0x1e690, 1456 0x1e6c0, 0x1e6c0, 1457 0x1e6e0, 0x1e6e0, 1458 0x1e700, 0x1e784, 1459 0x1e7c0, 0x1e7c8, 1460 0x1e808, 0x1e80c, 1461 0x1e840, 0x1e84c, 1462 0x1ea84, 0x1ea90, 1463 0x1eac0, 0x1eac0, 1464 0x1eae0, 0x1eae0, 1465 0x1eb00, 0x1eb84, 1466 0x1ebc0, 0x1ebc8, 1467 0x1ec08, 0x1ec0c, 1468 0x1ec40, 0x1ec4c, 1469 0x1ee84, 0x1ee90, 1470 0x1eec0, 0x1eec0, 1471 0x1eee0, 0x1eee0, 1472 0x1ef00, 0x1ef84, 1473 0x1efc0, 0x1efc8, 1474 0x1f008, 0x1f00c, 1475 0x1f040, 0x1f04c, 1476 0x1f284, 0x1f290, 1477 0x1f2c0, 0x1f2c0, 1478 0x1f2e0, 0x1f2e0, 1479 0x1f300, 0x1f384, 1480 0x1f3c0, 0x1f3c8, 1481 0x1f408, 0x1f40c, 1482 0x1f440, 0x1f44c, 1483 0x1f684, 0x1f690, 1484 0x1f6c0, 0x1f6c0, 1485 0x1f6e0, 0x1f6e0, 1486 0x1f700, 0x1f784, 1487 0x1f7c0, 0x1f7c8, 1488 0x1f808, 0x1f80c, 1489 0x1f840, 0x1f84c, 1490 0x1fa84, 0x1fa90, 1491 0x1fac0, 0x1fac0, 1492 0x1fae0, 0x1fae0, 1493 0x1fb00, 0x1fb84, 1494 0x1fbc0, 0x1fbc8, 1495 0x1fc08, 0x1fc0c, 1496 0x1fc40, 0x1fc4c, 1497 0x1fe84, 0x1fe90, 1498 0x1fec0, 0x1fec0, 1499 0x1fee0, 0x1fee0, 1500 0x1ff00, 0x1ff84, 1501 0x1ffc0, 0x1ffc8, 1502 0x30000, 0x30070, 1503 0x30100, 0x301d0, 1504 0x30200, 0x30320, 1505 0x30400, 0x3052c, 1506 0x30540, 0x3061c, 1507 0x30800, 0x30890, 1508 0x308c0, 0x30908, 1509 0x30910, 0x309b8, 1510 0x30a00, 0x30a04, 1511 0x30a0c, 0x30a2c, 1512 0x30a44, 0x30a50, 1513 0x30a74, 0x30c24, 1514 0x30d00, 0x30d3c, 1515 0x30d44, 0x30d7c, 1516 0x30de0, 0x30de0, 1517 0x30e00, 0x30ed4, 1518 0x30f00, 0x30fa4, 1519 0x30fc0, 0x30fc4, 1520 0x31000, 0x31004, 1521 0x31080, 0x310fc, 1522 0x31208, 0x31220, 1523 0x3123c, 0x31254, 1524 0x31300, 0x31300, 1525 0x31308, 0x3131c, 1526 0x31338, 0x3133c, 1527 0x31380, 0x31380, 1528 0x31388, 0x313a8, 1529 0x313b4, 0x313b4, 1530 0x31400, 0x31420, 1531 0x31438, 0x3143c, 1532 0x31480, 0x31480, 1533 0x314a8, 0x314a8, 1534 0x314b0, 0x314b4, 1535 0x314c8, 0x314d4, 1536 0x31a40, 0x31a4c, 1537 0x31af0, 0x31b20, 1538 0x31b38, 0x31b3c, 1539 0x31b80, 0x31b80, 1540 0x31ba8, 0x31ba8, 1541 0x31bb0, 0x31bb4, 1542 0x31bc8, 0x31bd4, 1543 0x32140, 0x3218c, 1544 0x321f0, 0x32200, 1545 0x32218, 0x32218, 1546 0x32400, 0x32400, 1547 0x32408, 0x3241c, 1548 0x32618, 0x32620, 1549 0x32664, 0x32664, 1550 0x326a8, 0x326a8, 1551 0x326ec, 0x326ec, 1552 0x32a00, 0x32abc, 1553 0x32b00, 0x32b78, 1554 0x32c00, 0x32c00, 1555 0x32c08, 0x32c3c, 1556 0x32e00, 0x32e2c, 1557 0x32f00, 0x32f2c, 1558 0x33000, 0x330ac, 1559 0x330c0, 0x331ac, 1560 0x331c0, 0x332c4, 1561 0x332e4, 0x333c4, 1562 0x333e4, 0x334ac, 1563 0x334c0, 0x335ac, 1564 0x335c0, 0x336c4, 1565 0x336e4, 0x337c4, 1566 0x337e4, 0x337fc, 1567 0x33814, 0x33814, 1568 0x33854, 0x33868, 1569 0x33880, 0x3388c, 1570 0x338c0, 0x338d0, 1571 0x338e8, 0x338ec, 1572 0x33900, 0x339ac, 1573 0x339c0, 0x33ac4, 1574 0x33ae4, 0x33b10, 1575 0x33b24, 0x33b50, 1576 0x33bf0, 0x33c10, 1577 0x33c24, 0x33c50, 1578 0x33cf0, 0x33cfc, 1579 0x34000, 0x34070, 1580 0x34100, 0x341d0, 1581 0x34200, 0x34320, 1582 0x34400, 0x3452c, 1583 0x34540, 0x3461c, 1584 0x34800, 0x34890, 1585 0x348c0, 0x34908, 1586 0x34910, 0x349b8, 1587 0x34a00, 0x34a04, 1588 0x34a0c, 0x34a2c, 1589 0x34a44, 0x34a50, 1590 0x34a74, 0x34c24, 1591 0x34d00, 0x34d3c, 1592 0x34d44, 0x34d7c, 1593 0x34de0, 0x34de0, 1594 0x34e00, 0x34ed4, 1595 0x34f00, 0x34fa4, 1596 0x34fc0, 0x34fc4, 1597 0x35000, 0x35004, 1598 0x35080, 0x350fc, 1599 0x35208, 0x35220, 1600 0x3523c, 0x35254, 1601 0x35300, 0x35300, 1602 0x35308, 0x3531c, 1603 0x35338, 0x3533c, 1604 0x35380, 0x35380, 1605 0x35388, 0x353a8, 1606 0x353b4, 0x353b4, 1607 0x35400, 0x35420, 1608 0x35438, 0x3543c, 1609 0x35480, 0x35480, 1610 0x354a8, 0x354a8, 1611 0x354b0, 0x354b4, 1612 0x354c8, 0x354d4, 1613 0x35a40, 0x35a4c, 1614 0x35af0, 0x35b20, 1615 0x35b38, 0x35b3c, 1616 0x35b80, 0x35b80, 1617 0x35ba8, 0x35ba8, 1618 0x35bb0, 0x35bb4, 1619 0x35bc8, 0x35bd4, 1620 0x36140, 0x3618c, 1621 0x361f0, 0x36200, 1622 0x36218, 0x36218, 1623 0x36400, 0x36400, 1624 0x36408, 0x3641c, 1625 0x36618, 0x36620, 1626 0x36664, 0x36664, 1627 0x366a8, 0x366a8, 1628 0x366ec, 0x366ec, 1629 0x36a00, 0x36abc, 1630 0x36b00, 0x36b78, 1631 0x36c00, 0x36c00, 1632 0x36c08, 0x36c3c, 1633 0x36e00, 0x36e2c, 1634 0x36f00, 0x36f2c, 1635 0x37000, 0x370ac, 1636 0x370c0, 0x371ac, 1637 0x371c0, 0x372c4, 1638 0x372e4, 0x373c4, 1639 0x373e4, 0x374ac, 1640 0x374c0, 0x375ac, 1641 0x375c0, 0x376c4, 1642 0x376e4, 0x377c4, 1643 0x377e4, 0x377fc, 1644 0x37814, 0x37814, 1645 0x37854, 0x37868, 1646 0x37880, 0x3788c, 1647 0x378c0, 0x378d0, 1648 0x378e8, 0x378ec, 1649 0x37900, 0x379ac, 1650 0x379c0, 0x37ac4, 1651 0x37ae4, 0x37b10, 1652 0x37b24, 0x37b50, 1653 0x37bf0, 0x37c10, 1654 0x37c24, 0x37c50, 1655 0x37cf0, 0x37cfc, 1656 0x40040, 0x40040, 1657 0x40080, 0x40084, 1658 0x40100, 0x40100, 1659 0x40140, 0x401bc, 1660 0x40200, 0x40214, 1661 0x40228, 0x40228, 1662 0x40240, 0x40258, 1663 0x40280, 0x40280, 1664 0x40304, 0x40304, 1665 0x40330, 0x4033c, 1666 0x41304, 0x413dc, 1667 0x41400, 0x4141c, 1668 0x41480, 0x414d0, 1669 0x44000, 0x4407c, 1670 0x440c0, 0x4427c, 1671 0x442c0, 0x4447c, 1672 0x444c0, 0x4467c, 1673 0x446c0, 0x4487c, 1674 0x448c0, 0x44a7c, 1675 0x44ac0, 0x44c7c, 1676 0x44cc0, 0x44e7c, 1677 0x44ec0, 0x4507c, 1678 0x450c0, 0x451fc, 1679 0x45800, 0x45868, 1680 0x45880, 0x45884, 1681 0x458a0, 0x458b0, 1682 0x45a00, 0x45a68, 1683 0x45a80, 0x45a84, 1684 0x45aa0, 0x45ab0, 1685 0x460c0, 0x460e4, 1686 0x47000, 0x4708c, 1687 0x47200, 0x47250, 1688 0x47400, 0x47420, 1689 0x47600, 0x47618, 1690 0x47800, 0x4782c, 1691 0x50000, 0x500cc, 1692 0x50400, 0x50400, 1693 0x50800, 0x508cc, 1694 0x50c00, 0x50c00, 1695 0x51000, 0x510b0, 1696 0x51300, 0x51324, 1697 }; 1698 1699 u32 *buf_end = (u32 *)((char *)buf + buf_size); 1700 const unsigned int *reg_ranges; 1701 int reg_ranges_size, range; 1702 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); 1703 1704 /* Select the right set of register ranges to dump depending on the 1705 * adapter chip type. 1706 */ 1707 switch (chip_version) { 1708 case CHELSIO_T4: 1709 reg_ranges = t4_reg_ranges; 1710 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 1711 break; 1712 1713 case CHELSIO_T5: 1714 reg_ranges = t5_reg_ranges; 1715 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 1716 break; 1717 1718 case CHELSIO_T6: 1719 reg_ranges = t6_reg_ranges; 1720 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 1721 break; 1722 1723 default: 1724 dev_err(adap->pdev_dev, 1725 "Unsupported chip version %d\n", chip_version); 1726 return; 1727 } 1728 1729 /* Clear the register buffer and insert the appropriate register 1730 * values selected by the above register ranges. 1731 */ 1732 memset(buf, 0, buf_size); 1733 for (range = 0; range < reg_ranges_size; range += 2) { 1734 unsigned int reg = reg_ranges[range]; 1735 unsigned int last_reg = reg_ranges[range + 1]; 1736 u32 *bufp = (u32 *)((char *)buf + reg); 1737 1738 /* Iterate across the register range filling in the register 1739 * buffer but don't write past the end of the register buffer. 1740 */ 1741 while (reg <= last_reg && bufp < buf_end) { 1742 *bufp++ = t4_read_reg(adap, reg); 1743 reg += sizeof(u32); 1744 } 1745 } 1746 } 1747 1748 #define EEPROM_STAT_ADDR 0x7bfc 1749 #define VPD_BASE 0x400 1750 #define VPD_BASE_OLD 0 1751 #define VPD_LEN 1024 1752 #define CHELSIO_VPD_UNIQUE_ID 0x82 1753 1754 /** 1755 * t4_seeprom_wp - enable/disable EEPROM write protection 1756 * @adapter: the adapter 1757 * @enable: whether to enable or disable write protection 1758 * 1759 * Enables or disables write protection on the serial EEPROM. 1760 */ 1761 int t4_seeprom_wp(struct adapter *adapter, bool enable) 1762 { 1763 unsigned int v = enable ? 0xc : 0; 1764 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v); 1765 return ret < 0 ? ret : 0; 1766 } 1767 1768 /** 1769 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM 1770 * @adapter: adapter to read 1771 * @p: where to store the parameters 1772 * 1773 * Reads card parameters stored in VPD EEPROM. 1774 */ 1775 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p) 1776 { 1777 int i, ret = 0, addr; 1778 int ec, sn, pn, na; 1779 u8 *vpd, csum; 1780 unsigned int vpdr_len, kw_offset, id_len; 1781 1782 vpd = vmalloc(VPD_LEN); 1783 if (!vpd) 1784 return -ENOMEM; 1785 1786 /* Card information normally starts at VPD_BASE but early cards had 1787 * it at 0. 1788 */ 1789 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd); 1790 if (ret < 0) 1791 goto out; 1792 1793 /* The VPD shall have a unique identifier specified by the PCI SIG. 1794 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 1795 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 1796 * is expected to automatically put this entry at the 1797 * beginning of the VPD. 1798 */ 1799 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 1800 1801 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd); 1802 if (ret < 0) 1803 goto out; 1804 1805 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) { 1806 dev_err(adapter->pdev_dev, "missing VPD ID string\n"); 1807 ret = -EINVAL; 1808 goto out; 1809 } 1810 1811 id_len = pci_vpd_lrdt_size(vpd); 1812 if (id_len > ID_LEN) 1813 id_len = ID_LEN; 1814 1815 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA); 1816 if (i < 0) { 1817 dev_err(adapter->pdev_dev, "missing VPD-R section\n"); 1818 ret = -EINVAL; 1819 goto out; 1820 } 1821 1822 vpdr_len = pci_vpd_lrdt_size(&vpd[i]); 1823 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE; 1824 if (vpdr_len + kw_offset > VPD_LEN) { 1825 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len); 1826 ret = -EINVAL; 1827 goto out; 1828 } 1829 1830 #define FIND_VPD_KW(var, name) do { \ 1831 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \ 1832 if (var < 0) { \ 1833 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \ 1834 ret = -EINVAL; \ 1835 goto out; \ 1836 } \ 1837 var += PCI_VPD_INFO_FLD_HDR_SIZE; \ 1838 } while (0) 1839 1840 FIND_VPD_KW(i, "RV"); 1841 for (csum = 0; i >= 0; i--) 1842 csum += vpd[i]; 1843 1844 if (csum) { 1845 dev_err(adapter->pdev_dev, 1846 "corrupted VPD EEPROM, actual csum %u\n", csum); 1847 ret = -EINVAL; 1848 goto out; 1849 } 1850 1851 FIND_VPD_KW(ec, "EC"); 1852 FIND_VPD_KW(sn, "SN"); 1853 FIND_VPD_KW(pn, "PN"); 1854 FIND_VPD_KW(na, "NA"); 1855 #undef FIND_VPD_KW 1856 1857 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len); 1858 strim(p->id); 1859 memcpy(p->ec, vpd + ec, EC_LEN); 1860 strim(p->ec); 1861 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE); 1862 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 1863 strim(p->sn); 1864 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE); 1865 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 1866 strim(p->pn); 1867 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 1868 strim((char *)p->na); 1869 1870 out: 1871 vfree(vpd); 1872 return ret; 1873 } 1874 1875 /** 1876 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock 1877 * @adapter: adapter to read 1878 * @p: where to store the parameters 1879 * 1880 * Reads card parameters stored in VPD EEPROM and retrieves the Core 1881 * Clock. This can only be called after a connection to the firmware 1882 * is established. 1883 */ 1884 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p) 1885 { 1886 u32 cclk_param, cclk_val; 1887 int ret; 1888 1889 /* Grab the raw VPD parameters. 1890 */ 1891 ret = t4_get_raw_vpd_params(adapter, p); 1892 if (ret) 1893 return ret; 1894 1895 /* Ask firmware for the Core Clock since it knows how to translate the 1896 * Reference Clock ('V2') VPD field into a Core Clock value ... 1897 */ 1898 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 1899 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK)); 1900 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 1901 1, &cclk_param, &cclk_val); 1902 1903 if (ret) 1904 return ret; 1905 p->cclk = cclk_val; 1906 1907 return 0; 1908 } 1909 1910 /* serial flash and firmware constants */ 1911 enum { 1912 SF_ATTEMPTS = 10, /* max retries for SF operations */ 1913 1914 /* flash command opcodes */ 1915 SF_PROG_PAGE = 2, /* program page */ 1916 SF_WR_DISABLE = 4, /* disable writes */ 1917 SF_RD_STATUS = 5, /* read status register */ 1918 SF_WR_ENABLE = 6, /* enable writes */ 1919 SF_RD_DATA_FAST = 0xb, /* read flash */ 1920 SF_RD_ID = 0x9f, /* read ID */ 1921 SF_ERASE_SECTOR = 0xd8, /* erase sector */ 1922 1923 FW_MAX_SIZE = 16 * SF_SEC_SIZE, 1924 }; 1925 1926 /** 1927 * sf1_read - read data from the serial flash 1928 * @adapter: the adapter 1929 * @byte_cnt: number of bytes to read 1930 * @cont: whether another operation will be chained 1931 * @lock: whether to lock SF for PL access only 1932 * @valp: where to store the read data 1933 * 1934 * Reads up to 4 bytes of data from the serial flash. The location of 1935 * the read needs to be specified prior to calling this by issuing the 1936 * appropriate commands to the serial flash. 1937 */ 1938 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 1939 int lock, u32 *valp) 1940 { 1941 int ret; 1942 1943 if (!byte_cnt || byte_cnt > 4) 1944 return -EINVAL; 1945 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F) 1946 return -EBUSY; 1947 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) | 1948 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1)); 1949 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5); 1950 if (!ret) 1951 *valp = t4_read_reg(adapter, SF_DATA_A); 1952 return ret; 1953 } 1954 1955 /** 1956 * sf1_write - write data to the serial flash 1957 * @adapter: the adapter 1958 * @byte_cnt: number of bytes to write 1959 * @cont: whether another operation will be chained 1960 * @lock: whether to lock SF for PL access only 1961 * @val: value to write 1962 * 1963 * Writes up to 4 bytes of data to the serial flash. The location of 1964 * the write needs to be specified prior to calling this by issuing the 1965 * appropriate commands to the serial flash. 1966 */ 1967 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 1968 int lock, u32 val) 1969 { 1970 if (!byte_cnt || byte_cnt > 4) 1971 return -EINVAL; 1972 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F) 1973 return -EBUSY; 1974 t4_write_reg(adapter, SF_DATA_A, val); 1975 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) | 1976 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1)); 1977 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5); 1978 } 1979 1980 /** 1981 * flash_wait_op - wait for a flash operation to complete 1982 * @adapter: the adapter 1983 * @attempts: max number of polls of the status register 1984 * @delay: delay between polls in ms 1985 * 1986 * Wait for a flash operation to complete by polling the status register. 1987 */ 1988 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 1989 { 1990 int ret; 1991 u32 status; 1992 1993 while (1) { 1994 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 1995 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 1996 return ret; 1997 if (!(status & 1)) 1998 return 0; 1999 if (--attempts == 0) 2000 return -EAGAIN; 2001 if (delay) 2002 msleep(delay); 2003 } 2004 } 2005 2006 /** 2007 * t4_read_flash - read words from serial flash 2008 * @adapter: the adapter 2009 * @addr: the start address for the read 2010 * @nwords: how many 32-bit words to read 2011 * @data: where to store the read data 2012 * @byte_oriented: whether to store data as bytes or as words 2013 * 2014 * Read the specified number of 32-bit words from the serial flash. 2015 * If @byte_oriented is set the read data is stored as a byte array 2016 * (i.e., big-endian), otherwise as 32-bit words in the platform's 2017 * natural endianness. 2018 */ 2019 int t4_read_flash(struct adapter *adapter, unsigned int addr, 2020 unsigned int nwords, u32 *data, int byte_oriented) 2021 { 2022 int ret; 2023 2024 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 2025 return -EINVAL; 2026 2027 addr = swab32(addr) | SF_RD_DATA_FAST; 2028 2029 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 2030 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 2031 return ret; 2032 2033 for ( ; nwords; nwords--, data++) { 2034 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 2035 if (nwords == 1) 2036 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ 2037 if (ret) 2038 return ret; 2039 if (byte_oriented) 2040 *data = (__force __u32)(cpu_to_be32(*data)); 2041 } 2042 return 0; 2043 } 2044 2045 /** 2046 * t4_write_flash - write up to a page of data to the serial flash 2047 * @adapter: the adapter 2048 * @addr: the start address to write 2049 * @n: length of data to write in bytes 2050 * @data: the data to write 2051 * 2052 * Writes up to a page of data (256 bytes) to the serial flash starting 2053 * at the given address. All the data must be written to the same page. 2054 */ 2055 static int t4_write_flash(struct adapter *adapter, unsigned int addr, 2056 unsigned int n, const u8 *data) 2057 { 2058 int ret; 2059 u32 buf[64]; 2060 unsigned int i, c, left, val, offset = addr & 0xff; 2061 2062 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 2063 return -EINVAL; 2064 2065 val = swab32(addr) | SF_PROG_PAGE; 2066 2067 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 2068 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 2069 goto unlock; 2070 2071 for (left = n; left; left -= c) { 2072 c = min(left, 4U); 2073 for (val = 0, i = 0; i < c; ++i) 2074 val = (val << 8) + *data++; 2075 2076 ret = sf1_write(adapter, c, c != left, 1, val); 2077 if (ret) 2078 goto unlock; 2079 } 2080 ret = flash_wait_op(adapter, 8, 1); 2081 if (ret) 2082 goto unlock; 2083 2084 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ 2085 2086 /* Read the page to verify the write succeeded */ 2087 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); 2088 if (ret) 2089 return ret; 2090 2091 if (memcmp(data - n, (u8 *)buf + offset, n)) { 2092 dev_err(adapter->pdev_dev, 2093 "failed to correctly write the flash page at %#x\n", 2094 addr); 2095 return -EIO; 2096 } 2097 return 0; 2098 2099 unlock: 2100 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ 2101 return ret; 2102 } 2103 2104 /** 2105 * t4_get_fw_version - read the firmware version 2106 * @adapter: the adapter 2107 * @vers: where to place the version 2108 * 2109 * Reads the FW version from flash. 2110 */ 2111 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 2112 { 2113 return t4_read_flash(adapter, FLASH_FW_START + 2114 offsetof(struct fw_hdr, fw_ver), 1, 2115 vers, 0); 2116 } 2117 2118 /** 2119 * t4_get_tp_version - read the TP microcode version 2120 * @adapter: the adapter 2121 * @vers: where to place the version 2122 * 2123 * Reads the TP microcode version from flash. 2124 */ 2125 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 2126 { 2127 return t4_read_flash(adapter, FLASH_FW_START + 2128 offsetof(struct fw_hdr, tp_microcode_ver), 2129 1, vers, 0); 2130 } 2131 2132 /** 2133 * t4_get_exprom_version - return the Expansion ROM version (if any) 2134 * @adapter: the adapter 2135 * @vers: where to place the version 2136 * 2137 * Reads the Expansion ROM header from FLASH and returns the version 2138 * number (if present) through the @vers return value pointer. We return 2139 * this in the Firmware Version Format since it's convenient. Return 2140 * 0 on success, -ENOENT if no Expansion ROM is present. 2141 */ 2142 int t4_get_exprom_version(struct adapter *adap, u32 *vers) 2143 { 2144 struct exprom_header { 2145 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 2146 unsigned char hdr_ver[4]; /* Expansion ROM version */ 2147 } *hdr; 2148 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 2149 sizeof(u32))]; 2150 int ret; 2151 2152 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, 2153 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 2154 0); 2155 if (ret) 2156 return ret; 2157 2158 hdr = (struct exprom_header *)exprom_header_buf; 2159 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 2160 return -ENOENT; 2161 2162 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) | 2163 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) | 2164 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) | 2165 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3])); 2166 return 0; 2167 } 2168 2169 /* Is the given firmware API compatible with the one the driver was compiled 2170 * with? 2171 */ 2172 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 2173 { 2174 2175 /* short circuit if it's the exact same firmware version */ 2176 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 2177 return 1; 2178 2179 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 2180 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 2181 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe)) 2182 return 1; 2183 #undef SAME_INTF 2184 2185 return 0; 2186 } 2187 2188 /* The firmware in the filesystem is usable, but should it be installed? 2189 * This routine explains itself in detail if it indicates the filesystem 2190 * firmware should be installed. 2191 */ 2192 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable, 2193 int k, int c) 2194 { 2195 const char *reason; 2196 2197 if (!card_fw_usable) { 2198 reason = "incompatible or unusable"; 2199 goto install; 2200 } 2201 2202 if (k > c) { 2203 reason = "older than the version supported with this driver"; 2204 goto install; 2205 } 2206 2207 return 0; 2208 2209 install: 2210 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, " 2211 "installing firmware %u.%u.%u.%u on card.\n", 2212 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c), 2213 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason, 2214 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), 2215 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); 2216 2217 return 1; 2218 } 2219 2220 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 2221 const u8 *fw_data, unsigned int fw_size, 2222 struct fw_hdr *card_fw, enum dev_state state, 2223 int *reset) 2224 { 2225 int ret, card_fw_usable, fs_fw_usable; 2226 const struct fw_hdr *fs_fw; 2227 const struct fw_hdr *drv_fw; 2228 2229 drv_fw = &fw_info->fw_hdr; 2230 2231 /* Read the header of the firmware on the card */ 2232 ret = -t4_read_flash(adap, FLASH_FW_START, 2233 sizeof(*card_fw) / sizeof(uint32_t), 2234 (uint32_t *)card_fw, 1); 2235 if (ret == 0) { 2236 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw); 2237 } else { 2238 dev_err(adap->pdev_dev, 2239 "Unable to read card's firmware header: %d\n", ret); 2240 card_fw_usable = 0; 2241 } 2242 2243 if (fw_data != NULL) { 2244 fs_fw = (const void *)fw_data; 2245 fs_fw_usable = fw_compatible(drv_fw, fs_fw); 2246 } else { 2247 fs_fw = NULL; 2248 fs_fw_usable = 0; 2249 } 2250 2251 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 2252 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) { 2253 /* Common case: the firmware on the card is an exact match and 2254 * the filesystem one is an exact match too, or the filesystem 2255 * one is absent/incompatible. 2256 */ 2257 } else if (fs_fw_usable && state == DEV_STATE_UNINIT && 2258 should_install_fs_fw(adap, card_fw_usable, 2259 be32_to_cpu(fs_fw->fw_ver), 2260 be32_to_cpu(card_fw->fw_ver))) { 2261 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data, 2262 fw_size, 0); 2263 if (ret != 0) { 2264 dev_err(adap->pdev_dev, 2265 "failed to install firmware: %d\n", ret); 2266 goto bye; 2267 } 2268 2269 /* Installed successfully, update the cached header too. */ 2270 *card_fw = *fs_fw; 2271 card_fw_usable = 1; 2272 *reset = 0; /* already reset as part of load_fw */ 2273 } 2274 2275 if (!card_fw_usable) { 2276 uint32_t d, c, k; 2277 2278 d = be32_to_cpu(drv_fw->fw_ver); 2279 c = be32_to_cpu(card_fw->fw_ver); 2280 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0; 2281 2282 dev_err(adap->pdev_dev, "Cannot find a usable firmware: " 2283 "chip state %d, " 2284 "driver compiled with %d.%d.%d.%d, " 2285 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n", 2286 state, 2287 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d), 2288 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d), 2289 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c), 2290 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), 2291 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), 2292 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); 2293 ret = EINVAL; 2294 goto bye; 2295 } 2296 2297 /* We're using whatever's on the card and it's known to be good. */ 2298 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); 2299 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); 2300 2301 bye: 2302 return ret; 2303 } 2304 2305 /** 2306 * t4_flash_erase_sectors - erase a range of flash sectors 2307 * @adapter: the adapter 2308 * @start: the first sector to erase 2309 * @end: the last sector to erase 2310 * 2311 * Erases the sectors in the given inclusive range. 2312 */ 2313 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 2314 { 2315 int ret = 0; 2316 2317 if (end >= adapter->params.sf_nsec) 2318 return -EINVAL; 2319 2320 while (start <= end) { 2321 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 2322 (ret = sf1_write(adapter, 4, 0, 1, 2323 SF_ERASE_SECTOR | (start << 8))) != 0 || 2324 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 2325 dev_err(adapter->pdev_dev, 2326 "erase of flash sector %d failed, error %d\n", 2327 start, ret); 2328 break; 2329 } 2330 start++; 2331 } 2332 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */ 2333 return ret; 2334 } 2335 2336 /** 2337 * t4_flash_cfg_addr - return the address of the flash configuration file 2338 * @adapter: the adapter 2339 * 2340 * Return the address within the flash where the Firmware Configuration 2341 * File is stored. 2342 */ 2343 unsigned int t4_flash_cfg_addr(struct adapter *adapter) 2344 { 2345 if (adapter->params.sf_size == 0x100000) 2346 return FLASH_FPGA_CFG_START; 2347 else 2348 return FLASH_CFG_START; 2349 } 2350 2351 /* Return TRUE if the specified firmware matches the adapter. I.e. T4 2352 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 2353 * and emit an error message for mismatched firmware to save our caller the 2354 * effort ... 2355 */ 2356 static bool t4_fw_matches_chip(const struct adapter *adap, 2357 const struct fw_hdr *hdr) 2358 { 2359 /* The expression below will return FALSE for any unsupported adapter 2360 * which will keep us "honest" in the future ... 2361 */ 2362 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || 2363 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) || 2364 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6)) 2365 return true; 2366 2367 dev_err(adap->pdev_dev, 2368 "FW image (%d) is not suitable for this adapter (%d)\n", 2369 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); 2370 return false; 2371 } 2372 2373 /** 2374 * t4_load_fw - download firmware 2375 * @adap: the adapter 2376 * @fw_data: the firmware image to write 2377 * @size: image size 2378 * 2379 * Write the supplied firmware image to the card's serial flash. 2380 */ 2381 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 2382 { 2383 u32 csum; 2384 int ret, addr; 2385 unsigned int i; 2386 u8 first_page[SF_PAGE_SIZE]; 2387 const __be32 *p = (const __be32 *)fw_data; 2388 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 2389 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 2390 unsigned int fw_img_start = adap->params.sf_fw_start; 2391 unsigned int fw_start_sec = fw_img_start / sf_sec_size; 2392 2393 if (!size) { 2394 dev_err(adap->pdev_dev, "FW image has no data\n"); 2395 return -EINVAL; 2396 } 2397 if (size & 511) { 2398 dev_err(adap->pdev_dev, 2399 "FW image size not multiple of 512 bytes\n"); 2400 return -EINVAL; 2401 } 2402 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) { 2403 dev_err(adap->pdev_dev, 2404 "FW image size differs from size in FW header\n"); 2405 return -EINVAL; 2406 } 2407 if (size > FW_MAX_SIZE) { 2408 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", 2409 FW_MAX_SIZE); 2410 return -EFBIG; 2411 } 2412 if (!t4_fw_matches_chip(adap, hdr)) 2413 return -EINVAL; 2414 2415 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 2416 csum += be32_to_cpu(p[i]); 2417 2418 if (csum != 0xffffffff) { 2419 dev_err(adap->pdev_dev, 2420 "corrupted firmware image, checksum %#x\n", csum); 2421 return -EINVAL; 2422 } 2423 2424 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 2425 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 2426 if (ret) 2427 goto out; 2428 2429 /* 2430 * We write the correct version at the end so the driver can see a bad 2431 * version if the FW write fails. Start by writing a copy of the 2432 * first page with a bad version. 2433 */ 2434 memcpy(first_page, fw_data, SF_PAGE_SIZE); 2435 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 2436 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page); 2437 if (ret) 2438 goto out; 2439 2440 addr = fw_img_start; 2441 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 2442 addr += SF_PAGE_SIZE; 2443 fw_data += SF_PAGE_SIZE; 2444 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); 2445 if (ret) 2446 goto out; 2447 } 2448 2449 ret = t4_write_flash(adap, 2450 fw_img_start + offsetof(struct fw_hdr, fw_ver), 2451 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver); 2452 out: 2453 if (ret) 2454 dev_err(adap->pdev_dev, "firmware download failed, error %d\n", 2455 ret); 2456 else 2457 ret = t4_get_fw_version(adap, &adap->params.fw_vers); 2458 return ret; 2459 } 2460 2461 /** 2462 * t4_phy_fw_ver - return current PHY firmware version 2463 * @adap: the adapter 2464 * @phy_fw_ver: return value buffer for PHY firmware version 2465 * 2466 * Returns the current version of external PHY firmware on the 2467 * adapter. 2468 */ 2469 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver) 2470 { 2471 u32 param, val; 2472 int ret; 2473 2474 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 2475 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) | 2476 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | 2477 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION)); 2478 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 2479 ¶m, &val); 2480 if (ret < 0) 2481 return ret; 2482 *phy_fw_ver = val; 2483 return 0; 2484 } 2485 2486 /** 2487 * t4_load_phy_fw - download port PHY firmware 2488 * @adap: the adapter 2489 * @win: the PCI-E Memory Window index to use for t4_memory_rw() 2490 * @win_lock: the lock to use to guard the memory copy 2491 * @phy_fw_version: function to check PHY firmware versions 2492 * @phy_fw_data: the PHY firmware image to write 2493 * @phy_fw_size: image size 2494 * 2495 * Transfer the specified PHY firmware to the adapter. If a non-NULL 2496 * @phy_fw_version is supplied, then it will be used to determine if 2497 * it's necessary to perform the transfer by comparing the version 2498 * of any existing adapter PHY firmware with that of the passed in 2499 * PHY firmware image. If @win_lock is non-NULL then it will be used 2500 * around the call to t4_memory_rw() which transfers the PHY firmware 2501 * to the adapter. 2502 * 2503 * A negative error number will be returned if an error occurs. If 2504 * version number support is available and there's no need to upgrade 2505 * the firmware, 0 will be returned. If firmware is successfully 2506 * transferred to the adapter, 1 will be retured. 2507 * 2508 * NOTE: some adapters only have local RAM to store the PHY firmware. As 2509 * a result, a RESET of the adapter would cause that RAM to lose its 2510 * contents. Thus, loading PHY firmware on such adapters must happen 2511 * after any FW_RESET_CMDs ... 2512 */ 2513 int t4_load_phy_fw(struct adapter *adap, 2514 int win, spinlock_t *win_lock, 2515 int (*phy_fw_version)(const u8 *, size_t), 2516 const u8 *phy_fw_data, size_t phy_fw_size) 2517 { 2518 unsigned long mtype = 0, maddr = 0; 2519 u32 param, val; 2520 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0; 2521 int ret; 2522 2523 /* If we have version number support, then check to see if the adapter 2524 * already has up-to-date PHY firmware loaded. 2525 */ 2526 if (phy_fw_version) { 2527 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size); 2528 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver); 2529 if (ret < 0) 2530 return ret; 2531 2532 if (cur_phy_fw_ver >= new_phy_fw_vers) { 2533 CH_WARN(adap, "PHY Firmware already up-to-date, " 2534 "version %#x\n", cur_phy_fw_ver); 2535 return 0; 2536 } 2537 } 2538 2539 /* Ask the firmware where it wants us to copy the PHY firmware image. 2540 * The size of the file requires a special version of the READ coommand 2541 * which will pass the file size via the values field in PARAMS_CMD and 2542 * retrieve the return value from firmware and place it in the same 2543 * buffer values 2544 */ 2545 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 2546 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) | 2547 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | 2548 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD)); 2549 val = phy_fw_size; 2550 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1, 2551 ¶m, &val, 1); 2552 if (ret < 0) 2553 return ret; 2554 mtype = val >> 8; 2555 maddr = (val & 0xff) << 16; 2556 2557 /* Copy the supplied PHY Firmware image to the adapter memory location 2558 * allocated by the adapter firmware. 2559 */ 2560 if (win_lock) 2561 spin_lock_bh(win_lock); 2562 ret = t4_memory_rw(adap, win, mtype, maddr, 2563 phy_fw_size, (__be32 *)phy_fw_data, 2564 T4_MEMORY_WRITE); 2565 if (win_lock) 2566 spin_unlock_bh(win_lock); 2567 if (ret) 2568 return ret; 2569 2570 /* Tell the firmware that the PHY firmware image has been written to 2571 * RAM and it can now start copying it over to the PHYs. The chip 2572 * firmware will RESET the affected PHYs as part of this operation 2573 * leaving them running the new PHY firmware image. 2574 */ 2575 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 2576 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) | 2577 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | 2578 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD)); 2579 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, 2580 ¶m, &val, 30000); 2581 2582 /* If we have version number support, then check to see that the new 2583 * firmware got loaded properly. 2584 */ 2585 if (phy_fw_version) { 2586 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver); 2587 if (ret < 0) 2588 return ret; 2589 2590 if (cur_phy_fw_ver != new_phy_fw_vers) { 2591 CH_WARN(adap, "PHY Firmware did not update: " 2592 "version on adapter %#x, " 2593 "version flashed %#x\n", 2594 cur_phy_fw_ver, new_phy_fw_vers); 2595 return -ENXIO; 2596 } 2597 } 2598 2599 return 1; 2600 } 2601 2602 /** 2603 * t4_fwcache - firmware cache operation 2604 * @adap: the adapter 2605 * @op : the operation (flush or flush and invalidate) 2606 */ 2607 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 2608 { 2609 struct fw_params_cmd c; 2610 2611 memset(&c, 0, sizeof(c)); 2612 c.op_to_vfn = 2613 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | 2614 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 2615 FW_PARAMS_CMD_PFN_V(adap->pf) | 2616 FW_PARAMS_CMD_VFN_V(0)); 2617 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 2618 c.param[0].mnem = 2619 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 2620 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE)); 2621 c.param[0].val = (__force __be32)op; 2622 2623 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 2624 } 2625 2626 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 2627 unsigned int *pif_req_wrptr, 2628 unsigned int *pif_rsp_wrptr) 2629 { 2630 int i, j; 2631 u32 cfg, val, req, rsp; 2632 2633 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); 2634 if (cfg & LADBGEN_F) 2635 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); 2636 2637 val = t4_read_reg(adap, CIM_DEBUGSTS_A); 2638 req = POLADBGWRPTR_G(val); 2639 rsp = PILADBGWRPTR_G(val); 2640 if (pif_req_wrptr) 2641 *pif_req_wrptr = req; 2642 if (pif_rsp_wrptr) 2643 *pif_rsp_wrptr = rsp; 2644 2645 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 2646 for (j = 0; j < 6; j++) { 2647 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) | 2648 PILADBGRDPTR_V(rsp)); 2649 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A); 2650 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A); 2651 req++; 2652 rsp++; 2653 } 2654 req = (req + 2) & POLADBGRDPTR_M; 2655 rsp = (rsp + 2) & PILADBGRDPTR_M; 2656 } 2657 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); 2658 } 2659 2660 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 2661 { 2662 u32 cfg; 2663 int i, j, idx; 2664 2665 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); 2666 if (cfg & LADBGEN_F) 2667 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); 2668 2669 for (i = 0; i < CIM_MALA_SIZE; i++) { 2670 for (j = 0; j < 5; j++) { 2671 idx = 8 * i + j; 2672 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) | 2673 PILADBGRDPTR_V(idx)); 2674 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A); 2675 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A); 2676 } 2677 } 2678 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); 2679 } 2680 2681 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 2682 { 2683 unsigned int i, j; 2684 2685 for (i = 0; i < 8; i++) { 2686 u32 *p = la_buf + i; 2687 2688 t4_write_reg(adap, ULP_RX_LA_CTL_A, i); 2689 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A); 2690 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j); 2691 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 2692 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A); 2693 } 2694 } 2695 2696 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ 2697 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \ 2698 FW_PORT_CAP_ANEG) 2699 2700 /** 2701 * t4_link_l1cfg - apply link configuration to MAC/PHY 2702 * @phy: the PHY to setup 2703 * @mac: the MAC to setup 2704 * @lc: the requested link configuration 2705 * 2706 * Set up a port's MAC and PHY according to a desired link configuration. 2707 * - If the PHY can auto-negotiate first decide what to advertise, then 2708 * enable/disable auto-negotiation as desired, and reset. 2709 * - If the PHY does not auto-negotiate just reset it. 2710 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 2711 * otherwise do it later based on the outcome of auto-negotiation. 2712 */ 2713 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 2714 struct link_config *lc) 2715 { 2716 struct fw_port_cmd c; 2717 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO); 2718 2719 lc->link_ok = 0; 2720 if (lc->requested_fc & PAUSE_RX) 2721 fc |= FW_PORT_CAP_FC_RX; 2722 if (lc->requested_fc & PAUSE_TX) 2723 fc |= FW_PORT_CAP_FC_TX; 2724 2725 memset(&c, 0, sizeof(c)); 2726 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | 2727 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 2728 FW_PORT_CMD_PORTID_V(port)); 2729 c.action_to_len16 = 2730 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) | 2731 FW_LEN16(c)); 2732 2733 if (!(lc->supported & FW_PORT_CAP_ANEG)) { 2734 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) | 2735 fc); 2736 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); 2737 } else if (lc->autoneg == AUTONEG_DISABLE) { 2738 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi); 2739 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); 2740 } else 2741 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi); 2742 2743 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 2744 } 2745 2746 /** 2747 * t4_restart_aneg - restart autonegotiation 2748 * @adap: the adapter 2749 * @mbox: mbox to use for the FW command 2750 * @port: the port id 2751 * 2752 * Restarts autonegotiation for the selected port. 2753 */ 2754 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 2755 { 2756 struct fw_port_cmd c; 2757 2758 memset(&c, 0, sizeof(c)); 2759 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | 2760 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 2761 FW_PORT_CMD_PORTID_V(port)); 2762 c.action_to_len16 = 2763 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) | 2764 FW_LEN16(c)); 2765 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 2766 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 2767 } 2768 2769 typedef void (*int_handler_t)(struct adapter *adap); 2770 2771 struct intr_info { 2772 unsigned int mask; /* bits to check in interrupt status */ 2773 const char *msg; /* message to print or NULL */ 2774 short stat_idx; /* stat counter to increment or -1 */ 2775 unsigned short fatal; /* whether the condition reported is fatal */ 2776 int_handler_t int_handler; /* platform-specific int handler */ 2777 }; 2778 2779 /** 2780 * t4_handle_intr_status - table driven interrupt handler 2781 * @adapter: the adapter that generated the interrupt 2782 * @reg: the interrupt status register to process 2783 * @acts: table of interrupt actions 2784 * 2785 * A table driven interrupt handler that applies a set of masks to an 2786 * interrupt status word and performs the corresponding actions if the 2787 * interrupts described by the mask have occurred. The actions include 2788 * optionally emitting a warning or alert message. The table is terminated 2789 * by an entry specifying mask 0. Returns the number of fatal interrupt 2790 * conditions. 2791 */ 2792 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, 2793 const struct intr_info *acts) 2794 { 2795 int fatal = 0; 2796 unsigned int mask = 0; 2797 unsigned int status = t4_read_reg(adapter, reg); 2798 2799 for ( ; acts->mask; ++acts) { 2800 if (!(status & acts->mask)) 2801 continue; 2802 if (acts->fatal) { 2803 fatal++; 2804 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, 2805 status & acts->mask); 2806 } else if (acts->msg && printk_ratelimit()) 2807 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, 2808 status & acts->mask); 2809 if (acts->int_handler) 2810 acts->int_handler(adapter); 2811 mask |= acts->mask; 2812 } 2813 status &= mask; 2814 if (status) /* clear processed interrupts */ 2815 t4_write_reg(adapter, reg, status); 2816 return fatal; 2817 } 2818 2819 /* 2820 * Interrupt handler for the PCIE module. 2821 */ 2822 static void pcie_intr_handler(struct adapter *adapter) 2823 { 2824 static const struct intr_info sysbus_intr_info[] = { 2825 { RNPP_F, "RXNP array parity error", -1, 1 }, 2826 { RPCP_F, "RXPC array parity error", -1, 1 }, 2827 { RCIP_F, "RXCIF array parity error", -1, 1 }, 2828 { RCCP_F, "Rx completions control array parity error", -1, 1 }, 2829 { RFTP_F, "RXFT array parity error", -1, 1 }, 2830 { 0 } 2831 }; 2832 static const struct intr_info pcie_port_intr_info[] = { 2833 { TPCP_F, "TXPC array parity error", -1, 1 }, 2834 { TNPP_F, "TXNP array parity error", -1, 1 }, 2835 { TFTP_F, "TXFT array parity error", -1, 1 }, 2836 { TCAP_F, "TXCA array parity error", -1, 1 }, 2837 { TCIP_F, "TXCIF array parity error", -1, 1 }, 2838 { RCAP_F, "RXCA array parity error", -1, 1 }, 2839 { OTDD_F, "outbound request TLP discarded", -1, 1 }, 2840 { RDPE_F, "Rx data parity error", -1, 1 }, 2841 { TDUE_F, "Tx uncorrectable data error", -1, 1 }, 2842 { 0 } 2843 }; 2844 static const struct intr_info pcie_intr_info[] = { 2845 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 }, 2846 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 }, 2847 { MSIDATAPERR_F, "MSI data parity error", -1, 1 }, 2848 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, 2849 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, 2850 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, 2851 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, 2852 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 }, 2853 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 }, 2854 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, 2855 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 }, 2856 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, 2857 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, 2858 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 }, 2859 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, 2860 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, 2861 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 }, 2862 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, 2863 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, 2864 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, 2865 { FIDPERR_F, "PCI FID parity error", -1, 1 }, 2866 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 }, 2867 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 }, 2868 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, 2869 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 }, 2870 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 }, 2871 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 }, 2872 { PCIESINT_F, "PCI core secondary fault", -1, 1 }, 2873 { PCIEPINT_F, "PCI core primary fault", -1, 1 }, 2874 { UNXSPLCPLERR_F, "PCI unexpected split completion error", 2875 -1, 0 }, 2876 { 0 } 2877 }; 2878 2879 static struct intr_info t5_pcie_intr_info[] = { 2880 { MSTGRPPERR_F, "Master Response Read Queue parity error", 2881 -1, 1 }, 2882 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, 2883 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 }, 2884 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, 2885 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, 2886 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, 2887 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, 2888 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error", 2889 -1, 1 }, 2890 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error", 2891 -1, 1 }, 2892 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, 2893 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 }, 2894 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, 2895 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, 2896 { DREQWRPERR_F, "PCI DMA channel write request parity error", 2897 -1, 1 }, 2898 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, 2899 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, 2900 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 }, 2901 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, 2902 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, 2903 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, 2904 { FIDPERR_F, "PCI FID parity error", -1, 1 }, 2905 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 }, 2906 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 }, 2907 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, 2908 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error", 2909 -1, 1 }, 2910 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error", 2911 -1, 1 }, 2912 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 }, 2913 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 }, 2914 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 2915 { READRSPERR_F, "Outbound read error", -1, 0 }, 2916 { 0 } 2917 }; 2918 2919 int fat; 2920 2921 if (is_t4(adapter->params.chip)) 2922 fat = t4_handle_intr_status(adapter, 2923 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A, 2924 sysbus_intr_info) + 2925 t4_handle_intr_status(adapter, 2926 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A, 2927 pcie_port_intr_info) + 2928 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A, 2929 pcie_intr_info); 2930 else 2931 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A, 2932 t5_pcie_intr_info); 2933 2934 if (fat) 2935 t4_fatal_err(adapter); 2936 } 2937 2938 /* 2939 * TP interrupt handler. 2940 */ 2941 static void tp_intr_handler(struct adapter *adapter) 2942 { 2943 static const struct intr_info tp_intr_info[] = { 2944 { 0x3fffffff, "TP parity error", -1, 1 }, 2945 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 }, 2946 { 0 } 2947 }; 2948 2949 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info)) 2950 t4_fatal_err(adapter); 2951 } 2952 2953 /* 2954 * SGE interrupt handler. 2955 */ 2956 static void sge_intr_handler(struct adapter *adapter) 2957 { 2958 u64 v; 2959 u32 err; 2960 2961 static const struct intr_info sge_intr_info[] = { 2962 { ERR_CPL_EXCEED_IQE_SIZE_F, 2963 "SGE received CPL exceeding IQE size", -1, 1 }, 2964 { ERR_INVALID_CIDX_INC_F, 2965 "SGE GTS CIDX increment too large", -1, 0 }, 2966 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 }, 2967 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full }, 2968 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F, 2969 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 2970 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1, 2971 0 }, 2972 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1, 2973 0 }, 2974 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1, 2975 0 }, 2976 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1, 2977 0 }, 2978 { ERR_ING_CTXT_PRIO_F, 2979 "SGE too many priority ingress contexts", -1, 0 }, 2980 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 }, 2981 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 }, 2982 { 0 } 2983 }; 2984 2985 static struct intr_info t4t5_sge_intr_info[] = { 2986 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped }, 2987 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full }, 2988 { ERR_EGR_CTXT_PRIO_F, 2989 "SGE too many priority egress contexts", -1, 0 }, 2990 { 0 } 2991 }; 2992 2993 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) | 2994 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32); 2995 if (v) { 2996 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n", 2997 (unsigned long long)v); 2998 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v); 2999 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32); 3000 } 3001 3002 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info); 3003 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) 3004 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, 3005 t4t5_sge_intr_info); 3006 3007 err = t4_read_reg(adapter, SGE_ERROR_STATS_A); 3008 if (err & ERROR_QID_VALID_F) { 3009 dev_err(adapter->pdev_dev, "SGE error for queue %u\n", 3010 ERROR_QID_G(err)); 3011 if (err & UNCAPTURED_ERROR_F) 3012 dev_err(adapter->pdev_dev, 3013 "SGE UNCAPTURED_ERROR set (clearing)\n"); 3014 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F | 3015 UNCAPTURED_ERROR_F); 3016 } 3017 3018 if (v != 0) 3019 t4_fatal_err(adapter); 3020 } 3021 3022 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\ 3023 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F) 3024 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\ 3025 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F) 3026 3027 /* 3028 * CIM interrupt handler. 3029 */ 3030 static void cim_intr_handler(struct adapter *adapter) 3031 { 3032 static const struct intr_info cim_intr_info[] = { 3033 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 }, 3034 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, 3035 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, 3036 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 }, 3037 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 }, 3038 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 }, 3039 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 }, 3040 { 0 } 3041 }; 3042 static const struct intr_info cim_upintr_info[] = { 3043 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 }, 3044 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 }, 3045 { ILLWRINT_F, "CIM illegal write", -1, 1 }, 3046 { ILLRDINT_F, "CIM illegal read", -1, 1 }, 3047 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 }, 3048 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 }, 3049 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 }, 3050 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 }, 3051 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 }, 3052 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 }, 3053 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 }, 3054 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 }, 3055 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 }, 3056 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 }, 3057 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 }, 3058 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 }, 3059 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 }, 3060 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 }, 3061 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 }, 3062 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 }, 3063 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 }, 3064 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 }, 3065 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 }, 3066 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 }, 3067 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 }, 3068 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 }, 3069 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 }, 3070 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 }, 3071 { 0 } 3072 }; 3073 3074 int fat; 3075 3076 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F) 3077 t4_report_fw_error(adapter); 3078 3079 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A, 3080 cim_intr_info) + 3081 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A, 3082 cim_upintr_info); 3083 if (fat) 3084 t4_fatal_err(adapter); 3085 } 3086 3087 /* 3088 * ULP RX interrupt handler. 3089 */ 3090 static void ulprx_intr_handler(struct adapter *adapter) 3091 { 3092 static const struct intr_info ulprx_intr_info[] = { 3093 { 0x1800000, "ULPRX context error", -1, 1 }, 3094 { 0x7fffff, "ULPRX parity error", -1, 1 }, 3095 { 0 } 3096 }; 3097 3098 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info)) 3099 t4_fatal_err(adapter); 3100 } 3101 3102 /* 3103 * ULP TX interrupt handler. 3104 */ 3105 static void ulptx_intr_handler(struct adapter *adapter) 3106 { 3107 static const struct intr_info ulptx_intr_info[] = { 3108 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1, 3109 0 }, 3110 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1, 3111 0 }, 3112 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1, 3113 0 }, 3114 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1, 3115 0 }, 3116 { 0xfffffff, "ULPTX parity error", -1, 1 }, 3117 { 0 } 3118 }; 3119 3120 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info)) 3121 t4_fatal_err(adapter); 3122 } 3123 3124 /* 3125 * PM TX interrupt handler. 3126 */ 3127 static void pmtx_intr_handler(struct adapter *adapter) 3128 { 3129 static const struct intr_info pmtx_intr_info[] = { 3130 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 }, 3131 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 }, 3132 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 }, 3133 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 }, 3134 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 }, 3135 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 }, 3136 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", 3137 -1, 1 }, 3138 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 }, 3139 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1}, 3140 { 0 } 3141 }; 3142 3143 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info)) 3144 t4_fatal_err(adapter); 3145 } 3146 3147 /* 3148 * PM RX interrupt handler. 3149 */ 3150 static void pmrx_intr_handler(struct adapter *adapter) 3151 { 3152 static const struct intr_info pmrx_intr_info[] = { 3153 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 }, 3154 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 }, 3155 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 }, 3156 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", 3157 -1, 1 }, 3158 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 }, 3159 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1}, 3160 { 0 } 3161 }; 3162 3163 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info)) 3164 t4_fatal_err(adapter); 3165 } 3166 3167 /* 3168 * CPL switch interrupt handler. 3169 */ 3170 static void cplsw_intr_handler(struct adapter *adapter) 3171 { 3172 static const struct intr_info cplsw_intr_info[] = { 3173 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 }, 3174 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 }, 3175 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 }, 3176 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 }, 3177 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 }, 3178 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 }, 3179 { 0 } 3180 }; 3181 3182 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info)) 3183 t4_fatal_err(adapter); 3184 } 3185 3186 /* 3187 * LE interrupt handler. 3188 */ 3189 static void le_intr_handler(struct adapter *adap) 3190 { 3191 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip); 3192 static const struct intr_info le_intr_info[] = { 3193 { LIPMISS_F, "LE LIP miss", -1, 0 }, 3194 { LIP0_F, "LE 0 LIP error", -1, 0 }, 3195 { PARITYERR_F, "LE parity error", -1, 1 }, 3196 { UNKNOWNCMD_F, "LE unknown command", -1, 1 }, 3197 { REQQPARERR_F, "LE request queue parity error", -1, 1 }, 3198 { 0 } 3199 }; 3200 3201 static struct intr_info t6_le_intr_info[] = { 3202 { T6_LIPMISS_F, "LE LIP miss", -1, 0 }, 3203 { T6_LIP0_F, "LE 0 LIP error", -1, 0 }, 3204 { TCAMINTPERR_F, "LE parity error", -1, 1 }, 3205 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 }, 3206 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 }, 3207 { 0 } 3208 }; 3209 3210 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, 3211 (chip <= CHELSIO_T5) ? 3212 le_intr_info : t6_le_intr_info)) 3213 t4_fatal_err(adap); 3214 } 3215 3216 /* 3217 * MPS interrupt handler. 3218 */ 3219 static void mps_intr_handler(struct adapter *adapter) 3220 { 3221 static const struct intr_info mps_rx_intr_info[] = { 3222 { 0xffffff, "MPS Rx parity error", -1, 1 }, 3223 { 0 } 3224 }; 3225 static const struct intr_info mps_tx_intr_info[] = { 3226 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 }, 3227 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 3228 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error", 3229 -1, 1 }, 3230 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error", 3231 -1, 1 }, 3232 { BUBBLE_F, "MPS Tx underflow", -1, 1 }, 3233 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 }, 3234 { FRMERR_F, "MPS Tx framing error", -1, 1 }, 3235 { 0 } 3236 }; 3237 static const struct intr_info mps_trc_intr_info[] = { 3238 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 }, 3239 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error", 3240 -1, 1 }, 3241 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 }, 3242 { 0 } 3243 }; 3244 static const struct intr_info mps_stat_sram_intr_info[] = { 3245 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, 3246 { 0 } 3247 }; 3248 static const struct intr_info mps_stat_tx_intr_info[] = { 3249 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, 3250 { 0 } 3251 }; 3252 static const struct intr_info mps_stat_rx_intr_info[] = { 3253 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, 3254 { 0 } 3255 }; 3256 static const struct intr_info mps_cls_intr_info[] = { 3257 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 }, 3258 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 }, 3259 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 }, 3260 { 0 } 3261 }; 3262 3263 int fat; 3264 3265 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A, 3266 mps_rx_intr_info) + 3267 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A, 3268 mps_tx_intr_info) + 3269 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A, 3270 mps_trc_intr_info) + 3271 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A, 3272 mps_stat_sram_intr_info) + 3273 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A, 3274 mps_stat_tx_intr_info) + 3275 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A, 3276 mps_stat_rx_intr_info) + 3277 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A, 3278 mps_cls_intr_info); 3279 3280 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0); 3281 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */ 3282 if (fat) 3283 t4_fatal_err(adapter); 3284 } 3285 3286 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \ 3287 ECC_UE_INT_CAUSE_F) 3288 3289 /* 3290 * EDC/MC interrupt handler. 3291 */ 3292 static void mem_intr_handler(struct adapter *adapter, int idx) 3293 { 3294 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" }; 3295 3296 unsigned int addr, cnt_addr, v; 3297 3298 if (idx <= MEM_EDC1) { 3299 addr = EDC_REG(EDC_INT_CAUSE_A, idx); 3300 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx); 3301 } else if (idx == MEM_MC) { 3302 if (is_t4(adapter->params.chip)) { 3303 addr = MC_INT_CAUSE_A; 3304 cnt_addr = MC_ECC_STATUS_A; 3305 } else { 3306 addr = MC_P_INT_CAUSE_A; 3307 cnt_addr = MC_P_ECC_STATUS_A; 3308 } 3309 } else { 3310 addr = MC_REG(MC_P_INT_CAUSE_A, 1); 3311 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1); 3312 } 3313 3314 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; 3315 if (v & PERR_INT_CAUSE_F) 3316 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n", 3317 name[idx]); 3318 if (v & ECC_CE_INT_CAUSE_F) { 3319 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr)); 3320 3321 t4_edc_err_read(adapter, idx); 3322 3323 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M)); 3324 if (printk_ratelimit()) 3325 dev_warn(adapter->pdev_dev, 3326 "%u %s correctable ECC data error%s\n", 3327 cnt, name[idx], cnt > 1 ? "s" : ""); 3328 } 3329 if (v & ECC_UE_INT_CAUSE_F) 3330 dev_alert(adapter->pdev_dev, 3331 "%s uncorrectable ECC data error\n", name[idx]); 3332 3333 t4_write_reg(adapter, addr, v); 3334 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F)) 3335 t4_fatal_err(adapter); 3336 } 3337 3338 /* 3339 * MA interrupt handler. 3340 */ 3341 static void ma_intr_handler(struct adapter *adap) 3342 { 3343 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A); 3344 3345 if (status & MEM_PERR_INT_CAUSE_F) { 3346 dev_alert(adap->pdev_dev, 3347 "MA parity error, parity status %#x\n", 3348 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A)); 3349 if (is_t5(adap->params.chip)) 3350 dev_alert(adap->pdev_dev, 3351 "MA parity error, parity status %#x\n", 3352 t4_read_reg(adap, 3353 MA_PARITY_ERROR_STATUS2_A)); 3354 } 3355 if (status & MEM_WRAP_INT_CAUSE_F) { 3356 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A); 3357 dev_alert(adap->pdev_dev, "MA address wrap-around error by " 3358 "client %u to address %#x\n", 3359 MEM_WRAP_CLIENT_NUM_G(v), 3360 MEM_WRAP_ADDRESS_G(v) << 4); 3361 } 3362 t4_write_reg(adap, MA_INT_CAUSE_A, status); 3363 t4_fatal_err(adap); 3364 } 3365 3366 /* 3367 * SMB interrupt handler. 3368 */ 3369 static void smb_intr_handler(struct adapter *adap) 3370 { 3371 static const struct intr_info smb_intr_info[] = { 3372 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 }, 3373 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 }, 3374 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 }, 3375 { 0 } 3376 }; 3377 3378 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info)) 3379 t4_fatal_err(adap); 3380 } 3381 3382 /* 3383 * NC-SI interrupt handler. 3384 */ 3385 static void ncsi_intr_handler(struct adapter *adap) 3386 { 3387 static const struct intr_info ncsi_intr_info[] = { 3388 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 }, 3389 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 }, 3390 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 }, 3391 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 }, 3392 { 0 } 3393 }; 3394 3395 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info)) 3396 t4_fatal_err(adap); 3397 } 3398 3399 /* 3400 * XGMAC interrupt handler. 3401 */ 3402 static void xgmac_intr_handler(struct adapter *adap, int port) 3403 { 3404 u32 v, int_cause_reg; 3405 3406 if (is_t4(adap->params.chip)) 3407 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A); 3408 else 3409 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A); 3410 3411 v = t4_read_reg(adap, int_cause_reg); 3412 3413 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F; 3414 if (!v) 3415 return; 3416 3417 if (v & TXFIFO_PRTY_ERR_F) 3418 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", 3419 port); 3420 if (v & RXFIFO_PRTY_ERR_F) 3421 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", 3422 port); 3423 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v); 3424 t4_fatal_err(adap); 3425 } 3426 3427 /* 3428 * PL interrupt handler. 3429 */ 3430 static void pl_intr_handler(struct adapter *adap) 3431 { 3432 static const struct intr_info pl_intr_info[] = { 3433 { FATALPERR_F, "T4 fatal parity error", -1, 1 }, 3434 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 }, 3435 { 0 } 3436 }; 3437 3438 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info)) 3439 t4_fatal_err(adap); 3440 } 3441 3442 #define PF_INTR_MASK (PFSW_F) 3443 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \ 3444 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \ 3445 CPL_SWITCH_F | SGE_F | ULP_TX_F) 3446 3447 /** 3448 * t4_slow_intr_handler - control path interrupt handler 3449 * @adapter: the adapter 3450 * 3451 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 3452 * The designation 'slow' is because it involves register reads, while 3453 * data interrupts typically don't involve any MMIOs. 3454 */ 3455 int t4_slow_intr_handler(struct adapter *adapter) 3456 { 3457 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A); 3458 3459 if (!(cause & GLBL_INTR_MASK)) 3460 return 0; 3461 if (cause & CIM_F) 3462 cim_intr_handler(adapter); 3463 if (cause & MPS_F) 3464 mps_intr_handler(adapter); 3465 if (cause & NCSI_F) 3466 ncsi_intr_handler(adapter); 3467 if (cause & PL_F) 3468 pl_intr_handler(adapter); 3469 if (cause & SMB_F) 3470 smb_intr_handler(adapter); 3471 if (cause & XGMAC0_F) 3472 xgmac_intr_handler(adapter, 0); 3473 if (cause & XGMAC1_F) 3474 xgmac_intr_handler(adapter, 1); 3475 if (cause & XGMAC_KR0_F) 3476 xgmac_intr_handler(adapter, 2); 3477 if (cause & XGMAC_KR1_F) 3478 xgmac_intr_handler(adapter, 3); 3479 if (cause & PCIE_F) 3480 pcie_intr_handler(adapter); 3481 if (cause & MC_F) 3482 mem_intr_handler(adapter, MEM_MC); 3483 if (is_t5(adapter->params.chip) && (cause & MC1_F)) 3484 mem_intr_handler(adapter, MEM_MC1); 3485 if (cause & EDC0_F) 3486 mem_intr_handler(adapter, MEM_EDC0); 3487 if (cause & EDC1_F) 3488 mem_intr_handler(adapter, MEM_EDC1); 3489 if (cause & LE_F) 3490 le_intr_handler(adapter); 3491 if (cause & TP_F) 3492 tp_intr_handler(adapter); 3493 if (cause & MA_F) 3494 ma_intr_handler(adapter); 3495 if (cause & PM_TX_F) 3496 pmtx_intr_handler(adapter); 3497 if (cause & PM_RX_F) 3498 pmrx_intr_handler(adapter); 3499 if (cause & ULP_RX_F) 3500 ulprx_intr_handler(adapter); 3501 if (cause & CPL_SWITCH_F) 3502 cplsw_intr_handler(adapter); 3503 if (cause & SGE_F) 3504 sge_intr_handler(adapter); 3505 if (cause & ULP_TX_F) 3506 ulptx_intr_handler(adapter); 3507 3508 /* Clear the interrupts just processed for which we are the master. */ 3509 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK); 3510 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */ 3511 return 1; 3512 } 3513 3514 /** 3515 * t4_intr_enable - enable interrupts 3516 * @adapter: the adapter whose interrupts should be enabled 3517 * 3518 * Enable PF-specific interrupts for the calling function and the top-level 3519 * interrupt concentrator for global interrupts. Interrupts are already 3520 * enabled at each module, here we just enable the roots of the interrupt 3521 * hierarchies. 3522 * 3523 * Note: this function should be called only when the driver manages 3524 * non PF-specific interrupts from the various HW modules. Only one PCI 3525 * function at a time should be doing this. 3526 */ 3527 void t4_intr_enable(struct adapter *adapter) 3528 { 3529 u32 val = 0; 3530 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A); 3531 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? 3532 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 3533 3534 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) 3535 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F; 3536 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F | 3537 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F | 3538 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F | 3539 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F | 3540 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F | 3541 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F | 3542 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val); 3543 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK); 3544 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf); 3545 } 3546 3547 /** 3548 * t4_intr_disable - disable interrupts 3549 * @adapter: the adapter whose interrupts should be disabled 3550 * 3551 * Disable interrupts. We only disable the top-level interrupt 3552 * concentrators. The caller must be a PCI function managing global 3553 * interrupts. 3554 */ 3555 void t4_intr_disable(struct adapter *adapter) 3556 { 3557 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A); 3558 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? 3559 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 3560 3561 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0); 3562 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0); 3563 } 3564 3565 /** 3566 * hash_mac_addr - return the hash value of a MAC address 3567 * @addr: the 48-bit Ethernet MAC address 3568 * 3569 * Hashes a MAC address according to the hash function used by HW inexact 3570 * (hash) address matching. 3571 */ 3572 static int hash_mac_addr(const u8 *addr) 3573 { 3574 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 3575 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 3576 a ^= b; 3577 a ^= (a >> 12); 3578 a ^= (a >> 6); 3579 return a & 0x3f; 3580 } 3581 3582 /** 3583 * t4_config_rss_range - configure a portion of the RSS mapping table 3584 * @adapter: the adapter 3585 * @mbox: mbox to use for the FW command 3586 * @viid: virtual interface whose RSS subtable is to be written 3587 * @start: start entry in the table to write 3588 * @n: how many table entries to write 3589 * @rspq: values for the response queue lookup table 3590 * @nrspq: number of values in @rspq 3591 * 3592 * Programs the selected part of the VI's RSS mapping table with the 3593 * provided values. If @nrspq < @n the supplied values are used repeatedly 3594 * until the full table range is populated. 3595 * 3596 * The caller must ensure the values in @rspq are in the range allowed for 3597 * @viid. 3598 */ 3599 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 3600 int start, int n, const u16 *rspq, unsigned int nrspq) 3601 { 3602 int ret; 3603 const u16 *rsp = rspq; 3604 const u16 *rsp_end = rspq + nrspq; 3605 struct fw_rss_ind_tbl_cmd cmd; 3606 3607 memset(&cmd, 0, sizeof(cmd)); 3608 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) | 3609 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 3610 FW_RSS_IND_TBL_CMD_VIID_V(viid)); 3611 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 3612 3613 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */ 3614 while (n > 0) { 3615 int nq = min(n, 32); 3616 __be32 *qp = &cmd.iq0_to_iq2; 3617 3618 cmd.niqid = cpu_to_be16(nq); 3619 cmd.startidx = cpu_to_be16(start); 3620 3621 start += nq; 3622 n -= nq; 3623 3624 while (nq > 0) { 3625 unsigned int v; 3626 3627 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp); 3628 if (++rsp >= rsp_end) 3629 rsp = rspq; 3630 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp); 3631 if (++rsp >= rsp_end) 3632 rsp = rspq; 3633 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp); 3634 if (++rsp >= rsp_end) 3635 rsp = rspq; 3636 3637 *qp++ = cpu_to_be32(v); 3638 nq -= 3; 3639 } 3640 3641 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 3642 if (ret) 3643 return ret; 3644 } 3645 return 0; 3646 } 3647 3648 /** 3649 * t4_config_glbl_rss - configure the global RSS mode 3650 * @adapter: the adapter 3651 * @mbox: mbox to use for the FW command 3652 * @mode: global RSS mode 3653 * @flags: mode-specific flags 3654 * 3655 * Sets the global RSS mode. 3656 */ 3657 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 3658 unsigned int flags) 3659 { 3660 struct fw_rss_glb_config_cmd c; 3661 3662 memset(&c, 0, sizeof(c)); 3663 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) | 3664 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3665 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3666 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 3667 c.u.manual.mode_pkd = 3668 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode)); 3669 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 3670 c.u.basicvirtual.mode_pkd = 3671 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode)); 3672 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 3673 } else 3674 return -EINVAL; 3675 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 3676 } 3677 3678 /** 3679 * t4_config_vi_rss - configure per VI RSS settings 3680 * @adapter: the adapter 3681 * @mbox: mbox to use for the FW command 3682 * @viid: the VI id 3683 * @flags: RSS flags 3684 * @defq: id of the default RSS queue for the VI. 3685 * 3686 * Configures VI-specific RSS properties. 3687 */ 3688 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 3689 unsigned int flags, unsigned int defq) 3690 { 3691 struct fw_rss_vi_config_cmd c; 3692 3693 memset(&c, 0, sizeof(c)); 3694 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) | 3695 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 3696 FW_RSS_VI_CONFIG_CMD_VIID_V(viid)); 3697 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3698 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 3699 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq)); 3700 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 3701 } 3702 3703 /* Read an RSS table row */ 3704 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 3705 { 3706 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row); 3707 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1, 3708 5, 0, val); 3709 } 3710 3711 /** 3712 * t4_read_rss - read the contents of the RSS mapping table 3713 * @adapter: the adapter 3714 * @map: holds the contents of the RSS mapping table 3715 * 3716 * Reads the contents of the RSS hash->queue mapping table. 3717 */ 3718 int t4_read_rss(struct adapter *adapter, u16 *map) 3719 { 3720 u32 val; 3721 int i, ret; 3722 3723 for (i = 0; i < RSS_NENTRIES / 2; ++i) { 3724 ret = rd_rss_row(adapter, i, &val); 3725 if (ret) 3726 return ret; 3727 *map++ = LKPTBLQUEUE0_G(val); 3728 *map++ = LKPTBLQUEUE1_G(val); 3729 } 3730 return 0; 3731 } 3732 3733 static unsigned int t4_use_ldst(struct adapter *adap) 3734 { 3735 return (adap->flags & FW_OK) || !adap->use_bd; 3736 } 3737 3738 /** 3739 * t4_fw_tp_pio_rw - Access TP PIO through LDST 3740 * @adap: the adapter 3741 * @vals: where the indirect register values are stored/written 3742 * @nregs: how many indirect registers to read/write 3743 * @start_idx: index of first indirect register to read/write 3744 * @rw: Read (1) or Write (0) 3745 * 3746 * Access TP PIO registers through LDST 3747 */ 3748 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, 3749 unsigned int start_index, unsigned int rw) 3750 { 3751 int ret, i; 3752 int cmd = FW_LDST_ADDRSPC_TP_PIO; 3753 struct fw_ldst_cmd c; 3754 3755 for (i = 0 ; i < nregs; i++) { 3756 memset(&c, 0, sizeof(c)); 3757 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 3758 FW_CMD_REQUEST_F | 3759 (rw ? FW_CMD_READ_F : 3760 FW_CMD_WRITE_F) | 3761 FW_LDST_CMD_ADDRSPACE_V(cmd)); 3762 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 3763 3764 c.u.addrval.addr = cpu_to_be32(start_index + i); 3765 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 3766 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); 3767 if (!ret && rw) 3768 vals[i] = be32_to_cpu(c.u.addrval.val); 3769 } 3770 } 3771 3772 /** 3773 * t4_read_rss_key - read the global RSS key 3774 * @adap: the adapter 3775 * @key: 10-entry array holding the 320-bit RSS key 3776 * 3777 * Reads the global 320-bit RSS key. 3778 */ 3779 void t4_read_rss_key(struct adapter *adap, u32 *key) 3780 { 3781 if (t4_use_ldst(adap)) 3782 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1); 3783 else 3784 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, 3785 TP_RSS_SECRET_KEY0_A); 3786 } 3787 3788 /** 3789 * t4_write_rss_key - program one of the RSS keys 3790 * @adap: the adapter 3791 * @key: 10-entry array holding the 320-bit RSS key 3792 * @idx: which RSS key to write 3793 * 3794 * Writes one of the RSS keys with the given 320-bit value. If @idx is 3795 * 0..15 the corresponding entry in the RSS key table is written, 3796 * otherwise the global RSS key is written. 3797 */ 3798 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx) 3799 { 3800 u8 rss_key_addr_cnt = 16; 3801 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A); 3802 3803 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 3804 * allows access to key addresses 16-63 by using KeyWrAddrX 3805 * as index[5:4](upper 2) into key table 3806 */ 3807 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) && 3808 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3)) 3809 rss_key_addr_cnt = 32; 3810 3811 if (t4_use_ldst(adap)) 3812 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0); 3813 else 3814 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, 3815 TP_RSS_SECRET_KEY0_A); 3816 3817 if (idx >= 0 && idx < rss_key_addr_cnt) { 3818 if (rss_key_addr_cnt > 16) 3819 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, 3820 KEYWRADDRX_V(idx >> 4) | 3821 T6_VFWRADDR_V(idx) | KEYWREN_F); 3822 else 3823 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, 3824 KEYWRADDR_V(idx) | KEYWREN_F); 3825 } 3826 } 3827 3828 /** 3829 * t4_read_rss_pf_config - read PF RSS Configuration Table 3830 * @adapter: the adapter 3831 * @index: the entry in the PF RSS table to read 3832 * @valp: where to store the returned value 3833 * 3834 * Reads the PF RSS Configuration Table at the specified index and returns 3835 * the value found there. 3836 */ 3837 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 3838 u32 *valp) 3839 { 3840 if (t4_use_ldst(adapter)) 3841 t4_fw_tp_pio_rw(adapter, valp, 1, 3842 TP_RSS_PF0_CONFIG_A + index, 1); 3843 else 3844 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3845 valp, 1, TP_RSS_PF0_CONFIG_A + index); 3846 } 3847 3848 /** 3849 * t4_read_rss_vf_config - read VF RSS Configuration Table 3850 * @adapter: the adapter 3851 * @index: the entry in the VF RSS table to read 3852 * @vfl: where to store the returned VFL 3853 * @vfh: where to store the returned VFH 3854 * 3855 * Reads the VF RSS Configuration Table at the specified index and returns 3856 * the (VFL, VFH) values found there. 3857 */ 3858 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 3859 u32 *vfl, u32 *vfh) 3860 { 3861 u32 vrt, mask, data; 3862 3863 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) { 3864 mask = VFWRADDR_V(VFWRADDR_M); 3865 data = VFWRADDR_V(index); 3866 } else { 3867 mask = T6_VFWRADDR_V(T6_VFWRADDR_M); 3868 data = T6_VFWRADDR_V(index); 3869 } 3870 3871 /* Request that the index'th VF Table values be read into VFL/VFH. 3872 */ 3873 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A); 3874 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask); 3875 vrt |= data | VFRDEN_F; 3876 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt); 3877 3878 /* Grab the VFL/VFH values ... 3879 */ 3880 if (t4_use_ldst(adapter)) { 3881 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1); 3882 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1); 3883 } else { 3884 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3885 vfl, 1, TP_RSS_VFL_CONFIG_A); 3886 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3887 vfh, 1, TP_RSS_VFH_CONFIG_A); 3888 } 3889 } 3890 3891 /** 3892 * t4_read_rss_pf_map - read PF RSS Map 3893 * @adapter: the adapter 3894 * 3895 * Reads the PF RSS Map register and returns its value. 3896 */ 3897 u32 t4_read_rss_pf_map(struct adapter *adapter) 3898 { 3899 u32 pfmap; 3900 3901 if (t4_use_ldst(adapter)) 3902 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1); 3903 else 3904 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3905 &pfmap, 1, TP_RSS_PF_MAP_A); 3906 return pfmap; 3907 } 3908 3909 /** 3910 * t4_read_rss_pf_mask - read PF RSS Mask 3911 * @adapter: the adapter 3912 * 3913 * Reads the PF RSS Mask register and returns its value. 3914 */ 3915 u32 t4_read_rss_pf_mask(struct adapter *adapter) 3916 { 3917 u32 pfmask; 3918 3919 if (t4_use_ldst(adapter)) 3920 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1); 3921 else 3922 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3923 &pfmask, 1, TP_RSS_PF_MSK_A); 3924 return pfmask; 3925 } 3926 3927 /** 3928 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 3929 * @adap: the adapter 3930 * @v4: holds the TCP/IP counter values 3931 * @v6: holds the TCP/IPv6 counter values 3932 * 3933 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 3934 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 3935 */ 3936 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 3937 struct tp_tcp_stats *v6) 3938 { 3939 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1]; 3940 3941 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A) 3942 #define STAT(x) val[STAT_IDX(x)] 3943 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 3944 3945 if (v4) { 3946 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 3947 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A); 3948 v4->tcp_out_rsts = STAT(OUT_RST); 3949 v4->tcp_in_segs = STAT64(IN_SEG); 3950 v4->tcp_out_segs = STAT64(OUT_SEG); 3951 v4->tcp_retrans_segs = STAT64(RXT_SEG); 3952 } 3953 if (v6) { 3954 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 3955 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A); 3956 v6->tcp_out_rsts = STAT(OUT_RST); 3957 v6->tcp_in_segs = STAT64(IN_SEG); 3958 v6->tcp_out_segs = STAT64(OUT_SEG); 3959 v6->tcp_retrans_segs = STAT64(RXT_SEG); 3960 } 3961 #undef STAT64 3962 #undef STAT 3963 #undef STAT_IDX 3964 } 3965 3966 /** 3967 * t4_tp_get_err_stats - read TP's error MIB counters 3968 * @adap: the adapter 3969 * @st: holds the counter values 3970 * 3971 * Returns the values of TP's error counters. 3972 */ 3973 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st) 3974 { 3975 int nchan = adap->params.arch.nchan; 3976 3977 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 3978 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A); 3979 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 3980 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A); 3981 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 3982 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A); 3983 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 3984 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A); 3985 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 3986 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A); 3987 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 3988 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A); 3989 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 3990 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A); 3991 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 3992 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A); 3993 3994 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, 3995 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A); 3996 } 3997 3998 /** 3999 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 4000 * @adap: the adapter 4001 * @st: holds the counter values 4002 * 4003 * Returns the values of TP's CPL counters. 4004 */ 4005 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st) 4006 { 4007 int nchan = adap->params.arch.nchan; 4008 4009 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req, 4010 nchan, TP_MIB_CPL_IN_REQ_0_A); 4011 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp, 4012 nchan, TP_MIB_CPL_OUT_RSP_0_A); 4013 4014 } 4015 4016 /** 4017 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 4018 * @adap: the adapter 4019 * @st: holds the counter values 4020 * 4021 * Returns the values of TP's RDMA counters. 4022 */ 4023 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st) 4024 { 4025 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt, 4026 2, TP_MIB_RQE_DFR_PKT_A); 4027 } 4028 4029 /** 4030 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 4031 * @adap: the adapter 4032 * @idx: the port index 4033 * @st: holds the counter values 4034 * 4035 * Returns the values of TP's FCoE counters for the selected port. 4036 */ 4037 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 4038 struct tp_fcoe_stats *st) 4039 { 4040 u32 val[2]; 4041 4042 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp, 4043 1, TP_MIB_FCOE_DDP_0_A + idx); 4044 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop, 4045 1, TP_MIB_FCOE_DROP_0_A + idx); 4046 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4047 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx); 4048 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 4049 } 4050 4051 /** 4052 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 4053 * @adap: the adapter 4054 * @st: holds the counter values 4055 * 4056 * Returns the values of TP's counters for non-TCP directly-placed packets. 4057 */ 4058 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st) 4059 { 4060 u32 val[4]; 4061 4062 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4, 4063 TP_MIB_USM_PKTS_A); 4064 st->frames = val[0]; 4065 st->drops = val[1]; 4066 st->octets = ((u64)val[2] << 32) | val[3]; 4067 } 4068 4069 /** 4070 * t4_read_mtu_tbl - returns the values in the HW path MTU table 4071 * @adap: the adapter 4072 * @mtus: where to store the MTU values 4073 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 4074 * 4075 * Reads the HW path MTU table. 4076 */ 4077 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 4078 { 4079 u32 v; 4080 int i; 4081 4082 for (i = 0; i < NMTUS; ++i) { 4083 t4_write_reg(adap, TP_MTU_TABLE_A, 4084 MTUINDEX_V(0xff) | MTUVALUE_V(i)); 4085 v = t4_read_reg(adap, TP_MTU_TABLE_A); 4086 mtus[i] = MTUVALUE_G(v); 4087 if (mtu_log) 4088 mtu_log[i] = MTUWIDTH_G(v); 4089 } 4090 } 4091 4092 /** 4093 * t4_read_cong_tbl - reads the congestion control table 4094 * @adap: the adapter 4095 * @incr: where to store the alpha values 4096 * 4097 * Reads the additive increments programmed into the HW congestion 4098 * control table. 4099 */ 4100 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 4101 { 4102 unsigned int mtu, w; 4103 4104 for (mtu = 0; mtu < NMTUS; ++mtu) 4105 for (w = 0; w < NCCTRL_WIN; ++w) { 4106 t4_write_reg(adap, TP_CCTRL_TABLE_A, 4107 ROWINDEX_V(0xffff) | (mtu << 5) | w); 4108 incr[mtu][w] = (u16)t4_read_reg(adap, 4109 TP_CCTRL_TABLE_A) & 0x1fff; 4110 } 4111 } 4112 4113 /** 4114 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 4115 * @adap: the adapter 4116 * @addr: the indirect TP register address 4117 * @mask: specifies the field within the register to modify 4118 * @val: new value for the field 4119 * 4120 * Sets a field of an indirect TP register to the given value. 4121 */ 4122 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 4123 unsigned int mask, unsigned int val) 4124 { 4125 t4_write_reg(adap, TP_PIO_ADDR_A, addr); 4126 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask; 4127 t4_write_reg(adap, TP_PIO_DATA_A, val); 4128 } 4129 4130 /** 4131 * init_cong_ctrl - initialize congestion control parameters 4132 * @a: the alpha values for congestion control 4133 * @b: the beta values for congestion control 4134 * 4135 * Initialize the congestion control parameters. 4136 */ 4137 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 4138 { 4139 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 4140 a[9] = 2; 4141 a[10] = 3; 4142 a[11] = 4; 4143 a[12] = 5; 4144 a[13] = 6; 4145 a[14] = 7; 4146 a[15] = 8; 4147 a[16] = 9; 4148 a[17] = 10; 4149 a[18] = 14; 4150 a[19] = 17; 4151 a[20] = 21; 4152 a[21] = 25; 4153 a[22] = 30; 4154 a[23] = 35; 4155 a[24] = 45; 4156 a[25] = 60; 4157 a[26] = 80; 4158 a[27] = 100; 4159 a[28] = 200; 4160 a[29] = 300; 4161 a[30] = 400; 4162 a[31] = 500; 4163 4164 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 4165 b[9] = b[10] = 1; 4166 b[11] = b[12] = 2; 4167 b[13] = b[14] = b[15] = b[16] = 3; 4168 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 4169 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 4170 b[28] = b[29] = 6; 4171 b[30] = b[31] = 7; 4172 } 4173 4174 /* The minimum additive increment value for the congestion control table */ 4175 #define CC_MIN_INCR 2U 4176 4177 /** 4178 * t4_load_mtus - write the MTU and congestion control HW tables 4179 * @adap: the adapter 4180 * @mtus: the values for the MTU table 4181 * @alpha: the values for the congestion control alpha parameter 4182 * @beta: the values for the congestion control beta parameter 4183 * 4184 * Write the HW MTU table with the supplied MTUs and the high-speed 4185 * congestion control table with the supplied alpha, beta, and MTUs. 4186 * We write the two tables together because the additive increments 4187 * depend on the MTUs. 4188 */ 4189 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 4190 const unsigned short *alpha, const unsigned short *beta) 4191 { 4192 static const unsigned int avg_pkts[NCCTRL_WIN] = { 4193 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 4194 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 4195 28672, 40960, 57344, 81920, 114688, 163840, 229376 4196 }; 4197 4198 unsigned int i, w; 4199 4200 for (i = 0; i < NMTUS; ++i) { 4201 unsigned int mtu = mtus[i]; 4202 unsigned int log2 = fls(mtu); 4203 4204 if (!(mtu & ((1 << log2) >> 2))) /* round */ 4205 log2--; 4206 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) | 4207 MTUWIDTH_V(log2) | MTUVALUE_V(mtu)); 4208 4209 for (w = 0; w < NCCTRL_WIN; ++w) { 4210 unsigned int inc; 4211 4212 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 4213 CC_MIN_INCR); 4214 4215 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) | 4216 (w << 16) | (beta[w] << 13) | inc); 4217 } 4218 } 4219 } 4220 4221 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core 4222 * clocks. The formula is 4223 * 4224 * bytes/s = bytes256 * 256 * ClkFreq / 4096 4225 * 4226 * which is equivalent to 4227 * 4228 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 4229 */ 4230 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 4231 { 4232 u64 v = bytes256 * adap->params.vpd.cclk; 4233 4234 return v * 62 + v / 2; 4235 } 4236 4237 /** 4238 * t4_get_chan_txrate - get the current per channel Tx rates 4239 * @adap: the adapter 4240 * @nic_rate: rates for NIC traffic 4241 * @ofld_rate: rates for offloaded traffic 4242 * 4243 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 4244 * for each channel. 4245 */ 4246 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 4247 { 4248 u32 v; 4249 4250 v = t4_read_reg(adap, TP_TX_TRATE_A); 4251 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v)); 4252 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v)); 4253 if (adap->params.arch.nchan == NCHAN) { 4254 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v)); 4255 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v)); 4256 } 4257 4258 v = t4_read_reg(adap, TP_TX_ORATE_A); 4259 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v)); 4260 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v)); 4261 if (adap->params.arch.nchan == NCHAN) { 4262 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v)); 4263 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v)); 4264 } 4265 } 4266 4267 /** 4268 * t4_pmtx_get_stats - returns the HW stats from PMTX 4269 * @adap: the adapter 4270 * @cnt: where to store the count statistics 4271 * @cycles: where to store the cycle statistics 4272 * 4273 * Returns performance statistics from PMTX. 4274 */ 4275 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 4276 { 4277 int i; 4278 u32 data[2]; 4279 4280 for (i = 0; i < PM_NSTATS; i++) { 4281 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1); 4282 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A); 4283 if (is_t4(adap->params.chip)) { 4284 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A); 4285 } else { 4286 t4_read_indirect(adap, PM_TX_DBG_CTRL_A, 4287 PM_TX_DBG_DATA_A, data, 2, 4288 PM_TX_DBG_STAT_MSB_A); 4289 cycles[i] = (((u64)data[0] << 32) | data[1]); 4290 } 4291 } 4292 } 4293 4294 /** 4295 * t4_pmrx_get_stats - returns the HW stats from PMRX 4296 * @adap: the adapter 4297 * @cnt: where to store the count statistics 4298 * @cycles: where to store the cycle statistics 4299 * 4300 * Returns performance statistics from PMRX. 4301 */ 4302 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 4303 { 4304 int i; 4305 u32 data[2]; 4306 4307 for (i = 0; i < PM_NSTATS; i++) { 4308 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1); 4309 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A); 4310 if (is_t4(adap->params.chip)) { 4311 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A); 4312 } else { 4313 t4_read_indirect(adap, PM_RX_DBG_CTRL_A, 4314 PM_RX_DBG_DATA_A, data, 2, 4315 PM_RX_DBG_STAT_MSB_A); 4316 cycles[i] = (((u64)data[0] << 32) | data[1]); 4317 } 4318 } 4319 } 4320 4321 /** 4322 * t4_get_mps_bg_map - return the buffer groups associated with a port 4323 * @adap: the adapter 4324 * @idx: the port index 4325 * 4326 * Returns a bitmap indicating which MPS buffer groups are associated 4327 * with the given port. Bit i is set if buffer group i is used by the 4328 * port. 4329 */ 4330 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 4331 { 4332 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A)); 4333 4334 if (n == 0) 4335 return idx == 0 ? 0xf : 0; 4336 if (n == 1) 4337 return idx < 2 ? (3 << (2 * idx)) : 0; 4338 return 1 << idx; 4339 } 4340 4341 /** 4342 * t4_get_port_type_description - return Port Type string description 4343 * @port_type: firmware Port Type enumeration 4344 */ 4345 const char *t4_get_port_type_description(enum fw_port_type port_type) 4346 { 4347 static const char *const port_type_description[] = { 4348 "R XFI", 4349 "R XAUI", 4350 "T SGMII", 4351 "T XFI", 4352 "T XAUI", 4353 "KX4", 4354 "CX4", 4355 "KX", 4356 "KR", 4357 "R SFP+", 4358 "KR/KX", 4359 "KR/KX/KX4", 4360 "R QSFP_10G", 4361 "R QSA", 4362 "R QSFP", 4363 "R BP40_BA", 4364 }; 4365 4366 if (port_type < ARRAY_SIZE(port_type_description)) 4367 return port_type_description[port_type]; 4368 return "UNKNOWN"; 4369 } 4370 4371 /** 4372 * t4_get_port_stats_offset - collect port stats relative to a previous 4373 * snapshot 4374 * @adap: The adapter 4375 * @idx: The port 4376 * @stats: Current stats to fill 4377 * @offset: Previous stats snapshot 4378 */ 4379 void t4_get_port_stats_offset(struct adapter *adap, int idx, 4380 struct port_stats *stats, 4381 struct port_stats *offset) 4382 { 4383 u64 *s, *o; 4384 int i; 4385 4386 t4_get_port_stats(adap, idx, stats); 4387 for (i = 0, s = (u64 *)stats, o = (u64 *)offset; 4388 i < (sizeof(struct port_stats) / sizeof(u64)); 4389 i++, s++, o++) 4390 *s -= *o; 4391 } 4392 4393 /** 4394 * t4_get_port_stats - collect port statistics 4395 * @adap: the adapter 4396 * @idx: the port index 4397 * @p: the stats structure to fill 4398 * 4399 * Collect statistics related to the given port from HW. 4400 */ 4401 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 4402 { 4403 u32 bgmap = t4_get_mps_bg_map(adap, idx); 4404 4405 #define GET_STAT(name) \ 4406 t4_read_reg64(adap, \ 4407 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ 4408 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L))) 4409 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) 4410 4411 p->tx_octets = GET_STAT(TX_PORT_BYTES); 4412 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 4413 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 4414 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 4415 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 4416 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 4417 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 4418 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 4419 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 4420 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 4421 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 4422 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 4423 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 4424 p->tx_drop = GET_STAT(TX_PORT_DROP); 4425 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 4426 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 4427 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 4428 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 4429 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 4430 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 4431 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 4432 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 4433 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 4434 4435 p->rx_octets = GET_STAT(RX_PORT_BYTES); 4436 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 4437 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 4438 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 4439 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 4440 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 4441 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 4442 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); 4443 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 4444 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 4445 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 4446 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 4447 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 4448 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 4449 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 4450 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 4451 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 4452 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 4453 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 4454 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 4455 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 4456 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 4457 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 4458 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 4459 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 4460 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 4461 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 4462 4463 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 4464 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 4465 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 4466 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 4467 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 4468 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 4469 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 4470 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 4471 4472 #undef GET_STAT 4473 #undef GET_STAT_COM 4474 } 4475 4476 /** 4477 * t4_get_lb_stats - collect loopback port statistics 4478 * @adap: the adapter 4479 * @idx: the loopback port index 4480 * @p: the stats structure to fill 4481 * 4482 * Return HW statistics for the given loopback port. 4483 */ 4484 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 4485 { 4486 u32 bgmap = t4_get_mps_bg_map(adap, idx); 4487 4488 #define GET_STAT(name) \ 4489 t4_read_reg64(adap, \ 4490 (is_t4(adap->params.chip) ? \ 4491 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \ 4492 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L))) 4493 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) 4494 4495 p->octets = GET_STAT(BYTES); 4496 p->frames = GET_STAT(FRAMES); 4497 p->bcast_frames = GET_STAT(BCAST); 4498 p->mcast_frames = GET_STAT(MCAST); 4499 p->ucast_frames = GET_STAT(UCAST); 4500 p->error_frames = GET_STAT(ERROR); 4501 4502 p->frames_64 = GET_STAT(64B); 4503 p->frames_65_127 = GET_STAT(65B_127B); 4504 p->frames_128_255 = GET_STAT(128B_255B); 4505 p->frames_256_511 = GET_STAT(256B_511B); 4506 p->frames_512_1023 = GET_STAT(512B_1023B); 4507 p->frames_1024_1518 = GET_STAT(1024B_1518B); 4508 p->frames_1519_max = GET_STAT(1519B_MAX); 4509 p->drop = GET_STAT(DROP_FRAMES); 4510 4511 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 4512 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 4513 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 4514 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 4515 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 4516 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 4517 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 4518 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 4519 4520 #undef GET_STAT 4521 #undef GET_STAT_COM 4522 } 4523 4524 /* t4_mk_filtdelwr - create a delete filter WR 4525 * @ftid: the filter ID 4526 * @wr: the filter work request to populate 4527 * @qid: ingress queue to receive the delete notification 4528 * 4529 * Creates a filter work request to delete the supplied filter. If @qid is 4530 * negative the delete notification is suppressed. 4531 */ 4532 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 4533 { 4534 memset(wr, 0, sizeof(*wr)); 4535 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR)); 4536 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16)); 4537 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) | 4538 FW_FILTER_WR_NOREPLY_V(qid < 0)); 4539 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F); 4540 if (qid >= 0) 4541 wr->rx_chan_rx_rpl_iq = 4542 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid)); 4543 } 4544 4545 #define INIT_CMD(var, cmd, rd_wr) do { \ 4546 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \ 4547 FW_CMD_REQUEST_F | \ 4548 FW_CMD_##rd_wr##_F); \ 4549 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 4550 } while (0) 4551 4552 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 4553 u32 addr, u32 val) 4554 { 4555 u32 ldst_addrspace; 4556 struct fw_ldst_cmd c; 4557 4558 memset(&c, 0, sizeof(c)); 4559 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE); 4560 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 4561 FW_CMD_REQUEST_F | 4562 FW_CMD_WRITE_F | 4563 ldst_addrspace); 4564 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4565 c.u.addrval.addr = cpu_to_be32(addr); 4566 c.u.addrval.val = cpu_to_be32(val); 4567 4568 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4569 } 4570 4571 /** 4572 * t4_mdio_rd - read a PHY register through MDIO 4573 * @adap: the adapter 4574 * @mbox: mailbox to use for the FW command 4575 * @phy_addr: the PHY address 4576 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 4577 * @reg: the register to read 4578 * @valp: where to store the value 4579 * 4580 * Issues a FW command through the given mailbox to read a PHY register. 4581 */ 4582 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 4583 unsigned int mmd, unsigned int reg, u16 *valp) 4584 { 4585 int ret; 4586 u32 ldst_addrspace; 4587 struct fw_ldst_cmd c; 4588 4589 memset(&c, 0, sizeof(c)); 4590 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO); 4591 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 4592 FW_CMD_REQUEST_F | FW_CMD_READ_F | 4593 ldst_addrspace); 4594 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4595 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) | 4596 FW_LDST_CMD_MMD_V(mmd)); 4597 c.u.mdio.raddr = cpu_to_be16(reg); 4598 4599 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4600 if (ret == 0) 4601 *valp = be16_to_cpu(c.u.mdio.rval); 4602 return ret; 4603 } 4604 4605 /** 4606 * t4_mdio_wr - write a PHY register through MDIO 4607 * @adap: the adapter 4608 * @mbox: mailbox to use for the FW command 4609 * @phy_addr: the PHY address 4610 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 4611 * @reg: the register to write 4612 * @valp: value to write 4613 * 4614 * Issues a FW command through the given mailbox to write a PHY register. 4615 */ 4616 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 4617 unsigned int mmd, unsigned int reg, u16 val) 4618 { 4619 u32 ldst_addrspace; 4620 struct fw_ldst_cmd c; 4621 4622 memset(&c, 0, sizeof(c)); 4623 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO); 4624 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 4625 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 4626 ldst_addrspace); 4627 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4628 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) | 4629 FW_LDST_CMD_MMD_V(mmd)); 4630 c.u.mdio.raddr = cpu_to_be16(reg); 4631 c.u.mdio.rval = cpu_to_be16(val); 4632 4633 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4634 } 4635 4636 /** 4637 * t4_sge_decode_idma_state - decode the idma state 4638 * @adap: the adapter 4639 * @state: the state idma is stuck in 4640 */ 4641 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 4642 { 4643 static const char * const t4_decode[] = { 4644 "IDMA_IDLE", 4645 "IDMA_PUSH_MORE_CPL_FIFO", 4646 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 4647 "Not used", 4648 "IDMA_PHYSADDR_SEND_PCIEHDR", 4649 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 4650 "IDMA_PHYSADDR_SEND_PAYLOAD", 4651 "IDMA_SEND_FIFO_TO_IMSG", 4652 "IDMA_FL_REQ_DATA_FL_PREP", 4653 "IDMA_FL_REQ_DATA_FL", 4654 "IDMA_FL_DROP", 4655 "IDMA_FL_H_REQ_HEADER_FL", 4656 "IDMA_FL_H_SEND_PCIEHDR", 4657 "IDMA_FL_H_PUSH_CPL_FIFO", 4658 "IDMA_FL_H_SEND_CPL", 4659 "IDMA_FL_H_SEND_IP_HDR_FIRST", 4660 "IDMA_FL_H_SEND_IP_HDR", 4661 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 4662 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 4663 "IDMA_FL_H_SEND_IP_HDR_PADDING", 4664 "IDMA_FL_D_SEND_PCIEHDR", 4665 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 4666 "IDMA_FL_D_REQ_NEXT_DATA_FL", 4667 "IDMA_FL_SEND_PCIEHDR", 4668 "IDMA_FL_PUSH_CPL_FIFO", 4669 "IDMA_FL_SEND_CPL", 4670 "IDMA_FL_SEND_PAYLOAD_FIRST", 4671 "IDMA_FL_SEND_PAYLOAD", 4672 "IDMA_FL_REQ_NEXT_DATA_FL", 4673 "IDMA_FL_SEND_NEXT_PCIEHDR", 4674 "IDMA_FL_SEND_PADDING", 4675 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 4676 "IDMA_FL_SEND_FIFO_TO_IMSG", 4677 "IDMA_FL_REQ_DATAFL_DONE", 4678 "IDMA_FL_REQ_HEADERFL_DONE", 4679 }; 4680 static const char * const t5_decode[] = { 4681 "IDMA_IDLE", 4682 "IDMA_ALMOST_IDLE", 4683 "IDMA_PUSH_MORE_CPL_FIFO", 4684 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 4685 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 4686 "IDMA_PHYSADDR_SEND_PCIEHDR", 4687 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 4688 "IDMA_PHYSADDR_SEND_PAYLOAD", 4689 "IDMA_SEND_FIFO_TO_IMSG", 4690 "IDMA_FL_REQ_DATA_FL", 4691 "IDMA_FL_DROP", 4692 "IDMA_FL_DROP_SEND_INC", 4693 "IDMA_FL_H_REQ_HEADER_FL", 4694 "IDMA_FL_H_SEND_PCIEHDR", 4695 "IDMA_FL_H_PUSH_CPL_FIFO", 4696 "IDMA_FL_H_SEND_CPL", 4697 "IDMA_FL_H_SEND_IP_HDR_FIRST", 4698 "IDMA_FL_H_SEND_IP_HDR", 4699 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 4700 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 4701 "IDMA_FL_H_SEND_IP_HDR_PADDING", 4702 "IDMA_FL_D_SEND_PCIEHDR", 4703 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 4704 "IDMA_FL_D_REQ_NEXT_DATA_FL", 4705 "IDMA_FL_SEND_PCIEHDR", 4706 "IDMA_FL_PUSH_CPL_FIFO", 4707 "IDMA_FL_SEND_CPL", 4708 "IDMA_FL_SEND_PAYLOAD_FIRST", 4709 "IDMA_FL_SEND_PAYLOAD", 4710 "IDMA_FL_REQ_NEXT_DATA_FL", 4711 "IDMA_FL_SEND_NEXT_PCIEHDR", 4712 "IDMA_FL_SEND_PADDING", 4713 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 4714 }; 4715 static const u32 sge_regs[] = { 4716 SGE_DEBUG_DATA_LOW_INDEX_2_A, 4717 SGE_DEBUG_DATA_LOW_INDEX_3_A, 4718 SGE_DEBUG_DATA_HIGH_INDEX_10_A, 4719 }; 4720 const char **sge_idma_decode; 4721 int sge_idma_decode_nstates; 4722 int i; 4723 4724 if (is_t4(adapter->params.chip)) { 4725 sge_idma_decode = (const char **)t4_decode; 4726 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 4727 } else { 4728 sge_idma_decode = (const char **)t5_decode; 4729 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 4730 } 4731 4732 if (state < sge_idma_decode_nstates) 4733 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 4734 else 4735 CH_WARN(adapter, "idma state %d unknown\n", state); 4736 4737 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 4738 CH_WARN(adapter, "SGE register %#x value %#x\n", 4739 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 4740 } 4741 4742 /** 4743 * t4_sge_ctxt_flush - flush the SGE context cache 4744 * @adap: the adapter 4745 * @mbox: mailbox to use for the FW command 4746 * 4747 * Issues a FW command through the given mailbox to flush the 4748 * SGE context cache. 4749 */ 4750 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) 4751 { 4752 int ret; 4753 u32 ldst_addrspace; 4754 struct fw_ldst_cmd c; 4755 4756 memset(&c, 0, sizeof(c)); 4757 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC); 4758 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) | 4759 FW_CMD_REQUEST_F | FW_CMD_READ_F | 4760 ldst_addrspace); 4761 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4762 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F); 4763 4764 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4765 return ret; 4766 } 4767 4768 /** 4769 * t4_fw_hello - establish communication with FW 4770 * @adap: the adapter 4771 * @mbox: mailbox to use for the FW command 4772 * @evt_mbox: mailbox to receive async FW events 4773 * @master: specifies the caller's willingness to be the device master 4774 * @state: returns the current device state (if non-NULL) 4775 * 4776 * Issues a command to establish communication with FW. Returns either 4777 * an error (negative integer) or the mailbox of the Master PF. 4778 */ 4779 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 4780 enum dev_master master, enum dev_state *state) 4781 { 4782 int ret; 4783 struct fw_hello_cmd c; 4784 u32 v; 4785 unsigned int master_mbox; 4786 int retries = FW_CMD_HELLO_RETRIES; 4787 4788 retry: 4789 memset(&c, 0, sizeof(c)); 4790 INIT_CMD(c, HELLO, WRITE); 4791 c.err_to_clearinit = cpu_to_be32( 4792 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) | 4793 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) | 4794 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ? 4795 mbox : FW_HELLO_CMD_MBMASTER_M) | 4796 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) | 4797 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) | 4798 FW_HELLO_CMD_CLEARINIT_F); 4799 4800 /* 4801 * Issue the HELLO command to the firmware. If it's not successful 4802 * but indicates that we got a "busy" or "timeout" condition, retry 4803 * the HELLO until we exhaust our retry limit. If we do exceed our 4804 * retry limit, check to see if the firmware left us any error 4805 * information and report that if so. 4806 */ 4807 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4808 if (ret < 0) { 4809 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 4810 goto retry; 4811 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F) 4812 t4_report_fw_error(adap); 4813 return ret; 4814 } 4815 4816 v = be32_to_cpu(c.err_to_clearinit); 4817 master_mbox = FW_HELLO_CMD_MBMASTER_G(v); 4818 if (state) { 4819 if (v & FW_HELLO_CMD_ERR_F) 4820 *state = DEV_STATE_ERR; 4821 else if (v & FW_HELLO_CMD_INIT_F) 4822 *state = DEV_STATE_INIT; 4823 else 4824 *state = DEV_STATE_UNINIT; 4825 } 4826 4827 /* 4828 * If we're not the Master PF then we need to wait around for the 4829 * Master PF Driver to finish setting up the adapter. 4830 * 4831 * Note that we also do this wait if we're a non-Master-capable PF and 4832 * there is no current Master PF; a Master PF may show up momentarily 4833 * and we wouldn't want to fail pointlessly. (This can happen when an 4834 * OS loads lots of different drivers rapidly at the same time). In 4835 * this case, the Master PF returned by the firmware will be 4836 * PCIE_FW_MASTER_M so the test below will work ... 4837 */ 4838 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 && 4839 master_mbox != mbox) { 4840 int waiting = FW_CMD_HELLO_TIMEOUT; 4841 4842 /* 4843 * Wait for the firmware to either indicate an error or 4844 * initialized state. If we see either of these we bail out 4845 * and report the issue to the caller. If we exhaust the 4846 * "hello timeout" and we haven't exhausted our retries, try 4847 * again. Otherwise bail with a timeout error. 4848 */ 4849 for (;;) { 4850 u32 pcie_fw; 4851 4852 msleep(50); 4853 waiting -= 50; 4854 4855 /* 4856 * If neither Error nor Initialialized are indicated 4857 * by the firmware keep waiting till we exaust our 4858 * timeout ... and then retry if we haven't exhausted 4859 * our retries ... 4860 */ 4861 pcie_fw = t4_read_reg(adap, PCIE_FW_A); 4862 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) { 4863 if (waiting <= 0) { 4864 if (retries-- > 0) 4865 goto retry; 4866 4867 return -ETIMEDOUT; 4868 } 4869 continue; 4870 } 4871 4872 /* 4873 * We either have an Error or Initialized condition 4874 * report errors preferentially. 4875 */ 4876 if (state) { 4877 if (pcie_fw & PCIE_FW_ERR_F) 4878 *state = DEV_STATE_ERR; 4879 else if (pcie_fw & PCIE_FW_INIT_F) 4880 *state = DEV_STATE_INIT; 4881 } 4882 4883 /* 4884 * If we arrived before a Master PF was selected and 4885 * there's not a valid Master PF, grab its identity 4886 * for our caller. 4887 */ 4888 if (master_mbox == PCIE_FW_MASTER_M && 4889 (pcie_fw & PCIE_FW_MASTER_VLD_F)) 4890 master_mbox = PCIE_FW_MASTER_G(pcie_fw); 4891 break; 4892 } 4893 } 4894 4895 return master_mbox; 4896 } 4897 4898 /** 4899 * t4_fw_bye - end communication with FW 4900 * @adap: the adapter 4901 * @mbox: mailbox to use for the FW command 4902 * 4903 * Issues a command to terminate communication with FW. 4904 */ 4905 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 4906 { 4907 struct fw_bye_cmd c; 4908 4909 memset(&c, 0, sizeof(c)); 4910 INIT_CMD(c, BYE, WRITE); 4911 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4912 } 4913 4914 /** 4915 * t4_init_cmd - ask FW to initialize the device 4916 * @adap: the adapter 4917 * @mbox: mailbox to use for the FW command 4918 * 4919 * Issues a command to FW to partially initialize the device. This 4920 * performs initialization that generally doesn't depend on user input. 4921 */ 4922 int t4_early_init(struct adapter *adap, unsigned int mbox) 4923 { 4924 struct fw_initialize_cmd c; 4925 4926 memset(&c, 0, sizeof(c)); 4927 INIT_CMD(c, INITIALIZE, WRITE); 4928 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4929 } 4930 4931 /** 4932 * t4_fw_reset - issue a reset to FW 4933 * @adap: the adapter 4934 * @mbox: mailbox to use for the FW command 4935 * @reset: specifies the type of reset to perform 4936 * 4937 * Issues a reset command of the specified type to FW. 4938 */ 4939 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 4940 { 4941 struct fw_reset_cmd c; 4942 4943 memset(&c, 0, sizeof(c)); 4944 INIT_CMD(c, RESET, WRITE); 4945 c.val = cpu_to_be32(reset); 4946 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4947 } 4948 4949 /** 4950 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 4951 * @adap: the adapter 4952 * @mbox: mailbox to use for the FW RESET command (if desired) 4953 * @force: force uP into RESET even if FW RESET command fails 4954 * 4955 * Issues a RESET command to firmware (if desired) with a HALT indication 4956 * and then puts the microprocessor into RESET state. The RESET command 4957 * will only be issued if a legitimate mailbox is provided (mbox <= 4958 * PCIE_FW_MASTER_M). 4959 * 4960 * This is generally used in order for the host to safely manipulate the 4961 * adapter without fear of conflicting with whatever the firmware might 4962 * be doing. The only way out of this state is to RESTART the firmware 4963 * ... 4964 */ 4965 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 4966 { 4967 int ret = 0; 4968 4969 /* 4970 * If a legitimate mailbox is provided, issue a RESET command 4971 * with a HALT indication. 4972 */ 4973 if (mbox <= PCIE_FW_MASTER_M) { 4974 struct fw_reset_cmd c; 4975 4976 memset(&c, 0, sizeof(c)); 4977 INIT_CMD(c, RESET, WRITE); 4978 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F); 4979 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F); 4980 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4981 } 4982 4983 /* 4984 * Normally we won't complete the operation if the firmware RESET 4985 * command fails but if our caller insists we'll go ahead and put the 4986 * uP into RESET. This can be useful if the firmware is hung or even 4987 * missing ... We'll have to take the risk of putting the uP into 4988 * RESET without the cooperation of firmware in that case. 4989 * 4990 * We also force the firmware's HALT flag to be on in case we bypassed 4991 * the firmware RESET command above or we're dealing with old firmware 4992 * which doesn't have the HALT capability. This will serve as a flag 4993 * for the incoming firmware to know that it's coming out of a HALT 4994 * rather than a RESET ... if it's new enough to understand that ... 4995 */ 4996 if (ret == 0 || force) { 4997 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F); 4998 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 4999 PCIE_FW_HALT_F); 5000 } 5001 5002 /* 5003 * And we always return the result of the firmware RESET command 5004 * even when we force the uP into RESET ... 5005 */ 5006 return ret; 5007 } 5008 5009 /** 5010 * t4_fw_restart - restart the firmware by taking the uP out of RESET 5011 * @adap: the adapter 5012 * @reset: if we want to do a RESET to restart things 5013 * 5014 * Restart firmware previously halted by t4_fw_halt(). On successful 5015 * return the previous PF Master remains as the new PF Master and there 5016 * is no need to issue a new HELLO command, etc. 5017 * 5018 * We do this in two ways: 5019 * 5020 * 1. If we're dealing with newer firmware we'll simply want to take 5021 * the chip's microprocessor out of RESET. This will cause the 5022 * firmware to start up from its start vector. And then we'll loop 5023 * until the firmware indicates it's started again (PCIE_FW.HALT 5024 * reset to 0) or we timeout. 5025 * 5026 * 2. If we're dealing with older firmware then we'll need to RESET 5027 * the chip since older firmware won't recognize the PCIE_FW.HALT 5028 * flag and automatically RESET itself on startup. 5029 */ 5030 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) 5031 { 5032 if (reset) { 5033 /* 5034 * Since we're directing the RESET instead of the firmware 5035 * doing it automatically, we need to clear the PCIE_FW.HALT 5036 * bit. 5037 */ 5038 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0); 5039 5040 /* 5041 * If we've been given a valid mailbox, first try to get the 5042 * firmware to do the RESET. If that works, great and we can 5043 * return success. Otherwise, if we haven't been given a 5044 * valid mailbox or the RESET command failed, fall back to 5045 * hitting the chip with a hammer. 5046 */ 5047 if (mbox <= PCIE_FW_MASTER_M) { 5048 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); 5049 msleep(100); 5050 if (t4_fw_reset(adap, mbox, 5051 PIORST_F | PIORSTMODE_F) == 0) 5052 return 0; 5053 } 5054 5055 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F); 5056 msleep(2000); 5057 } else { 5058 int ms; 5059 5060 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); 5061 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 5062 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F)) 5063 return 0; 5064 msleep(100); 5065 ms += 100; 5066 } 5067 return -ETIMEDOUT; 5068 } 5069 return 0; 5070 } 5071 5072 /** 5073 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 5074 * @adap: the adapter 5075 * @mbox: mailbox to use for the FW RESET command (if desired) 5076 * @fw_data: the firmware image to write 5077 * @size: image size 5078 * @force: force upgrade even if firmware doesn't cooperate 5079 * 5080 * Perform all of the steps necessary for upgrading an adapter's 5081 * firmware image. Normally this requires the cooperation of the 5082 * existing firmware in order to halt all existing activities 5083 * but if an invalid mailbox token is passed in we skip that step 5084 * (though we'll still put the adapter microprocessor into RESET in 5085 * that case). 5086 * 5087 * On successful return the new firmware will have been loaded and 5088 * the adapter will have been fully RESET losing all previous setup 5089 * state. On unsuccessful return the adapter may be completely hosed ... 5090 * positive errno indicates that the adapter is ~probably~ intact, a 5091 * negative errno indicates that things are looking bad ... 5092 */ 5093 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 5094 const u8 *fw_data, unsigned int size, int force) 5095 { 5096 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 5097 int reset, ret; 5098 5099 if (!t4_fw_matches_chip(adap, fw_hdr)) 5100 return -EINVAL; 5101 5102 ret = t4_fw_halt(adap, mbox, force); 5103 if (ret < 0 && !force) 5104 return ret; 5105 5106 ret = t4_load_fw(adap, fw_data, size); 5107 if (ret < 0) 5108 return ret; 5109 5110 /* 5111 * Older versions of the firmware don't understand the new 5112 * PCIE_FW.HALT flag and so won't know to perform a RESET when they 5113 * restart. So for newly loaded older firmware we'll have to do the 5114 * RESET for it so it starts up on a clean slate. We can tell if 5115 * the newly loaded firmware will handle this right by checking 5116 * its header flags to see if it advertises the capability. 5117 */ 5118 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); 5119 return t4_fw_restart(adap, mbox, reset); 5120 } 5121 5122 /** 5123 * t4_fixup_host_params - fix up host-dependent parameters 5124 * @adap: the adapter 5125 * @page_size: the host's Base Page Size 5126 * @cache_line_size: the host's Cache Line Size 5127 * 5128 * Various registers in T4 contain values which are dependent on the 5129 * host's Base Page and Cache Line Sizes. This function will fix all of 5130 * those registers with the appropriate values as passed in ... 5131 */ 5132 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 5133 unsigned int cache_line_size) 5134 { 5135 unsigned int page_shift = fls(page_size) - 1; 5136 unsigned int sge_hps = page_shift - 10; 5137 unsigned int stat_len = cache_line_size > 64 ? 128 : 64; 5138 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size; 5139 unsigned int fl_align_log = fls(fl_align) - 1; 5140 5141 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A, 5142 HOSTPAGESIZEPF0_V(sge_hps) | 5143 HOSTPAGESIZEPF1_V(sge_hps) | 5144 HOSTPAGESIZEPF2_V(sge_hps) | 5145 HOSTPAGESIZEPF3_V(sge_hps) | 5146 HOSTPAGESIZEPF4_V(sge_hps) | 5147 HOSTPAGESIZEPF5_V(sge_hps) | 5148 HOSTPAGESIZEPF6_V(sge_hps) | 5149 HOSTPAGESIZEPF7_V(sge_hps)); 5150 5151 if (is_t4(adap->params.chip)) { 5152 t4_set_reg_field(adap, SGE_CONTROL_A, 5153 INGPADBOUNDARY_V(INGPADBOUNDARY_M) | 5154 EGRSTATUSPAGESIZE_F, 5155 INGPADBOUNDARY_V(fl_align_log - 5156 INGPADBOUNDARY_SHIFT_X) | 5157 EGRSTATUSPAGESIZE_V(stat_len != 64)); 5158 } else { 5159 /* T5 introduced the separation of the Free List Padding and 5160 * Packing Boundaries. Thus, we can select a smaller Padding 5161 * Boundary to avoid uselessly chewing up PCIe Link and Memory 5162 * Bandwidth, and use a Packing Boundary which is large enough 5163 * to avoid false sharing between CPUs, etc. 5164 * 5165 * For the PCI Link, the smaller the Padding Boundary the 5166 * better. For the Memory Controller, a smaller Padding 5167 * Boundary is better until we cross under the Memory Line 5168 * Size (the minimum unit of transfer to/from Memory). If we 5169 * have a Padding Boundary which is smaller than the Memory 5170 * Line Size, that'll involve a Read-Modify-Write cycle on the 5171 * Memory Controller which is never good. For T5 the smallest 5172 * Padding Boundary which we can select is 32 bytes which is 5173 * larger than any known Memory Controller Line Size so we'll 5174 * use that. 5175 * 5176 * T5 has a different interpretation of the "0" value for the 5177 * Packing Boundary. This corresponds to 16 bytes instead of 5178 * the expected 32 bytes. We never have a Packing Boundary 5179 * less than 32 bytes so we can't use that special value but 5180 * on the other hand, if we wanted 32 bytes, the best we can 5181 * really do is 64 bytes. 5182 */ 5183 if (fl_align <= 32) { 5184 fl_align = 64; 5185 fl_align_log = 6; 5186 } 5187 t4_set_reg_field(adap, SGE_CONTROL_A, 5188 INGPADBOUNDARY_V(INGPADBOUNDARY_M) | 5189 EGRSTATUSPAGESIZE_F, 5190 INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X) | 5191 EGRSTATUSPAGESIZE_V(stat_len != 64)); 5192 t4_set_reg_field(adap, SGE_CONTROL2_A, 5193 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M), 5194 INGPACKBOUNDARY_V(fl_align_log - 5195 INGPACKBOUNDARY_SHIFT_X)); 5196 } 5197 /* 5198 * Adjust various SGE Free List Host Buffer Sizes. 5199 * 5200 * This is something of a crock since we're using fixed indices into 5201 * the array which are also known by the sge.c code and the T4 5202 * Firmware Configuration File. We need to come up with a much better 5203 * approach to managing this array. For now, the first four entries 5204 * are: 5205 * 5206 * 0: Host Page Size 5207 * 1: 64KB 5208 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode) 5209 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode) 5210 * 5211 * For the single-MTU buffers in unpacked mode we need to include 5212 * space for the SGE Control Packet Shift, 14 byte Ethernet header, 5213 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet 5214 * Padding boundary. All of these are accommodated in the Factory 5215 * Default Firmware Configuration File but we need to adjust it for 5216 * this host's cache line size. 5217 */ 5218 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size); 5219 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A, 5220 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1) 5221 & ~(fl_align-1)); 5222 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A, 5223 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) 5224 & ~(fl_align-1)); 5225 5226 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12)); 5227 5228 return 0; 5229 } 5230 5231 /** 5232 * t4_fw_initialize - ask FW to initialize the device 5233 * @adap: the adapter 5234 * @mbox: mailbox to use for the FW command 5235 * 5236 * Issues a command to FW to partially initialize the device. This 5237 * performs initialization that generally doesn't depend on user input. 5238 */ 5239 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 5240 { 5241 struct fw_initialize_cmd c; 5242 5243 memset(&c, 0, sizeof(c)); 5244 INIT_CMD(c, INITIALIZE, WRITE); 5245 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5246 } 5247 5248 /** 5249 * t4_query_params_rw - query FW or device parameters 5250 * @adap: the adapter 5251 * @mbox: mailbox to use for the FW command 5252 * @pf: the PF 5253 * @vf: the VF 5254 * @nparams: the number of parameters 5255 * @params: the parameter names 5256 * @val: the parameter values 5257 * @rw: Write and read flag 5258 * 5259 * Reads the value of FW or device parameters. Up to 7 parameters can be 5260 * queried at once. 5261 */ 5262 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 5263 unsigned int vf, unsigned int nparams, const u32 *params, 5264 u32 *val, int rw) 5265 { 5266 int i, ret; 5267 struct fw_params_cmd c; 5268 __be32 *p = &c.param[0].mnem; 5269 5270 if (nparams > 7) 5271 return -EINVAL; 5272 5273 memset(&c, 0, sizeof(c)); 5274 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | 5275 FW_CMD_REQUEST_F | FW_CMD_READ_F | 5276 FW_PARAMS_CMD_PFN_V(pf) | 5277 FW_PARAMS_CMD_VFN_V(vf)); 5278 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5279 5280 for (i = 0; i < nparams; i++) { 5281 *p++ = cpu_to_be32(*params++); 5282 if (rw) 5283 *p = cpu_to_be32(*(val + i)); 5284 p++; 5285 } 5286 5287 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 5288 if (ret == 0) 5289 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 5290 *val++ = be32_to_cpu(*p); 5291 return ret; 5292 } 5293 5294 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 5295 unsigned int vf, unsigned int nparams, const u32 *params, 5296 u32 *val) 5297 { 5298 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 5299 } 5300 5301 /** 5302 * t4_set_params_timeout - sets FW or device parameters 5303 * @adap: the adapter 5304 * @mbox: mailbox to use for the FW command 5305 * @pf: the PF 5306 * @vf: the VF 5307 * @nparams: the number of parameters 5308 * @params: the parameter names 5309 * @val: the parameter values 5310 * @timeout: the timeout time 5311 * 5312 * Sets the value of FW or device parameters. Up to 7 parameters can be 5313 * specified at once. 5314 */ 5315 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 5316 unsigned int pf, unsigned int vf, 5317 unsigned int nparams, const u32 *params, 5318 const u32 *val, int timeout) 5319 { 5320 struct fw_params_cmd c; 5321 __be32 *p = &c.param[0].mnem; 5322 5323 if (nparams > 7) 5324 return -EINVAL; 5325 5326 memset(&c, 0, sizeof(c)); 5327 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) | 5328 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 5329 FW_PARAMS_CMD_PFN_V(pf) | 5330 FW_PARAMS_CMD_VFN_V(vf)); 5331 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5332 5333 while (nparams--) { 5334 *p++ = cpu_to_be32(*params++); 5335 *p++ = cpu_to_be32(*val++); 5336 } 5337 5338 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 5339 } 5340 5341 /** 5342 * t4_set_params - sets FW or device parameters 5343 * @adap: the adapter 5344 * @mbox: mailbox to use for the FW command 5345 * @pf: the PF 5346 * @vf: the VF 5347 * @nparams: the number of parameters 5348 * @params: the parameter names 5349 * @val: the parameter values 5350 * 5351 * Sets the value of FW or device parameters. Up to 7 parameters can be 5352 * specified at once. 5353 */ 5354 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 5355 unsigned int vf, unsigned int nparams, const u32 *params, 5356 const u32 *val) 5357 { 5358 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 5359 FW_CMD_MAX_TIMEOUT); 5360 } 5361 5362 /** 5363 * t4_cfg_pfvf - configure PF/VF resource limits 5364 * @adap: the adapter 5365 * @mbox: mailbox to use for the FW command 5366 * @pf: the PF being configured 5367 * @vf: the VF being configured 5368 * @txq: the max number of egress queues 5369 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 5370 * @rxqi: the max number of interrupt-capable ingress queues 5371 * @rxq: the max number of interruptless ingress queues 5372 * @tc: the PCI traffic class 5373 * @vi: the max number of virtual interfaces 5374 * @cmask: the channel access rights mask for the PF/VF 5375 * @pmask: the port access rights mask for the PF/VF 5376 * @nexact: the maximum number of exact MPS filters 5377 * @rcaps: read capabilities 5378 * @wxcaps: write/execute capabilities 5379 * 5380 * Configures resource limits and capabilities for a physical or virtual 5381 * function. 5382 */ 5383 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 5384 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 5385 unsigned int rxqi, unsigned int rxq, unsigned int tc, 5386 unsigned int vi, unsigned int cmask, unsigned int pmask, 5387 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 5388 { 5389 struct fw_pfvf_cmd c; 5390 5391 memset(&c, 0, sizeof(c)); 5392 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F | 5393 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) | 5394 FW_PFVF_CMD_VFN_V(vf)); 5395 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5396 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) | 5397 FW_PFVF_CMD_NIQ_V(rxq)); 5398 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) | 5399 FW_PFVF_CMD_PMASK_V(pmask) | 5400 FW_PFVF_CMD_NEQ_V(txq)); 5401 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) | 5402 FW_PFVF_CMD_NVI_V(vi) | 5403 FW_PFVF_CMD_NEXACTF_V(nexact)); 5404 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) | 5405 FW_PFVF_CMD_WX_CAPS_V(wxcaps) | 5406 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl)); 5407 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5408 } 5409 5410 /** 5411 * t4_alloc_vi - allocate a virtual interface 5412 * @adap: the adapter 5413 * @mbox: mailbox to use for the FW command 5414 * @port: physical port associated with the VI 5415 * @pf: the PF owning the VI 5416 * @vf: the VF owning the VI 5417 * @nmac: number of MAC addresses needed (1 to 5) 5418 * @mac: the MAC addresses of the VI 5419 * @rss_size: size of RSS table slice associated with this VI 5420 * 5421 * Allocates a virtual interface for the given physical port. If @mac is 5422 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 5423 * @mac should be large enough to hold @nmac Ethernet addresses, they are 5424 * stored consecutively so the space needed is @nmac * 6 bytes. 5425 * Returns a negative error number or the non-negative VI id. 5426 */ 5427 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 5428 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 5429 unsigned int *rss_size) 5430 { 5431 int ret; 5432 struct fw_vi_cmd c; 5433 5434 memset(&c, 0, sizeof(c)); 5435 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F | 5436 FW_CMD_WRITE_F | FW_CMD_EXEC_F | 5437 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf)); 5438 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c)); 5439 c.portid_pkd = FW_VI_CMD_PORTID_V(port); 5440 c.nmac = nmac - 1; 5441 5442 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 5443 if (ret) 5444 return ret; 5445 5446 if (mac) { 5447 memcpy(mac, c.mac, sizeof(c.mac)); 5448 switch (nmac) { 5449 case 5: 5450 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 5451 case 4: 5452 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 5453 case 3: 5454 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 5455 case 2: 5456 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 5457 } 5458 } 5459 if (rss_size) 5460 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd)); 5461 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid)); 5462 } 5463 5464 /** 5465 * t4_free_vi - free a virtual interface 5466 * @adap: the adapter 5467 * @mbox: mailbox to use for the FW command 5468 * @pf: the PF owning the VI 5469 * @vf: the VF owning the VI 5470 * @viid: virtual interface identifiler 5471 * 5472 * Free a previously allocated virtual interface. 5473 */ 5474 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 5475 unsigned int vf, unsigned int viid) 5476 { 5477 struct fw_vi_cmd c; 5478 5479 memset(&c, 0, sizeof(c)); 5480 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | 5481 FW_CMD_REQUEST_F | 5482 FW_CMD_EXEC_F | 5483 FW_VI_CMD_PFN_V(pf) | 5484 FW_VI_CMD_VFN_V(vf)); 5485 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c)); 5486 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid)); 5487 5488 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 5489 } 5490 5491 /** 5492 * t4_set_rxmode - set Rx properties of a virtual interface 5493 * @adap: the adapter 5494 * @mbox: mailbox to use for the FW command 5495 * @viid: the VI id 5496 * @mtu: the new MTU or -1 5497 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 5498 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 5499 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 5500 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 5501 * @sleep_ok: if true we may sleep while awaiting command completion 5502 * 5503 * Sets Rx properties of a virtual interface. 5504 */ 5505 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 5506 int mtu, int promisc, int all_multi, int bcast, int vlanex, 5507 bool sleep_ok) 5508 { 5509 struct fw_vi_rxmode_cmd c; 5510 5511 /* convert to FW values */ 5512 if (mtu < 0) 5513 mtu = FW_RXMODE_MTU_NO_CHG; 5514 if (promisc < 0) 5515 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M; 5516 if (all_multi < 0) 5517 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M; 5518 if (bcast < 0) 5519 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M; 5520 if (vlanex < 0) 5521 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M; 5522 5523 memset(&c, 0, sizeof(c)); 5524 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) | 5525 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 5526 FW_VI_RXMODE_CMD_VIID_V(viid)); 5527 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5528 c.mtu_to_vlanexen = 5529 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) | 5530 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) | 5531 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) | 5532 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) | 5533 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex)); 5534 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 5535 } 5536 5537 /** 5538 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 5539 * @adap: the adapter 5540 * @mbox: mailbox to use for the FW command 5541 * @viid: the VI id 5542 * @free: if true any existing filters for this VI id are first removed 5543 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 5544 * @addr: the MAC address(es) 5545 * @idx: where to store the index of each allocated filter 5546 * @hash: pointer to hash address filter bitmap 5547 * @sleep_ok: call is allowed to sleep 5548 * 5549 * Allocates an exact-match filter for each of the supplied addresses and 5550 * sets it to the corresponding address. If @idx is not %NULL it should 5551 * have at least @naddr entries, each of which will be set to the index of 5552 * the filter allocated for the corresponding MAC address. If a filter 5553 * could not be allocated for an address its index is set to 0xffff. 5554 * If @hash is not %NULL addresses that fail to allocate an exact filter 5555 * are hashed and update the hash filter bitmap pointed at by @hash. 5556 * 5557 * Returns a negative error number or the number of filters allocated. 5558 */ 5559 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 5560 unsigned int viid, bool free, unsigned int naddr, 5561 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 5562 { 5563 int offset, ret = 0; 5564 struct fw_vi_mac_cmd c; 5565 unsigned int nfilters = 0; 5566 unsigned int max_naddr = adap->params.arch.mps_tcam_size; 5567 unsigned int rem = naddr; 5568 5569 if (naddr > max_naddr) 5570 return -EINVAL; 5571 5572 for (offset = 0; offset < naddr ; /**/) { 5573 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ? 5574 rem : ARRAY_SIZE(c.u.exact)); 5575 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 5576 u.exact[fw_naddr]), 16); 5577 struct fw_vi_mac_exact *p; 5578 int i; 5579 5580 memset(&c, 0, sizeof(c)); 5581 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) | 5582 FW_CMD_REQUEST_F | 5583 FW_CMD_WRITE_F | 5584 FW_CMD_EXEC_V(free) | 5585 FW_VI_MAC_CMD_VIID_V(viid)); 5586 c.freemacs_to_len16 = 5587 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) | 5588 FW_CMD_LEN16_V(len16)); 5589 5590 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 5591 p->valid_to_idx = 5592 cpu_to_be16(FW_VI_MAC_CMD_VALID_F | 5593 FW_VI_MAC_CMD_IDX_V( 5594 FW_VI_MAC_ADD_MAC)); 5595 memcpy(p->macaddr, addr[offset + i], 5596 sizeof(p->macaddr)); 5597 } 5598 5599 /* It's okay if we run out of space in our MAC address arena. 5600 * Some of the addresses we submit may get stored so we need 5601 * to run through the reply to see what the results were ... 5602 */ 5603 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 5604 if (ret && ret != -FW_ENOMEM) 5605 break; 5606 5607 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 5608 u16 index = FW_VI_MAC_CMD_IDX_G( 5609 be16_to_cpu(p->valid_to_idx)); 5610 5611 if (idx) 5612 idx[offset + i] = (index >= max_naddr ? 5613 0xffff : index); 5614 if (index < max_naddr) 5615 nfilters++; 5616 else if (hash) 5617 *hash |= (1ULL << 5618 hash_mac_addr(addr[offset + i])); 5619 } 5620 5621 free = false; 5622 offset += fw_naddr; 5623 rem -= fw_naddr; 5624 } 5625 5626 if (ret == 0 || ret == -FW_ENOMEM) 5627 ret = nfilters; 5628 return ret; 5629 } 5630 5631 /** 5632 * t4_change_mac - modifies the exact-match filter for a MAC address 5633 * @adap: the adapter 5634 * @mbox: mailbox to use for the FW command 5635 * @viid: the VI id 5636 * @idx: index of existing filter for old value of MAC address, or -1 5637 * @addr: the new MAC address value 5638 * @persist: whether a new MAC allocation should be persistent 5639 * @add_smt: if true also add the address to the HW SMT 5640 * 5641 * Modifies an exact-match filter and sets it to the new MAC address. 5642 * Note that in general it is not possible to modify the value of a given 5643 * filter so the generic way to modify an address filter is to free the one 5644 * being used by the old address value and allocate a new filter for the 5645 * new address value. @idx can be -1 if the address is a new addition. 5646 * 5647 * Returns a negative error number or the index of the filter with the new 5648 * MAC value. 5649 */ 5650 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 5651 int idx, const u8 *addr, bool persist, bool add_smt) 5652 { 5653 int ret, mode; 5654 struct fw_vi_mac_cmd c; 5655 struct fw_vi_mac_exact *p = c.u.exact; 5656 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size; 5657 5658 if (idx < 0) /* new allocation */ 5659 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 5660 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 5661 5662 memset(&c, 0, sizeof(c)); 5663 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) | 5664 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 5665 FW_VI_MAC_CMD_VIID_V(viid)); 5666 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1)); 5667 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F | 5668 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) | 5669 FW_VI_MAC_CMD_IDX_V(idx)); 5670 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 5671 5672 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 5673 if (ret == 0) { 5674 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx)); 5675 if (ret >= max_mac_addr) 5676 ret = -ENOMEM; 5677 } 5678 return ret; 5679 } 5680 5681 /** 5682 * t4_set_addr_hash - program the MAC inexact-match hash filter 5683 * @adap: the adapter 5684 * @mbox: mailbox to use for the FW command 5685 * @viid: the VI id 5686 * @ucast: whether the hash filter should also match unicast addresses 5687 * @vec: the value to be written to the hash filter 5688 * @sleep_ok: call is allowed to sleep 5689 * 5690 * Sets the 64-bit inexact-match hash filter for a virtual interface. 5691 */ 5692 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 5693 bool ucast, u64 vec, bool sleep_ok) 5694 { 5695 struct fw_vi_mac_cmd c; 5696 5697 memset(&c, 0, sizeof(c)); 5698 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) | 5699 FW_CMD_REQUEST_F | FW_CMD_WRITE_F | 5700 FW_VI_ENABLE_CMD_VIID_V(viid)); 5701 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F | 5702 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) | 5703 FW_CMD_LEN16_V(1)); 5704 c.u.hash.hashvec = cpu_to_be64(vec); 5705 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 5706 } 5707 5708 /** 5709 * t4_enable_vi_params - enable/disable a virtual interface 5710 * @adap: the adapter 5711 * @mbox: mailbox to use for the FW command 5712 * @viid: the VI id 5713 * @rx_en: 1=enable Rx, 0=disable Rx 5714 * @tx_en: 1=enable Tx, 0=disable Tx 5715 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 5716 * 5717 * Enables/disables a virtual interface. Note that setting DCB Enable 5718 * only makes sense when enabling a Virtual Interface ... 5719 */ 5720 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 5721 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 5722 { 5723 struct fw_vi_enable_cmd c; 5724 5725 memset(&c, 0, sizeof(c)); 5726 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | 5727 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 5728 FW_VI_ENABLE_CMD_VIID_V(viid)); 5729 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) | 5730 FW_VI_ENABLE_CMD_EEN_V(tx_en) | 5731 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) | 5732 FW_LEN16(c)); 5733 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 5734 } 5735 5736 /** 5737 * t4_enable_vi - enable/disable a virtual interface 5738 * @adap: the adapter 5739 * @mbox: mailbox to use for the FW command 5740 * @viid: the VI id 5741 * @rx_en: 1=enable Rx, 0=disable Rx 5742 * @tx_en: 1=enable Tx, 0=disable Tx 5743 * 5744 * Enables/disables a virtual interface. 5745 */ 5746 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 5747 bool rx_en, bool tx_en) 5748 { 5749 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 5750 } 5751 5752 /** 5753 * t4_identify_port - identify a VI's port by blinking its LED 5754 * @adap: the adapter 5755 * @mbox: mailbox to use for the FW command 5756 * @viid: the VI id 5757 * @nblinks: how many times to blink LED at 2.5 Hz 5758 * 5759 * Identifies a VI's port by blinking its LED. 5760 */ 5761 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 5762 unsigned int nblinks) 5763 { 5764 struct fw_vi_enable_cmd c; 5765 5766 memset(&c, 0, sizeof(c)); 5767 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | 5768 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 5769 FW_VI_ENABLE_CMD_VIID_V(viid)); 5770 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c)); 5771 c.blinkdur = cpu_to_be16(nblinks); 5772 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5773 } 5774 5775 /** 5776 * t4_iq_free - free an ingress queue and its FLs 5777 * @adap: the adapter 5778 * @mbox: mailbox to use for the FW command 5779 * @pf: the PF owning the queues 5780 * @vf: the VF owning the queues 5781 * @iqtype: the ingress queue type 5782 * @iqid: ingress queue id 5783 * @fl0id: FL0 queue id or 0xffff if no attached FL0 5784 * @fl1id: FL1 queue id or 0xffff if no attached FL1 5785 * 5786 * Frees an ingress queue and its associated FLs, if any. 5787 */ 5788 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 5789 unsigned int vf, unsigned int iqtype, unsigned int iqid, 5790 unsigned int fl0id, unsigned int fl1id) 5791 { 5792 struct fw_iq_cmd c; 5793 5794 memset(&c, 0, sizeof(c)); 5795 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F | 5796 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) | 5797 FW_IQ_CMD_VFN_V(vf)); 5798 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c)); 5799 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype)); 5800 c.iqid = cpu_to_be16(iqid); 5801 c.fl0id = cpu_to_be16(fl0id); 5802 c.fl1id = cpu_to_be16(fl1id); 5803 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5804 } 5805 5806 /** 5807 * t4_eth_eq_free - free an Ethernet egress queue 5808 * @adap: the adapter 5809 * @mbox: mailbox to use for the FW command 5810 * @pf: the PF owning the queue 5811 * @vf: the VF owning the queue 5812 * @eqid: egress queue id 5813 * 5814 * Frees an Ethernet egress queue. 5815 */ 5816 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 5817 unsigned int vf, unsigned int eqid) 5818 { 5819 struct fw_eq_eth_cmd c; 5820 5821 memset(&c, 0, sizeof(c)); 5822 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) | 5823 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 5824 FW_EQ_ETH_CMD_PFN_V(pf) | 5825 FW_EQ_ETH_CMD_VFN_V(vf)); 5826 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c)); 5827 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid)); 5828 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5829 } 5830 5831 /** 5832 * t4_ctrl_eq_free - free a control egress queue 5833 * @adap: the adapter 5834 * @mbox: mailbox to use for the FW command 5835 * @pf: the PF owning the queue 5836 * @vf: the VF owning the queue 5837 * @eqid: egress queue id 5838 * 5839 * Frees a control egress queue. 5840 */ 5841 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 5842 unsigned int vf, unsigned int eqid) 5843 { 5844 struct fw_eq_ctrl_cmd c; 5845 5846 memset(&c, 0, sizeof(c)); 5847 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | 5848 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 5849 FW_EQ_CTRL_CMD_PFN_V(pf) | 5850 FW_EQ_CTRL_CMD_VFN_V(vf)); 5851 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c)); 5852 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid)); 5853 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5854 } 5855 5856 /** 5857 * t4_ofld_eq_free - free an offload egress queue 5858 * @adap: the adapter 5859 * @mbox: mailbox to use for the FW command 5860 * @pf: the PF owning the queue 5861 * @vf: the VF owning the queue 5862 * @eqid: egress queue id 5863 * 5864 * Frees a control egress queue. 5865 */ 5866 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 5867 unsigned int vf, unsigned int eqid) 5868 { 5869 struct fw_eq_ofld_cmd c; 5870 5871 memset(&c, 0, sizeof(c)); 5872 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | 5873 FW_CMD_REQUEST_F | FW_CMD_EXEC_F | 5874 FW_EQ_OFLD_CMD_PFN_V(pf) | 5875 FW_EQ_OFLD_CMD_VFN_V(vf)); 5876 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c)); 5877 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid)); 5878 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5879 } 5880 5881 /** 5882 * t4_handle_fw_rpl - process a FW reply message 5883 * @adap: the adapter 5884 * @rpl: start of the FW message 5885 * 5886 * Processes a FW message, such as link state change messages. 5887 */ 5888 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 5889 { 5890 u8 opcode = *(const u8 *)rpl; 5891 5892 if (opcode == FW_PORT_CMD) { /* link/module state change message */ 5893 int speed = 0, fc = 0; 5894 const struct fw_port_cmd *p = (void *)rpl; 5895 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid)); 5896 int port = adap->chan_map[chan]; 5897 struct port_info *pi = adap2pinfo(adap, port); 5898 struct link_config *lc = &pi->link_cfg; 5899 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 5900 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0; 5901 u32 mod = FW_PORT_CMD_MODTYPE_G(stat); 5902 5903 if (stat & FW_PORT_CMD_RXPAUSE_F) 5904 fc |= PAUSE_RX; 5905 if (stat & FW_PORT_CMD_TXPAUSE_F) 5906 fc |= PAUSE_TX; 5907 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M)) 5908 speed = 100; 5909 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G)) 5910 speed = 1000; 5911 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G)) 5912 speed = 10000; 5913 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G)) 5914 speed = 40000; 5915 5916 if (link_ok != lc->link_ok || speed != lc->speed || 5917 fc != lc->fc) { /* something changed */ 5918 lc->link_ok = link_ok; 5919 lc->speed = speed; 5920 lc->fc = fc; 5921 lc->supported = be16_to_cpu(p->u.info.pcap); 5922 t4_os_link_changed(adap, port, link_ok); 5923 } 5924 if (mod != pi->mod_type) { 5925 pi->mod_type = mod; 5926 t4_os_portmod_changed(adap, port); 5927 } 5928 } 5929 return 0; 5930 } 5931 5932 static void get_pci_mode(struct adapter *adapter, struct pci_params *p) 5933 { 5934 u16 val; 5935 5936 if (pci_is_pcie(adapter->pdev)) { 5937 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); 5938 p->speed = val & PCI_EXP_LNKSTA_CLS; 5939 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 5940 } 5941 } 5942 5943 /** 5944 * init_link_config - initialize a link's SW state 5945 * @lc: structure holding the link state 5946 * @caps: link capabilities 5947 * 5948 * Initializes the SW state maintained for each link, including the link's 5949 * capabilities and default speed/flow-control/autonegotiation settings. 5950 */ 5951 static void init_link_config(struct link_config *lc, unsigned int caps) 5952 { 5953 lc->supported = caps; 5954 lc->requested_speed = 0; 5955 lc->speed = 0; 5956 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; 5957 if (lc->supported & FW_PORT_CAP_ANEG) { 5958 lc->advertising = lc->supported & ADVERT_MASK; 5959 lc->autoneg = AUTONEG_ENABLE; 5960 lc->requested_fc |= PAUSE_AUTONEG; 5961 } else { 5962 lc->advertising = 0; 5963 lc->autoneg = AUTONEG_DISABLE; 5964 } 5965 } 5966 5967 #define CIM_PF_NOACCESS 0xeeeeeeee 5968 5969 int t4_wait_dev_ready(void __iomem *regs) 5970 { 5971 u32 whoami; 5972 5973 whoami = readl(regs + PL_WHOAMI_A); 5974 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS) 5975 return 0; 5976 5977 msleep(500); 5978 whoami = readl(regs + PL_WHOAMI_A); 5979 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO); 5980 } 5981 5982 struct flash_desc { 5983 u32 vendor_and_model_id; 5984 u32 size_mb; 5985 }; 5986 5987 static int get_flash_params(struct adapter *adap) 5988 { 5989 /* Table for non-Numonix supported flash parts. Numonix parts are left 5990 * to the preexisting code. All flash parts have 64KB sectors. 5991 */ 5992 static struct flash_desc supported_flash[] = { 5993 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 5994 }; 5995 5996 int ret; 5997 u32 info; 5998 5999 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID); 6000 if (!ret) 6001 ret = sf1_read(adap, 3, 0, 1, &info); 6002 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */ 6003 if (ret) 6004 return ret; 6005 6006 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret) 6007 if (supported_flash[ret].vendor_and_model_id == info) { 6008 adap->params.sf_size = supported_flash[ret].size_mb; 6009 adap->params.sf_nsec = 6010 adap->params.sf_size / SF_SEC_SIZE; 6011 return 0; 6012 } 6013 6014 if ((info & 0xff) != 0x20) /* not a Numonix flash */ 6015 return -EINVAL; 6016 info >>= 16; /* log2 of size */ 6017 if (info >= 0x14 && info < 0x18) 6018 adap->params.sf_nsec = 1 << (info - 16); 6019 else if (info == 0x18) 6020 adap->params.sf_nsec = 64; 6021 else 6022 return -EINVAL; 6023 adap->params.sf_size = 1 << info; 6024 adap->params.sf_fw_start = 6025 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M; 6026 6027 if (adap->params.sf_size < FLASH_MIN_SIZE) 6028 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n", 6029 adap->params.sf_size, FLASH_MIN_SIZE); 6030 return 0; 6031 } 6032 6033 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range) 6034 { 6035 u16 val; 6036 u32 pcie_cap; 6037 6038 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 6039 if (pcie_cap) { 6040 pci_read_config_word(adapter->pdev, 6041 pcie_cap + PCI_EXP_DEVCTL2, &val); 6042 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT; 6043 val |= range; 6044 pci_write_config_word(adapter->pdev, 6045 pcie_cap + PCI_EXP_DEVCTL2, val); 6046 } 6047 } 6048 6049 /** 6050 * t4_prep_adapter - prepare SW and HW for operation 6051 * @adapter: the adapter 6052 * @reset: if true perform a HW reset 6053 * 6054 * Initialize adapter SW state for the various HW modules, set initial 6055 * values for some adapter tunables, take PHYs out of reset, and 6056 * initialize the MDIO interface. 6057 */ 6058 int t4_prep_adapter(struct adapter *adapter) 6059 { 6060 int ret, ver; 6061 uint16_t device_id; 6062 u32 pl_rev; 6063 6064 get_pci_mode(adapter, &adapter->params.pci); 6065 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A)); 6066 6067 ret = get_flash_params(adapter); 6068 if (ret < 0) { 6069 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret); 6070 return ret; 6071 } 6072 6073 /* Retrieve adapter's device ID 6074 */ 6075 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id); 6076 ver = device_id >> 12; 6077 adapter->params.chip = 0; 6078 switch (ver) { 6079 case CHELSIO_T4: 6080 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); 6081 adapter->params.arch.sge_fl_db = DBPRIO_F; 6082 adapter->params.arch.mps_tcam_size = 6083 NUM_MPS_CLS_SRAM_L_INSTANCES; 6084 adapter->params.arch.mps_rplc_size = 128; 6085 adapter->params.arch.nchan = NCHAN; 6086 adapter->params.arch.vfcount = 128; 6087 break; 6088 case CHELSIO_T5: 6089 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); 6090 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F; 6091 adapter->params.arch.mps_tcam_size = 6092 NUM_MPS_T5_CLS_SRAM_L_INSTANCES; 6093 adapter->params.arch.mps_rplc_size = 128; 6094 adapter->params.arch.nchan = NCHAN; 6095 adapter->params.arch.vfcount = 128; 6096 break; 6097 case CHELSIO_T6: 6098 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); 6099 adapter->params.arch.sge_fl_db = 0; 6100 adapter->params.arch.mps_tcam_size = 6101 NUM_MPS_T5_CLS_SRAM_L_INSTANCES; 6102 adapter->params.arch.mps_rplc_size = 256; 6103 adapter->params.arch.nchan = 2; 6104 adapter->params.arch.vfcount = 256; 6105 break; 6106 default: 6107 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 6108 device_id); 6109 return -EINVAL; 6110 } 6111 6112 adapter->params.cim_la_size = CIMLA_SIZE; 6113 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 6114 6115 /* 6116 * Default port for debugging in case we can't reach FW. 6117 */ 6118 adapter->params.nports = 1; 6119 adapter->params.portvec = 1; 6120 adapter->params.vpd.cclk = 50000; 6121 6122 /* Set pci completion timeout value to 4 seconds. */ 6123 set_pcie_completion_timeout(adapter, 0xd); 6124 return 0; 6125 } 6126 6127 /** 6128 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 6129 * @adapter: the adapter 6130 * @qid: the Queue ID 6131 * @qtype: the Ingress or Egress type for @qid 6132 * @user: true if this request is for a user mode queue 6133 * @pbar2_qoffset: BAR2 Queue Offset 6134 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 6135 * 6136 * Returns the BAR2 SGE Queue Registers information associated with the 6137 * indicated Absolute Queue ID. These are passed back in return value 6138 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 6139 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 6140 * 6141 * This may return an error which indicates that BAR2 SGE Queue 6142 * registers aren't available. If an error is not returned, then the 6143 * following values are returned: 6144 * 6145 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 6146 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 6147 * 6148 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 6149 * require the "Inferred Queue ID" ability may be used. E.g. the 6150 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 6151 * then these "Inferred Queue ID" register may not be used. 6152 */ 6153 int t4_bar2_sge_qregs(struct adapter *adapter, 6154 unsigned int qid, 6155 enum t4_bar2_qtype qtype, 6156 int user, 6157 u64 *pbar2_qoffset, 6158 unsigned int *pbar2_qid) 6159 { 6160 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 6161 u64 bar2_page_offset, bar2_qoffset; 6162 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 6163 6164 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */ 6165 if (!user && is_t4(adapter->params.chip)) 6166 return -EINVAL; 6167 6168 /* Get our SGE Page Size parameters. 6169 */ 6170 page_shift = adapter->params.sge.hps + 10; 6171 page_size = 1 << page_shift; 6172 6173 /* Get the right Queues per Page parameters for our Queue. 6174 */ 6175 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 6176 ? adapter->params.sge.eq_qpp 6177 : adapter->params.sge.iq_qpp); 6178 qpp_mask = (1 << qpp_shift) - 1; 6179 6180 /* Calculate the basics of the BAR2 SGE Queue register area: 6181 * o The BAR2 page the Queue registers will be in. 6182 * o The BAR2 Queue ID. 6183 * o The BAR2 Queue ID Offset into the BAR2 page. 6184 */ 6185 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 6186 bar2_qid = qid & qpp_mask; 6187 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 6188 6189 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 6190 * hardware will infer the Absolute Queue ID simply from the writes to 6191 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 6192 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 6193 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 6194 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 6195 * from the BAR2 Page and BAR2 Queue ID. 6196 * 6197 * One important censequence of this is that some BAR2 SGE registers 6198 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 6199 * there. But other registers synthesize the SGE Queue ID purely 6200 * from the writes to the registers -- the Write Combined Doorbell 6201 * Buffer is a good example. These BAR2 SGE Registers are only 6202 * available for those BAR2 SGE Register areas where the SGE Absolute 6203 * Queue ID can be inferred from simple writes. 6204 */ 6205 bar2_qoffset = bar2_page_offset; 6206 bar2_qinferred = (bar2_qid_offset < page_size); 6207 if (bar2_qinferred) { 6208 bar2_qoffset += bar2_qid_offset; 6209 bar2_qid = 0; 6210 } 6211 6212 *pbar2_qoffset = bar2_qoffset; 6213 *pbar2_qid = bar2_qid; 6214 return 0; 6215 } 6216 6217 /** 6218 * t4_init_devlog_params - initialize adapter->params.devlog 6219 * @adap: the adapter 6220 * 6221 * Initialize various fields of the adapter's Firmware Device Log 6222 * Parameters structure. 6223 */ 6224 int t4_init_devlog_params(struct adapter *adap) 6225 { 6226 struct devlog_params *dparams = &adap->params.devlog; 6227 u32 pf_dparams; 6228 unsigned int devlog_meminfo; 6229 struct fw_devlog_cmd devlog_cmd; 6230 int ret; 6231 6232 /* If we're dealing with newer firmware, the Device Log Paramerters 6233 * are stored in a designated register which allows us to access the 6234 * Device Log even if we can't talk to the firmware. 6235 */ 6236 pf_dparams = 6237 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG)); 6238 if (pf_dparams) { 6239 unsigned int nentries, nentries128; 6240 6241 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams); 6242 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4; 6243 6244 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams); 6245 nentries = (nentries128 + 1) * 128; 6246 dparams->size = nentries * sizeof(struct fw_devlog_e); 6247 6248 return 0; 6249 } 6250 6251 /* Otherwise, ask the firmware for it's Device Log Parameters. 6252 */ 6253 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 6254 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) | 6255 FW_CMD_REQUEST_F | FW_CMD_READ_F); 6256 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 6257 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 6258 &devlog_cmd); 6259 if (ret) 6260 return ret; 6261 6262 devlog_meminfo = 6263 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 6264 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo); 6265 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4; 6266 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 6267 6268 return 0; 6269 } 6270 6271 /** 6272 * t4_init_sge_params - initialize adap->params.sge 6273 * @adapter: the adapter 6274 * 6275 * Initialize various fields of the adapter's SGE Parameters structure. 6276 */ 6277 int t4_init_sge_params(struct adapter *adapter) 6278 { 6279 struct sge_params *sge_params = &adapter->params.sge; 6280 u32 hps, qpp; 6281 unsigned int s_hps, s_qpp; 6282 6283 /* Extract the SGE Page Size for our PF. 6284 */ 6285 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A); 6286 s_hps = (HOSTPAGESIZEPF0_S + 6287 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf); 6288 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M); 6289 6290 /* Extract the SGE Egress and Ingess Queues Per Page for our PF. 6291 */ 6292 s_qpp = (QUEUESPERPAGEPF0_S + 6293 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf); 6294 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A); 6295 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); 6296 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A); 6297 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); 6298 6299 return 0; 6300 } 6301 6302 /** 6303 * t4_init_tp_params - initialize adap->params.tp 6304 * @adap: the adapter 6305 * 6306 * Initialize various fields of the adapter's TP Parameters structure. 6307 */ 6308 int t4_init_tp_params(struct adapter *adap) 6309 { 6310 int chan; 6311 u32 v; 6312 6313 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); 6314 adap->params.tp.tre = TIMERRESOLUTION_G(v); 6315 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); 6316 6317 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 6318 for (chan = 0; chan < NCHAN; chan++) 6319 adap->params.tp.tx_modq[chan] = chan; 6320 6321 /* Cache the adapter's Compressed Filter Mode and global Incress 6322 * Configuration. 6323 */ 6324 if (t4_use_ldst(adap)) { 6325 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1, 6326 TP_VLAN_PRI_MAP_A, 1); 6327 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1, 6328 TP_INGRESS_CONFIG_A, 1); 6329 } else { 6330 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 6331 &adap->params.tp.vlan_pri_map, 1, 6332 TP_VLAN_PRI_MAP_A); 6333 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 6334 &adap->params.tp.ingress_config, 1, 6335 TP_INGRESS_CONFIG_A); 6336 } 6337 6338 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 6339 * shift positions of several elements of the Compressed Filter Tuple 6340 * for this adapter which we need frequently ... 6341 */ 6342 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); 6343 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); 6344 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); 6345 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, 6346 PROTOCOL_F); 6347 6348 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID 6349 * represents the presence of an Outer VLAN instead of a VNIC ID. 6350 */ 6351 if ((adap->params.tp.ingress_config & VNIC_F) == 0) 6352 adap->params.tp.vnic_shift = -1; 6353 6354 return 0; 6355 } 6356 6357 /** 6358 * t4_filter_field_shift - calculate filter field shift 6359 * @adap: the adapter 6360 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 6361 * 6362 * Return the shift position of a filter field within the Compressed 6363 * Filter Tuple. The filter field is specified via its selection bit 6364 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 6365 */ 6366 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 6367 { 6368 unsigned int filter_mode = adap->params.tp.vlan_pri_map; 6369 unsigned int sel; 6370 int field_shift; 6371 6372 if ((filter_mode & filter_sel) == 0) 6373 return -1; 6374 6375 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 6376 switch (filter_mode & sel) { 6377 case FCOE_F: 6378 field_shift += FT_FCOE_W; 6379 break; 6380 case PORT_F: 6381 field_shift += FT_PORT_W; 6382 break; 6383 case VNIC_ID_F: 6384 field_shift += FT_VNIC_ID_W; 6385 break; 6386 case VLAN_F: 6387 field_shift += FT_VLAN_W; 6388 break; 6389 case TOS_F: 6390 field_shift += FT_TOS_W; 6391 break; 6392 case PROTOCOL_F: 6393 field_shift += FT_PROTOCOL_W; 6394 break; 6395 case ETHERTYPE_F: 6396 field_shift += FT_ETHERTYPE_W; 6397 break; 6398 case MACMATCH_F: 6399 field_shift += FT_MACMATCH_W; 6400 break; 6401 case MPSHITTYPE_F: 6402 field_shift += FT_MPSHITTYPE_W; 6403 break; 6404 case FRAGMENTATION_F: 6405 field_shift += FT_FRAGMENTATION_W; 6406 break; 6407 } 6408 } 6409 return field_shift; 6410 } 6411 6412 int t4_init_rss_mode(struct adapter *adap, int mbox) 6413 { 6414 int i, ret; 6415 struct fw_rss_vi_config_cmd rvc; 6416 6417 memset(&rvc, 0, sizeof(rvc)); 6418 6419 for_each_port(adap, i) { 6420 struct port_info *p = adap2pinfo(adap, i); 6421 6422 rvc.op_to_viid = 6423 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) | 6424 FW_CMD_REQUEST_F | FW_CMD_READ_F | 6425 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid)); 6426 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc)); 6427 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); 6428 if (ret) 6429 return ret; 6430 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen); 6431 } 6432 return 0; 6433 } 6434 6435 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf) 6436 { 6437 u8 addr[6]; 6438 int ret, i, j = 0; 6439 struct fw_port_cmd c; 6440 struct fw_rss_vi_config_cmd rvc; 6441 6442 memset(&c, 0, sizeof(c)); 6443 memset(&rvc, 0, sizeof(rvc)); 6444 6445 for_each_port(adap, i) { 6446 unsigned int rss_size; 6447 struct port_info *p = adap2pinfo(adap, i); 6448 6449 while ((adap->params.portvec & (1 << j)) == 0) 6450 j++; 6451 6452 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | 6453 FW_CMD_REQUEST_F | FW_CMD_READ_F | 6454 FW_PORT_CMD_PORTID_V(j)); 6455 c.action_to_len16 = cpu_to_be32( 6456 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) | 6457 FW_LEN16(c)); 6458 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6459 if (ret) 6460 return ret; 6461 6462 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); 6463 if (ret < 0) 6464 return ret; 6465 6466 p->viid = ret; 6467 p->tx_chan = j; 6468 p->lport = j; 6469 p->rss_size = rss_size; 6470 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); 6471 adap->port[i]->dev_port = j; 6472 6473 ret = be32_to_cpu(c.u.info.lstatus_to_modtype); 6474 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ? 6475 FW_PORT_CMD_MDIOADDR_G(ret) : -1; 6476 p->port_type = FW_PORT_CMD_PTYPE_G(ret); 6477 p->mod_type = FW_PORT_MOD_TYPE_NA; 6478 6479 rvc.op_to_viid = 6480 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) | 6481 FW_CMD_REQUEST_F | FW_CMD_READ_F | 6482 FW_RSS_VI_CONFIG_CMD_VIID(p->viid)); 6483 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc)); 6484 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); 6485 if (ret) 6486 return ret; 6487 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen); 6488 6489 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap)); 6490 j++; 6491 } 6492 return 0; 6493 } 6494 6495 /** 6496 * t4_read_cimq_cfg - read CIM queue configuration 6497 * @adap: the adapter 6498 * @base: holds the queue base addresses in bytes 6499 * @size: holds the queue sizes in bytes 6500 * @thres: holds the queue full thresholds in bytes 6501 * 6502 * Returns the current configuration of the CIM queues, starting with 6503 * the IBQs, then the OBQs. 6504 */ 6505 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 6506 { 6507 unsigned int i, v; 6508 int cim_num_obq = is_t4(adap->params.chip) ? 6509 CIM_NUM_OBQ : CIM_NUM_OBQ_T5; 6510 6511 for (i = 0; i < CIM_NUM_IBQ; i++) { 6512 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F | 6513 QUENUMSELECT_V(i)); 6514 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); 6515 /* value is in 256-byte units */ 6516 *base++ = CIMQBASE_G(v) * 256; 6517 *size++ = CIMQSIZE_G(v) * 256; 6518 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */ 6519 } 6520 for (i = 0; i < cim_num_obq; i++) { 6521 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | 6522 QUENUMSELECT_V(i)); 6523 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); 6524 /* value is in 256-byte units */ 6525 *base++ = CIMQBASE_G(v) * 256; 6526 *size++ = CIMQSIZE_G(v) * 256; 6527 } 6528 } 6529 6530 /** 6531 * t4_read_cim_ibq - read the contents of a CIM inbound queue 6532 * @adap: the adapter 6533 * @qid: the queue index 6534 * @data: where to store the queue contents 6535 * @n: capacity of @data in 32-bit words 6536 * 6537 * Reads the contents of the selected CIM queue starting at address 0 up 6538 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 6539 * error and the number of 32-bit words actually read on success. 6540 */ 6541 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 6542 { 6543 int i, err, attempts; 6544 unsigned int addr; 6545 const unsigned int nwords = CIM_IBQ_SIZE * 4; 6546 6547 if (qid > 5 || (n & 3)) 6548 return -EINVAL; 6549 6550 addr = qid * nwords; 6551 if (n > nwords) 6552 n = nwords; 6553 6554 /* It might take 3-10ms before the IBQ debug read access is allowed. 6555 * Wait for 1 Sec with a delay of 1 usec. 6556 */ 6557 attempts = 1000000; 6558 6559 for (i = 0; i < n; i++, addr++) { 6560 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) | 6561 IBQDBGEN_F); 6562 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0, 6563 attempts, 1); 6564 if (err) 6565 return err; 6566 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A); 6567 } 6568 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0); 6569 return i; 6570 } 6571 6572 /** 6573 * t4_read_cim_obq - read the contents of a CIM outbound queue 6574 * @adap: the adapter 6575 * @qid: the queue index 6576 * @data: where to store the queue contents 6577 * @n: capacity of @data in 32-bit words 6578 * 6579 * Reads the contents of the selected CIM queue starting at address 0 up 6580 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 6581 * error and the number of 32-bit words actually read on success. 6582 */ 6583 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 6584 { 6585 int i, err; 6586 unsigned int addr, v, nwords; 6587 int cim_num_obq = is_t4(adap->params.chip) ? 6588 CIM_NUM_OBQ : CIM_NUM_OBQ_T5; 6589 6590 if ((qid > (cim_num_obq - 1)) || (n & 3)) 6591 return -EINVAL; 6592 6593 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | 6594 QUENUMSELECT_V(qid)); 6595 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); 6596 6597 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */ 6598 nwords = CIMQSIZE_G(v) * 64; /* same */ 6599 if (n > nwords) 6600 n = nwords; 6601 6602 for (i = 0; i < n; i++, addr++) { 6603 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) | 6604 OBQDBGEN_F); 6605 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0, 6606 2, 1); 6607 if (err) 6608 return err; 6609 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A); 6610 } 6611 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0); 6612 return i; 6613 } 6614 6615 /** 6616 * t4_cim_read - read a block from CIM internal address space 6617 * @adap: the adapter 6618 * @addr: the start address within the CIM address space 6619 * @n: number of words to read 6620 * @valp: where to store the result 6621 * 6622 * Reads a block of 4-byte words from the CIM intenal address space. 6623 */ 6624 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 6625 unsigned int *valp) 6626 { 6627 int ret = 0; 6628 6629 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) 6630 return -EBUSY; 6631 6632 for ( ; !ret && n--; addr += 4) { 6633 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr); 6634 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, 6635 0, 5, 2); 6636 if (!ret) 6637 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A); 6638 } 6639 return ret; 6640 } 6641 6642 /** 6643 * t4_cim_write - write a block into CIM internal address space 6644 * @adap: the adapter 6645 * @addr: the start address within the CIM address space 6646 * @n: number of words to write 6647 * @valp: set of values to write 6648 * 6649 * Writes a block of 4-byte words into the CIM intenal address space. 6650 */ 6651 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 6652 const unsigned int *valp) 6653 { 6654 int ret = 0; 6655 6656 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) 6657 return -EBUSY; 6658 6659 for ( ; !ret && n--; addr += 4) { 6660 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++); 6661 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F); 6662 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, 6663 0, 5, 2); 6664 } 6665 return ret; 6666 } 6667 6668 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 6669 unsigned int val) 6670 { 6671 return t4_cim_write(adap, addr, 1, &val); 6672 } 6673 6674 /** 6675 * t4_cim_read_la - read CIM LA capture buffer 6676 * @adap: the adapter 6677 * @la_buf: where to store the LA data 6678 * @wrptr: the HW write pointer within the capture buffer 6679 * 6680 * Reads the contents of the CIM LA buffer with the most recent entry at 6681 * the end of the returned data and with the entry at @wrptr first. 6682 * We try to leave the LA in the running state we find it in. 6683 */ 6684 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 6685 { 6686 int i, ret; 6687 unsigned int cfg, val, idx; 6688 6689 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg); 6690 if (ret) 6691 return ret; 6692 6693 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */ 6694 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0); 6695 if (ret) 6696 return ret; 6697 } 6698 6699 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); 6700 if (ret) 6701 goto restart; 6702 6703 idx = UPDBGLAWRPTR_G(val); 6704 if (wrptr) 6705 *wrptr = idx; 6706 6707 for (i = 0; i < adap->params.cim_la_size; i++) { 6708 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 6709 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F); 6710 if (ret) 6711 break; 6712 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); 6713 if (ret) 6714 break; 6715 if (val & UPDBGLARDEN_F) { 6716 ret = -ETIMEDOUT; 6717 break; 6718 } 6719 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]); 6720 if (ret) 6721 break; 6722 idx = (idx + 1) & UPDBGLARDPTR_M; 6723 } 6724 restart: 6725 if (cfg & UPDBGLAEN_F) { 6726 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 6727 cfg & ~UPDBGLARDEN_F); 6728 if (!ret) 6729 ret = r; 6730 } 6731 return ret; 6732 } 6733 6734 /** 6735 * t4_tp_read_la - read TP LA capture buffer 6736 * @adap: the adapter 6737 * @la_buf: where to store the LA data 6738 * @wrptr: the HW write pointer within the capture buffer 6739 * 6740 * Reads the contents of the TP LA buffer with the most recent entry at 6741 * the end of the returned data and with the entry at @wrptr first. 6742 * We leave the LA in the running state we find it in. 6743 */ 6744 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 6745 { 6746 bool last_incomplete; 6747 unsigned int i, cfg, val, idx; 6748 6749 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff; 6750 if (cfg & DBGLAENABLE_F) /* freeze LA */ 6751 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, 6752 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); 6753 6754 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A); 6755 idx = DBGLAWPTR_G(val); 6756 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0; 6757 if (last_incomplete) 6758 idx = (idx + 1) & DBGLARPTR_M; 6759 if (wrptr) 6760 *wrptr = idx; 6761 6762 val &= 0xffff; 6763 val &= ~DBGLARPTR_V(DBGLARPTR_M); 6764 val |= adap->params.tp.la_mask; 6765 6766 for (i = 0; i < TPLA_SIZE; i++) { 6767 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val); 6768 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A); 6769 idx = (idx + 1) & DBGLARPTR_M; 6770 } 6771 6772 /* Wipe out last entry if it isn't valid */ 6773 if (last_incomplete) 6774 la_buf[TPLA_SIZE - 1] = ~0ULL; 6775 6776 if (cfg & DBGLAENABLE_F) /* restore running state */ 6777 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, 6778 cfg | adap->params.tp.la_mask); 6779 } 6780 6781 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 6782 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 6783 * state for more than the Warning Threshold then we'll issue a warning about 6784 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 6785 * appears to be hung every Warning Repeat second till the situation clears. 6786 * If the situation clears, we'll note that as well. 6787 */ 6788 #define SGE_IDMA_WARN_THRESH 1 6789 #define SGE_IDMA_WARN_REPEAT 300 6790 6791 /** 6792 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 6793 * @adapter: the adapter 6794 * @idma: the adapter IDMA Monitor state 6795 * 6796 * Initialize the state of an SGE Ingress DMA Monitor. 6797 */ 6798 void t4_idma_monitor_init(struct adapter *adapter, 6799 struct sge_idma_monitor_state *idma) 6800 { 6801 /* Initialize the state variables for detecting an SGE Ingress DMA 6802 * hang. The SGE has internal counters which count up on each clock 6803 * tick whenever the SGE finds its Ingress DMA State Engines in the 6804 * same state they were on the previous clock tick. The clock used is 6805 * the Core Clock so we have a limit on the maximum "time" they can 6806 * record; typically a very small number of seconds. For instance, 6807 * with a 600MHz Core Clock, we can only count up to a bit more than 6808 * 7s. So we'll synthesize a larger counter in order to not run the 6809 * risk of having the "timers" overflow and give us the flexibility to 6810 * maintain a Hung SGE State Machine of our own which operates across 6811 * a longer time frame. 6812 */ 6813 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 6814 idma->idma_stalled[0] = 0; 6815 idma->idma_stalled[1] = 0; 6816 } 6817 6818 /** 6819 * t4_idma_monitor - monitor SGE Ingress DMA state 6820 * @adapter: the adapter 6821 * @idma: the adapter IDMA Monitor state 6822 * @hz: number of ticks/second 6823 * @ticks: number of ticks since the last IDMA Monitor call 6824 */ 6825 void t4_idma_monitor(struct adapter *adapter, 6826 struct sge_idma_monitor_state *idma, 6827 int hz, int ticks) 6828 { 6829 int i, idma_same_state_cnt[2]; 6830 6831 /* Read the SGE Debug Ingress DMA Same State Count registers. These 6832 * are counters inside the SGE which count up on each clock when the 6833 * SGE finds its Ingress DMA State Engines in the same states they 6834 * were in the previous clock. The counters will peg out at 6835 * 0xffffffff without wrapping around so once they pass the 1s 6836 * threshold they'll stay above that till the IDMA state changes. 6837 */ 6838 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13); 6839 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A); 6840 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); 6841 6842 for (i = 0; i < 2; i++) { 6843 u32 debug0, debug11; 6844 6845 /* If the Ingress DMA Same State Counter ("timer") is less 6846 * than 1s, then we can reset our synthesized Stall Timer and 6847 * continue. If we have previously emitted warnings about a 6848 * potential stalled Ingress Queue, issue a note indicating 6849 * that the Ingress Queue has resumed forward progress. 6850 */ 6851 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 6852 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz) 6853 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, " 6854 "resumed after %d seconds\n", 6855 i, idma->idma_qid[i], 6856 idma->idma_stalled[i] / hz); 6857 idma->idma_stalled[i] = 0; 6858 continue; 6859 } 6860 6861 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 6862 * domain. The first time we get here it'll be because we 6863 * passed the 1s Threshold; each additional time it'll be 6864 * because the RX Timer Callback is being fired on its regular 6865 * schedule. 6866 * 6867 * If the stall is below our Potential Hung Ingress Queue 6868 * Warning Threshold, continue. 6869 */ 6870 if (idma->idma_stalled[i] == 0) { 6871 idma->idma_stalled[i] = hz; 6872 idma->idma_warn[i] = 0; 6873 } else { 6874 idma->idma_stalled[i] += ticks; 6875 idma->idma_warn[i] -= ticks; 6876 } 6877 6878 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz) 6879 continue; 6880 6881 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 6882 */ 6883 if (idma->idma_warn[i] > 0) 6884 continue; 6885 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz; 6886 6887 /* Read and save the SGE IDMA State and Queue ID information. 6888 * We do this every time in case it changes across time ... 6889 * can't be too careful ... 6890 */ 6891 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0); 6892 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); 6893 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 6894 6895 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11); 6896 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); 6897 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 6898 6899 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in " 6900 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 6901 i, idma->idma_qid[i], idma->idma_state[i], 6902 idma->idma_stalled[i] / hz, 6903 debug0, debug11); 6904 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 6905 } 6906 } 6907