1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/skbuff.h> 36 #include <linux/netdevice.h> 37 #include <linux/etherdevice.h> 38 #include <linux/if_vlan.h> 39 #include <linux/ip.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/jiffies.h> 42 #include <linux/prefetch.h> 43 #include <linux/export.h> 44 #include <net/ipv6.h> 45 #include <net/tcp.h> 46 #ifdef CONFIG_NET_RX_BUSY_POLL 47 #include <net/busy_poll.h> 48 #endif /* CONFIG_NET_RX_BUSY_POLL */ 49 #ifdef CONFIG_CHELSIO_T4_FCOE 50 #include <scsi/fc/fc_fcoe.h> 51 #endif /* CONFIG_CHELSIO_T4_FCOE */ 52 #include "cxgb4.h" 53 #include "t4_regs.h" 54 #include "t4_values.h" 55 #include "t4_msg.h" 56 #include "t4fw_api.h" 57 58 /* 59 * Rx buffer size. We use largish buffers if possible but settle for single 60 * pages under memory shortage. 61 */ 62 #if PAGE_SHIFT >= 16 63 # define FL_PG_ORDER 0 64 #else 65 # define FL_PG_ORDER (16 - PAGE_SHIFT) 66 #endif 67 68 /* RX_PULL_LEN should be <= RX_COPY_THRES */ 69 #define RX_COPY_THRES 256 70 #define RX_PULL_LEN 128 71 72 /* 73 * Main body length for sk_buffs used for Rx Ethernet packets with fragments. 74 * Should be >= RX_PULL_LEN but possibly bigger to give pskb_may_pull some room. 75 */ 76 #define RX_PKT_SKB_LEN 512 77 78 /* 79 * Max number of Tx descriptors we clean up at a time. Should be modest as 80 * freeing skbs isn't cheap and it happens while holding locks. We just need 81 * to free packets faster than they arrive, we eventually catch up and keep 82 * the amortized cost reasonable. Must be >= 2 * TXQ_STOP_THRES. 83 */ 84 #define MAX_TX_RECLAIM 16 85 86 /* 87 * Max number of Rx buffers we replenish at a time. Again keep this modest, 88 * allocating buffers isn't cheap either. 89 */ 90 #define MAX_RX_REFILL 16U 91 92 /* 93 * Period of the Rx queue check timer. This timer is infrequent as it has 94 * something to do only when the system experiences severe memory shortage. 95 */ 96 #define RX_QCHECK_PERIOD (HZ / 2) 97 98 /* 99 * Period of the Tx queue check timer. 100 */ 101 #define TX_QCHECK_PERIOD (HZ / 2) 102 103 /* 104 * Max number of Tx descriptors to be reclaimed by the Tx timer. 105 */ 106 #define MAX_TIMER_TX_RECLAIM 100 107 108 /* 109 * Timer index used when backing off due to memory shortage. 110 */ 111 #define NOMEM_TMR_IDX (SGE_NTIMERS - 1) 112 113 /* 114 * Suspend an Ethernet Tx queue with fewer available descriptors than this. 115 * This is the same as calc_tx_descs() for a TSO packet with 116 * nr_frags == MAX_SKB_FRAGS. 117 */ 118 #define ETHTXQ_STOP_THRES \ 119 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 120 121 /* 122 * Suspension threshold for non-Ethernet Tx queues. We require enough room 123 * for a full sized WR. 124 */ 125 #define TXQ_STOP_THRES (SGE_MAX_WR_LEN / sizeof(struct tx_desc)) 126 127 /* 128 * Max Tx descriptor space we allow for an Ethernet packet to be inlined 129 * into a WR. 130 */ 131 #define MAX_IMM_TX_PKT_LEN 256 132 133 /* 134 * Max size of a WR sent through a control Tx queue. 135 */ 136 #define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN 137 138 struct tx_sw_desc { /* SW state per Tx descriptor */ 139 struct sk_buff *skb; 140 struct ulptx_sgl *sgl; 141 }; 142 143 struct rx_sw_desc { /* SW state per Rx descriptor */ 144 struct page *page; 145 dma_addr_t dma_addr; 146 }; 147 148 /* 149 * Rx buffer sizes for "useskbs" Free List buffers (one ingress packet pe skb 150 * buffer). We currently only support two sizes for 1500- and 9000-byte MTUs. 151 * We could easily support more but there doesn't seem to be much need for 152 * that ... 153 */ 154 #define FL_MTU_SMALL 1500 155 #define FL_MTU_LARGE 9000 156 157 static inline unsigned int fl_mtu_bufsize(struct adapter *adapter, 158 unsigned int mtu) 159 { 160 struct sge *s = &adapter->sge; 161 162 return ALIGN(s->pktshift + ETH_HLEN + VLAN_HLEN + mtu, s->fl_align); 163 } 164 165 #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL) 166 #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE) 167 168 /* 169 * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses 170 * these to specify the buffer size as an index into the SGE Free List Buffer 171 * Size register array. We also use bit 4, when the buffer has been unmapped 172 * for DMA, but this is of course never sent to the hardware and is only used 173 * to prevent double unmappings. All of the above requires that the Free List 174 * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are 175 * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal 176 * Free List Buffer alignment is 32 bytes, this works out for us ... 177 */ 178 enum { 179 RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */ 180 RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */ 181 RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */ 182 183 /* 184 * XXX We shouldn't depend on being able to use these indices. 185 * XXX Especially when some other Master PF has initialized the 186 * XXX adapter or we use the Firmware Configuration File. We 187 * XXX should really search through the Host Buffer Size register 188 * XXX array for the appropriately sized buffer indices. 189 */ 190 RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */ 191 RX_LARGE_PG_BUF = 0x1, /* buffer large (FL_PG_ORDER) page buffer */ 192 193 RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */ 194 RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */ 195 }; 196 197 static int timer_pkt_quota[] = {1, 1, 2, 3, 4, 5}; 198 #define MIN_NAPI_WORK 1 199 200 static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *d) 201 { 202 return d->dma_addr & ~(dma_addr_t)RX_BUF_FLAGS; 203 } 204 205 static inline bool is_buf_mapped(const struct rx_sw_desc *d) 206 { 207 return !(d->dma_addr & RX_UNMAPPED_BUF); 208 } 209 210 /** 211 * txq_avail - return the number of available slots in a Tx queue 212 * @q: the Tx queue 213 * 214 * Returns the number of descriptors in a Tx queue available to write new 215 * packets. 216 */ 217 static inline unsigned int txq_avail(const struct sge_txq *q) 218 { 219 return q->size - 1 - q->in_use; 220 } 221 222 /** 223 * fl_cap - return the capacity of a free-buffer list 224 * @fl: the FL 225 * 226 * Returns the capacity of a free-buffer list. The capacity is less than 227 * the size because one descriptor needs to be left unpopulated, otherwise 228 * HW will think the FL is empty. 229 */ 230 static inline unsigned int fl_cap(const struct sge_fl *fl) 231 { 232 return fl->size - 8; /* 1 descriptor = 8 buffers */ 233 } 234 235 /** 236 * fl_starving - return whether a Free List is starving. 237 * @adapter: pointer to the adapter 238 * @fl: the Free List 239 * 240 * Tests specified Free List to see whether the number of buffers 241 * available to the hardware has falled below our "starvation" 242 * threshold. 243 */ 244 static inline bool fl_starving(const struct adapter *adapter, 245 const struct sge_fl *fl) 246 { 247 const struct sge *s = &adapter->sge; 248 249 return fl->avail - fl->pend_cred <= s->fl_starve_thres; 250 } 251 252 static int map_skb(struct device *dev, const struct sk_buff *skb, 253 dma_addr_t *addr) 254 { 255 const skb_frag_t *fp, *end; 256 const struct skb_shared_info *si; 257 258 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); 259 if (dma_mapping_error(dev, *addr)) 260 goto out_err; 261 262 si = skb_shinfo(skb); 263 end = &si->frags[si->nr_frags]; 264 265 for (fp = si->frags; fp < end; fp++) { 266 *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp), 267 DMA_TO_DEVICE); 268 if (dma_mapping_error(dev, *addr)) 269 goto unwind; 270 } 271 return 0; 272 273 unwind: 274 while (fp-- > si->frags) 275 dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE); 276 277 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE); 278 out_err: 279 return -ENOMEM; 280 } 281 282 #ifdef CONFIG_NEED_DMA_MAP_STATE 283 static void unmap_skb(struct device *dev, const struct sk_buff *skb, 284 const dma_addr_t *addr) 285 { 286 const skb_frag_t *fp, *end; 287 const struct skb_shared_info *si; 288 289 dma_unmap_single(dev, *addr++, skb_headlen(skb), DMA_TO_DEVICE); 290 291 si = skb_shinfo(skb); 292 end = &si->frags[si->nr_frags]; 293 for (fp = si->frags; fp < end; fp++) 294 dma_unmap_page(dev, *addr++, skb_frag_size(fp), DMA_TO_DEVICE); 295 } 296 297 /** 298 * deferred_unmap_destructor - unmap a packet when it is freed 299 * @skb: the packet 300 * 301 * This is the packet destructor used for Tx packets that need to remain 302 * mapped until they are freed rather than until their Tx descriptors are 303 * freed. 304 */ 305 static void deferred_unmap_destructor(struct sk_buff *skb) 306 { 307 unmap_skb(skb->dev->dev.parent, skb, (dma_addr_t *)skb->head); 308 } 309 #endif 310 311 static void unmap_sgl(struct device *dev, const struct sk_buff *skb, 312 const struct ulptx_sgl *sgl, const struct sge_txq *q) 313 { 314 const struct ulptx_sge_pair *p; 315 unsigned int nfrags = skb_shinfo(skb)->nr_frags; 316 317 if (likely(skb_headlen(skb))) 318 dma_unmap_single(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0), 319 DMA_TO_DEVICE); 320 else { 321 dma_unmap_page(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0), 322 DMA_TO_DEVICE); 323 nfrags--; 324 } 325 326 /* 327 * the complexity below is because of the possibility of a wrap-around 328 * in the middle of an SGL 329 */ 330 for (p = sgl->sge; nfrags >= 2; nfrags -= 2) { 331 if (likely((u8 *)(p + 1) <= (u8 *)q->stat)) { 332 unmap: dma_unmap_page(dev, be64_to_cpu(p->addr[0]), 333 ntohl(p->len[0]), DMA_TO_DEVICE); 334 dma_unmap_page(dev, be64_to_cpu(p->addr[1]), 335 ntohl(p->len[1]), DMA_TO_DEVICE); 336 p++; 337 } else if ((u8 *)p == (u8 *)q->stat) { 338 p = (const struct ulptx_sge_pair *)q->desc; 339 goto unmap; 340 } else if ((u8 *)p + 8 == (u8 *)q->stat) { 341 const __be64 *addr = (const __be64 *)q->desc; 342 343 dma_unmap_page(dev, be64_to_cpu(addr[0]), 344 ntohl(p->len[0]), DMA_TO_DEVICE); 345 dma_unmap_page(dev, be64_to_cpu(addr[1]), 346 ntohl(p->len[1]), DMA_TO_DEVICE); 347 p = (const struct ulptx_sge_pair *)&addr[2]; 348 } else { 349 const __be64 *addr = (const __be64 *)q->desc; 350 351 dma_unmap_page(dev, be64_to_cpu(p->addr[0]), 352 ntohl(p->len[0]), DMA_TO_DEVICE); 353 dma_unmap_page(dev, be64_to_cpu(addr[0]), 354 ntohl(p->len[1]), DMA_TO_DEVICE); 355 p = (const struct ulptx_sge_pair *)&addr[1]; 356 } 357 } 358 if (nfrags) { 359 __be64 addr; 360 361 if ((u8 *)p == (u8 *)q->stat) 362 p = (const struct ulptx_sge_pair *)q->desc; 363 addr = (u8 *)p + 16 <= (u8 *)q->stat ? p->addr[0] : 364 *(const __be64 *)q->desc; 365 dma_unmap_page(dev, be64_to_cpu(addr), ntohl(p->len[0]), 366 DMA_TO_DEVICE); 367 } 368 } 369 370 /** 371 * free_tx_desc - reclaims Tx descriptors and their buffers 372 * @adapter: the adapter 373 * @q: the Tx queue to reclaim descriptors from 374 * @n: the number of descriptors to reclaim 375 * @unmap: whether the buffers should be unmapped for DMA 376 * 377 * Reclaims Tx descriptors from an SGE Tx queue and frees the associated 378 * Tx buffers. Called with the Tx queue lock held. 379 */ 380 static void free_tx_desc(struct adapter *adap, struct sge_txq *q, 381 unsigned int n, bool unmap) 382 { 383 struct tx_sw_desc *d; 384 unsigned int cidx = q->cidx; 385 struct device *dev = adap->pdev_dev; 386 387 d = &q->sdesc[cidx]; 388 while (n--) { 389 if (d->skb) { /* an SGL is present */ 390 if (unmap) 391 unmap_sgl(dev, d->skb, d->sgl, q); 392 dev_consume_skb_any(d->skb); 393 d->skb = NULL; 394 } 395 ++d; 396 if (++cidx == q->size) { 397 cidx = 0; 398 d = q->sdesc; 399 } 400 } 401 q->cidx = cidx; 402 } 403 404 /* 405 * Return the number of reclaimable descriptors in a Tx queue. 406 */ 407 static inline int reclaimable(const struct sge_txq *q) 408 { 409 int hw_cidx = ntohs(q->stat->cidx); 410 hw_cidx -= q->cidx; 411 return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx; 412 } 413 414 /** 415 * reclaim_completed_tx - reclaims completed Tx descriptors 416 * @adap: the adapter 417 * @q: the Tx queue to reclaim completed descriptors from 418 * @unmap: whether the buffers should be unmapped for DMA 419 * 420 * Reclaims Tx descriptors that the SGE has indicated it has processed, 421 * and frees the associated buffers if possible. Called with the Tx 422 * queue locked. 423 */ 424 static inline void reclaim_completed_tx(struct adapter *adap, struct sge_txq *q, 425 bool unmap) 426 { 427 int avail = reclaimable(q); 428 429 if (avail) { 430 /* 431 * Limit the amount of clean up work we do at a time to keep 432 * the Tx lock hold time O(1). 433 */ 434 if (avail > MAX_TX_RECLAIM) 435 avail = MAX_TX_RECLAIM; 436 437 free_tx_desc(adap, q, avail, unmap); 438 q->in_use -= avail; 439 } 440 } 441 442 static inline int get_buf_size(struct adapter *adapter, 443 const struct rx_sw_desc *d) 444 { 445 struct sge *s = &adapter->sge; 446 unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE; 447 int buf_size; 448 449 switch (rx_buf_size_idx) { 450 case RX_SMALL_PG_BUF: 451 buf_size = PAGE_SIZE; 452 break; 453 454 case RX_LARGE_PG_BUF: 455 buf_size = PAGE_SIZE << s->fl_pg_order; 456 break; 457 458 case RX_SMALL_MTU_BUF: 459 buf_size = FL_MTU_SMALL_BUFSIZE(adapter); 460 break; 461 462 case RX_LARGE_MTU_BUF: 463 buf_size = FL_MTU_LARGE_BUFSIZE(adapter); 464 break; 465 466 default: 467 BUG_ON(1); 468 } 469 470 return buf_size; 471 } 472 473 /** 474 * free_rx_bufs - free the Rx buffers on an SGE free list 475 * @adap: the adapter 476 * @q: the SGE free list to free buffers from 477 * @n: how many buffers to free 478 * 479 * Release the next @n buffers on an SGE free-buffer Rx queue. The 480 * buffers must be made inaccessible to HW before calling this function. 481 */ 482 static void free_rx_bufs(struct adapter *adap, struct sge_fl *q, int n) 483 { 484 while (n--) { 485 struct rx_sw_desc *d = &q->sdesc[q->cidx]; 486 487 if (is_buf_mapped(d)) 488 dma_unmap_page(adap->pdev_dev, get_buf_addr(d), 489 get_buf_size(adap, d), 490 PCI_DMA_FROMDEVICE); 491 put_page(d->page); 492 d->page = NULL; 493 if (++q->cidx == q->size) 494 q->cidx = 0; 495 q->avail--; 496 } 497 } 498 499 /** 500 * unmap_rx_buf - unmap the current Rx buffer on an SGE free list 501 * @adap: the adapter 502 * @q: the SGE free list 503 * 504 * Unmap the current buffer on an SGE free-buffer Rx queue. The 505 * buffer must be made inaccessible to HW before calling this function. 506 * 507 * This is similar to @free_rx_bufs above but does not free the buffer. 508 * Do note that the FL still loses any further access to the buffer. 509 */ 510 static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q) 511 { 512 struct rx_sw_desc *d = &q->sdesc[q->cidx]; 513 514 if (is_buf_mapped(d)) 515 dma_unmap_page(adap->pdev_dev, get_buf_addr(d), 516 get_buf_size(adap, d), PCI_DMA_FROMDEVICE); 517 d->page = NULL; 518 if (++q->cidx == q->size) 519 q->cidx = 0; 520 q->avail--; 521 } 522 523 static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) 524 { 525 if (q->pend_cred >= 8) { 526 u32 val = adap->params.arch.sge_fl_db; 527 528 if (is_t4(adap->params.chip)) 529 val |= PIDX_V(q->pend_cred / 8); 530 else 531 val |= PIDX_T5_V(q->pend_cred / 8); 532 533 /* Make sure all memory writes to the Free List queue are 534 * committed before we tell the hardware about them. 535 */ 536 wmb(); 537 538 /* If we don't have access to the new User Doorbell (T5+), use 539 * the old doorbell mechanism; otherwise use the new BAR2 540 * mechanism. 541 */ 542 if (unlikely(q->bar2_addr == NULL)) { 543 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 544 val | QID_V(q->cntxt_id)); 545 } else { 546 writel(val | QID_V(q->bar2_qid), 547 q->bar2_addr + SGE_UDB_KDOORBELL); 548 549 /* This Write memory Barrier will force the write to 550 * the User Doorbell area to be flushed. 551 */ 552 wmb(); 553 } 554 q->pend_cred &= 7; 555 } 556 } 557 558 static inline void set_rx_sw_desc(struct rx_sw_desc *sd, struct page *pg, 559 dma_addr_t mapping) 560 { 561 sd->page = pg; 562 sd->dma_addr = mapping; /* includes size low bits */ 563 } 564 565 /** 566 * refill_fl - refill an SGE Rx buffer ring 567 * @adap: the adapter 568 * @q: the ring to refill 569 * @n: the number of new buffers to allocate 570 * @gfp: the gfp flags for the allocations 571 * 572 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers, 573 * allocated with the supplied gfp flags. The caller must assure that 574 * @n does not exceed the queue's capacity. If afterwards the queue is 575 * found critically low mark it as starving in the bitmap of starving FLs. 576 * 577 * Returns the number of buffers allocated. 578 */ 579 static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n, 580 gfp_t gfp) 581 { 582 struct sge *s = &adap->sge; 583 struct page *pg; 584 dma_addr_t mapping; 585 unsigned int cred = q->avail; 586 __be64 *d = &q->desc[q->pidx]; 587 struct rx_sw_desc *sd = &q->sdesc[q->pidx]; 588 int node; 589 590 #ifdef CONFIG_DEBUG_FS 591 if (test_bit(q->cntxt_id - adap->sge.egr_start, adap->sge.blocked_fl)) 592 goto out; 593 #endif 594 595 gfp |= __GFP_NOWARN; 596 node = dev_to_node(adap->pdev_dev); 597 598 if (s->fl_pg_order == 0) 599 goto alloc_small_pages; 600 601 /* 602 * Prefer large buffers 603 */ 604 while (n) { 605 pg = alloc_pages_node(node, gfp | __GFP_COMP, s->fl_pg_order); 606 if (unlikely(!pg)) { 607 q->large_alloc_failed++; 608 break; /* fall back to single pages */ 609 } 610 611 mapping = dma_map_page(adap->pdev_dev, pg, 0, 612 PAGE_SIZE << s->fl_pg_order, 613 PCI_DMA_FROMDEVICE); 614 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { 615 __free_pages(pg, s->fl_pg_order); 616 goto out; /* do not try small pages for this error */ 617 } 618 mapping |= RX_LARGE_PG_BUF; 619 *d++ = cpu_to_be64(mapping); 620 621 set_rx_sw_desc(sd, pg, mapping); 622 sd++; 623 624 q->avail++; 625 if (++q->pidx == q->size) { 626 q->pidx = 0; 627 sd = q->sdesc; 628 d = q->desc; 629 } 630 n--; 631 } 632 633 alloc_small_pages: 634 while (n--) { 635 pg = alloc_pages_node(node, gfp, 0); 636 if (unlikely(!pg)) { 637 q->alloc_failed++; 638 break; 639 } 640 641 mapping = dma_map_page(adap->pdev_dev, pg, 0, PAGE_SIZE, 642 PCI_DMA_FROMDEVICE); 643 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { 644 put_page(pg); 645 goto out; 646 } 647 *d++ = cpu_to_be64(mapping); 648 649 set_rx_sw_desc(sd, pg, mapping); 650 sd++; 651 652 q->avail++; 653 if (++q->pidx == q->size) { 654 q->pidx = 0; 655 sd = q->sdesc; 656 d = q->desc; 657 } 658 } 659 660 out: cred = q->avail - cred; 661 q->pend_cred += cred; 662 ring_fl_db(adap, q); 663 664 if (unlikely(fl_starving(adap, q))) { 665 smp_wmb(); 666 set_bit(q->cntxt_id - adap->sge.egr_start, 667 adap->sge.starving_fl); 668 } 669 670 return cred; 671 } 672 673 static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl) 674 { 675 refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail), 676 GFP_ATOMIC); 677 } 678 679 /** 680 * alloc_ring - allocate resources for an SGE descriptor ring 681 * @dev: the PCI device's core device 682 * @nelem: the number of descriptors 683 * @elem_size: the size of each descriptor 684 * @sw_size: the size of the SW state associated with each ring element 685 * @phys: the physical address of the allocated ring 686 * @metadata: address of the array holding the SW state for the ring 687 * @stat_size: extra space in HW ring for status information 688 * @node: preferred node for memory allocations 689 * 690 * Allocates resources for an SGE descriptor ring, such as Tx queues, 691 * free buffer lists, or response queues. Each SGE ring requires 692 * space for its HW descriptors plus, optionally, space for the SW state 693 * associated with each HW entry (the metadata). The function returns 694 * three values: the virtual address for the HW ring (the return value 695 * of the function), the bus address of the HW ring, and the address 696 * of the SW ring. 697 */ 698 static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size, 699 size_t sw_size, dma_addr_t *phys, void *metadata, 700 size_t stat_size, int node) 701 { 702 size_t len = nelem * elem_size + stat_size; 703 void *s = NULL; 704 void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL); 705 706 if (!p) 707 return NULL; 708 if (sw_size) { 709 s = kzalloc_node(nelem * sw_size, GFP_KERNEL, node); 710 711 if (!s) { 712 dma_free_coherent(dev, len, p, *phys); 713 return NULL; 714 } 715 } 716 if (metadata) 717 *(void **)metadata = s; 718 memset(p, 0, len); 719 return p; 720 } 721 722 /** 723 * sgl_len - calculates the size of an SGL of the given capacity 724 * @n: the number of SGL entries 725 * 726 * Calculates the number of flits needed for a scatter/gather list that 727 * can hold the given number of entries. 728 */ 729 static inline unsigned int sgl_len(unsigned int n) 730 { 731 /* A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA 732 * addresses. The DSGL Work Request starts off with a 32-bit DSGL 733 * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N, 734 * repeated sequences of { Length[i], Length[i+1], Address[i], 735 * Address[i+1] } (this ensures that all addresses are on 64-bit 736 * boundaries). If N is even, then Length[N+1] should be set to 0 and 737 * Address[N+1] is omitted. 738 * 739 * The following calculation incorporates all of the above. It's 740 * somewhat hard to follow but, briefly: the "+2" accounts for the 741 * first two flits which include the DSGL header, Length0 and 742 * Address0; the "(3*(n-1))/2" covers the main body of list entries (3 743 * flits for every pair of the remaining N) +1 if (n-1) is odd; and 744 * finally the "+((n-1)&1)" adds the one remaining flit needed if 745 * (n-1) is odd ... 746 */ 747 n--; 748 return (3 * n) / 2 + (n & 1) + 2; 749 } 750 751 /** 752 * flits_to_desc - returns the num of Tx descriptors for the given flits 753 * @n: the number of flits 754 * 755 * Returns the number of Tx descriptors needed for the supplied number 756 * of flits. 757 */ 758 static inline unsigned int flits_to_desc(unsigned int n) 759 { 760 BUG_ON(n > SGE_MAX_WR_LEN / 8); 761 return DIV_ROUND_UP(n, 8); 762 } 763 764 /** 765 * is_eth_imm - can an Ethernet packet be sent as immediate data? 766 * @skb: the packet 767 * 768 * Returns whether an Ethernet packet is small enough to fit as 769 * immediate data. Return value corresponds to headroom required. 770 */ 771 static inline int is_eth_imm(const struct sk_buff *skb) 772 { 773 int hdrlen = skb_shinfo(skb)->gso_size ? 774 sizeof(struct cpl_tx_pkt_lso_core) : 0; 775 776 hdrlen += sizeof(struct cpl_tx_pkt); 777 if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen) 778 return hdrlen; 779 return 0; 780 } 781 782 /** 783 * calc_tx_flits - calculate the number of flits for a packet Tx WR 784 * @skb: the packet 785 * 786 * Returns the number of flits needed for a Tx WR for the given Ethernet 787 * packet, including the needed WR and CPL headers. 788 */ 789 static inline unsigned int calc_tx_flits(const struct sk_buff *skb) 790 { 791 unsigned int flits; 792 int hdrlen = is_eth_imm(skb); 793 794 /* If the skb is small enough, we can pump it out as a work request 795 * with only immediate data. In that case we just have to have the 796 * TX Packet header plus the skb data in the Work Request. 797 */ 798 799 if (hdrlen) 800 return DIV_ROUND_UP(skb->len + hdrlen, sizeof(__be64)); 801 802 /* Otherwise, we're going to have to construct a Scatter gather list 803 * of the skb body and fragments. We also include the flits necessary 804 * for the TX Packet Work Request and CPL. We always have a firmware 805 * Write Header (incorporated as part of the cpl_tx_pkt_lso and 806 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL 807 * message or, if we're doing a Large Send Offload, an LSO CPL message 808 * with an embedded TX Packet Write CPL message. 809 */ 810 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1); 811 if (skb_shinfo(skb)->gso_size) 812 flits += (sizeof(struct fw_eth_tx_pkt_wr) + 813 sizeof(struct cpl_tx_pkt_lso_core) + 814 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64); 815 else 816 flits += (sizeof(struct fw_eth_tx_pkt_wr) + 817 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64); 818 return flits; 819 } 820 821 /** 822 * calc_tx_descs - calculate the number of Tx descriptors for a packet 823 * @skb: the packet 824 * 825 * Returns the number of Tx descriptors needed for the given Ethernet 826 * packet, including the needed WR and CPL headers. 827 */ 828 static inline unsigned int calc_tx_descs(const struct sk_buff *skb) 829 { 830 return flits_to_desc(calc_tx_flits(skb)); 831 } 832 833 /** 834 * write_sgl - populate a scatter/gather list for a packet 835 * @skb: the packet 836 * @q: the Tx queue we are writing into 837 * @sgl: starting location for writing the SGL 838 * @end: points right after the end of the SGL 839 * @start: start offset into skb main-body data to include in the SGL 840 * @addr: the list of bus addresses for the SGL elements 841 * 842 * Generates a gather list for the buffers that make up a packet. 843 * The caller must provide adequate space for the SGL that will be written. 844 * The SGL includes all of the packet's page fragments and the data in its 845 * main body except for the first @start bytes. @sgl must be 16-byte 846 * aligned and within a Tx descriptor with available space. @end points 847 * right after the end of the SGL but does not account for any potential 848 * wrap around, i.e., @end > @sgl. 849 */ 850 static void write_sgl(const struct sk_buff *skb, struct sge_txq *q, 851 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 852 const dma_addr_t *addr) 853 { 854 unsigned int i, len; 855 struct ulptx_sge_pair *to; 856 const struct skb_shared_info *si = skb_shinfo(skb); 857 unsigned int nfrags = si->nr_frags; 858 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1]; 859 860 len = skb_headlen(skb) - start; 861 if (likely(len)) { 862 sgl->len0 = htonl(len); 863 sgl->addr0 = cpu_to_be64(addr[0] + start); 864 nfrags++; 865 } else { 866 sgl->len0 = htonl(skb_frag_size(&si->frags[0])); 867 sgl->addr0 = cpu_to_be64(addr[1]); 868 } 869 870 sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) | 871 ULPTX_NSGE_V(nfrags)); 872 if (likely(--nfrags == 0)) 873 return; 874 /* 875 * Most of the complexity below deals with the possibility we hit the 876 * end of the queue in the middle of writing the SGL. For this case 877 * only we create the SGL in a temporary buffer and then copy it. 878 */ 879 to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge; 880 881 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) { 882 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i])); 883 to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i])); 884 to->addr[0] = cpu_to_be64(addr[i]); 885 to->addr[1] = cpu_to_be64(addr[++i]); 886 } 887 if (nfrags) { 888 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i])); 889 to->len[1] = cpu_to_be32(0); 890 to->addr[0] = cpu_to_be64(addr[i + 1]); 891 } 892 if (unlikely((u8 *)end > (u8 *)q->stat)) { 893 unsigned int part0 = (u8 *)q->stat - (u8 *)sgl->sge, part1; 894 895 if (likely(part0)) 896 memcpy(sgl->sge, buf, part0); 897 part1 = (u8 *)end - (u8 *)q->stat; 898 memcpy(q->desc, (u8 *)buf + part0, part1); 899 end = (void *)q->desc + part1; 900 } 901 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */ 902 *end = 0; 903 } 904 905 /* This function copies 64 byte coalesced work request to 906 * memory mapped BAR2 space. For coalesced WR SGE fetches 907 * data from the FIFO instead of from Host. 908 */ 909 static void cxgb_pio_copy(u64 __iomem *dst, u64 *src) 910 { 911 int count = 8; 912 913 while (count) { 914 writeq(*src, dst); 915 src++; 916 dst++; 917 count--; 918 } 919 } 920 921 /** 922 * ring_tx_db - check and potentially ring a Tx queue's doorbell 923 * @adap: the adapter 924 * @q: the Tx queue 925 * @n: number of new descriptors to give to HW 926 * 927 * Ring the doorbel for a Tx queue. 928 */ 929 static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) 930 { 931 /* Make sure that all writes to the TX Descriptors are committed 932 * before we tell the hardware about them. 933 */ 934 wmb(); 935 936 /* If we don't have access to the new User Doorbell (T5+), use the old 937 * doorbell mechanism; otherwise use the new BAR2 mechanism. 938 */ 939 if (unlikely(q->bar2_addr == NULL)) { 940 u32 val = PIDX_V(n); 941 unsigned long flags; 942 943 /* For T4 we need to participate in the Doorbell Recovery 944 * mechanism. 945 */ 946 spin_lock_irqsave(&q->db_lock, flags); 947 if (!q->db_disabled) 948 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 949 QID_V(q->cntxt_id) | val); 950 else 951 q->db_pidx_inc += n; 952 q->db_pidx = q->pidx; 953 spin_unlock_irqrestore(&q->db_lock, flags); 954 } else { 955 u32 val = PIDX_T5_V(n); 956 957 /* T4 and later chips share the same PIDX field offset within 958 * the doorbell, but T5 and later shrank the field in order to 959 * gain a bit for Doorbell Priority. The field was absurdly 960 * large in the first place (14 bits) so we just use the T5 961 * and later limits and warn if a Queue ID is too large. 962 */ 963 WARN_ON(val & DBPRIO_F); 964 965 /* If we're only writing a single TX Descriptor and we can use 966 * Inferred QID registers, we can use the Write Combining 967 * Gather Buffer; otherwise we use the simple doorbell. 968 */ 969 if (n == 1 && q->bar2_qid == 0) { 970 int index = (q->pidx 971 ? (q->pidx - 1) 972 : (q->size - 1)); 973 u64 *wr = (u64 *)&q->desc[index]; 974 975 cxgb_pio_copy((u64 __iomem *) 976 (q->bar2_addr + SGE_UDB_WCDOORBELL), 977 wr); 978 } else { 979 writel(val | QID_V(q->bar2_qid), 980 q->bar2_addr + SGE_UDB_KDOORBELL); 981 } 982 983 /* This Write Memory Barrier will force the write to the User 984 * Doorbell area to be flushed. This is needed to prevent 985 * writes on different CPUs for the same queue from hitting 986 * the adapter out of order. This is required when some Work 987 * Requests take the Write Combine Gather Buffer path (user 988 * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some 989 * take the traditional path where we simply increment the 990 * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the 991 * hardware DMA read the actual Work Request. 992 */ 993 wmb(); 994 } 995 } 996 997 /** 998 * inline_tx_skb - inline a packet's data into Tx descriptors 999 * @skb: the packet 1000 * @q: the Tx queue where the packet will be inlined 1001 * @pos: starting position in the Tx queue where to inline the packet 1002 * 1003 * Inline a packet's contents directly into Tx descriptors, starting at 1004 * the given position within the Tx DMA ring. 1005 * Most of the complexity of this operation is dealing with wrap arounds 1006 * in the middle of the packet we want to inline. 1007 */ 1008 static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1009 void *pos) 1010 { 1011 u64 *p; 1012 int left = (void *)q->stat - pos; 1013 1014 if (likely(skb->len <= left)) { 1015 if (likely(!skb->data_len)) 1016 skb_copy_from_linear_data(skb, pos, skb->len); 1017 else 1018 skb_copy_bits(skb, 0, pos, skb->len); 1019 pos += skb->len; 1020 } else { 1021 skb_copy_bits(skb, 0, pos, left); 1022 skb_copy_bits(skb, left, q->desc, skb->len - left); 1023 pos = (void *)q->desc + (skb->len - left); 1024 } 1025 1026 /* 0-pad to multiple of 16 */ 1027 p = PTR_ALIGN(pos, 8); 1028 if ((uintptr_t)p & 8) 1029 *p = 0; 1030 } 1031 1032 /* 1033 * Figure out what HW csum a packet wants and return the appropriate control 1034 * bits. 1035 */ 1036 static u64 hwcsum(enum chip_type chip, const struct sk_buff *skb) 1037 { 1038 int csum_type; 1039 const struct iphdr *iph = ip_hdr(skb); 1040 1041 if (iph->version == 4) { 1042 if (iph->protocol == IPPROTO_TCP) 1043 csum_type = TX_CSUM_TCPIP; 1044 else if (iph->protocol == IPPROTO_UDP) 1045 csum_type = TX_CSUM_UDPIP; 1046 else { 1047 nocsum: /* 1048 * unknown protocol, disable HW csum 1049 * and hope a bad packet is detected 1050 */ 1051 return TXPKT_L4CSUM_DIS_F; 1052 } 1053 } else { 1054 /* 1055 * this doesn't work with extension headers 1056 */ 1057 const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph; 1058 1059 if (ip6h->nexthdr == IPPROTO_TCP) 1060 csum_type = TX_CSUM_TCPIP6; 1061 else if (ip6h->nexthdr == IPPROTO_UDP) 1062 csum_type = TX_CSUM_UDPIP6; 1063 else 1064 goto nocsum; 1065 } 1066 1067 if (likely(csum_type >= TX_CSUM_TCPIP)) { 1068 u64 hdr_len = TXPKT_IPHDR_LEN_V(skb_network_header_len(skb)); 1069 int eth_hdr_len = skb_network_offset(skb) - ETH_HLEN; 1070 1071 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 1072 hdr_len |= TXPKT_ETHHDR_LEN_V(eth_hdr_len); 1073 else 1074 hdr_len |= T6_TXPKT_ETHHDR_LEN_V(eth_hdr_len); 1075 return TXPKT_CSUM_TYPE_V(csum_type) | hdr_len; 1076 } else { 1077 int start = skb_transport_offset(skb); 1078 1079 return TXPKT_CSUM_TYPE_V(csum_type) | 1080 TXPKT_CSUM_START_V(start) | 1081 TXPKT_CSUM_LOC_V(start + skb->csum_offset); 1082 } 1083 } 1084 1085 static void eth_txq_stop(struct sge_eth_txq *q) 1086 { 1087 netif_tx_stop_queue(q->txq); 1088 q->q.stops++; 1089 } 1090 1091 static inline void txq_advance(struct sge_txq *q, unsigned int n) 1092 { 1093 q->in_use += n; 1094 q->pidx += n; 1095 if (q->pidx >= q->size) 1096 q->pidx -= q->size; 1097 } 1098 1099 #ifdef CONFIG_CHELSIO_T4_FCOE 1100 static inline int 1101 cxgb_fcoe_offload(struct sk_buff *skb, struct adapter *adap, 1102 const struct port_info *pi, u64 *cntrl) 1103 { 1104 const struct cxgb_fcoe *fcoe = &pi->fcoe; 1105 1106 if (!(fcoe->flags & CXGB_FCOE_ENABLED)) 1107 return 0; 1108 1109 if (skb->protocol != htons(ETH_P_FCOE)) 1110 return 0; 1111 1112 skb_reset_mac_header(skb); 1113 skb->mac_len = sizeof(struct ethhdr); 1114 1115 skb_set_network_header(skb, skb->mac_len); 1116 skb_set_transport_header(skb, skb->mac_len + sizeof(struct fcoe_hdr)); 1117 1118 if (!cxgb_fcoe_sof_eof_supported(adap, skb)) 1119 return -ENOTSUPP; 1120 1121 /* FC CRC offload */ 1122 *cntrl = TXPKT_CSUM_TYPE_V(TX_CSUM_FCOE) | 1123 TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F | 1124 TXPKT_CSUM_START_V(CXGB_FCOE_TXPKT_CSUM_START) | 1125 TXPKT_CSUM_END_V(CXGB_FCOE_TXPKT_CSUM_END) | 1126 TXPKT_CSUM_LOC_V(CXGB_FCOE_TXPKT_CSUM_END); 1127 return 0; 1128 } 1129 #endif /* CONFIG_CHELSIO_T4_FCOE */ 1130 1131 /** 1132 * t4_eth_xmit - add a packet to an Ethernet Tx queue 1133 * @skb: the packet 1134 * @dev: the egress net device 1135 * 1136 * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled. 1137 */ 1138 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev) 1139 { 1140 u32 wr_mid, ctrl0; 1141 u64 cntrl, *end; 1142 int qidx, credits; 1143 unsigned int flits, ndesc; 1144 struct adapter *adap; 1145 struct sge_eth_txq *q; 1146 const struct port_info *pi; 1147 struct fw_eth_tx_pkt_wr *wr; 1148 struct cpl_tx_pkt_core *cpl; 1149 const struct skb_shared_info *ssi; 1150 dma_addr_t addr[MAX_SKB_FRAGS + 1]; 1151 bool immediate = false; 1152 int len, max_pkt_len; 1153 #ifdef CONFIG_CHELSIO_T4_FCOE 1154 int err; 1155 #endif /* CONFIG_CHELSIO_T4_FCOE */ 1156 1157 /* 1158 * The chip min packet length is 10 octets but play safe and reject 1159 * anything shorter than an Ethernet header. 1160 */ 1161 if (unlikely(skb->len < ETH_HLEN)) { 1162 out_free: dev_kfree_skb_any(skb); 1163 return NETDEV_TX_OK; 1164 } 1165 1166 /* Discard the packet if the length is greater than mtu */ 1167 max_pkt_len = ETH_HLEN + dev->mtu; 1168 if (skb_vlan_tag_present(skb)) 1169 max_pkt_len += VLAN_HLEN; 1170 if (!skb_shinfo(skb)->gso_size && (unlikely(skb->len > max_pkt_len))) 1171 goto out_free; 1172 1173 pi = netdev_priv(dev); 1174 adap = pi->adapter; 1175 qidx = skb_get_queue_mapping(skb); 1176 q = &adap->sge.ethtxq[qidx + pi->first_qset]; 1177 1178 reclaim_completed_tx(adap, &q->q, true); 1179 cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F; 1180 1181 #ifdef CONFIG_CHELSIO_T4_FCOE 1182 err = cxgb_fcoe_offload(skb, adap, pi, &cntrl); 1183 if (unlikely(err == -ENOTSUPP)) 1184 goto out_free; 1185 #endif /* CONFIG_CHELSIO_T4_FCOE */ 1186 1187 flits = calc_tx_flits(skb); 1188 ndesc = flits_to_desc(flits); 1189 credits = txq_avail(&q->q) - ndesc; 1190 1191 if (unlikely(credits < 0)) { 1192 eth_txq_stop(q); 1193 dev_err(adap->pdev_dev, 1194 "%s: Tx ring %u full while queue awake!\n", 1195 dev->name, qidx); 1196 return NETDEV_TX_BUSY; 1197 } 1198 1199 if (is_eth_imm(skb)) 1200 immediate = true; 1201 1202 if (!immediate && 1203 unlikely(map_skb(adap->pdev_dev, skb, addr) < 0)) { 1204 q->mapping_err++; 1205 goto out_free; 1206 } 1207 1208 wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2)); 1209 if (unlikely(credits < ETHTXQ_STOP_THRES)) { 1210 eth_txq_stop(q); 1211 wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F; 1212 } 1213 1214 wr = (void *)&q->q.desc[q->q.pidx]; 1215 wr->equiq_to_len16 = htonl(wr_mid); 1216 wr->r3 = cpu_to_be64(0); 1217 end = (u64 *)wr + flits; 1218 1219 len = immediate ? skb->len : 0; 1220 ssi = skb_shinfo(skb); 1221 if (ssi->gso_size) { 1222 struct cpl_tx_pkt_lso *lso = (void *)wr; 1223 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0; 1224 int l3hdr_len = skb_network_header_len(skb); 1225 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN; 1226 1227 len += sizeof(*lso); 1228 wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) | 1229 FW_WR_IMMDLEN_V(len)); 1230 lso->c.lso_ctrl = htonl(LSO_OPCODE_V(CPL_TX_PKT_LSO) | 1231 LSO_FIRST_SLICE_F | LSO_LAST_SLICE_F | 1232 LSO_IPV6_V(v6) | 1233 LSO_ETHHDR_LEN_V(eth_xtra_len / 4) | 1234 LSO_IPHDR_LEN_V(l3hdr_len / 4) | 1235 LSO_TCPHDR_LEN_V(tcp_hdr(skb)->doff)); 1236 lso->c.ipid_ofst = htons(0); 1237 lso->c.mss = htons(ssi->gso_size); 1238 lso->c.seqno_offset = htonl(0); 1239 if (is_t4(adap->params.chip)) 1240 lso->c.len = htonl(skb->len); 1241 else 1242 lso->c.len = htonl(LSO_T5_XFER_SIZE_V(skb->len)); 1243 cpl = (void *)(lso + 1); 1244 1245 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 1246 cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len); 1247 else 1248 cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len); 1249 1250 cntrl |= TXPKT_CSUM_TYPE_V(v6 ? 1251 TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) | 1252 TXPKT_IPHDR_LEN_V(l3hdr_len); 1253 q->tso++; 1254 q->tx_cso += ssi->gso_segs; 1255 } else { 1256 len += sizeof(*cpl); 1257 wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) | 1258 FW_WR_IMMDLEN_V(len)); 1259 cpl = (void *)(wr + 1); 1260 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1261 cntrl = hwcsum(adap->params.chip, skb) | 1262 TXPKT_IPCSUM_DIS_F; 1263 q->tx_cso++; 1264 } 1265 } 1266 1267 if (skb_vlan_tag_present(skb)) { 1268 q->vlan_ins++; 1269 cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb)); 1270 #ifdef CONFIG_CHELSIO_T4_FCOE 1271 if (skb->protocol == htons(ETH_P_FCOE)) 1272 cntrl |= TXPKT_VLAN_V( 1273 ((skb->priority & 0x7) << VLAN_PRIO_SHIFT)); 1274 #endif /* CONFIG_CHELSIO_T4_FCOE */ 1275 } 1276 1277 ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) | 1278 TXPKT_PF_V(adap->pf); 1279 #ifdef CONFIG_CHELSIO_T4_DCB 1280 if (is_t4(adap->params.chip)) 1281 ctrl0 |= TXPKT_OVLAN_IDX_V(q->dcb_prio); 1282 else 1283 ctrl0 |= TXPKT_T5_OVLAN_IDX_V(q->dcb_prio); 1284 #endif 1285 cpl->ctrl0 = htonl(ctrl0); 1286 cpl->pack = htons(0); 1287 cpl->len = htons(skb->len); 1288 cpl->ctrl1 = cpu_to_be64(cntrl); 1289 1290 if (immediate) { 1291 inline_tx_skb(skb, &q->q, cpl + 1); 1292 dev_consume_skb_any(skb); 1293 } else { 1294 int last_desc; 1295 1296 write_sgl(skb, &q->q, (struct ulptx_sgl *)(cpl + 1), end, 0, 1297 addr); 1298 skb_orphan(skb); 1299 1300 last_desc = q->q.pidx + ndesc - 1; 1301 if (last_desc >= q->q.size) 1302 last_desc -= q->q.size; 1303 q->q.sdesc[last_desc].skb = skb; 1304 q->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1); 1305 } 1306 1307 txq_advance(&q->q, ndesc); 1308 1309 ring_tx_db(adap, &q->q, ndesc); 1310 return NETDEV_TX_OK; 1311 } 1312 1313 /** 1314 * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs 1315 * @q: the SGE control Tx queue 1316 * 1317 * This is a variant of reclaim_completed_tx() that is used for Tx queues 1318 * that send only immediate data (presently just the control queues) and 1319 * thus do not have any sk_buffs to release. 1320 */ 1321 static inline void reclaim_completed_tx_imm(struct sge_txq *q) 1322 { 1323 int hw_cidx = ntohs(q->stat->cidx); 1324 int reclaim = hw_cidx - q->cidx; 1325 1326 if (reclaim < 0) 1327 reclaim += q->size; 1328 1329 q->in_use -= reclaim; 1330 q->cidx = hw_cidx; 1331 } 1332 1333 /** 1334 * is_imm - check whether a packet can be sent as immediate data 1335 * @skb: the packet 1336 * 1337 * Returns true if a packet can be sent as a WR with immediate data. 1338 */ 1339 static inline int is_imm(const struct sk_buff *skb) 1340 { 1341 return skb->len <= MAX_CTRL_WR_LEN; 1342 } 1343 1344 /** 1345 * ctrlq_check_stop - check if a control queue is full and should stop 1346 * @q: the queue 1347 * @wr: most recent WR written to the queue 1348 * 1349 * Check if a control queue has become full and should be stopped. 1350 * We clean up control queue descriptors very lazily, only when we are out. 1351 * If the queue is still full after reclaiming any completed descriptors 1352 * we suspend it and have the last WR wake it up. 1353 */ 1354 static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr) 1355 { 1356 reclaim_completed_tx_imm(&q->q); 1357 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { 1358 wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F); 1359 q->q.stops++; 1360 q->full = 1; 1361 } 1362 } 1363 1364 /** 1365 * ctrl_xmit - send a packet through an SGE control Tx queue 1366 * @q: the control queue 1367 * @skb: the packet 1368 * 1369 * Send a packet through an SGE control Tx queue. Packets sent through 1370 * a control queue must fit entirely as immediate data. 1371 */ 1372 static int ctrl_xmit(struct sge_ctrl_txq *q, struct sk_buff *skb) 1373 { 1374 unsigned int ndesc; 1375 struct fw_wr_hdr *wr; 1376 1377 if (unlikely(!is_imm(skb))) { 1378 WARN_ON(1); 1379 dev_kfree_skb(skb); 1380 return NET_XMIT_DROP; 1381 } 1382 1383 ndesc = DIV_ROUND_UP(skb->len, sizeof(struct tx_desc)); 1384 spin_lock(&q->sendq.lock); 1385 1386 if (unlikely(q->full)) { 1387 skb->priority = ndesc; /* save for restart */ 1388 __skb_queue_tail(&q->sendq, skb); 1389 spin_unlock(&q->sendq.lock); 1390 return NET_XMIT_CN; 1391 } 1392 1393 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx]; 1394 inline_tx_skb(skb, &q->q, wr); 1395 1396 txq_advance(&q->q, ndesc); 1397 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) 1398 ctrlq_check_stop(q, wr); 1399 1400 ring_tx_db(q->adap, &q->q, ndesc); 1401 spin_unlock(&q->sendq.lock); 1402 1403 kfree_skb(skb); 1404 return NET_XMIT_SUCCESS; 1405 } 1406 1407 /** 1408 * restart_ctrlq - restart a suspended control queue 1409 * @data: the control queue to restart 1410 * 1411 * Resumes transmission on a suspended Tx control queue. 1412 */ 1413 static void restart_ctrlq(unsigned long data) 1414 { 1415 struct sk_buff *skb; 1416 unsigned int written = 0; 1417 struct sge_ctrl_txq *q = (struct sge_ctrl_txq *)data; 1418 1419 spin_lock(&q->sendq.lock); 1420 reclaim_completed_tx_imm(&q->q); 1421 BUG_ON(txq_avail(&q->q) < TXQ_STOP_THRES); /* q should be empty */ 1422 1423 while ((skb = __skb_dequeue(&q->sendq)) != NULL) { 1424 struct fw_wr_hdr *wr; 1425 unsigned int ndesc = skb->priority; /* previously saved */ 1426 1427 written += ndesc; 1428 /* Write descriptors and free skbs outside the lock to limit 1429 * wait times. q->full is still set so new skbs will be queued. 1430 */ 1431 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx]; 1432 txq_advance(&q->q, ndesc); 1433 spin_unlock(&q->sendq.lock); 1434 1435 inline_tx_skb(skb, &q->q, wr); 1436 kfree_skb(skb); 1437 1438 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { 1439 unsigned long old = q->q.stops; 1440 1441 ctrlq_check_stop(q, wr); 1442 if (q->q.stops != old) { /* suspended anew */ 1443 spin_lock(&q->sendq.lock); 1444 goto ringdb; 1445 } 1446 } 1447 if (written > 16) { 1448 ring_tx_db(q->adap, &q->q, written); 1449 written = 0; 1450 } 1451 spin_lock(&q->sendq.lock); 1452 } 1453 q->full = 0; 1454 ringdb: if (written) 1455 ring_tx_db(q->adap, &q->q, written); 1456 spin_unlock(&q->sendq.lock); 1457 } 1458 1459 /** 1460 * t4_mgmt_tx - send a management message 1461 * @adap: the adapter 1462 * @skb: the packet containing the management message 1463 * 1464 * Send a management message through control queue 0. 1465 */ 1466 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb) 1467 { 1468 int ret; 1469 1470 local_bh_disable(); 1471 ret = ctrl_xmit(&adap->sge.ctrlq[0], skb); 1472 local_bh_enable(); 1473 return ret; 1474 } 1475 1476 /** 1477 * is_ofld_imm - check whether a packet can be sent as immediate data 1478 * @skb: the packet 1479 * 1480 * Returns true if a packet can be sent as an offload WR with immediate 1481 * data. We currently use the same limit as for Ethernet packets. 1482 */ 1483 static inline int is_ofld_imm(const struct sk_buff *skb) 1484 { 1485 return skb->len <= MAX_IMM_TX_PKT_LEN; 1486 } 1487 1488 /** 1489 * calc_tx_flits_ofld - calculate # of flits for an offload packet 1490 * @skb: the packet 1491 * 1492 * Returns the number of flits needed for the given offload packet. 1493 * These packets are already fully constructed and no additional headers 1494 * will be added. 1495 */ 1496 static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb) 1497 { 1498 unsigned int flits, cnt; 1499 1500 if (is_ofld_imm(skb)) 1501 return DIV_ROUND_UP(skb->len, 8); 1502 1503 flits = skb_transport_offset(skb) / 8U; /* headers */ 1504 cnt = skb_shinfo(skb)->nr_frags; 1505 if (skb_tail_pointer(skb) != skb_transport_header(skb)) 1506 cnt++; 1507 return flits + sgl_len(cnt); 1508 } 1509 1510 /** 1511 * txq_stop_maperr - stop a Tx queue due to I/O MMU exhaustion 1512 * @adap: the adapter 1513 * @q: the queue to stop 1514 * 1515 * Mark a Tx queue stopped due to I/O MMU exhaustion and resulting 1516 * inability to map packets. A periodic timer attempts to restart 1517 * queues so marked. 1518 */ 1519 static void txq_stop_maperr(struct sge_ofld_txq *q) 1520 { 1521 q->mapping_err++; 1522 q->q.stops++; 1523 set_bit(q->q.cntxt_id - q->adap->sge.egr_start, 1524 q->adap->sge.txq_maperr); 1525 } 1526 1527 /** 1528 * ofldtxq_stop - stop an offload Tx queue that has become full 1529 * @q: the queue to stop 1530 * @skb: the packet causing the queue to become full 1531 * 1532 * Stops an offload Tx queue that has become full and modifies the packet 1533 * being written to request a wakeup. 1534 */ 1535 static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb) 1536 { 1537 struct fw_wr_hdr *wr = (struct fw_wr_hdr *)skb->data; 1538 1539 wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F); 1540 q->q.stops++; 1541 q->full = 1; 1542 } 1543 1544 /** 1545 * service_ofldq - restart a suspended offload queue 1546 * @q: the offload queue 1547 * 1548 * Services an offload Tx queue by moving packets from its packet queue 1549 * to the HW Tx ring. The function starts and ends with the queue locked. 1550 */ 1551 static void service_ofldq(struct sge_ofld_txq *q) 1552 { 1553 u64 *pos; 1554 int credits; 1555 struct sk_buff *skb; 1556 unsigned int written = 0; 1557 unsigned int flits, ndesc; 1558 1559 while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) { 1560 /* 1561 * We drop the lock but leave skb on sendq, thus retaining 1562 * exclusive access to the state of the queue. 1563 */ 1564 spin_unlock(&q->sendq.lock); 1565 1566 reclaim_completed_tx(q->adap, &q->q, false); 1567 1568 flits = skb->priority; /* previously saved */ 1569 ndesc = flits_to_desc(flits); 1570 credits = txq_avail(&q->q) - ndesc; 1571 BUG_ON(credits < 0); 1572 if (unlikely(credits < TXQ_STOP_THRES)) 1573 ofldtxq_stop(q, skb); 1574 1575 pos = (u64 *)&q->q.desc[q->q.pidx]; 1576 if (is_ofld_imm(skb)) 1577 inline_tx_skb(skb, &q->q, pos); 1578 else if (map_skb(q->adap->pdev_dev, skb, 1579 (dma_addr_t *)skb->head)) { 1580 txq_stop_maperr(q); 1581 spin_lock(&q->sendq.lock); 1582 break; 1583 } else { 1584 int last_desc, hdr_len = skb_transport_offset(skb); 1585 1586 memcpy(pos, skb->data, hdr_len); 1587 write_sgl(skb, &q->q, (void *)pos + hdr_len, 1588 pos + flits, hdr_len, 1589 (dma_addr_t *)skb->head); 1590 #ifdef CONFIG_NEED_DMA_MAP_STATE 1591 skb->dev = q->adap->port[0]; 1592 skb->destructor = deferred_unmap_destructor; 1593 #endif 1594 last_desc = q->q.pidx + ndesc - 1; 1595 if (last_desc >= q->q.size) 1596 last_desc -= q->q.size; 1597 q->q.sdesc[last_desc].skb = skb; 1598 } 1599 1600 txq_advance(&q->q, ndesc); 1601 written += ndesc; 1602 if (unlikely(written > 32)) { 1603 ring_tx_db(q->adap, &q->q, written); 1604 written = 0; 1605 } 1606 1607 spin_lock(&q->sendq.lock); 1608 __skb_unlink(skb, &q->sendq); 1609 if (is_ofld_imm(skb)) 1610 kfree_skb(skb); 1611 } 1612 if (likely(written)) 1613 ring_tx_db(q->adap, &q->q, written); 1614 } 1615 1616 /** 1617 * ofld_xmit - send a packet through an offload queue 1618 * @q: the Tx offload queue 1619 * @skb: the packet 1620 * 1621 * Send an offload packet through an SGE offload queue. 1622 */ 1623 static int ofld_xmit(struct sge_ofld_txq *q, struct sk_buff *skb) 1624 { 1625 skb->priority = calc_tx_flits_ofld(skb); /* save for restart */ 1626 spin_lock(&q->sendq.lock); 1627 __skb_queue_tail(&q->sendq, skb); 1628 if (q->sendq.qlen == 1) 1629 service_ofldq(q); 1630 spin_unlock(&q->sendq.lock); 1631 return NET_XMIT_SUCCESS; 1632 } 1633 1634 /** 1635 * restart_ofldq - restart a suspended offload queue 1636 * @data: the offload queue to restart 1637 * 1638 * Resumes transmission on a suspended Tx offload queue. 1639 */ 1640 static void restart_ofldq(unsigned long data) 1641 { 1642 struct sge_ofld_txq *q = (struct sge_ofld_txq *)data; 1643 1644 spin_lock(&q->sendq.lock); 1645 q->full = 0; /* the queue actually is completely empty now */ 1646 service_ofldq(q); 1647 spin_unlock(&q->sendq.lock); 1648 } 1649 1650 /** 1651 * skb_txq - return the Tx queue an offload packet should use 1652 * @skb: the packet 1653 * 1654 * Returns the Tx queue an offload packet should use as indicated by bits 1655 * 1-15 in the packet's queue_mapping. 1656 */ 1657 static inline unsigned int skb_txq(const struct sk_buff *skb) 1658 { 1659 return skb->queue_mapping >> 1; 1660 } 1661 1662 /** 1663 * is_ctrl_pkt - return whether an offload packet is a control packet 1664 * @skb: the packet 1665 * 1666 * Returns whether an offload packet should use an OFLD or a CTRL 1667 * Tx queue as indicated by bit 0 in the packet's queue_mapping. 1668 */ 1669 static inline unsigned int is_ctrl_pkt(const struct sk_buff *skb) 1670 { 1671 return skb->queue_mapping & 1; 1672 } 1673 1674 static inline int ofld_send(struct adapter *adap, struct sk_buff *skb) 1675 { 1676 unsigned int idx = skb_txq(skb); 1677 1678 if (unlikely(is_ctrl_pkt(skb))) { 1679 /* Single ctrl queue is a requirement for LE workaround path */ 1680 if (adap->tids.nsftids) 1681 idx = 0; 1682 return ctrl_xmit(&adap->sge.ctrlq[idx], skb); 1683 } 1684 return ofld_xmit(&adap->sge.ofldtxq[idx], skb); 1685 } 1686 1687 /** 1688 * t4_ofld_send - send an offload packet 1689 * @adap: the adapter 1690 * @skb: the packet 1691 * 1692 * Sends an offload packet. We use the packet queue_mapping to select the 1693 * appropriate Tx queue as follows: bit 0 indicates whether the packet 1694 * should be sent as regular or control, bits 1-15 select the queue. 1695 */ 1696 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb) 1697 { 1698 int ret; 1699 1700 local_bh_disable(); 1701 ret = ofld_send(adap, skb); 1702 local_bh_enable(); 1703 return ret; 1704 } 1705 1706 /** 1707 * cxgb4_ofld_send - send an offload packet 1708 * @dev: the net device 1709 * @skb: the packet 1710 * 1711 * Sends an offload packet. This is an exported version of @t4_ofld_send, 1712 * intended for ULDs. 1713 */ 1714 int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb) 1715 { 1716 return t4_ofld_send(netdev2adap(dev), skb); 1717 } 1718 EXPORT_SYMBOL(cxgb4_ofld_send); 1719 1720 static inline void copy_frags(struct sk_buff *skb, 1721 const struct pkt_gl *gl, unsigned int offset) 1722 { 1723 int i; 1724 1725 /* usually there's just one frag */ 1726 __skb_fill_page_desc(skb, 0, gl->frags[0].page, 1727 gl->frags[0].offset + offset, 1728 gl->frags[0].size - offset); 1729 skb_shinfo(skb)->nr_frags = gl->nfrags; 1730 for (i = 1; i < gl->nfrags; i++) 1731 __skb_fill_page_desc(skb, i, gl->frags[i].page, 1732 gl->frags[i].offset, 1733 gl->frags[i].size); 1734 1735 /* get a reference to the last page, we don't own it */ 1736 get_page(gl->frags[gl->nfrags - 1].page); 1737 } 1738 1739 /** 1740 * cxgb4_pktgl_to_skb - build an sk_buff from a packet gather list 1741 * @gl: the gather list 1742 * @skb_len: size of sk_buff main body if it carries fragments 1743 * @pull_len: amount of data to move to the sk_buff's main body 1744 * 1745 * Builds an sk_buff from the given packet gather list. Returns the 1746 * sk_buff or %NULL if sk_buff allocation failed. 1747 */ 1748 struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl, 1749 unsigned int skb_len, unsigned int pull_len) 1750 { 1751 struct sk_buff *skb; 1752 1753 /* 1754 * Below we rely on RX_COPY_THRES being less than the smallest Rx buffer 1755 * size, which is expected since buffers are at least PAGE_SIZEd. 1756 * In this case packets up to RX_COPY_THRES have only one fragment. 1757 */ 1758 if (gl->tot_len <= RX_COPY_THRES) { 1759 skb = dev_alloc_skb(gl->tot_len); 1760 if (unlikely(!skb)) 1761 goto out; 1762 __skb_put(skb, gl->tot_len); 1763 skb_copy_to_linear_data(skb, gl->va, gl->tot_len); 1764 } else { 1765 skb = dev_alloc_skb(skb_len); 1766 if (unlikely(!skb)) 1767 goto out; 1768 __skb_put(skb, pull_len); 1769 skb_copy_to_linear_data(skb, gl->va, pull_len); 1770 1771 copy_frags(skb, gl, pull_len); 1772 skb->len = gl->tot_len; 1773 skb->data_len = skb->len - pull_len; 1774 skb->truesize += skb->data_len; 1775 } 1776 out: return skb; 1777 } 1778 EXPORT_SYMBOL(cxgb4_pktgl_to_skb); 1779 1780 /** 1781 * t4_pktgl_free - free a packet gather list 1782 * @gl: the gather list 1783 * 1784 * Releases the pages of a packet gather list. We do not own the last 1785 * page on the list and do not free it. 1786 */ 1787 static void t4_pktgl_free(const struct pkt_gl *gl) 1788 { 1789 int n; 1790 const struct page_frag *p; 1791 1792 for (p = gl->frags, n = gl->nfrags - 1; n--; p++) 1793 put_page(p->page); 1794 } 1795 1796 /* 1797 * Process an MPS trace packet. Give it an unused protocol number so it won't 1798 * be delivered to anyone and send it to the stack for capture. 1799 */ 1800 static noinline int handle_trace_pkt(struct adapter *adap, 1801 const struct pkt_gl *gl) 1802 { 1803 struct sk_buff *skb; 1804 1805 skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN); 1806 if (unlikely(!skb)) { 1807 t4_pktgl_free(gl); 1808 return 0; 1809 } 1810 1811 if (is_t4(adap->params.chip)) 1812 __skb_pull(skb, sizeof(struct cpl_trace_pkt)); 1813 else 1814 __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt)); 1815 1816 skb_reset_mac_header(skb); 1817 skb->protocol = htons(0xffff); 1818 skb->dev = adap->port[0]; 1819 netif_receive_skb(skb); 1820 return 0; 1821 } 1822 1823 static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl, 1824 const struct cpl_rx_pkt *pkt) 1825 { 1826 struct adapter *adapter = rxq->rspq.adap; 1827 struct sge *s = &adapter->sge; 1828 int ret; 1829 struct sk_buff *skb; 1830 1831 skb = napi_get_frags(&rxq->rspq.napi); 1832 if (unlikely(!skb)) { 1833 t4_pktgl_free(gl); 1834 rxq->stats.rx_drops++; 1835 return; 1836 } 1837 1838 copy_frags(skb, gl, s->pktshift); 1839 skb->len = gl->tot_len - s->pktshift; 1840 skb->data_len = skb->len; 1841 skb->truesize += skb->data_len; 1842 skb->ip_summed = CHECKSUM_UNNECESSARY; 1843 skb_record_rx_queue(skb, rxq->rspq.idx); 1844 skb_mark_napi_id(skb, &rxq->rspq.napi); 1845 if (rxq->rspq.netdev->features & NETIF_F_RXHASH) 1846 skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val, 1847 PKT_HASH_TYPE_L3); 1848 1849 if (unlikely(pkt->vlan_ex)) { 1850 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); 1851 rxq->stats.vlan_ex++; 1852 } 1853 ret = napi_gro_frags(&rxq->rspq.napi); 1854 if (ret == GRO_HELD) 1855 rxq->stats.lro_pkts++; 1856 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE) 1857 rxq->stats.lro_merged++; 1858 rxq->stats.pkts++; 1859 rxq->stats.rx_cso++; 1860 } 1861 1862 /** 1863 * t4_ethrx_handler - process an ingress ethernet packet 1864 * @q: the response queue that received the packet 1865 * @rsp: the response queue descriptor holding the RX_PKT message 1866 * @si: the gather list of packet fragments 1867 * 1868 * Process an ingress ethernet packet and deliver it to the stack. 1869 */ 1870 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1871 const struct pkt_gl *si) 1872 { 1873 bool csum_ok; 1874 struct sk_buff *skb; 1875 const struct cpl_rx_pkt *pkt; 1876 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); 1877 struct sge *s = &q->adap->sge; 1878 int cpl_trace_pkt = is_t4(q->adap->params.chip) ? 1879 CPL_TRACE_PKT : CPL_TRACE_PKT_T5; 1880 #ifdef CONFIG_CHELSIO_T4_FCOE 1881 struct port_info *pi; 1882 #endif 1883 1884 if (unlikely(*(u8 *)rsp == cpl_trace_pkt)) 1885 return handle_trace_pkt(q->adap, si); 1886 1887 pkt = (const struct cpl_rx_pkt *)rsp; 1888 csum_ok = pkt->csum_calc && !pkt->err_vec && 1889 (q->netdev->features & NETIF_F_RXCSUM); 1890 if ((pkt->l2info & htonl(RXF_TCP_F)) && 1891 !(cxgb_poll_busy_polling(q)) && 1892 (q->netdev->features & NETIF_F_GRO) && csum_ok && !pkt->ip_frag) { 1893 do_gro(rxq, si, pkt); 1894 return 0; 1895 } 1896 1897 skb = cxgb4_pktgl_to_skb(si, RX_PKT_SKB_LEN, RX_PULL_LEN); 1898 if (unlikely(!skb)) { 1899 t4_pktgl_free(si); 1900 rxq->stats.rx_drops++; 1901 return 0; 1902 } 1903 1904 __skb_pull(skb, s->pktshift); /* remove ethernet header padding */ 1905 skb->protocol = eth_type_trans(skb, q->netdev); 1906 skb_record_rx_queue(skb, q->idx); 1907 if (skb->dev->features & NETIF_F_RXHASH) 1908 skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val, 1909 PKT_HASH_TYPE_L3); 1910 1911 rxq->stats.pkts++; 1912 1913 if (csum_ok && (pkt->l2info & htonl(RXF_UDP_F | RXF_TCP_F))) { 1914 if (!pkt->ip_frag) { 1915 skb->ip_summed = CHECKSUM_UNNECESSARY; 1916 rxq->stats.rx_cso++; 1917 } else if (pkt->l2info & htonl(RXF_IP_F)) { 1918 __sum16 c = (__force __sum16)pkt->csum; 1919 skb->csum = csum_unfold(c); 1920 skb->ip_summed = CHECKSUM_COMPLETE; 1921 rxq->stats.rx_cso++; 1922 } 1923 } else { 1924 skb_checksum_none_assert(skb); 1925 #ifdef CONFIG_CHELSIO_T4_FCOE 1926 #define CPL_RX_PKT_FLAGS (RXF_PSH_F | RXF_SYN_F | RXF_UDP_F | \ 1927 RXF_TCP_F | RXF_IP_F | RXF_IP6_F | RXF_LRO_F) 1928 1929 pi = netdev_priv(skb->dev); 1930 if (!(pkt->l2info & cpu_to_be32(CPL_RX_PKT_FLAGS))) { 1931 if ((pkt->l2info & cpu_to_be32(RXF_FCOE_F)) && 1932 (pi->fcoe.flags & CXGB_FCOE_ENABLED)) { 1933 if (!(pkt->err_vec & cpu_to_be16(RXERR_CSUM_F))) 1934 skb->ip_summed = CHECKSUM_UNNECESSARY; 1935 } 1936 } 1937 1938 #undef CPL_RX_PKT_FLAGS 1939 #endif /* CONFIG_CHELSIO_T4_FCOE */ 1940 } 1941 1942 if (unlikely(pkt->vlan_ex)) { 1943 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); 1944 rxq->stats.vlan_ex++; 1945 } 1946 skb_mark_napi_id(skb, &q->napi); 1947 netif_receive_skb(skb); 1948 return 0; 1949 } 1950 1951 /** 1952 * restore_rx_bufs - put back a packet's Rx buffers 1953 * @si: the packet gather list 1954 * @q: the SGE free list 1955 * @frags: number of FL buffers to restore 1956 * 1957 * Puts back on an FL the Rx buffers associated with @si. The buffers 1958 * have already been unmapped and are left unmapped, we mark them so to 1959 * prevent further unmapping attempts. 1960 * 1961 * This function undoes a series of @unmap_rx_buf calls when we find out 1962 * that the current packet can't be processed right away afterall and we 1963 * need to come back to it later. This is a very rare event and there's 1964 * no effort to make this particularly efficient. 1965 */ 1966 static void restore_rx_bufs(const struct pkt_gl *si, struct sge_fl *q, 1967 int frags) 1968 { 1969 struct rx_sw_desc *d; 1970 1971 while (frags--) { 1972 if (q->cidx == 0) 1973 q->cidx = q->size - 1; 1974 else 1975 q->cidx--; 1976 d = &q->sdesc[q->cidx]; 1977 d->page = si->frags[frags].page; 1978 d->dma_addr |= RX_UNMAPPED_BUF; 1979 q->avail++; 1980 } 1981 } 1982 1983 /** 1984 * is_new_response - check if a response is newly written 1985 * @r: the response descriptor 1986 * @q: the response queue 1987 * 1988 * Returns true if a response descriptor contains a yet unprocessed 1989 * response. 1990 */ 1991 static inline bool is_new_response(const struct rsp_ctrl *r, 1992 const struct sge_rspq *q) 1993 { 1994 return (r->type_gen >> RSPD_GEN_S) == q->gen; 1995 } 1996 1997 /** 1998 * rspq_next - advance to the next entry in a response queue 1999 * @q: the queue 2000 * 2001 * Updates the state of a response queue to advance it to the next entry. 2002 */ 2003 static inline void rspq_next(struct sge_rspq *q) 2004 { 2005 q->cur_desc = (void *)q->cur_desc + q->iqe_len; 2006 if (unlikely(++q->cidx == q->size)) { 2007 q->cidx = 0; 2008 q->gen ^= 1; 2009 q->cur_desc = q->desc; 2010 } 2011 } 2012 2013 /** 2014 * process_responses - process responses from an SGE response queue 2015 * @q: the ingress queue to process 2016 * @budget: how many responses can be processed in this round 2017 * 2018 * Process responses from an SGE response queue up to the supplied budget. 2019 * Responses include received packets as well as control messages from FW 2020 * or HW. 2021 * 2022 * Additionally choose the interrupt holdoff time for the next interrupt 2023 * on this queue. If the system is under memory shortage use a fairly 2024 * long delay to help recovery. 2025 */ 2026 static int process_responses(struct sge_rspq *q, int budget) 2027 { 2028 int ret, rsp_type; 2029 int budget_left = budget; 2030 const struct rsp_ctrl *rc; 2031 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); 2032 struct adapter *adapter = q->adap; 2033 struct sge *s = &adapter->sge; 2034 2035 while (likely(budget_left)) { 2036 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc)); 2037 if (!is_new_response(rc, q)) 2038 break; 2039 2040 dma_rmb(); 2041 rsp_type = RSPD_TYPE_G(rc->type_gen); 2042 if (likely(rsp_type == RSPD_TYPE_FLBUF_X)) { 2043 struct page_frag *fp; 2044 struct pkt_gl si; 2045 const struct rx_sw_desc *rsd; 2046 u32 len = ntohl(rc->pldbuflen_qid), bufsz, frags; 2047 2048 if (len & RSPD_NEWBUF_F) { 2049 if (likely(q->offset > 0)) { 2050 free_rx_bufs(q->adap, &rxq->fl, 1); 2051 q->offset = 0; 2052 } 2053 len = RSPD_LEN_G(len); 2054 } 2055 si.tot_len = len; 2056 2057 /* gather packet fragments */ 2058 for (frags = 0, fp = si.frags; ; frags++, fp++) { 2059 rsd = &rxq->fl.sdesc[rxq->fl.cidx]; 2060 bufsz = get_buf_size(adapter, rsd); 2061 fp->page = rsd->page; 2062 fp->offset = q->offset; 2063 fp->size = min(bufsz, len); 2064 len -= fp->size; 2065 if (!len) 2066 break; 2067 unmap_rx_buf(q->adap, &rxq->fl); 2068 } 2069 2070 /* 2071 * Last buffer remains mapped so explicitly make it 2072 * coherent for CPU access. 2073 */ 2074 dma_sync_single_for_cpu(q->adap->pdev_dev, 2075 get_buf_addr(rsd), 2076 fp->size, DMA_FROM_DEVICE); 2077 2078 si.va = page_address(si.frags[0].page) + 2079 si.frags[0].offset; 2080 prefetch(si.va); 2081 2082 si.nfrags = frags + 1; 2083 ret = q->handler(q, q->cur_desc, &si); 2084 if (likely(ret == 0)) 2085 q->offset += ALIGN(fp->size, s->fl_align); 2086 else 2087 restore_rx_bufs(&si, &rxq->fl, frags); 2088 } else if (likely(rsp_type == RSPD_TYPE_CPL_X)) { 2089 ret = q->handler(q, q->cur_desc, NULL); 2090 } else { 2091 ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN); 2092 } 2093 2094 if (unlikely(ret)) { 2095 /* couldn't process descriptor, back off for recovery */ 2096 q->next_intr_params = QINTR_TIMER_IDX_V(NOMEM_TMR_IDX); 2097 break; 2098 } 2099 2100 rspq_next(q); 2101 budget_left--; 2102 } 2103 2104 if (q->offset >= 0 && rxq->fl.size - rxq->fl.avail >= 16) 2105 __refill_fl(q->adap, &rxq->fl); 2106 return budget - budget_left; 2107 } 2108 2109 #ifdef CONFIG_NET_RX_BUSY_POLL 2110 int cxgb_busy_poll(struct napi_struct *napi) 2111 { 2112 struct sge_rspq *q = container_of(napi, struct sge_rspq, napi); 2113 unsigned int params, work_done; 2114 u32 val; 2115 2116 if (!cxgb_poll_lock_poll(q)) 2117 return LL_FLUSH_BUSY; 2118 2119 work_done = process_responses(q, 4); 2120 params = QINTR_TIMER_IDX_V(TIMERREG_COUNTER0_X) | QINTR_CNT_EN_V(1); 2121 q->next_intr_params = params; 2122 val = CIDXINC_V(work_done) | SEINTARM_V(params); 2123 2124 /* If we don't have access to the new User GTS (T5+), use the old 2125 * doorbell mechanism; otherwise use the new BAR2 mechanism. 2126 */ 2127 if (unlikely(!q->bar2_addr)) 2128 t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A), 2129 val | INGRESSQID_V((u32)q->cntxt_id)); 2130 else { 2131 writel(val | INGRESSQID_V(q->bar2_qid), 2132 q->bar2_addr + SGE_UDB_GTS); 2133 wmb(); 2134 } 2135 2136 cxgb_poll_unlock_poll(q); 2137 return work_done; 2138 } 2139 #endif /* CONFIG_NET_RX_BUSY_POLL */ 2140 2141 /** 2142 * napi_rx_handler - the NAPI handler for Rx processing 2143 * @napi: the napi instance 2144 * @budget: how many packets we can process in this round 2145 * 2146 * Handler for new data events when using NAPI. This does not need any 2147 * locking or protection from interrupts as data interrupts are off at 2148 * this point and other adapter interrupts do not interfere (the latter 2149 * in not a concern at all with MSI-X as non-data interrupts then have 2150 * a separate handler). 2151 */ 2152 static int napi_rx_handler(struct napi_struct *napi, int budget) 2153 { 2154 unsigned int params; 2155 struct sge_rspq *q = container_of(napi, struct sge_rspq, napi); 2156 int work_done; 2157 u32 val; 2158 2159 if (!cxgb_poll_lock_napi(q)) 2160 return budget; 2161 2162 work_done = process_responses(q, budget); 2163 if (likely(work_done < budget)) { 2164 int timer_index; 2165 2166 napi_complete(napi); 2167 timer_index = QINTR_TIMER_IDX_G(q->next_intr_params); 2168 2169 if (q->adaptive_rx) { 2170 if (work_done > max(timer_pkt_quota[timer_index], 2171 MIN_NAPI_WORK)) 2172 timer_index = (timer_index + 1); 2173 else 2174 timer_index = timer_index - 1; 2175 2176 timer_index = clamp(timer_index, 0, SGE_TIMERREGS - 1); 2177 q->next_intr_params = 2178 QINTR_TIMER_IDX_V(timer_index) | 2179 QINTR_CNT_EN_V(0); 2180 params = q->next_intr_params; 2181 } else { 2182 params = q->next_intr_params; 2183 q->next_intr_params = q->intr_params; 2184 } 2185 } else 2186 params = QINTR_TIMER_IDX_V(7); 2187 2188 val = CIDXINC_V(work_done) | SEINTARM_V(params); 2189 2190 /* If we don't have access to the new User GTS (T5+), use the old 2191 * doorbell mechanism; otherwise use the new BAR2 mechanism. 2192 */ 2193 if (unlikely(q->bar2_addr == NULL)) { 2194 t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A), 2195 val | INGRESSQID_V((u32)q->cntxt_id)); 2196 } else { 2197 writel(val | INGRESSQID_V(q->bar2_qid), 2198 q->bar2_addr + SGE_UDB_GTS); 2199 wmb(); 2200 } 2201 cxgb_poll_unlock_napi(q); 2202 return work_done; 2203 } 2204 2205 /* 2206 * The MSI-X interrupt handler for an SGE response queue. 2207 */ 2208 irqreturn_t t4_sge_intr_msix(int irq, void *cookie) 2209 { 2210 struct sge_rspq *q = cookie; 2211 2212 napi_schedule(&q->napi); 2213 return IRQ_HANDLED; 2214 } 2215 2216 /* 2217 * Process the indirect interrupt entries in the interrupt queue and kick off 2218 * NAPI for each queue that has generated an entry. 2219 */ 2220 static unsigned int process_intrq(struct adapter *adap) 2221 { 2222 unsigned int credits; 2223 const struct rsp_ctrl *rc; 2224 struct sge_rspq *q = &adap->sge.intrq; 2225 u32 val; 2226 2227 spin_lock(&adap->sge.intrq_lock); 2228 for (credits = 0; ; credits++) { 2229 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc)); 2230 if (!is_new_response(rc, q)) 2231 break; 2232 2233 dma_rmb(); 2234 if (RSPD_TYPE_G(rc->type_gen) == RSPD_TYPE_INTR_X) { 2235 unsigned int qid = ntohl(rc->pldbuflen_qid); 2236 2237 qid -= adap->sge.ingr_start; 2238 napi_schedule(&adap->sge.ingr_map[qid]->napi); 2239 } 2240 2241 rspq_next(q); 2242 } 2243 2244 val = CIDXINC_V(credits) | SEINTARM_V(q->intr_params); 2245 2246 /* If we don't have access to the new User GTS (T5+), use the old 2247 * doorbell mechanism; otherwise use the new BAR2 mechanism. 2248 */ 2249 if (unlikely(q->bar2_addr == NULL)) { 2250 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), 2251 val | INGRESSQID_V(q->cntxt_id)); 2252 } else { 2253 writel(val | INGRESSQID_V(q->bar2_qid), 2254 q->bar2_addr + SGE_UDB_GTS); 2255 wmb(); 2256 } 2257 spin_unlock(&adap->sge.intrq_lock); 2258 return credits; 2259 } 2260 2261 /* 2262 * The MSI interrupt handler, which handles data events from SGE response queues 2263 * as well as error and other async events as they all use the same MSI vector. 2264 */ 2265 static irqreturn_t t4_intr_msi(int irq, void *cookie) 2266 { 2267 struct adapter *adap = cookie; 2268 2269 if (adap->flags & MASTER_PF) 2270 t4_slow_intr_handler(adap); 2271 process_intrq(adap); 2272 return IRQ_HANDLED; 2273 } 2274 2275 /* 2276 * Interrupt handler for legacy INTx interrupts. 2277 * Handles data events from SGE response queues as well as error and other 2278 * async events as they all use the same interrupt line. 2279 */ 2280 static irqreturn_t t4_intr_intx(int irq, void *cookie) 2281 { 2282 struct adapter *adap = cookie; 2283 2284 t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0); 2285 if (((adap->flags & MASTER_PF) && t4_slow_intr_handler(adap)) | 2286 process_intrq(adap)) 2287 return IRQ_HANDLED; 2288 return IRQ_NONE; /* probably shared interrupt */ 2289 } 2290 2291 /** 2292 * t4_intr_handler - select the top-level interrupt handler 2293 * @adap: the adapter 2294 * 2295 * Selects the top-level interrupt handler based on the type of interrupts 2296 * (MSI-X, MSI, or INTx). 2297 */ 2298 irq_handler_t t4_intr_handler(struct adapter *adap) 2299 { 2300 if (adap->flags & USING_MSIX) 2301 return t4_sge_intr_msix; 2302 if (adap->flags & USING_MSI) 2303 return t4_intr_msi; 2304 return t4_intr_intx; 2305 } 2306 2307 static void sge_rx_timer_cb(unsigned long data) 2308 { 2309 unsigned long m; 2310 unsigned int i; 2311 struct adapter *adap = (struct adapter *)data; 2312 struct sge *s = &adap->sge; 2313 2314 for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++) 2315 for (m = s->starving_fl[i]; m; m &= m - 1) { 2316 struct sge_eth_rxq *rxq; 2317 unsigned int id = __ffs(m) + i * BITS_PER_LONG; 2318 struct sge_fl *fl = s->egr_map[id]; 2319 2320 clear_bit(id, s->starving_fl); 2321 smp_mb__after_atomic(); 2322 2323 if (fl_starving(adap, fl)) { 2324 rxq = container_of(fl, struct sge_eth_rxq, fl); 2325 if (napi_reschedule(&rxq->rspq.napi)) 2326 fl->starving++; 2327 else 2328 set_bit(id, s->starving_fl); 2329 } 2330 } 2331 /* The remainder of the SGE RX Timer Callback routine is dedicated to 2332 * global Master PF activities like checking for chip ingress stalls, 2333 * etc. 2334 */ 2335 if (!(adap->flags & MASTER_PF)) 2336 goto done; 2337 2338 t4_idma_monitor(adap, &s->idma_monitor, HZ, RX_QCHECK_PERIOD); 2339 2340 done: 2341 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD); 2342 } 2343 2344 static void sge_tx_timer_cb(unsigned long data) 2345 { 2346 unsigned long m; 2347 unsigned int i, budget; 2348 struct adapter *adap = (struct adapter *)data; 2349 struct sge *s = &adap->sge; 2350 2351 for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++) 2352 for (m = s->txq_maperr[i]; m; m &= m - 1) { 2353 unsigned long id = __ffs(m) + i * BITS_PER_LONG; 2354 struct sge_ofld_txq *txq = s->egr_map[id]; 2355 2356 clear_bit(id, s->txq_maperr); 2357 tasklet_schedule(&txq->qresume_tsk); 2358 } 2359 2360 budget = MAX_TIMER_TX_RECLAIM; 2361 i = s->ethtxq_rover; 2362 do { 2363 struct sge_eth_txq *q = &s->ethtxq[i]; 2364 2365 if (q->q.in_use && 2366 time_after_eq(jiffies, q->txq->trans_start + HZ / 100) && 2367 __netif_tx_trylock(q->txq)) { 2368 int avail = reclaimable(&q->q); 2369 2370 if (avail) { 2371 if (avail > budget) 2372 avail = budget; 2373 2374 free_tx_desc(adap, &q->q, avail, true); 2375 q->q.in_use -= avail; 2376 budget -= avail; 2377 } 2378 __netif_tx_unlock(q->txq); 2379 } 2380 2381 if (++i >= s->ethqsets) 2382 i = 0; 2383 } while (budget && i != s->ethtxq_rover); 2384 s->ethtxq_rover = i; 2385 mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2)); 2386 } 2387 2388 /** 2389 * bar2_address - return the BAR2 address for an SGE Queue's Registers 2390 * @adapter: the adapter 2391 * @qid: the SGE Queue ID 2392 * @qtype: the SGE Queue Type (Egress or Ingress) 2393 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 2394 * 2395 * Returns the BAR2 address for the SGE Queue Registers associated with 2396 * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also 2397 * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE 2398 * Queue Registers. If the BAR2 Queue ID is 0, then "Inferred Queue ID" 2399 * Registers are supported (e.g. the Write Combining Doorbell Buffer). 2400 */ 2401 static void __iomem *bar2_address(struct adapter *adapter, 2402 unsigned int qid, 2403 enum t4_bar2_qtype qtype, 2404 unsigned int *pbar2_qid) 2405 { 2406 u64 bar2_qoffset; 2407 int ret; 2408 2409 ret = t4_bar2_sge_qregs(adapter, qid, qtype, 0, 2410 &bar2_qoffset, pbar2_qid); 2411 if (ret) 2412 return NULL; 2413 2414 return adapter->bar2 + bar2_qoffset; 2415 } 2416 2417 /* @intr_idx: MSI/MSI-X vector if >=0, -(absolute qid + 1) if < 0 2418 * @cong: < 0 -> no congestion feedback, >= 0 -> congestion channel map 2419 */ 2420 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 2421 struct net_device *dev, int intr_idx, 2422 struct sge_fl *fl, rspq_handler_t hnd, int cong) 2423 { 2424 int ret, flsz = 0; 2425 struct fw_iq_cmd c; 2426 struct sge *s = &adap->sge; 2427 struct port_info *pi = netdev_priv(dev); 2428 2429 /* Size needs to be multiple of 16, including status entry. */ 2430 iq->size = roundup(iq->size, 16); 2431 2432 iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0, 2433 &iq->phys_addr, NULL, 0, NUMA_NO_NODE); 2434 if (!iq->desc) 2435 return -ENOMEM; 2436 2437 memset(&c, 0, sizeof(c)); 2438 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F | 2439 FW_CMD_WRITE_F | FW_CMD_EXEC_F | 2440 FW_IQ_CMD_PFN_V(adap->pf) | FW_IQ_CMD_VFN_V(0)); 2441 c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F | FW_IQ_CMD_IQSTART_F | 2442 FW_LEN16(c)); 2443 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) | 2444 FW_IQ_CMD_IQASYNCH_V(fwevtq) | FW_IQ_CMD_VIID_V(pi->viid) | 2445 FW_IQ_CMD_IQANDST_V(intr_idx < 0) | 2446 FW_IQ_CMD_IQANUD_V(UPDATEDELIVERY_INTERRUPT_X) | 2447 FW_IQ_CMD_IQANDSTINDEX_V(intr_idx >= 0 ? intr_idx : 2448 -intr_idx - 1)); 2449 c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(pi->tx_chan) | 2450 FW_IQ_CMD_IQGTSMODE_F | 2451 FW_IQ_CMD_IQINTCNTTHRESH_V(iq->pktcnt_idx) | 2452 FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4)); 2453 c.iqsize = htons(iq->size); 2454 c.iqaddr = cpu_to_be64(iq->phys_addr); 2455 if (cong >= 0) 2456 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F); 2457 2458 if (fl) { 2459 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip); 2460 2461 /* Allocate the ring for the hardware free list (with space 2462 * for its status page) along with the associated software 2463 * descriptor ring. The free list size needs to be a multiple 2464 * of the Egress Queue Unit and at least 2 Egress Units larger 2465 * than the SGE's Egress Congrestion Threshold 2466 * (fl_starve_thres - 1). 2467 */ 2468 if (fl->size < s->fl_starve_thres - 1 + 2 * 8) 2469 fl->size = s->fl_starve_thres - 1 + 2 * 8; 2470 fl->size = roundup(fl->size, 8); 2471 fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64), 2472 sizeof(struct rx_sw_desc), &fl->addr, 2473 &fl->sdesc, s->stat_len, NUMA_NO_NODE); 2474 if (!fl->desc) 2475 goto fl_nomem; 2476 2477 flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc); 2478 c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F | 2479 FW_IQ_CMD_FL0FETCHRO_F | 2480 FW_IQ_CMD_FL0DATARO_F | 2481 FW_IQ_CMD_FL0PADEN_F); 2482 if (cong >= 0) 2483 c.iqns_to_fl0congen |= 2484 htonl(FW_IQ_CMD_FL0CNGCHMAP_V(cong) | 2485 FW_IQ_CMD_FL0CONGCIF_F | 2486 FW_IQ_CMD_FL0CONGEN_F); 2487 c.fl0dcaen_to_fl0cidxfthresh = 2488 htons(FW_IQ_CMD_FL0FBMIN_V(FETCHBURSTMIN_64B_X) | 2489 FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ? 2490 FETCHBURSTMAX_512B_X : 2491 FETCHBURSTMAX_256B_X)); 2492 c.fl0size = htons(flsz); 2493 c.fl0addr = cpu_to_be64(fl->addr); 2494 } 2495 2496 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); 2497 if (ret) 2498 goto err; 2499 2500 netif_napi_add(dev, &iq->napi, napi_rx_handler, 64); 2501 napi_hash_add(&iq->napi); 2502 iq->cur_desc = iq->desc; 2503 iq->cidx = 0; 2504 iq->gen = 1; 2505 iq->next_intr_params = iq->intr_params; 2506 iq->cntxt_id = ntohs(c.iqid); 2507 iq->abs_id = ntohs(c.physiqid); 2508 iq->bar2_addr = bar2_address(adap, 2509 iq->cntxt_id, 2510 T4_BAR2_QTYPE_INGRESS, 2511 &iq->bar2_qid); 2512 iq->size--; /* subtract status entry */ 2513 iq->netdev = dev; 2514 iq->handler = hnd; 2515 2516 /* set offset to -1 to distinguish ingress queues without FL */ 2517 iq->offset = fl ? 0 : -1; 2518 2519 adap->sge.ingr_map[iq->cntxt_id - adap->sge.ingr_start] = iq; 2520 2521 if (fl) { 2522 fl->cntxt_id = ntohs(c.fl0id); 2523 fl->avail = fl->pend_cred = 0; 2524 fl->pidx = fl->cidx = 0; 2525 fl->alloc_failed = fl->large_alloc_failed = fl->starving = 0; 2526 adap->sge.egr_map[fl->cntxt_id - adap->sge.egr_start] = fl; 2527 2528 /* Note, we must initialize the BAR2 Free List User Doorbell 2529 * information before refilling the Free List! 2530 */ 2531 fl->bar2_addr = bar2_address(adap, 2532 fl->cntxt_id, 2533 T4_BAR2_QTYPE_EGRESS, 2534 &fl->bar2_qid); 2535 refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL); 2536 } 2537 2538 /* For T5 and later we attempt to set up the Congestion Manager values 2539 * of the new RX Ethernet Queue. This should really be handled by 2540 * firmware because it's more complex than any host driver wants to 2541 * get involved with and it's different per chip and this is almost 2542 * certainly wrong. Firmware would be wrong as well, but it would be 2543 * a lot easier to fix in one place ... For now we do something very 2544 * simple (and hopefully less wrong). 2545 */ 2546 if (!is_t4(adap->params.chip) && cong >= 0) { 2547 u32 param, val; 2548 int i; 2549 2550 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 2551 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2552 FW_PARAMS_PARAM_YZ_V(iq->cntxt_id)); 2553 if (cong == 0) { 2554 val = CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_QUEUE_X); 2555 } else { 2556 val = 2557 CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_CHANNEL_X); 2558 for (i = 0; i < 4; i++) { 2559 if (cong & (1 << i)) 2560 val |= 2561 CONMCTXT_CNGCHMAP_V(1 << (i << 2)); 2562 } 2563 } 2564 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 2565 ¶m, &val); 2566 if (ret) 2567 dev_warn(adap->pdev_dev, "Failed to set Congestion" 2568 " Manager Context for Ingress Queue %d: %d\n", 2569 iq->cntxt_id, -ret); 2570 } 2571 2572 return 0; 2573 2574 fl_nomem: 2575 ret = -ENOMEM; 2576 err: 2577 if (iq->desc) { 2578 dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len, 2579 iq->desc, iq->phys_addr); 2580 iq->desc = NULL; 2581 } 2582 if (fl && fl->desc) { 2583 kfree(fl->sdesc); 2584 fl->sdesc = NULL; 2585 dma_free_coherent(adap->pdev_dev, flsz * sizeof(struct tx_desc), 2586 fl->desc, fl->addr); 2587 fl->desc = NULL; 2588 } 2589 return ret; 2590 } 2591 2592 static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id) 2593 { 2594 q->cntxt_id = id; 2595 q->bar2_addr = bar2_address(adap, 2596 q->cntxt_id, 2597 T4_BAR2_QTYPE_EGRESS, 2598 &q->bar2_qid); 2599 q->in_use = 0; 2600 q->cidx = q->pidx = 0; 2601 q->stops = q->restarts = 0; 2602 q->stat = (void *)&q->desc[q->size]; 2603 spin_lock_init(&q->db_lock); 2604 adap->sge.egr_map[id - adap->sge.egr_start] = q; 2605 } 2606 2607 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 2608 struct net_device *dev, struct netdev_queue *netdevq, 2609 unsigned int iqid) 2610 { 2611 int ret, nentries; 2612 struct fw_eq_eth_cmd c; 2613 struct sge *s = &adap->sge; 2614 struct port_info *pi = netdev_priv(dev); 2615 2616 /* Add status entries */ 2617 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); 2618 2619 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size, 2620 sizeof(struct tx_desc), sizeof(struct tx_sw_desc), 2621 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len, 2622 netdev_queue_numa_node_read(netdevq)); 2623 if (!txq->q.desc) 2624 return -ENOMEM; 2625 2626 memset(&c, 0, sizeof(c)); 2627 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F | 2628 FW_CMD_WRITE_F | FW_CMD_EXEC_F | 2629 FW_EQ_ETH_CMD_PFN_V(adap->pf) | 2630 FW_EQ_ETH_CMD_VFN_V(0)); 2631 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F | 2632 FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c)); 2633 c.viid_pkd = htonl(FW_EQ_ETH_CMD_AUTOEQUEQE_F | 2634 FW_EQ_ETH_CMD_VIID_V(pi->viid)); 2635 c.fetchszm_to_iqid = 2636 htonl(FW_EQ_ETH_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) | 2637 FW_EQ_ETH_CMD_PCIECHN_V(pi->tx_chan) | 2638 FW_EQ_ETH_CMD_FETCHRO_F | FW_EQ_ETH_CMD_IQID_V(iqid)); 2639 c.dcaen_to_eqsize = 2640 htonl(FW_EQ_ETH_CMD_FBMIN_V(FETCHBURSTMIN_64B_X) | 2641 FW_EQ_ETH_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) | 2642 FW_EQ_ETH_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) | 2643 FW_EQ_ETH_CMD_EQSIZE_V(nentries)); 2644 c.eqaddr = cpu_to_be64(txq->q.phys_addr); 2645 2646 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); 2647 if (ret) { 2648 kfree(txq->q.sdesc); 2649 txq->q.sdesc = NULL; 2650 dma_free_coherent(adap->pdev_dev, 2651 nentries * sizeof(struct tx_desc), 2652 txq->q.desc, txq->q.phys_addr); 2653 txq->q.desc = NULL; 2654 return ret; 2655 } 2656 2657 init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_G(ntohl(c.eqid_pkd))); 2658 txq->txq = netdevq; 2659 txq->tso = txq->tx_cso = txq->vlan_ins = 0; 2660 txq->mapping_err = 0; 2661 return 0; 2662 } 2663 2664 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 2665 struct net_device *dev, unsigned int iqid, 2666 unsigned int cmplqid) 2667 { 2668 int ret, nentries; 2669 struct fw_eq_ctrl_cmd c; 2670 struct sge *s = &adap->sge; 2671 struct port_info *pi = netdev_priv(dev); 2672 2673 /* Add status entries */ 2674 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); 2675 2676 txq->q.desc = alloc_ring(adap->pdev_dev, nentries, 2677 sizeof(struct tx_desc), 0, &txq->q.phys_addr, 2678 NULL, 0, dev_to_node(adap->pdev_dev)); 2679 if (!txq->q.desc) 2680 return -ENOMEM; 2681 2682 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F | 2683 FW_CMD_WRITE_F | FW_CMD_EXEC_F | 2684 FW_EQ_CTRL_CMD_PFN_V(adap->pf) | 2685 FW_EQ_CTRL_CMD_VFN_V(0)); 2686 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F | 2687 FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c)); 2688 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID_V(cmplqid)); 2689 c.physeqid_pkd = htonl(0); 2690 c.fetchszm_to_iqid = 2691 htonl(FW_EQ_CTRL_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) | 2692 FW_EQ_CTRL_CMD_PCIECHN_V(pi->tx_chan) | 2693 FW_EQ_CTRL_CMD_FETCHRO_F | FW_EQ_CTRL_CMD_IQID_V(iqid)); 2694 c.dcaen_to_eqsize = 2695 htonl(FW_EQ_CTRL_CMD_FBMIN_V(FETCHBURSTMIN_64B_X) | 2696 FW_EQ_CTRL_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) | 2697 FW_EQ_CTRL_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) | 2698 FW_EQ_CTRL_CMD_EQSIZE_V(nentries)); 2699 c.eqaddr = cpu_to_be64(txq->q.phys_addr); 2700 2701 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); 2702 if (ret) { 2703 dma_free_coherent(adap->pdev_dev, 2704 nentries * sizeof(struct tx_desc), 2705 txq->q.desc, txq->q.phys_addr); 2706 txq->q.desc = NULL; 2707 return ret; 2708 } 2709 2710 init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_G(ntohl(c.cmpliqid_eqid))); 2711 txq->adap = adap; 2712 skb_queue_head_init(&txq->sendq); 2713 tasklet_init(&txq->qresume_tsk, restart_ctrlq, (unsigned long)txq); 2714 txq->full = 0; 2715 return 0; 2716 } 2717 2718 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 2719 struct net_device *dev, unsigned int iqid) 2720 { 2721 int ret, nentries; 2722 struct fw_eq_ofld_cmd c; 2723 struct sge *s = &adap->sge; 2724 struct port_info *pi = netdev_priv(dev); 2725 2726 /* Add status entries */ 2727 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); 2728 2729 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size, 2730 sizeof(struct tx_desc), sizeof(struct tx_sw_desc), 2731 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len, 2732 NUMA_NO_NODE); 2733 if (!txq->q.desc) 2734 return -ENOMEM; 2735 2736 memset(&c, 0, sizeof(c)); 2737 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F | 2738 FW_CMD_WRITE_F | FW_CMD_EXEC_F | 2739 FW_EQ_OFLD_CMD_PFN_V(adap->pf) | 2740 FW_EQ_OFLD_CMD_VFN_V(0)); 2741 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F | 2742 FW_EQ_OFLD_CMD_EQSTART_F | FW_LEN16(c)); 2743 c.fetchszm_to_iqid = 2744 htonl(FW_EQ_OFLD_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) | 2745 FW_EQ_OFLD_CMD_PCIECHN_V(pi->tx_chan) | 2746 FW_EQ_OFLD_CMD_FETCHRO_F | FW_EQ_OFLD_CMD_IQID_V(iqid)); 2747 c.dcaen_to_eqsize = 2748 htonl(FW_EQ_OFLD_CMD_FBMIN_V(FETCHBURSTMIN_64B_X) | 2749 FW_EQ_OFLD_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) | 2750 FW_EQ_OFLD_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) | 2751 FW_EQ_OFLD_CMD_EQSIZE_V(nentries)); 2752 c.eqaddr = cpu_to_be64(txq->q.phys_addr); 2753 2754 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); 2755 if (ret) { 2756 kfree(txq->q.sdesc); 2757 txq->q.sdesc = NULL; 2758 dma_free_coherent(adap->pdev_dev, 2759 nentries * sizeof(struct tx_desc), 2760 txq->q.desc, txq->q.phys_addr); 2761 txq->q.desc = NULL; 2762 return ret; 2763 } 2764 2765 init_txq(adap, &txq->q, FW_EQ_OFLD_CMD_EQID_G(ntohl(c.eqid_pkd))); 2766 txq->adap = adap; 2767 skb_queue_head_init(&txq->sendq); 2768 tasklet_init(&txq->qresume_tsk, restart_ofldq, (unsigned long)txq); 2769 txq->full = 0; 2770 txq->mapping_err = 0; 2771 return 0; 2772 } 2773 2774 static void free_txq(struct adapter *adap, struct sge_txq *q) 2775 { 2776 struct sge *s = &adap->sge; 2777 2778 dma_free_coherent(adap->pdev_dev, 2779 q->size * sizeof(struct tx_desc) + s->stat_len, 2780 q->desc, q->phys_addr); 2781 q->cntxt_id = 0; 2782 q->sdesc = NULL; 2783 q->desc = NULL; 2784 } 2785 2786 static void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, 2787 struct sge_fl *fl) 2788 { 2789 struct sge *s = &adap->sge; 2790 unsigned int fl_id = fl ? fl->cntxt_id : 0xffff; 2791 2792 adap->sge.ingr_map[rq->cntxt_id - adap->sge.ingr_start] = NULL; 2793 t4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 2794 rq->cntxt_id, fl_id, 0xffff); 2795 dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len, 2796 rq->desc, rq->phys_addr); 2797 napi_hash_del(&rq->napi); 2798 netif_napi_del(&rq->napi); 2799 rq->netdev = NULL; 2800 rq->cntxt_id = rq->abs_id = 0; 2801 rq->desc = NULL; 2802 2803 if (fl) { 2804 free_rx_bufs(adap, fl, fl->avail); 2805 dma_free_coherent(adap->pdev_dev, fl->size * 8 + s->stat_len, 2806 fl->desc, fl->addr); 2807 kfree(fl->sdesc); 2808 fl->sdesc = NULL; 2809 fl->cntxt_id = 0; 2810 fl->desc = NULL; 2811 } 2812 } 2813 2814 /** 2815 * t4_free_ofld_rxqs - free a block of consecutive Rx queues 2816 * @adap: the adapter 2817 * @n: number of queues 2818 * @q: pointer to first queue 2819 * 2820 * Release the resources of a consecutive block of offload Rx queues. 2821 */ 2822 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q) 2823 { 2824 for ( ; n; n--, q++) 2825 if (q->rspq.desc) 2826 free_rspq_fl(adap, &q->rspq, 2827 q->fl.size ? &q->fl : NULL); 2828 } 2829 2830 /** 2831 * t4_free_sge_resources - free SGE resources 2832 * @adap: the adapter 2833 * 2834 * Frees resources used by the SGE queue sets. 2835 */ 2836 void t4_free_sge_resources(struct adapter *adap) 2837 { 2838 int i; 2839 struct sge_eth_rxq *eq = adap->sge.ethrxq; 2840 struct sge_eth_txq *etq = adap->sge.ethtxq; 2841 2842 /* clean up Ethernet Tx/Rx queues */ 2843 for (i = 0; i < adap->sge.ethqsets; i++, eq++, etq++) { 2844 if (eq->rspq.desc) 2845 free_rspq_fl(adap, &eq->rspq, 2846 eq->fl.size ? &eq->fl : NULL); 2847 if (etq->q.desc) { 2848 t4_eth_eq_free(adap, adap->mbox, adap->pf, 0, 2849 etq->q.cntxt_id); 2850 free_tx_desc(adap, &etq->q, etq->q.in_use, true); 2851 kfree(etq->q.sdesc); 2852 free_txq(adap, &etq->q); 2853 } 2854 } 2855 2856 /* clean up RDMA and iSCSI Rx queues */ 2857 t4_free_ofld_rxqs(adap, adap->sge.ofldqsets, adap->sge.ofldrxq); 2858 t4_free_ofld_rxqs(adap, adap->sge.rdmaqs, adap->sge.rdmarxq); 2859 t4_free_ofld_rxqs(adap, adap->sge.rdmaciqs, adap->sge.rdmaciq); 2860 2861 /* clean up offload Tx queues */ 2862 for (i = 0; i < ARRAY_SIZE(adap->sge.ofldtxq); i++) { 2863 struct sge_ofld_txq *q = &adap->sge.ofldtxq[i]; 2864 2865 if (q->q.desc) { 2866 tasklet_kill(&q->qresume_tsk); 2867 t4_ofld_eq_free(adap, adap->mbox, adap->pf, 0, 2868 q->q.cntxt_id); 2869 free_tx_desc(adap, &q->q, q->q.in_use, false); 2870 kfree(q->q.sdesc); 2871 __skb_queue_purge(&q->sendq); 2872 free_txq(adap, &q->q); 2873 } 2874 } 2875 2876 /* clean up control Tx queues */ 2877 for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) { 2878 struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i]; 2879 2880 if (cq->q.desc) { 2881 tasklet_kill(&cq->qresume_tsk); 2882 t4_ctrl_eq_free(adap, adap->mbox, adap->pf, 0, 2883 cq->q.cntxt_id); 2884 __skb_queue_purge(&cq->sendq); 2885 free_txq(adap, &cq->q); 2886 } 2887 } 2888 2889 if (adap->sge.fw_evtq.desc) 2890 free_rspq_fl(adap, &adap->sge.fw_evtq, NULL); 2891 2892 if (adap->sge.intrq.desc) 2893 free_rspq_fl(adap, &adap->sge.intrq, NULL); 2894 2895 /* clear the reverse egress queue map */ 2896 memset(adap->sge.egr_map, 0, 2897 adap->sge.egr_sz * sizeof(*adap->sge.egr_map)); 2898 } 2899 2900 void t4_sge_start(struct adapter *adap) 2901 { 2902 adap->sge.ethtxq_rover = 0; 2903 mod_timer(&adap->sge.rx_timer, jiffies + RX_QCHECK_PERIOD); 2904 mod_timer(&adap->sge.tx_timer, jiffies + TX_QCHECK_PERIOD); 2905 } 2906 2907 /** 2908 * t4_sge_stop - disable SGE operation 2909 * @adap: the adapter 2910 * 2911 * Stop tasklets and timers associated with the DMA engine. Note that 2912 * this is effective only if measures have been taken to disable any HW 2913 * events that may restart them. 2914 */ 2915 void t4_sge_stop(struct adapter *adap) 2916 { 2917 int i; 2918 struct sge *s = &adap->sge; 2919 2920 if (in_interrupt()) /* actions below require waiting */ 2921 return; 2922 2923 if (s->rx_timer.function) 2924 del_timer_sync(&s->rx_timer); 2925 if (s->tx_timer.function) 2926 del_timer_sync(&s->tx_timer); 2927 2928 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) { 2929 struct sge_ofld_txq *q = &s->ofldtxq[i]; 2930 2931 if (q->q.desc) 2932 tasklet_kill(&q->qresume_tsk); 2933 } 2934 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) { 2935 struct sge_ctrl_txq *cq = &s->ctrlq[i]; 2936 2937 if (cq->q.desc) 2938 tasklet_kill(&cq->qresume_tsk); 2939 } 2940 } 2941 2942 /** 2943 * t4_sge_init_soft - grab core SGE values needed by SGE code 2944 * @adap: the adapter 2945 * 2946 * We need to grab the SGE operating parameters that we need to have 2947 * in order to do our job and make sure we can live with them. 2948 */ 2949 2950 static int t4_sge_init_soft(struct adapter *adap) 2951 { 2952 struct sge *s = &adap->sge; 2953 u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu; 2954 u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5; 2955 u32 ingress_rx_threshold; 2956 2957 /* 2958 * Verify that CPL messages are going to the Ingress Queue for 2959 * process_responses() and that only packet data is going to the 2960 * Free Lists. 2961 */ 2962 if ((t4_read_reg(adap, SGE_CONTROL_A) & RXPKTCPLMODE_F) != 2963 RXPKTCPLMODE_V(RXPKTCPLMODE_SPLIT_X)) { 2964 dev_err(adap->pdev_dev, "bad SGE CPL MODE\n"); 2965 return -EINVAL; 2966 } 2967 2968 /* 2969 * Validate the Host Buffer Register Array indices that we want to 2970 * use ... 2971 * 2972 * XXX Note that we should really read through the Host Buffer Size 2973 * XXX register array and find the indices of the Buffer Sizes which 2974 * XXX meet our needs! 2975 */ 2976 #define READ_FL_BUF(x) \ 2977 t4_read_reg(adap, SGE_FL_BUFFER_SIZE0_A+(x)*sizeof(u32)) 2978 2979 fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF); 2980 fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF); 2981 fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF); 2982 fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF); 2983 2984 /* We only bother using the Large Page logic if the Large Page Buffer 2985 * is larger than our Page Size Buffer. 2986 */ 2987 if (fl_large_pg <= fl_small_pg) 2988 fl_large_pg = 0; 2989 2990 #undef READ_FL_BUF 2991 2992 /* The Page Size Buffer must be exactly equal to our Page Size and the 2993 * Large Page Size Buffer should be 0 (per above) or a power of 2. 2994 */ 2995 if (fl_small_pg != PAGE_SIZE || 2996 (fl_large_pg & (fl_large_pg-1)) != 0) { 2997 dev_err(adap->pdev_dev, "bad SGE FL page buffer sizes [%d, %d]\n", 2998 fl_small_pg, fl_large_pg); 2999 return -EINVAL; 3000 } 3001 if (fl_large_pg) 3002 s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT; 3003 3004 if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap) || 3005 fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) { 3006 dev_err(adap->pdev_dev, "bad SGE FL MTU sizes [%d, %d]\n", 3007 fl_small_mtu, fl_large_mtu); 3008 return -EINVAL; 3009 } 3010 3011 /* 3012 * Retrieve our RX interrupt holdoff timer values and counter 3013 * threshold values from the SGE parameters. 3014 */ 3015 timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A); 3016 timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A); 3017 timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A); 3018 s->timer_val[0] = core_ticks_to_us(adap, 3019 TIMERVALUE0_G(timer_value_0_and_1)); 3020 s->timer_val[1] = core_ticks_to_us(adap, 3021 TIMERVALUE1_G(timer_value_0_and_1)); 3022 s->timer_val[2] = core_ticks_to_us(adap, 3023 TIMERVALUE2_G(timer_value_2_and_3)); 3024 s->timer_val[3] = core_ticks_to_us(adap, 3025 TIMERVALUE3_G(timer_value_2_and_3)); 3026 s->timer_val[4] = core_ticks_to_us(adap, 3027 TIMERVALUE4_G(timer_value_4_and_5)); 3028 s->timer_val[5] = core_ticks_to_us(adap, 3029 TIMERVALUE5_G(timer_value_4_and_5)); 3030 3031 ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A); 3032 s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold); 3033 s->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold); 3034 s->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold); 3035 s->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold); 3036 3037 return 0; 3038 } 3039 3040 /** 3041 * t4_sge_init - initialize SGE 3042 * @adap: the adapter 3043 * 3044 * Perform low-level SGE code initialization needed every time after a 3045 * chip reset. 3046 */ 3047 int t4_sge_init(struct adapter *adap) 3048 { 3049 struct sge *s = &adap->sge; 3050 u32 sge_control, sge_control2, sge_conm_ctrl; 3051 unsigned int ingpadboundary, ingpackboundary; 3052 int ret, egress_threshold; 3053 3054 /* 3055 * Ingress Padding Boundary and Egress Status Page Size are set up by 3056 * t4_fixup_host_params(). 3057 */ 3058 sge_control = t4_read_reg(adap, SGE_CONTROL_A); 3059 s->pktshift = PKTSHIFT_G(sge_control); 3060 s->stat_len = (sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64; 3061 3062 /* T4 uses a single control field to specify both the PCIe Padding and 3063 * Packing Boundary. T5 introduced the ability to specify these 3064 * separately. The actual Ingress Packet Data alignment boundary 3065 * within Packed Buffer Mode is the maximum of these two 3066 * specifications. (Note that it makes no real practical sense to 3067 * have the Pading Boudary be larger than the Packing Boundary but you 3068 * could set the chip up that way and, in fact, legacy T4 code would 3069 * end doing this because it would initialize the Padding Boundary and 3070 * leave the Packing Boundary initialized to 0 (16 bytes).) 3071 */ 3072 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + 3073 INGPADBOUNDARY_SHIFT_X); 3074 if (is_t4(adap->params.chip)) { 3075 s->fl_align = ingpadboundary; 3076 } else { 3077 /* T5 has a different interpretation of one of the PCIe Packing 3078 * Boundary values. 3079 */ 3080 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A); 3081 ingpackboundary = INGPACKBOUNDARY_G(sge_control2); 3082 if (ingpackboundary == INGPACKBOUNDARY_16B_X) 3083 ingpackboundary = 16; 3084 else 3085 ingpackboundary = 1 << (ingpackboundary + 3086 INGPACKBOUNDARY_SHIFT_X); 3087 3088 s->fl_align = max(ingpadboundary, ingpackboundary); 3089 } 3090 3091 ret = t4_sge_init_soft(adap); 3092 if (ret < 0) 3093 return ret; 3094 3095 /* 3096 * A FL with <= fl_starve_thres buffers is starving and a periodic 3097 * timer will attempt to refill it. This needs to be larger than the 3098 * SGE's Egress Congestion Threshold. If it isn't, then we can get 3099 * stuck waiting for new packets while the SGE is waiting for us to 3100 * give it more Free List entries. (Note that the SGE's Egress 3101 * Congestion Threshold is in units of 2 Free List pointers.) For T4, 3102 * there was only a single field to control this. For T5 there's the 3103 * original field which now only applies to Unpacked Mode Free List 3104 * buffers and a new field which only applies to Packed Mode Free List 3105 * buffers. 3106 */ 3107 sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A); 3108 if (is_t4(adap->params.chip)) 3109 egress_threshold = EGRTHRESHOLD_G(sge_conm_ctrl); 3110 else 3111 egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl); 3112 s->fl_starve_thres = 2*egress_threshold + 1; 3113 3114 t4_idma_monitor_init(adap, &s->idma_monitor); 3115 3116 /* Set up timers used for recuring callbacks to process RX and TX 3117 * administrative tasks. 3118 */ 3119 setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap); 3120 setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adap); 3121 3122 spin_lock_init(&s->intrq_lock); 3123 3124 return 0; 3125 } 3126