1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4ce100b8bSAnish Bhatt * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #include <linux/skbuff.h> 36f7917c00SJeff Kirsher #include <linux/netdevice.h> 37f7917c00SJeff Kirsher #include <linux/etherdevice.h> 38f7917c00SJeff Kirsher #include <linux/if_vlan.h> 39f7917c00SJeff Kirsher #include <linux/ip.h> 40f7917c00SJeff Kirsher #include <linux/dma-mapping.h> 41f7917c00SJeff Kirsher #include <linux/jiffies.h> 42f7917c00SJeff Kirsher #include <linux/prefetch.h> 43ee40fa06SPaul Gortmaker #include <linux/export.h> 44f7917c00SJeff Kirsher #include <net/ipv6.h> 45f7917c00SJeff Kirsher #include <net/tcp.h> 463a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 473a336cb1SHariprasad Shenai #include <net/busy_poll.h> 483a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 4984a200b3SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 5084a200b3SVarun Prakash #include <scsi/fc/fc_fcoe.h> 5184a200b3SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 52f7917c00SJeff Kirsher #include "cxgb4.h" 53f7917c00SJeff Kirsher #include "t4_regs.h" 54f612b815SHariprasad Shenai #include "t4_values.h" 55f7917c00SJeff Kirsher #include "t4_msg.h" 56f7917c00SJeff Kirsher #include "t4fw_api.h" 57f7917c00SJeff Kirsher 58f7917c00SJeff Kirsher /* 59f7917c00SJeff Kirsher * Rx buffer size. We use largish buffers if possible but settle for single 60f7917c00SJeff Kirsher * pages under memory shortage. 61f7917c00SJeff Kirsher */ 62f7917c00SJeff Kirsher #if PAGE_SHIFT >= 16 63f7917c00SJeff Kirsher # define FL_PG_ORDER 0 64f7917c00SJeff Kirsher #else 65f7917c00SJeff Kirsher # define FL_PG_ORDER (16 - PAGE_SHIFT) 66f7917c00SJeff Kirsher #endif 67f7917c00SJeff Kirsher 68f7917c00SJeff Kirsher /* RX_PULL_LEN should be <= RX_COPY_THRES */ 69f7917c00SJeff Kirsher #define RX_COPY_THRES 256 70f7917c00SJeff Kirsher #define RX_PULL_LEN 128 71f7917c00SJeff Kirsher 72f7917c00SJeff Kirsher /* 73f7917c00SJeff Kirsher * Main body length for sk_buffs used for Rx Ethernet packets with fragments. 74f7917c00SJeff Kirsher * Should be >= RX_PULL_LEN but possibly bigger to give pskb_may_pull some room. 75f7917c00SJeff Kirsher */ 76f7917c00SJeff Kirsher #define RX_PKT_SKB_LEN 512 77f7917c00SJeff Kirsher 78f7917c00SJeff Kirsher /* 79f7917c00SJeff Kirsher * Max number of Tx descriptors we clean up at a time. Should be modest as 80f7917c00SJeff Kirsher * freeing skbs isn't cheap and it happens while holding locks. We just need 81f7917c00SJeff Kirsher * to free packets faster than they arrive, we eventually catch up and keep 82f7917c00SJeff Kirsher * the amortized cost reasonable. Must be >= 2 * TXQ_STOP_THRES. 83f7917c00SJeff Kirsher */ 84f7917c00SJeff Kirsher #define MAX_TX_RECLAIM 16 85f7917c00SJeff Kirsher 86f7917c00SJeff Kirsher /* 87f7917c00SJeff Kirsher * Max number of Rx buffers we replenish at a time. Again keep this modest, 88f7917c00SJeff Kirsher * allocating buffers isn't cheap either. 89f7917c00SJeff Kirsher */ 90f7917c00SJeff Kirsher #define MAX_RX_REFILL 16U 91f7917c00SJeff Kirsher 92f7917c00SJeff Kirsher /* 93f7917c00SJeff Kirsher * Period of the Rx queue check timer. This timer is infrequent as it has 94f7917c00SJeff Kirsher * something to do only when the system experiences severe memory shortage. 95f7917c00SJeff Kirsher */ 96f7917c00SJeff Kirsher #define RX_QCHECK_PERIOD (HZ / 2) 97f7917c00SJeff Kirsher 98f7917c00SJeff Kirsher /* 99f7917c00SJeff Kirsher * Period of the Tx queue check timer. 100f7917c00SJeff Kirsher */ 101f7917c00SJeff Kirsher #define TX_QCHECK_PERIOD (HZ / 2) 102f7917c00SJeff Kirsher 1030f4d201fSKumar Sanghvi /* SGE Hung Ingress DMA Threshold Warning time (in Hz) and Warning Repeat Rate 1040f4d201fSKumar Sanghvi * (in RX_QCHECK_PERIOD multiples). If we find one of the SGE Ingress DMA 1050f4d201fSKumar Sanghvi * State Machines in the same state for this amount of time (in HZ) then we'll 1060f4d201fSKumar Sanghvi * issue a warning about a potential hang. We'll repeat the warning as the 1070f4d201fSKumar Sanghvi * SGE Ingress DMA Channel appears to be hung every N RX_QCHECK_PERIODs till 1080f4d201fSKumar Sanghvi * the situation clears. If the situation clears, we'll note that as well. 1090f4d201fSKumar Sanghvi */ 1100f4d201fSKumar Sanghvi #define SGE_IDMA_WARN_THRESH (1 * HZ) 1110f4d201fSKumar Sanghvi #define SGE_IDMA_WARN_REPEAT (20 * RX_QCHECK_PERIOD) 1120f4d201fSKumar Sanghvi 113f7917c00SJeff Kirsher /* 114f7917c00SJeff Kirsher * Max number of Tx descriptors to be reclaimed by the Tx timer. 115f7917c00SJeff Kirsher */ 116f7917c00SJeff Kirsher #define MAX_TIMER_TX_RECLAIM 100 117f7917c00SJeff Kirsher 118f7917c00SJeff Kirsher /* 119f7917c00SJeff Kirsher * Timer index used when backing off due to memory shortage. 120f7917c00SJeff Kirsher */ 121f7917c00SJeff Kirsher #define NOMEM_TMR_IDX (SGE_NTIMERS - 1) 122f7917c00SJeff Kirsher 123f7917c00SJeff Kirsher /* 124f7917c00SJeff Kirsher * Suspend an Ethernet Tx queue with fewer available descriptors than this. 125f7917c00SJeff Kirsher * This is the same as calc_tx_descs() for a TSO packet with 126f7917c00SJeff Kirsher * nr_frags == MAX_SKB_FRAGS. 127f7917c00SJeff Kirsher */ 128f7917c00SJeff Kirsher #define ETHTXQ_STOP_THRES \ 129f7917c00SJeff Kirsher (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 130f7917c00SJeff Kirsher 131f7917c00SJeff Kirsher /* 132f7917c00SJeff Kirsher * Suspension threshold for non-Ethernet Tx queues. We require enough room 133f7917c00SJeff Kirsher * for a full sized WR. 134f7917c00SJeff Kirsher */ 135f7917c00SJeff Kirsher #define TXQ_STOP_THRES (SGE_MAX_WR_LEN / sizeof(struct tx_desc)) 136f7917c00SJeff Kirsher 137f7917c00SJeff Kirsher /* 138f7917c00SJeff Kirsher * Max Tx descriptor space we allow for an Ethernet packet to be inlined 139f7917c00SJeff Kirsher * into a WR. 140f7917c00SJeff Kirsher */ 14121dcfad6SHariprasad Shenai #define MAX_IMM_TX_PKT_LEN 256 142f7917c00SJeff Kirsher 143f7917c00SJeff Kirsher /* 144f7917c00SJeff Kirsher * Max size of a WR sent through a control Tx queue. 145f7917c00SJeff Kirsher */ 146f7917c00SJeff Kirsher #define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN 147f7917c00SJeff Kirsher 148f7917c00SJeff Kirsher struct tx_sw_desc { /* SW state per Tx descriptor */ 149f7917c00SJeff Kirsher struct sk_buff *skb; 150f7917c00SJeff Kirsher struct ulptx_sgl *sgl; 151f7917c00SJeff Kirsher }; 152f7917c00SJeff Kirsher 153f7917c00SJeff Kirsher struct rx_sw_desc { /* SW state per Rx descriptor */ 154f7917c00SJeff Kirsher struct page *page; 155f7917c00SJeff Kirsher dma_addr_t dma_addr; 156f7917c00SJeff Kirsher }; 157f7917c00SJeff Kirsher 158f7917c00SJeff Kirsher /* 15952367a76SVipul Pandya * Rx buffer sizes for "useskbs" Free List buffers (one ingress packet pe skb 16052367a76SVipul Pandya * buffer). We currently only support two sizes for 1500- and 9000-byte MTUs. 16152367a76SVipul Pandya * We could easily support more but there doesn't seem to be much need for 16252367a76SVipul Pandya * that ... 16352367a76SVipul Pandya */ 16452367a76SVipul Pandya #define FL_MTU_SMALL 1500 16552367a76SVipul Pandya #define FL_MTU_LARGE 9000 16652367a76SVipul Pandya 16752367a76SVipul Pandya static inline unsigned int fl_mtu_bufsize(struct adapter *adapter, 16852367a76SVipul Pandya unsigned int mtu) 16952367a76SVipul Pandya { 17052367a76SVipul Pandya struct sge *s = &adapter->sge; 17152367a76SVipul Pandya 17252367a76SVipul Pandya return ALIGN(s->pktshift + ETH_HLEN + VLAN_HLEN + mtu, s->fl_align); 17352367a76SVipul Pandya } 17452367a76SVipul Pandya 17552367a76SVipul Pandya #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL) 17652367a76SVipul Pandya #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE) 17752367a76SVipul Pandya 17852367a76SVipul Pandya /* 17952367a76SVipul Pandya * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses 18052367a76SVipul Pandya * these to specify the buffer size as an index into the SGE Free List Buffer 18152367a76SVipul Pandya * Size register array. We also use bit 4, when the buffer has been unmapped 18252367a76SVipul Pandya * for DMA, but this is of course never sent to the hardware and is only used 18352367a76SVipul Pandya * to prevent double unmappings. All of the above requires that the Free List 18452367a76SVipul Pandya * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are 18552367a76SVipul Pandya * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal 18652367a76SVipul Pandya * Free List Buffer alignment is 32 bytes, this works out for us ... 187f7917c00SJeff Kirsher */ 188f7917c00SJeff Kirsher enum { 18952367a76SVipul Pandya RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */ 19052367a76SVipul Pandya RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */ 19152367a76SVipul Pandya RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */ 19252367a76SVipul Pandya 19352367a76SVipul Pandya /* 19452367a76SVipul Pandya * XXX We shouldn't depend on being able to use these indices. 19552367a76SVipul Pandya * XXX Especially when some other Master PF has initialized the 19652367a76SVipul Pandya * XXX adapter or we use the Firmware Configuration File. We 19752367a76SVipul Pandya * XXX should really search through the Host Buffer Size register 19852367a76SVipul Pandya * XXX array for the appropriately sized buffer indices. 19952367a76SVipul Pandya */ 20052367a76SVipul Pandya RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */ 20152367a76SVipul Pandya RX_LARGE_PG_BUF = 0x1, /* buffer large (FL_PG_ORDER) page buffer */ 20252367a76SVipul Pandya 20352367a76SVipul Pandya RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */ 20452367a76SVipul Pandya RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */ 205f7917c00SJeff Kirsher }; 206f7917c00SJeff Kirsher 207e553ec3fSHariprasad Shenai static int timer_pkt_quota[] = {1, 1, 2, 3, 4, 5}; 208e553ec3fSHariprasad Shenai #define MIN_NAPI_WORK 1 209e553ec3fSHariprasad Shenai 210f7917c00SJeff Kirsher static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *d) 211f7917c00SJeff Kirsher { 21252367a76SVipul Pandya return d->dma_addr & ~(dma_addr_t)RX_BUF_FLAGS; 213f7917c00SJeff Kirsher } 214f7917c00SJeff Kirsher 215f7917c00SJeff Kirsher static inline bool is_buf_mapped(const struct rx_sw_desc *d) 216f7917c00SJeff Kirsher { 217f7917c00SJeff Kirsher return !(d->dma_addr & RX_UNMAPPED_BUF); 218f7917c00SJeff Kirsher } 219f7917c00SJeff Kirsher 220f7917c00SJeff Kirsher /** 221f7917c00SJeff Kirsher * txq_avail - return the number of available slots in a Tx queue 222f7917c00SJeff Kirsher * @q: the Tx queue 223f7917c00SJeff Kirsher * 224f7917c00SJeff Kirsher * Returns the number of descriptors in a Tx queue available to write new 225f7917c00SJeff Kirsher * packets. 226f7917c00SJeff Kirsher */ 227f7917c00SJeff Kirsher static inline unsigned int txq_avail(const struct sge_txq *q) 228f7917c00SJeff Kirsher { 229f7917c00SJeff Kirsher return q->size - 1 - q->in_use; 230f7917c00SJeff Kirsher } 231f7917c00SJeff Kirsher 232f7917c00SJeff Kirsher /** 233f7917c00SJeff Kirsher * fl_cap - return the capacity of a free-buffer list 234f7917c00SJeff Kirsher * @fl: the FL 235f7917c00SJeff Kirsher * 236f7917c00SJeff Kirsher * Returns the capacity of a free-buffer list. The capacity is less than 237f7917c00SJeff Kirsher * the size because one descriptor needs to be left unpopulated, otherwise 238f7917c00SJeff Kirsher * HW will think the FL is empty. 239f7917c00SJeff Kirsher */ 240f7917c00SJeff Kirsher static inline unsigned int fl_cap(const struct sge_fl *fl) 241f7917c00SJeff Kirsher { 242f7917c00SJeff Kirsher return fl->size - 8; /* 1 descriptor = 8 buffers */ 243f7917c00SJeff Kirsher } 244f7917c00SJeff Kirsher 245c098b026SHariprasad Shenai /** 246c098b026SHariprasad Shenai * fl_starving - return whether a Free List is starving. 247c098b026SHariprasad Shenai * @adapter: pointer to the adapter 248c098b026SHariprasad Shenai * @fl: the Free List 249c098b026SHariprasad Shenai * 250c098b026SHariprasad Shenai * Tests specified Free List to see whether the number of buffers 251c098b026SHariprasad Shenai * available to the hardware has falled below our "starvation" 252c098b026SHariprasad Shenai * threshold. 253c098b026SHariprasad Shenai */ 254c098b026SHariprasad Shenai static inline bool fl_starving(const struct adapter *adapter, 255c098b026SHariprasad Shenai const struct sge_fl *fl) 256f7917c00SJeff Kirsher { 257c098b026SHariprasad Shenai const struct sge *s = &adapter->sge; 258c098b026SHariprasad Shenai 259c098b026SHariprasad Shenai return fl->avail - fl->pend_cred <= s->fl_starve_thres; 260f7917c00SJeff Kirsher } 261f7917c00SJeff Kirsher 262f7917c00SJeff Kirsher static int map_skb(struct device *dev, const struct sk_buff *skb, 263f7917c00SJeff Kirsher dma_addr_t *addr) 264f7917c00SJeff Kirsher { 265f7917c00SJeff Kirsher const skb_frag_t *fp, *end; 266f7917c00SJeff Kirsher const struct skb_shared_info *si; 267f7917c00SJeff Kirsher 268f7917c00SJeff Kirsher *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); 269f7917c00SJeff Kirsher if (dma_mapping_error(dev, *addr)) 270f7917c00SJeff Kirsher goto out_err; 271f7917c00SJeff Kirsher 272f7917c00SJeff Kirsher si = skb_shinfo(skb); 273f7917c00SJeff Kirsher end = &si->frags[si->nr_frags]; 274f7917c00SJeff Kirsher 275f7917c00SJeff Kirsher for (fp = si->frags; fp < end; fp++) { 276e91b0f24SIan Campbell *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp), 277e91b0f24SIan Campbell DMA_TO_DEVICE); 278f7917c00SJeff Kirsher if (dma_mapping_error(dev, *addr)) 279f7917c00SJeff Kirsher goto unwind; 280f7917c00SJeff Kirsher } 281f7917c00SJeff Kirsher return 0; 282f7917c00SJeff Kirsher 283f7917c00SJeff Kirsher unwind: 284f7917c00SJeff Kirsher while (fp-- > si->frags) 2859e903e08SEric Dumazet dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE); 286f7917c00SJeff Kirsher 287f7917c00SJeff Kirsher dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE); 288f7917c00SJeff Kirsher out_err: 289f7917c00SJeff Kirsher return -ENOMEM; 290f7917c00SJeff Kirsher } 291f7917c00SJeff Kirsher 292f7917c00SJeff Kirsher #ifdef CONFIG_NEED_DMA_MAP_STATE 293f7917c00SJeff Kirsher static void unmap_skb(struct device *dev, const struct sk_buff *skb, 294f7917c00SJeff Kirsher const dma_addr_t *addr) 295f7917c00SJeff Kirsher { 296f7917c00SJeff Kirsher const skb_frag_t *fp, *end; 297f7917c00SJeff Kirsher const struct skb_shared_info *si; 298f7917c00SJeff Kirsher 299f7917c00SJeff Kirsher dma_unmap_single(dev, *addr++, skb_headlen(skb), DMA_TO_DEVICE); 300f7917c00SJeff Kirsher 301f7917c00SJeff Kirsher si = skb_shinfo(skb); 302f7917c00SJeff Kirsher end = &si->frags[si->nr_frags]; 303f7917c00SJeff Kirsher for (fp = si->frags; fp < end; fp++) 3049e903e08SEric Dumazet dma_unmap_page(dev, *addr++, skb_frag_size(fp), DMA_TO_DEVICE); 305f7917c00SJeff Kirsher } 306f7917c00SJeff Kirsher 307f7917c00SJeff Kirsher /** 308f7917c00SJeff Kirsher * deferred_unmap_destructor - unmap a packet when it is freed 309f7917c00SJeff Kirsher * @skb: the packet 310f7917c00SJeff Kirsher * 311f7917c00SJeff Kirsher * This is the packet destructor used for Tx packets that need to remain 312f7917c00SJeff Kirsher * mapped until they are freed rather than until their Tx descriptors are 313f7917c00SJeff Kirsher * freed. 314f7917c00SJeff Kirsher */ 315f7917c00SJeff Kirsher static void deferred_unmap_destructor(struct sk_buff *skb) 316f7917c00SJeff Kirsher { 317f7917c00SJeff Kirsher unmap_skb(skb->dev->dev.parent, skb, (dma_addr_t *)skb->head); 318f7917c00SJeff Kirsher } 319f7917c00SJeff Kirsher #endif 320f7917c00SJeff Kirsher 321f7917c00SJeff Kirsher static void unmap_sgl(struct device *dev, const struct sk_buff *skb, 322f7917c00SJeff Kirsher const struct ulptx_sgl *sgl, const struct sge_txq *q) 323f7917c00SJeff Kirsher { 324f7917c00SJeff Kirsher const struct ulptx_sge_pair *p; 325f7917c00SJeff Kirsher unsigned int nfrags = skb_shinfo(skb)->nr_frags; 326f7917c00SJeff Kirsher 327f7917c00SJeff Kirsher if (likely(skb_headlen(skb))) 328f7917c00SJeff Kirsher dma_unmap_single(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0), 329f7917c00SJeff Kirsher DMA_TO_DEVICE); 330f7917c00SJeff Kirsher else { 331f7917c00SJeff Kirsher dma_unmap_page(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0), 332f7917c00SJeff Kirsher DMA_TO_DEVICE); 333f7917c00SJeff Kirsher nfrags--; 334f7917c00SJeff Kirsher } 335f7917c00SJeff Kirsher 336f7917c00SJeff Kirsher /* 337f7917c00SJeff Kirsher * the complexity below is because of the possibility of a wrap-around 338f7917c00SJeff Kirsher * in the middle of an SGL 339f7917c00SJeff Kirsher */ 340f7917c00SJeff Kirsher for (p = sgl->sge; nfrags >= 2; nfrags -= 2) { 341f7917c00SJeff Kirsher if (likely((u8 *)(p + 1) <= (u8 *)q->stat)) { 342f7917c00SJeff Kirsher unmap: dma_unmap_page(dev, be64_to_cpu(p->addr[0]), 343f7917c00SJeff Kirsher ntohl(p->len[0]), DMA_TO_DEVICE); 344f7917c00SJeff Kirsher dma_unmap_page(dev, be64_to_cpu(p->addr[1]), 345f7917c00SJeff Kirsher ntohl(p->len[1]), DMA_TO_DEVICE); 346f7917c00SJeff Kirsher p++; 347f7917c00SJeff Kirsher } else if ((u8 *)p == (u8 *)q->stat) { 348f7917c00SJeff Kirsher p = (const struct ulptx_sge_pair *)q->desc; 349f7917c00SJeff Kirsher goto unmap; 350f7917c00SJeff Kirsher } else if ((u8 *)p + 8 == (u8 *)q->stat) { 351f7917c00SJeff Kirsher const __be64 *addr = (const __be64 *)q->desc; 352f7917c00SJeff Kirsher 353f7917c00SJeff Kirsher dma_unmap_page(dev, be64_to_cpu(addr[0]), 354f7917c00SJeff Kirsher ntohl(p->len[0]), DMA_TO_DEVICE); 355f7917c00SJeff Kirsher dma_unmap_page(dev, be64_to_cpu(addr[1]), 356f7917c00SJeff Kirsher ntohl(p->len[1]), DMA_TO_DEVICE); 357f7917c00SJeff Kirsher p = (const struct ulptx_sge_pair *)&addr[2]; 358f7917c00SJeff Kirsher } else { 359f7917c00SJeff Kirsher const __be64 *addr = (const __be64 *)q->desc; 360f7917c00SJeff Kirsher 361f7917c00SJeff Kirsher dma_unmap_page(dev, be64_to_cpu(p->addr[0]), 362f7917c00SJeff Kirsher ntohl(p->len[0]), DMA_TO_DEVICE); 363f7917c00SJeff Kirsher dma_unmap_page(dev, be64_to_cpu(addr[0]), 364f7917c00SJeff Kirsher ntohl(p->len[1]), DMA_TO_DEVICE); 365f7917c00SJeff Kirsher p = (const struct ulptx_sge_pair *)&addr[1]; 366f7917c00SJeff Kirsher } 367f7917c00SJeff Kirsher } 368f7917c00SJeff Kirsher if (nfrags) { 369f7917c00SJeff Kirsher __be64 addr; 370f7917c00SJeff Kirsher 371f7917c00SJeff Kirsher if ((u8 *)p == (u8 *)q->stat) 372f7917c00SJeff Kirsher p = (const struct ulptx_sge_pair *)q->desc; 373f7917c00SJeff Kirsher addr = (u8 *)p + 16 <= (u8 *)q->stat ? p->addr[0] : 374f7917c00SJeff Kirsher *(const __be64 *)q->desc; 375f7917c00SJeff Kirsher dma_unmap_page(dev, be64_to_cpu(addr), ntohl(p->len[0]), 376f7917c00SJeff Kirsher DMA_TO_DEVICE); 377f7917c00SJeff Kirsher } 378f7917c00SJeff Kirsher } 379f7917c00SJeff Kirsher 380f7917c00SJeff Kirsher /** 381f7917c00SJeff Kirsher * free_tx_desc - reclaims Tx descriptors and their buffers 382f7917c00SJeff Kirsher * @adapter: the adapter 383f7917c00SJeff Kirsher * @q: the Tx queue to reclaim descriptors from 384f7917c00SJeff Kirsher * @n: the number of descriptors to reclaim 385f7917c00SJeff Kirsher * @unmap: whether the buffers should be unmapped for DMA 386f7917c00SJeff Kirsher * 387f7917c00SJeff Kirsher * Reclaims Tx descriptors from an SGE Tx queue and frees the associated 388f7917c00SJeff Kirsher * Tx buffers. Called with the Tx queue lock held. 389f7917c00SJeff Kirsher */ 390f7917c00SJeff Kirsher static void free_tx_desc(struct adapter *adap, struct sge_txq *q, 391f7917c00SJeff Kirsher unsigned int n, bool unmap) 392f7917c00SJeff Kirsher { 393f7917c00SJeff Kirsher struct tx_sw_desc *d; 394f7917c00SJeff Kirsher unsigned int cidx = q->cidx; 395f7917c00SJeff Kirsher struct device *dev = adap->pdev_dev; 396f7917c00SJeff Kirsher 397f7917c00SJeff Kirsher d = &q->sdesc[cidx]; 398f7917c00SJeff Kirsher while (n--) { 399f7917c00SJeff Kirsher if (d->skb) { /* an SGL is present */ 400f7917c00SJeff Kirsher if (unmap) 401f7917c00SJeff Kirsher unmap_sgl(dev, d->skb, d->sgl, q); 402a7525198SEric W. Biederman dev_consume_skb_any(d->skb); 403f7917c00SJeff Kirsher d->skb = NULL; 404f7917c00SJeff Kirsher } 405f7917c00SJeff Kirsher ++d; 406f7917c00SJeff Kirsher if (++cidx == q->size) { 407f7917c00SJeff Kirsher cidx = 0; 408f7917c00SJeff Kirsher d = q->sdesc; 409f7917c00SJeff Kirsher } 410f7917c00SJeff Kirsher } 411f7917c00SJeff Kirsher q->cidx = cidx; 412f7917c00SJeff Kirsher } 413f7917c00SJeff Kirsher 414f7917c00SJeff Kirsher /* 415f7917c00SJeff Kirsher * Return the number of reclaimable descriptors in a Tx queue. 416f7917c00SJeff Kirsher */ 417f7917c00SJeff Kirsher static inline int reclaimable(const struct sge_txq *q) 418f7917c00SJeff Kirsher { 419f7917c00SJeff Kirsher int hw_cidx = ntohs(q->stat->cidx); 420f7917c00SJeff Kirsher hw_cidx -= q->cidx; 421f7917c00SJeff Kirsher return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx; 422f7917c00SJeff Kirsher } 423f7917c00SJeff Kirsher 424f7917c00SJeff Kirsher /** 425f7917c00SJeff Kirsher * reclaim_completed_tx - reclaims completed Tx descriptors 426f7917c00SJeff Kirsher * @adap: the adapter 427f7917c00SJeff Kirsher * @q: the Tx queue to reclaim completed descriptors from 428f7917c00SJeff Kirsher * @unmap: whether the buffers should be unmapped for DMA 429f7917c00SJeff Kirsher * 430f7917c00SJeff Kirsher * Reclaims Tx descriptors that the SGE has indicated it has processed, 431f7917c00SJeff Kirsher * and frees the associated buffers if possible. Called with the Tx 432f7917c00SJeff Kirsher * queue locked. 433f7917c00SJeff Kirsher */ 434f7917c00SJeff Kirsher static inline void reclaim_completed_tx(struct adapter *adap, struct sge_txq *q, 435f7917c00SJeff Kirsher bool unmap) 436f7917c00SJeff Kirsher { 437f7917c00SJeff Kirsher int avail = reclaimable(q); 438f7917c00SJeff Kirsher 439f7917c00SJeff Kirsher if (avail) { 440f7917c00SJeff Kirsher /* 441f7917c00SJeff Kirsher * Limit the amount of clean up work we do at a time to keep 442f7917c00SJeff Kirsher * the Tx lock hold time O(1). 443f7917c00SJeff Kirsher */ 444f7917c00SJeff Kirsher if (avail > MAX_TX_RECLAIM) 445f7917c00SJeff Kirsher avail = MAX_TX_RECLAIM; 446f7917c00SJeff Kirsher 447f7917c00SJeff Kirsher free_tx_desc(adap, q, avail, unmap); 448f7917c00SJeff Kirsher q->in_use -= avail; 449f7917c00SJeff Kirsher } 450f7917c00SJeff Kirsher } 451f7917c00SJeff Kirsher 45252367a76SVipul Pandya static inline int get_buf_size(struct adapter *adapter, 45352367a76SVipul Pandya const struct rx_sw_desc *d) 454f7917c00SJeff Kirsher { 45552367a76SVipul Pandya struct sge *s = &adapter->sge; 45652367a76SVipul Pandya unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE; 45752367a76SVipul Pandya int buf_size; 45852367a76SVipul Pandya 45952367a76SVipul Pandya switch (rx_buf_size_idx) { 46052367a76SVipul Pandya case RX_SMALL_PG_BUF: 46152367a76SVipul Pandya buf_size = PAGE_SIZE; 46252367a76SVipul Pandya break; 46352367a76SVipul Pandya 46452367a76SVipul Pandya case RX_LARGE_PG_BUF: 46552367a76SVipul Pandya buf_size = PAGE_SIZE << s->fl_pg_order; 46652367a76SVipul Pandya break; 46752367a76SVipul Pandya 46852367a76SVipul Pandya case RX_SMALL_MTU_BUF: 46952367a76SVipul Pandya buf_size = FL_MTU_SMALL_BUFSIZE(adapter); 47052367a76SVipul Pandya break; 47152367a76SVipul Pandya 47252367a76SVipul Pandya case RX_LARGE_MTU_BUF: 47352367a76SVipul Pandya buf_size = FL_MTU_LARGE_BUFSIZE(adapter); 47452367a76SVipul Pandya break; 47552367a76SVipul Pandya 47652367a76SVipul Pandya default: 47752367a76SVipul Pandya BUG_ON(1); 47852367a76SVipul Pandya } 47952367a76SVipul Pandya 48052367a76SVipul Pandya return buf_size; 481f7917c00SJeff Kirsher } 482f7917c00SJeff Kirsher 483f7917c00SJeff Kirsher /** 484f7917c00SJeff Kirsher * free_rx_bufs - free the Rx buffers on an SGE free list 485f7917c00SJeff Kirsher * @adap: the adapter 486f7917c00SJeff Kirsher * @q: the SGE free list to free buffers from 487f7917c00SJeff Kirsher * @n: how many buffers to free 488f7917c00SJeff Kirsher * 489f7917c00SJeff Kirsher * Release the next @n buffers on an SGE free-buffer Rx queue. The 490f7917c00SJeff Kirsher * buffers must be made inaccessible to HW before calling this function. 491f7917c00SJeff Kirsher */ 492f7917c00SJeff Kirsher static void free_rx_bufs(struct adapter *adap, struct sge_fl *q, int n) 493f7917c00SJeff Kirsher { 494f7917c00SJeff Kirsher while (n--) { 495f7917c00SJeff Kirsher struct rx_sw_desc *d = &q->sdesc[q->cidx]; 496f7917c00SJeff Kirsher 497f7917c00SJeff Kirsher if (is_buf_mapped(d)) 498f7917c00SJeff Kirsher dma_unmap_page(adap->pdev_dev, get_buf_addr(d), 49952367a76SVipul Pandya get_buf_size(adap, d), 50052367a76SVipul Pandya PCI_DMA_FROMDEVICE); 501f7917c00SJeff Kirsher put_page(d->page); 502f7917c00SJeff Kirsher d->page = NULL; 503f7917c00SJeff Kirsher if (++q->cidx == q->size) 504f7917c00SJeff Kirsher q->cidx = 0; 505f7917c00SJeff Kirsher q->avail--; 506f7917c00SJeff Kirsher } 507f7917c00SJeff Kirsher } 508f7917c00SJeff Kirsher 509f7917c00SJeff Kirsher /** 510f7917c00SJeff Kirsher * unmap_rx_buf - unmap the current Rx buffer on an SGE free list 511f7917c00SJeff Kirsher * @adap: the adapter 512f7917c00SJeff Kirsher * @q: the SGE free list 513f7917c00SJeff Kirsher * 514f7917c00SJeff Kirsher * Unmap the current buffer on an SGE free-buffer Rx queue. The 515f7917c00SJeff Kirsher * buffer must be made inaccessible to HW before calling this function. 516f7917c00SJeff Kirsher * 517f7917c00SJeff Kirsher * This is similar to @free_rx_bufs above but does not free the buffer. 518f7917c00SJeff Kirsher * Do note that the FL still loses any further access to the buffer. 519f7917c00SJeff Kirsher */ 520f7917c00SJeff Kirsher static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q) 521f7917c00SJeff Kirsher { 522f7917c00SJeff Kirsher struct rx_sw_desc *d = &q->sdesc[q->cidx]; 523f7917c00SJeff Kirsher 524f7917c00SJeff Kirsher if (is_buf_mapped(d)) 525f7917c00SJeff Kirsher dma_unmap_page(adap->pdev_dev, get_buf_addr(d), 52652367a76SVipul Pandya get_buf_size(adap, d), PCI_DMA_FROMDEVICE); 527f7917c00SJeff Kirsher d->page = NULL; 528f7917c00SJeff Kirsher if (++q->cidx == q->size) 529f7917c00SJeff Kirsher q->cidx = 0; 530f7917c00SJeff Kirsher q->avail--; 531f7917c00SJeff Kirsher } 532f7917c00SJeff Kirsher 533f7917c00SJeff Kirsher static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) 534f7917c00SJeff Kirsher { 5350a57a536SSantosh Rastapur u32 val; 536f7917c00SJeff Kirsher if (q->pend_cred >= 8) { 537f612b815SHariprasad Shenai if (is_t4(adap->params.chip)) 538f612b815SHariprasad Shenai val = PIDX_V(q->pend_cred / 8); 539f612b815SHariprasad Shenai else 540f612b815SHariprasad Shenai val = PIDX_T5_V(q->pend_cred / 8) | 541f612b815SHariprasad Shenai DBTYPE_F; 542f612b815SHariprasad Shenai val |= DBPRIO_F; 543f7917c00SJeff Kirsher wmb(); 544d63a6dcfSHariprasad Shenai 545df64e4d3SHariprasad Shenai /* If we don't have access to the new User Doorbell (T5+), use 546df64e4d3SHariprasad Shenai * the old doorbell mechanism; otherwise use the new BAR2 547df64e4d3SHariprasad Shenai * mechanism. 548d63a6dcfSHariprasad Shenai */ 549df64e4d3SHariprasad Shenai if (unlikely(q->bar2_addr == NULL)) { 550f612b815SHariprasad Shenai t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 551f612b815SHariprasad Shenai val | QID_V(q->cntxt_id)); 552d63a6dcfSHariprasad Shenai } else { 553f612b815SHariprasad Shenai writel(val | QID_V(q->bar2_qid), 554df64e4d3SHariprasad Shenai q->bar2_addr + SGE_UDB_KDOORBELL); 555d63a6dcfSHariprasad Shenai 556d63a6dcfSHariprasad Shenai /* This Write memory Barrier will force the write to 557d63a6dcfSHariprasad Shenai * the User Doorbell area to be flushed. 558d63a6dcfSHariprasad Shenai */ 559d63a6dcfSHariprasad Shenai wmb(); 560d63a6dcfSHariprasad Shenai } 561f7917c00SJeff Kirsher q->pend_cred &= 7; 562f7917c00SJeff Kirsher } 563f7917c00SJeff Kirsher } 564f7917c00SJeff Kirsher 565f7917c00SJeff Kirsher static inline void set_rx_sw_desc(struct rx_sw_desc *sd, struct page *pg, 566f7917c00SJeff Kirsher dma_addr_t mapping) 567f7917c00SJeff Kirsher { 568f7917c00SJeff Kirsher sd->page = pg; 569f7917c00SJeff Kirsher sd->dma_addr = mapping; /* includes size low bits */ 570f7917c00SJeff Kirsher } 571f7917c00SJeff Kirsher 572f7917c00SJeff Kirsher /** 573f7917c00SJeff Kirsher * refill_fl - refill an SGE Rx buffer ring 574f7917c00SJeff Kirsher * @adap: the adapter 575f7917c00SJeff Kirsher * @q: the ring to refill 576f7917c00SJeff Kirsher * @n: the number of new buffers to allocate 577f7917c00SJeff Kirsher * @gfp: the gfp flags for the allocations 578f7917c00SJeff Kirsher * 579f7917c00SJeff Kirsher * (Re)populate an SGE free-buffer queue with up to @n new packet buffers, 580f7917c00SJeff Kirsher * allocated with the supplied gfp flags. The caller must assure that 581f7917c00SJeff Kirsher * @n does not exceed the queue's capacity. If afterwards the queue is 582f7917c00SJeff Kirsher * found critically low mark it as starving in the bitmap of starving FLs. 583f7917c00SJeff Kirsher * 584f7917c00SJeff Kirsher * Returns the number of buffers allocated. 585f7917c00SJeff Kirsher */ 586f7917c00SJeff Kirsher static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n, 587f7917c00SJeff Kirsher gfp_t gfp) 588f7917c00SJeff Kirsher { 58952367a76SVipul Pandya struct sge *s = &adap->sge; 590f7917c00SJeff Kirsher struct page *pg; 591f7917c00SJeff Kirsher dma_addr_t mapping; 592f7917c00SJeff Kirsher unsigned int cred = q->avail; 593f7917c00SJeff Kirsher __be64 *d = &q->desc[q->pidx]; 594f7917c00SJeff Kirsher struct rx_sw_desc *sd = &q->sdesc[q->pidx]; 595d52ce920SHariprasad Shenai int node; 596f7917c00SJeff Kirsher 597aa9cd31cSAlexander Duyck gfp |= __GFP_NOWARN; 598d52ce920SHariprasad Shenai node = dev_to_node(adap->pdev_dev); 599f7917c00SJeff Kirsher 60052367a76SVipul Pandya if (s->fl_pg_order == 0) 60152367a76SVipul Pandya goto alloc_small_pages; 60252367a76SVipul Pandya 603f7917c00SJeff Kirsher /* 604f7917c00SJeff Kirsher * Prefer large buffers 605f7917c00SJeff Kirsher */ 606f7917c00SJeff Kirsher while (n) { 607d52ce920SHariprasad Shenai pg = alloc_pages_node(node, gfp | __GFP_COMP, s->fl_pg_order); 608f7917c00SJeff Kirsher if (unlikely(!pg)) { 609f7917c00SJeff Kirsher q->large_alloc_failed++; 610f7917c00SJeff Kirsher break; /* fall back to single pages */ 611f7917c00SJeff Kirsher } 612f7917c00SJeff Kirsher 613f7917c00SJeff Kirsher mapping = dma_map_page(adap->pdev_dev, pg, 0, 61452367a76SVipul Pandya PAGE_SIZE << s->fl_pg_order, 615f7917c00SJeff Kirsher PCI_DMA_FROMDEVICE); 616f7917c00SJeff Kirsher if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { 61752367a76SVipul Pandya __free_pages(pg, s->fl_pg_order); 618f7917c00SJeff Kirsher goto out; /* do not try small pages for this error */ 619f7917c00SJeff Kirsher } 62052367a76SVipul Pandya mapping |= RX_LARGE_PG_BUF; 621f7917c00SJeff Kirsher *d++ = cpu_to_be64(mapping); 622f7917c00SJeff Kirsher 623f7917c00SJeff Kirsher set_rx_sw_desc(sd, pg, mapping); 624f7917c00SJeff Kirsher sd++; 625f7917c00SJeff Kirsher 626f7917c00SJeff Kirsher q->avail++; 627f7917c00SJeff Kirsher if (++q->pidx == q->size) { 628f7917c00SJeff Kirsher q->pidx = 0; 629f7917c00SJeff Kirsher sd = q->sdesc; 630f7917c00SJeff Kirsher d = q->desc; 631f7917c00SJeff Kirsher } 632f7917c00SJeff Kirsher n--; 633f7917c00SJeff Kirsher } 634f7917c00SJeff Kirsher 63552367a76SVipul Pandya alloc_small_pages: 636f7917c00SJeff Kirsher while (n--) { 637d52ce920SHariprasad Shenai pg = alloc_pages_node(node, gfp, 0); 638f7917c00SJeff Kirsher if (unlikely(!pg)) { 639f7917c00SJeff Kirsher q->alloc_failed++; 640f7917c00SJeff Kirsher break; 641f7917c00SJeff Kirsher } 642f7917c00SJeff Kirsher 643f7917c00SJeff Kirsher mapping = dma_map_page(adap->pdev_dev, pg, 0, PAGE_SIZE, 644f7917c00SJeff Kirsher PCI_DMA_FROMDEVICE); 645f7917c00SJeff Kirsher if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { 6461f2149c1SEric Dumazet put_page(pg); 647f7917c00SJeff Kirsher goto out; 648f7917c00SJeff Kirsher } 649f7917c00SJeff Kirsher *d++ = cpu_to_be64(mapping); 650f7917c00SJeff Kirsher 651f7917c00SJeff Kirsher set_rx_sw_desc(sd, pg, mapping); 652f7917c00SJeff Kirsher sd++; 653f7917c00SJeff Kirsher 654f7917c00SJeff Kirsher q->avail++; 655f7917c00SJeff Kirsher if (++q->pidx == q->size) { 656f7917c00SJeff Kirsher q->pidx = 0; 657f7917c00SJeff Kirsher sd = q->sdesc; 658f7917c00SJeff Kirsher d = q->desc; 659f7917c00SJeff Kirsher } 660f7917c00SJeff Kirsher } 661f7917c00SJeff Kirsher 662f7917c00SJeff Kirsher out: cred = q->avail - cred; 663f7917c00SJeff Kirsher q->pend_cred += cred; 664f7917c00SJeff Kirsher ring_fl_db(adap, q); 665f7917c00SJeff Kirsher 666c098b026SHariprasad Shenai if (unlikely(fl_starving(adap, q))) { 667f7917c00SJeff Kirsher smp_wmb(); 668f7917c00SJeff Kirsher set_bit(q->cntxt_id - adap->sge.egr_start, 669f7917c00SJeff Kirsher adap->sge.starving_fl); 670f7917c00SJeff Kirsher } 671f7917c00SJeff Kirsher 672f7917c00SJeff Kirsher return cred; 673f7917c00SJeff Kirsher } 674f7917c00SJeff Kirsher 675f7917c00SJeff Kirsher static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl) 676f7917c00SJeff Kirsher { 677f7917c00SJeff Kirsher refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail), 678f7917c00SJeff Kirsher GFP_ATOMIC); 679f7917c00SJeff Kirsher } 680f7917c00SJeff Kirsher 681f7917c00SJeff Kirsher /** 682f7917c00SJeff Kirsher * alloc_ring - allocate resources for an SGE descriptor ring 683f7917c00SJeff Kirsher * @dev: the PCI device's core device 684f7917c00SJeff Kirsher * @nelem: the number of descriptors 685f7917c00SJeff Kirsher * @elem_size: the size of each descriptor 686f7917c00SJeff Kirsher * @sw_size: the size of the SW state associated with each ring element 687f7917c00SJeff Kirsher * @phys: the physical address of the allocated ring 688f7917c00SJeff Kirsher * @metadata: address of the array holding the SW state for the ring 689f7917c00SJeff Kirsher * @stat_size: extra space in HW ring for status information 690f7917c00SJeff Kirsher * @node: preferred node for memory allocations 691f7917c00SJeff Kirsher * 692f7917c00SJeff Kirsher * Allocates resources for an SGE descriptor ring, such as Tx queues, 693f7917c00SJeff Kirsher * free buffer lists, or response queues. Each SGE ring requires 694f7917c00SJeff Kirsher * space for its HW descriptors plus, optionally, space for the SW state 695f7917c00SJeff Kirsher * associated with each HW entry (the metadata). The function returns 696f7917c00SJeff Kirsher * three values: the virtual address for the HW ring (the return value 697f7917c00SJeff Kirsher * of the function), the bus address of the HW ring, and the address 698f7917c00SJeff Kirsher * of the SW ring. 699f7917c00SJeff Kirsher */ 700f7917c00SJeff Kirsher static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size, 701f7917c00SJeff Kirsher size_t sw_size, dma_addr_t *phys, void *metadata, 702f7917c00SJeff Kirsher size_t stat_size, int node) 703f7917c00SJeff Kirsher { 704f7917c00SJeff Kirsher size_t len = nelem * elem_size + stat_size; 705f7917c00SJeff Kirsher void *s = NULL; 706f7917c00SJeff Kirsher void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL); 707f7917c00SJeff Kirsher 708f7917c00SJeff Kirsher if (!p) 709f7917c00SJeff Kirsher return NULL; 710f7917c00SJeff Kirsher if (sw_size) { 711f7917c00SJeff Kirsher s = kzalloc_node(nelem * sw_size, GFP_KERNEL, node); 712f7917c00SJeff Kirsher 713f7917c00SJeff Kirsher if (!s) { 714f7917c00SJeff Kirsher dma_free_coherent(dev, len, p, *phys); 715f7917c00SJeff Kirsher return NULL; 716f7917c00SJeff Kirsher } 717f7917c00SJeff Kirsher } 718f7917c00SJeff Kirsher if (metadata) 719f7917c00SJeff Kirsher *(void **)metadata = s; 720f7917c00SJeff Kirsher memset(p, 0, len); 721f7917c00SJeff Kirsher return p; 722f7917c00SJeff Kirsher } 723f7917c00SJeff Kirsher 724f7917c00SJeff Kirsher /** 725f7917c00SJeff Kirsher * sgl_len - calculates the size of an SGL of the given capacity 726f7917c00SJeff Kirsher * @n: the number of SGL entries 727f7917c00SJeff Kirsher * 728f7917c00SJeff Kirsher * Calculates the number of flits needed for a scatter/gather list that 729f7917c00SJeff Kirsher * can hold the given number of entries. 730f7917c00SJeff Kirsher */ 731f7917c00SJeff Kirsher static inline unsigned int sgl_len(unsigned int n) 732f7917c00SJeff Kirsher { 733f7917c00SJeff Kirsher n--; 734f7917c00SJeff Kirsher return (3 * n) / 2 + (n & 1) + 2; 735f7917c00SJeff Kirsher } 736f7917c00SJeff Kirsher 737f7917c00SJeff Kirsher /** 738f7917c00SJeff Kirsher * flits_to_desc - returns the num of Tx descriptors for the given flits 739f7917c00SJeff Kirsher * @n: the number of flits 740f7917c00SJeff Kirsher * 741f7917c00SJeff Kirsher * Returns the number of Tx descriptors needed for the supplied number 742f7917c00SJeff Kirsher * of flits. 743f7917c00SJeff Kirsher */ 744f7917c00SJeff Kirsher static inline unsigned int flits_to_desc(unsigned int n) 745f7917c00SJeff Kirsher { 746f7917c00SJeff Kirsher BUG_ON(n > SGE_MAX_WR_LEN / 8); 747f7917c00SJeff Kirsher return DIV_ROUND_UP(n, 8); 748f7917c00SJeff Kirsher } 749f7917c00SJeff Kirsher 750f7917c00SJeff Kirsher /** 751f7917c00SJeff Kirsher * is_eth_imm - can an Ethernet packet be sent as immediate data? 752f7917c00SJeff Kirsher * @skb: the packet 753f7917c00SJeff Kirsher * 754f7917c00SJeff Kirsher * Returns whether an Ethernet packet is small enough to fit as 7550034b298SKumar Sanghvi * immediate data. Return value corresponds to headroom required. 756f7917c00SJeff Kirsher */ 757f7917c00SJeff Kirsher static inline int is_eth_imm(const struct sk_buff *skb) 758f7917c00SJeff Kirsher { 7590034b298SKumar Sanghvi int hdrlen = skb_shinfo(skb)->gso_size ? 7600034b298SKumar Sanghvi sizeof(struct cpl_tx_pkt_lso_core) : 0; 7610034b298SKumar Sanghvi 7620034b298SKumar Sanghvi hdrlen += sizeof(struct cpl_tx_pkt); 7630034b298SKumar Sanghvi if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen) 7640034b298SKumar Sanghvi return hdrlen; 7650034b298SKumar Sanghvi return 0; 766f7917c00SJeff Kirsher } 767f7917c00SJeff Kirsher 768f7917c00SJeff Kirsher /** 769f7917c00SJeff Kirsher * calc_tx_flits - calculate the number of flits for a packet Tx WR 770f7917c00SJeff Kirsher * @skb: the packet 771f7917c00SJeff Kirsher * 772f7917c00SJeff Kirsher * Returns the number of flits needed for a Tx WR for the given Ethernet 773f7917c00SJeff Kirsher * packet, including the needed WR and CPL headers. 774f7917c00SJeff Kirsher */ 775f7917c00SJeff Kirsher static inline unsigned int calc_tx_flits(const struct sk_buff *skb) 776f7917c00SJeff Kirsher { 777f7917c00SJeff Kirsher unsigned int flits; 7780034b298SKumar Sanghvi int hdrlen = is_eth_imm(skb); 779f7917c00SJeff Kirsher 7800034b298SKumar Sanghvi if (hdrlen) 7810034b298SKumar Sanghvi return DIV_ROUND_UP(skb->len + hdrlen, sizeof(__be64)); 782f7917c00SJeff Kirsher 783f7917c00SJeff Kirsher flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 4; 784f7917c00SJeff Kirsher if (skb_shinfo(skb)->gso_size) 785f7917c00SJeff Kirsher flits += 2; 786f7917c00SJeff Kirsher return flits; 787f7917c00SJeff Kirsher } 788f7917c00SJeff Kirsher 789f7917c00SJeff Kirsher /** 790f7917c00SJeff Kirsher * calc_tx_descs - calculate the number of Tx descriptors for a packet 791f7917c00SJeff Kirsher * @skb: the packet 792f7917c00SJeff Kirsher * 793f7917c00SJeff Kirsher * Returns the number of Tx descriptors needed for the given Ethernet 794f7917c00SJeff Kirsher * packet, including the needed WR and CPL headers. 795f7917c00SJeff Kirsher */ 796f7917c00SJeff Kirsher static inline unsigned int calc_tx_descs(const struct sk_buff *skb) 797f7917c00SJeff Kirsher { 798f7917c00SJeff Kirsher return flits_to_desc(calc_tx_flits(skb)); 799f7917c00SJeff Kirsher } 800f7917c00SJeff Kirsher 801f7917c00SJeff Kirsher /** 802f7917c00SJeff Kirsher * write_sgl - populate a scatter/gather list for a packet 803f7917c00SJeff Kirsher * @skb: the packet 804f7917c00SJeff Kirsher * @q: the Tx queue we are writing into 805f7917c00SJeff Kirsher * @sgl: starting location for writing the SGL 806f7917c00SJeff Kirsher * @end: points right after the end of the SGL 807f7917c00SJeff Kirsher * @start: start offset into skb main-body data to include in the SGL 808f7917c00SJeff Kirsher * @addr: the list of bus addresses for the SGL elements 809f7917c00SJeff Kirsher * 810f7917c00SJeff Kirsher * Generates a gather list for the buffers that make up a packet. 811f7917c00SJeff Kirsher * The caller must provide adequate space for the SGL that will be written. 812f7917c00SJeff Kirsher * The SGL includes all of the packet's page fragments and the data in its 813f7917c00SJeff Kirsher * main body except for the first @start bytes. @sgl must be 16-byte 814f7917c00SJeff Kirsher * aligned and within a Tx descriptor with available space. @end points 815f7917c00SJeff Kirsher * right after the end of the SGL but does not account for any potential 816f7917c00SJeff Kirsher * wrap around, i.e., @end > @sgl. 817f7917c00SJeff Kirsher */ 818f7917c00SJeff Kirsher static void write_sgl(const struct sk_buff *skb, struct sge_txq *q, 819f7917c00SJeff Kirsher struct ulptx_sgl *sgl, u64 *end, unsigned int start, 820f7917c00SJeff Kirsher const dma_addr_t *addr) 821f7917c00SJeff Kirsher { 822f7917c00SJeff Kirsher unsigned int i, len; 823f7917c00SJeff Kirsher struct ulptx_sge_pair *to; 824f7917c00SJeff Kirsher const struct skb_shared_info *si = skb_shinfo(skb); 825f7917c00SJeff Kirsher unsigned int nfrags = si->nr_frags; 826f7917c00SJeff Kirsher struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1]; 827f7917c00SJeff Kirsher 828f7917c00SJeff Kirsher len = skb_headlen(skb) - start; 829f7917c00SJeff Kirsher if (likely(len)) { 830f7917c00SJeff Kirsher sgl->len0 = htonl(len); 831f7917c00SJeff Kirsher sgl->addr0 = cpu_to_be64(addr[0] + start); 832f7917c00SJeff Kirsher nfrags++; 833f7917c00SJeff Kirsher } else { 8349e903e08SEric Dumazet sgl->len0 = htonl(skb_frag_size(&si->frags[0])); 835f7917c00SJeff Kirsher sgl->addr0 = cpu_to_be64(addr[1]); 836f7917c00SJeff Kirsher } 837f7917c00SJeff Kirsher 838bdc590b9SHariprasad Shenai sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) | 839bdc590b9SHariprasad Shenai ULPTX_NSGE_V(nfrags)); 840f7917c00SJeff Kirsher if (likely(--nfrags == 0)) 841f7917c00SJeff Kirsher return; 842f7917c00SJeff Kirsher /* 843f7917c00SJeff Kirsher * Most of the complexity below deals with the possibility we hit the 844f7917c00SJeff Kirsher * end of the queue in the middle of writing the SGL. For this case 845f7917c00SJeff Kirsher * only we create the SGL in a temporary buffer and then copy it. 846f7917c00SJeff Kirsher */ 847f7917c00SJeff Kirsher to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge; 848f7917c00SJeff Kirsher 849f7917c00SJeff Kirsher for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) { 8509e903e08SEric Dumazet to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i])); 8519e903e08SEric Dumazet to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i])); 852f7917c00SJeff Kirsher to->addr[0] = cpu_to_be64(addr[i]); 853f7917c00SJeff Kirsher to->addr[1] = cpu_to_be64(addr[++i]); 854f7917c00SJeff Kirsher } 855f7917c00SJeff Kirsher if (nfrags) { 8569e903e08SEric Dumazet to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i])); 857f7917c00SJeff Kirsher to->len[1] = cpu_to_be32(0); 858f7917c00SJeff Kirsher to->addr[0] = cpu_to_be64(addr[i + 1]); 859f7917c00SJeff Kirsher } 860f7917c00SJeff Kirsher if (unlikely((u8 *)end > (u8 *)q->stat)) { 861f7917c00SJeff Kirsher unsigned int part0 = (u8 *)q->stat - (u8 *)sgl->sge, part1; 862f7917c00SJeff Kirsher 863f7917c00SJeff Kirsher if (likely(part0)) 864f7917c00SJeff Kirsher memcpy(sgl->sge, buf, part0); 865f7917c00SJeff Kirsher part1 = (u8 *)end - (u8 *)q->stat; 866f7917c00SJeff Kirsher memcpy(q->desc, (u8 *)buf + part0, part1); 867f7917c00SJeff Kirsher end = (void *)q->desc + part1; 868f7917c00SJeff Kirsher } 869f7917c00SJeff Kirsher if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */ 87064699336SJoe Perches *end = 0; 871f7917c00SJeff Kirsher } 872f7917c00SJeff Kirsher 873df64e4d3SHariprasad Shenai /* This function copies 64 byte coalesced work request to 874df64e4d3SHariprasad Shenai * memory mapped BAR2 space. For coalesced WR SGE fetches 875df64e4d3SHariprasad Shenai * data from the FIFO instead of from Host. 87622adfe0aSSantosh Rastapur */ 877df64e4d3SHariprasad Shenai static void cxgb_pio_copy(u64 __iomem *dst, u64 *src) 87822adfe0aSSantosh Rastapur { 879df64e4d3SHariprasad Shenai int count = 8; 88022adfe0aSSantosh Rastapur 88122adfe0aSSantosh Rastapur while (count) { 88222adfe0aSSantosh Rastapur writeq(*src, dst); 88322adfe0aSSantosh Rastapur src++; 88422adfe0aSSantosh Rastapur dst++; 88522adfe0aSSantosh Rastapur count--; 88622adfe0aSSantosh Rastapur } 88722adfe0aSSantosh Rastapur } 88822adfe0aSSantosh Rastapur 889f7917c00SJeff Kirsher /** 890f7917c00SJeff Kirsher * ring_tx_db - check and potentially ring a Tx queue's doorbell 891f7917c00SJeff Kirsher * @adap: the adapter 892f7917c00SJeff Kirsher * @q: the Tx queue 893f7917c00SJeff Kirsher * @n: number of new descriptors to give to HW 894f7917c00SJeff Kirsher * 895f7917c00SJeff Kirsher * Ring the doorbel for a Tx queue. 896f7917c00SJeff Kirsher */ 897f7917c00SJeff Kirsher static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) 898f7917c00SJeff Kirsher { 899d63a6dcfSHariprasad Shenai wmb(); /* write descriptors before telling HW */ 900d63a6dcfSHariprasad Shenai 901df64e4d3SHariprasad Shenai /* If we don't have access to the new User Doorbell (T5+), use the old 902df64e4d3SHariprasad Shenai * doorbell mechanism; otherwise use the new BAR2 mechanism. 903df64e4d3SHariprasad Shenai */ 904df64e4d3SHariprasad Shenai if (unlikely(q->bar2_addr == NULL)) { 905f612b815SHariprasad Shenai u32 val = PIDX_V(n); 90605eb2389SSteve Wise unsigned long flags; 90722adfe0aSSantosh Rastapur 908d63a6dcfSHariprasad Shenai /* For T4 we need to participate in the Doorbell Recovery 909d63a6dcfSHariprasad Shenai * mechanism. 910d63a6dcfSHariprasad Shenai */ 91105eb2389SSteve Wise spin_lock_irqsave(&q->db_lock, flags); 912d63a6dcfSHariprasad Shenai if (!q->db_disabled) 913f612b815SHariprasad Shenai t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 914f612b815SHariprasad Shenai QID_V(q->cntxt_id) | val); 915d63a6dcfSHariprasad Shenai else 91605eb2389SSteve Wise q->db_pidx_inc += n; 9173069ee9bSVipul Pandya q->db_pidx = q->pidx; 91805eb2389SSteve Wise spin_unlock_irqrestore(&q->db_lock, flags); 919d63a6dcfSHariprasad Shenai } else { 920f612b815SHariprasad Shenai u32 val = PIDX_T5_V(n); 921d63a6dcfSHariprasad Shenai 922d63a6dcfSHariprasad Shenai /* T4 and later chips share the same PIDX field offset within 923d63a6dcfSHariprasad Shenai * the doorbell, but T5 and later shrank the field in order to 924d63a6dcfSHariprasad Shenai * gain a bit for Doorbell Priority. The field was absurdly 925d63a6dcfSHariprasad Shenai * large in the first place (14 bits) so we just use the T5 926d63a6dcfSHariprasad Shenai * and later limits and warn if a Queue ID is too large. 927d63a6dcfSHariprasad Shenai */ 928f612b815SHariprasad Shenai WARN_ON(val & DBPRIO_F); 929d63a6dcfSHariprasad Shenai 930df64e4d3SHariprasad Shenai /* If we're only writing a single TX Descriptor and we can use 931df64e4d3SHariprasad Shenai * Inferred QID registers, we can use the Write Combining 932df64e4d3SHariprasad Shenai * Gather Buffer; otherwise we use the simple doorbell. 933d63a6dcfSHariprasad Shenai */ 934df64e4d3SHariprasad Shenai if (n == 1 && q->bar2_qid == 0) { 935d63a6dcfSHariprasad Shenai int index = (q->pidx 936d63a6dcfSHariprasad Shenai ? (q->pidx - 1) 937d63a6dcfSHariprasad Shenai : (q->size - 1)); 938df64e4d3SHariprasad Shenai u64 *wr = (u64 *)&q->desc[index]; 939d63a6dcfSHariprasad Shenai 940df64e4d3SHariprasad Shenai cxgb_pio_copy((u64 __iomem *) 941df64e4d3SHariprasad Shenai (q->bar2_addr + SGE_UDB_WCDOORBELL), 942df64e4d3SHariprasad Shenai wr); 943d63a6dcfSHariprasad Shenai } else { 944f612b815SHariprasad Shenai writel(val | QID_V(q->bar2_qid), 945df64e4d3SHariprasad Shenai q->bar2_addr + SGE_UDB_KDOORBELL); 946d63a6dcfSHariprasad Shenai } 947d63a6dcfSHariprasad Shenai 948d63a6dcfSHariprasad Shenai /* This Write Memory Barrier will force the write to the User 949d63a6dcfSHariprasad Shenai * Doorbell area to be flushed. This is needed to prevent 950d63a6dcfSHariprasad Shenai * writes on different CPUs for the same queue from hitting 951d63a6dcfSHariprasad Shenai * the adapter out of order. This is required when some Work 952d63a6dcfSHariprasad Shenai * Requests take the Write Combine Gather Buffer path (user 953d63a6dcfSHariprasad Shenai * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some 954d63a6dcfSHariprasad Shenai * take the traditional path where we simply increment the 955d63a6dcfSHariprasad Shenai * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the 956d63a6dcfSHariprasad Shenai * hardware DMA read the actual Work Request. 957d63a6dcfSHariprasad Shenai */ 958d63a6dcfSHariprasad Shenai wmb(); 959d63a6dcfSHariprasad Shenai } 960f7917c00SJeff Kirsher } 961f7917c00SJeff Kirsher 962f7917c00SJeff Kirsher /** 963f7917c00SJeff Kirsher * inline_tx_skb - inline a packet's data into Tx descriptors 964f7917c00SJeff Kirsher * @skb: the packet 965f7917c00SJeff Kirsher * @q: the Tx queue where the packet will be inlined 966f7917c00SJeff Kirsher * @pos: starting position in the Tx queue where to inline the packet 967f7917c00SJeff Kirsher * 968f7917c00SJeff Kirsher * Inline a packet's contents directly into Tx descriptors, starting at 969f7917c00SJeff Kirsher * the given position within the Tx DMA ring. 970f7917c00SJeff Kirsher * Most of the complexity of this operation is dealing with wrap arounds 971f7917c00SJeff Kirsher * in the middle of the packet we want to inline. 972f7917c00SJeff Kirsher */ 973f7917c00SJeff Kirsher static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 974f7917c00SJeff Kirsher void *pos) 975f7917c00SJeff Kirsher { 976f7917c00SJeff Kirsher u64 *p; 977f7917c00SJeff Kirsher int left = (void *)q->stat - pos; 978f7917c00SJeff Kirsher 979f7917c00SJeff Kirsher if (likely(skb->len <= left)) { 980f7917c00SJeff Kirsher if (likely(!skb->data_len)) 981f7917c00SJeff Kirsher skb_copy_from_linear_data(skb, pos, skb->len); 982f7917c00SJeff Kirsher else 983f7917c00SJeff Kirsher skb_copy_bits(skb, 0, pos, skb->len); 984f7917c00SJeff Kirsher pos += skb->len; 985f7917c00SJeff Kirsher } else { 986f7917c00SJeff Kirsher skb_copy_bits(skb, 0, pos, left); 987f7917c00SJeff Kirsher skb_copy_bits(skb, left, q->desc, skb->len - left); 988f7917c00SJeff Kirsher pos = (void *)q->desc + (skb->len - left); 989f7917c00SJeff Kirsher } 990f7917c00SJeff Kirsher 991f7917c00SJeff Kirsher /* 0-pad to multiple of 16 */ 992f7917c00SJeff Kirsher p = PTR_ALIGN(pos, 8); 993f7917c00SJeff Kirsher if ((uintptr_t)p & 8) 994f7917c00SJeff Kirsher *p = 0; 995f7917c00SJeff Kirsher } 996f7917c00SJeff Kirsher 997f7917c00SJeff Kirsher /* 998f7917c00SJeff Kirsher * Figure out what HW csum a packet wants and return the appropriate control 999f7917c00SJeff Kirsher * bits. 1000f7917c00SJeff Kirsher */ 1001f7917c00SJeff Kirsher static u64 hwcsum(const struct sk_buff *skb) 1002f7917c00SJeff Kirsher { 1003f7917c00SJeff Kirsher int csum_type; 1004f7917c00SJeff Kirsher const struct iphdr *iph = ip_hdr(skb); 1005f7917c00SJeff Kirsher 1006f7917c00SJeff Kirsher if (iph->version == 4) { 1007f7917c00SJeff Kirsher if (iph->protocol == IPPROTO_TCP) 1008f7917c00SJeff Kirsher csum_type = TX_CSUM_TCPIP; 1009f7917c00SJeff Kirsher else if (iph->protocol == IPPROTO_UDP) 1010f7917c00SJeff Kirsher csum_type = TX_CSUM_UDPIP; 1011f7917c00SJeff Kirsher else { 1012f7917c00SJeff Kirsher nocsum: /* 1013f7917c00SJeff Kirsher * unknown protocol, disable HW csum 1014f7917c00SJeff Kirsher * and hope a bad packet is detected 1015f7917c00SJeff Kirsher */ 1016f7917c00SJeff Kirsher return TXPKT_L4CSUM_DIS; 1017f7917c00SJeff Kirsher } 1018f7917c00SJeff Kirsher } else { 1019f7917c00SJeff Kirsher /* 1020f7917c00SJeff Kirsher * this doesn't work with extension headers 1021f7917c00SJeff Kirsher */ 1022f7917c00SJeff Kirsher const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph; 1023f7917c00SJeff Kirsher 1024f7917c00SJeff Kirsher if (ip6h->nexthdr == IPPROTO_TCP) 1025f7917c00SJeff Kirsher csum_type = TX_CSUM_TCPIP6; 1026f7917c00SJeff Kirsher else if (ip6h->nexthdr == IPPROTO_UDP) 1027f7917c00SJeff Kirsher csum_type = TX_CSUM_UDPIP6; 1028f7917c00SJeff Kirsher else 1029f7917c00SJeff Kirsher goto nocsum; 1030f7917c00SJeff Kirsher } 1031f7917c00SJeff Kirsher 1032f7917c00SJeff Kirsher if (likely(csum_type >= TX_CSUM_TCPIP)) 1033f7917c00SJeff Kirsher return TXPKT_CSUM_TYPE(csum_type) | 1034f7917c00SJeff Kirsher TXPKT_IPHDR_LEN(skb_network_header_len(skb)) | 1035f7917c00SJeff Kirsher TXPKT_ETHHDR_LEN(skb_network_offset(skb) - ETH_HLEN); 1036f7917c00SJeff Kirsher else { 1037f7917c00SJeff Kirsher int start = skb_transport_offset(skb); 1038f7917c00SJeff Kirsher 1039f7917c00SJeff Kirsher return TXPKT_CSUM_TYPE(csum_type) | TXPKT_CSUM_START(start) | 1040f7917c00SJeff Kirsher TXPKT_CSUM_LOC(start + skb->csum_offset); 1041f7917c00SJeff Kirsher } 1042f7917c00SJeff Kirsher } 1043f7917c00SJeff Kirsher 1044f7917c00SJeff Kirsher static void eth_txq_stop(struct sge_eth_txq *q) 1045f7917c00SJeff Kirsher { 1046f7917c00SJeff Kirsher netif_tx_stop_queue(q->txq); 1047f7917c00SJeff Kirsher q->q.stops++; 1048f7917c00SJeff Kirsher } 1049f7917c00SJeff Kirsher 1050f7917c00SJeff Kirsher static inline void txq_advance(struct sge_txq *q, unsigned int n) 1051f7917c00SJeff Kirsher { 1052f7917c00SJeff Kirsher q->in_use += n; 1053f7917c00SJeff Kirsher q->pidx += n; 1054f7917c00SJeff Kirsher if (q->pidx >= q->size) 1055f7917c00SJeff Kirsher q->pidx -= q->size; 1056f7917c00SJeff Kirsher } 1057f7917c00SJeff Kirsher 105884a200b3SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 105984a200b3SVarun Prakash static inline int 106084a200b3SVarun Prakash cxgb_fcoe_offload(struct sk_buff *skb, struct adapter *adap, 106184a200b3SVarun Prakash const struct port_info *pi, u64 *cntrl) 106284a200b3SVarun Prakash { 106384a200b3SVarun Prakash const struct cxgb_fcoe *fcoe = &pi->fcoe; 106484a200b3SVarun Prakash 106584a200b3SVarun Prakash if (!(fcoe->flags & CXGB_FCOE_ENABLED)) 106684a200b3SVarun Prakash return 0; 106784a200b3SVarun Prakash 106884a200b3SVarun Prakash if (skb->protocol != htons(ETH_P_FCOE)) 106984a200b3SVarun Prakash return 0; 107084a200b3SVarun Prakash 107184a200b3SVarun Prakash skb_reset_mac_header(skb); 107284a200b3SVarun Prakash skb->mac_len = sizeof(struct ethhdr); 107384a200b3SVarun Prakash 107484a200b3SVarun Prakash skb_set_network_header(skb, skb->mac_len); 107584a200b3SVarun Prakash skb_set_transport_header(skb, skb->mac_len + sizeof(struct fcoe_hdr)); 107684a200b3SVarun Prakash 107784a200b3SVarun Prakash if (!cxgb_fcoe_sof_eof_supported(adap, skb)) 107884a200b3SVarun Prakash return -ENOTSUPP; 107984a200b3SVarun Prakash 108084a200b3SVarun Prakash /* FC CRC offload */ 108184a200b3SVarun Prakash *cntrl = TXPKT_CSUM_TYPE(TX_CSUM_FCOE) | 108284a200b3SVarun Prakash TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS | 108384a200b3SVarun Prakash TXPKT_CSUM_START(CXGB_FCOE_TXPKT_CSUM_START) | 108484a200b3SVarun Prakash TXPKT_CSUM_END(CXGB_FCOE_TXPKT_CSUM_END) | 108584a200b3SVarun Prakash TXPKT_CSUM_LOC(CXGB_FCOE_TXPKT_CSUM_END); 108684a200b3SVarun Prakash return 0; 108784a200b3SVarun Prakash } 108884a200b3SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 108984a200b3SVarun Prakash 1090f7917c00SJeff Kirsher /** 1091f7917c00SJeff Kirsher * t4_eth_xmit - add a packet to an Ethernet Tx queue 1092f7917c00SJeff Kirsher * @skb: the packet 1093f7917c00SJeff Kirsher * @dev: the egress net device 1094f7917c00SJeff Kirsher * 1095f7917c00SJeff Kirsher * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled. 1096f7917c00SJeff Kirsher */ 1097f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev) 1098f7917c00SJeff Kirsher { 10990034b298SKumar Sanghvi int len; 1100f7917c00SJeff Kirsher u32 wr_mid; 1101f7917c00SJeff Kirsher u64 cntrl, *end; 1102f7917c00SJeff Kirsher int qidx, credits; 1103f7917c00SJeff Kirsher unsigned int flits, ndesc; 1104f7917c00SJeff Kirsher struct adapter *adap; 1105f7917c00SJeff Kirsher struct sge_eth_txq *q; 1106f7917c00SJeff Kirsher const struct port_info *pi; 1107f7917c00SJeff Kirsher struct fw_eth_tx_pkt_wr *wr; 1108f7917c00SJeff Kirsher struct cpl_tx_pkt_core *cpl; 1109f7917c00SJeff Kirsher const struct skb_shared_info *ssi; 1110f7917c00SJeff Kirsher dma_addr_t addr[MAX_SKB_FRAGS + 1]; 11110034b298SKumar Sanghvi bool immediate = false; 111284a200b3SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 111384a200b3SVarun Prakash int err; 111484a200b3SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 1115f7917c00SJeff Kirsher 1116f7917c00SJeff Kirsher /* 1117f7917c00SJeff Kirsher * The chip min packet length is 10 octets but play safe and reject 1118f7917c00SJeff Kirsher * anything shorter than an Ethernet header. 1119f7917c00SJeff Kirsher */ 1120f7917c00SJeff Kirsher if (unlikely(skb->len < ETH_HLEN)) { 1121a7525198SEric W. Biederman out_free: dev_kfree_skb_any(skb); 1122f7917c00SJeff Kirsher return NETDEV_TX_OK; 1123f7917c00SJeff Kirsher } 1124f7917c00SJeff Kirsher 1125f7917c00SJeff Kirsher pi = netdev_priv(dev); 1126f7917c00SJeff Kirsher adap = pi->adapter; 1127f7917c00SJeff Kirsher qidx = skb_get_queue_mapping(skb); 1128f7917c00SJeff Kirsher q = &adap->sge.ethtxq[qidx + pi->first_qset]; 1129f7917c00SJeff Kirsher 1130f7917c00SJeff Kirsher reclaim_completed_tx(adap, &q->q, true); 113184a200b3SVarun Prakash cntrl = TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS; 113284a200b3SVarun Prakash 113384a200b3SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 113484a200b3SVarun Prakash err = cxgb_fcoe_offload(skb, adap, pi, &cntrl); 113584a200b3SVarun Prakash if (unlikely(err == -ENOTSUPP)) 113684a200b3SVarun Prakash goto out_free; 113784a200b3SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 1138f7917c00SJeff Kirsher 1139f7917c00SJeff Kirsher flits = calc_tx_flits(skb); 1140f7917c00SJeff Kirsher ndesc = flits_to_desc(flits); 1141f7917c00SJeff Kirsher credits = txq_avail(&q->q) - ndesc; 1142f7917c00SJeff Kirsher 1143f7917c00SJeff Kirsher if (unlikely(credits < 0)) { 1144f7917c00SJeff Kirsher eth_txq_stop(q); 1145f7917c00SJeff Kirsher dev_err(adap->pdev_dev, 1146f7917c00SJeff Kirsher "%s: Tx ring %u full while queue awake!\n", 1147f7917c00SJeff Kirsher dev->name, qidx); 1148f7917c00SJeff Kirsher return NETDEV_TX_BUSY; 1149f7917c00SJeff Kirsher } 1150f7917c00SJeff Kirsher 11510034b298SKumar Sanghvi if (is_eth_imm(skb)) 11520034b298SKumar Sanghvi immediate = true; 11530034b298SKumar Sanghvi 11540034b298SKumar Sanghvi if (!immediate && 1155f7917c00SJeff Kirsher unlikely(map_skb(adap->pdev_dev, skb, addr) < 0)) { 1156f7917c00SJeff Kirsher q->mapping_err++; 1157f7917c00SJeff Kirsher goto out_free; 1158f7917c00SJeff Kirsher } 1159f7917c00SJeff Kirsher 1160e2ac9628SHariprasad Shenai wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2)); 1161f7917c00SJeff Kirsher if (unlikely(credits < ETHTXQ_STOP_THRES)) { 1162f7917c00SJeff Kirsher eth_txq_stop(q); 1163e2ac9628SHariprasad Shenai wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F; 1164f7917c00SJeff Kirsher } 1165f7917c00SJeff Kirsher 1166f7917c00SJeff Kirsher wr = (void *)&q->q.desc[q->q.pidx]; 1167f7917c00SJeff Kirsher wr->equiq_to_len16 = htonl(wr_mid); 1168f7917c00SJeff Kirsher wr->r3 = cpu_to_be64(0); 1169f7917c00SJeff Kirsher end = (u64 *)wr + flits; 1170f7917c00SJeff Kirsher 11710034b298SKumar Sanghvi len = immediate ? skb->len : 0; 1172f7917c00SJeff Kirsher ssi = skb_shinfo(skb); 1173f7917c00SJeff Kirsher if (ssi->gso_size) { 1174f7917c00SJeff Kirsher struct cpl_tx_pkt_lso *lso = (void *)wr; 1175f7917c00SJeff Kirsher bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0; 1176f7917c00SJeff Kirsher int l3hdr_len = skb_network_header_len(skb); 1177f7917c00SJeff Kirsher int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN; 1178f7917c00SJeff Kirsher 11790034b298SKumar Sanghvi len += sizeof(*lso); 1180e2ac9628SHariprasad Shenai wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) | 1181e2ac9628SHariprasad Shenai FW_WR_IMMDLEN_V(len)); 1182f7917c00SJeff Kirsher lso->c.lso_ctrl = htonl(LSO_OPCODE(CPL_TX_PKT_LSO) | 1183f7917c00SJeff Kirsher LSO_FIRST_SLICE | LSO_LAST_SLICE | 1184f7917c00SJeff Kirsher LSO_IPV6(v6) | 1185f7917c00SJeff Kirsher LSO_ETHHDR_LEN(eth_xtra_len / 4) | 1186f7917c00SJeff Kirsher LSO_IPHDR_LEN(l3hdr_len / 4) | 1187f7917c00SJeff Kirsher LSO_TCPHDR_LEN(tcp_hdr(skb)->doff)); 1188f7917c00SJeff Kirsher lso->c.ipid_ofst = htons(0); 1189f7917c00SJeff Kirsher lso->c.mss = htons(ssi->gso_size); 1190f7917c00SJeff Kirsher lso->c.seqno_offset = htonl(0); 11917207c0d1SHariprasad Shenai if (is_t4(adap->params.chip)) 1192f7917c00SJeff Kirsher lso->c.len = htonl(skb->len); 11937207c0d1SHariprasad Shenai else 11947207c0d1SHariprasad Shenai lso->c.len = htonl(LSO_T5_XFER_SIZE(skb->len)); 1195f7917c00SJeff Kirsher cpl = (void *)(lso + 1); 1196f7917c00SJeff Kirsher cntrl = TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) | 1197f7917c00SJeff Kirsher TXPKT_IPHDR_LEN(l3hdr_len) | 1198f7917c00SJeff Kirsher TXPKT_ETHHDR_LEN(eth_xtra_len); 1199f7917c00SJeff Kirsher q->tso++; 1200f7917c00SJeff Kirsher q->tx_cso += ssi->gso_segs; 1201f7917c00SJeff Kirsher } else { 1202ca71de6bSKumar Sanghvi len += sizeof(*cpl); 1203e2ac9628SHariprasad Shenai wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) | 1204e2ac9628SHariprasad Shenai FW_WR_IMMDLEN_V(len)); 1205f7917c00SJeff Kirsher cpl = (void *)(wr + 1); 1206f7917c00SJeff Kirsher if (skb->ip_summed == CHECKSUM_PARTIAL) { 1207f7917c00SJeff Kirsher cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS; 1208f7917c00SJeff Kirsher q->tx_cso++; 120984a200b3SVarun Prakash } 1210f7917c00SJeff Kirsher } 1211f7917c00SJeff Kirsher 1212df8a39deSJiri Pirko if (skb_vlan_tag_present(skb)) { 1213f7917c00SJeff Kirsher q->vlan_ins++; 1214df8a39deSJiri Pirko cntrl |= TXPKT_VLAN_VLD | TXPKT_VLAN(skb_vlan_tag_get(skb)); 121584a200b3SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 121684a200b3SVarun Prakash if (skb->protocol == htons(ETH_P_FCOE)) 121784a200b3SVarun Prakash cntrl |= TXPKT_VLAN( 121884a200b3SVarun Prakash ((skb->priority & 0x7) << VLAN_PRIO_SHIFT)); 121984a200b3SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 1220f7917c00SJeff Kirsher } 1221f7917c00SJeff Kirsher 1222f7917c00SJeff Kirsher cpl->ctrl0 = htonl(TXPKT_OPCODE(CPL_TX_PKT_XT) | 1223f7917c00SJeff Kirsher TXPKT_INTF(pi->tx_chan) | TXPKT_PF(adap->fn)); 1224f7917c00SJeff Kirsher cpl->pack = htons(0); 1225f7917c00SJeff Kirsher cpl->len = htons(skb->len); 1226f7917c00SJeff Kirsher cpl->ctrl1 = cpu_to_be64(cntrl); 1227f7917c00SJeff Kirsher 12280034b298SKumar Sanghvi if (immediate) { 1229f7917c00SJeff Kirsher inline_tx_skb(skb, &q->q, cpl + 1); 1230a7525198SEric W. Biederman dev_consume_skb_any(skb); 1231f7917c00SJeff Kirsher } else { 1232f7917c00SJeff Kirsher int last_desc; 1233f7917c00SJeff Kirsher 1234f7917c00SJeff Kirsher write_sgl(skb, &q->q, (struct ulptx_sgl *)(cpl + 1), end, 0, 1235f7917c00SJeff Kirsher addr); 1236f7917c00SJeff Kirsher skb_orphan(skb); 1237f7917c00SJeff Kirsher 1238f7917c00SJeff Kirsher last_desc = q->q.pidx + ndesc - 1; 1239f7917c00SJeff Kirsher if (last_desc >= q->q.size) 1240f7917c00SJeff Kirsher last_desc -= q->q.size; 1241f7917c00SJeff Kirsher q->q.sdesc[last_desc].skb = skb; 1242f7917c00SJeff Kirsher q->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1); 1243f7917c00SJeff Kirsher } 1244f7917c00SJeff Kirsher 1245f7917c00SJeff Kirsher txq_advance(&q->q, ndesc); 1246f7917c00SJeff Kirsher 1247f7917c00SJeff Kirsher ring_tx_db(adap, &q->q, ndesc); 1248f7917c00SJeff Kirsher return NETDEV_TX_OK; 1249f7917c00SJeff Kirsher } 1250f7917c00SJeff Kirsher 1251f7917c00SJeff Kirsher /** 1252f7917c00SJeff Kirsher * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs 1253f7917c00SJeff Kirsher * @q: the SGE control Tx queue 1254f7917c00SJeff Kirsher * 1255f7917c00SJeff Kirsher * This is a variant of reclaim_completed_tx() that is used for Tx queues 1256f7917c00SJeff Kirsher * that send only immediate data (presently just the control queues) and 1257f7917c00SJeff Kirsher * thus do not have any sk_buffs to release. 1258f7917c00SJeff Kirsher */ 1259f7917c00SJeff Kirsher static inline void reclaim_completed_tx_imm(struct sge_txq *q) 1260f7917c00SJeff Kirsher { 1261f7917c00SJeff Kirsher int hw_cidx = ntohs(q->stat->cidx); 1262f7917c00SJeff Kirsher int reclaim = hw_cidx - q->cidx; 1263f7917c00SJeff Kirsher 1264f7917c00SJeff Kirsher if (reclaim < 0) 1265f7917c00SJeff Kirsher reclaim += q->size; 1266f7917c00SJeff Kirsher 1267f7917c00SJeff Kirsher q->in_use -= reclaim; 1268f7917c00SJeff Kirsher q->cidx = hw_cidx; 1269f7917c00SJeff Kirsher } 1270f7917c00SJeff Kirsher 1271f7917c00SJeff Kirsher /** 1272f7917c00SJeff Kirsher * is_imm - check whether a packet can be sent as immediate data 1273f7917c00SJeff Kirsher * @skb: the packet 1274f7917c00SJeff Kirsher * 1275f7917c00SJeff Kirsher * Returns true if a packet can be sent as a WR with immediate data. 1276f7917c00SJeff Kirsher */ 1277f7917c00SJeff Kirsher static inline int is_imm(const struct sk_buff *skb) 1278f7917c00SJeff Kirsher { 1279f7917c00SJeff Kirsher return skb->len <= MAX_CTRL_WR_LEN; 1280f7917c00SJeff Kirsher } 1281f7917c00SJeff Kirsher 1282f7917c00SJeff Kirsher /** 1283f7917c00SJeff Kirsher * ctrlq_check_stop - check if a control queue is full and should stop 1284f7917c00SJeff Kirsher * @q: the queue 1285f7917c00SJeff Kirsher * @wr: most recent WR written to the queue 1286f7917c00SJeff Kirsher * 1287f7917c00SJeff Kirsher * Check if a control queue has become full and should be stopped. 1288f7917c00SJeff Kirsher * We clean up control queue descriptors very lazily, only when we are out. 1289f7917c00SJeff Kirsher * If the queue is still full after reclaiming any completed descriptors 1290f7917c00SJeff Kirsher * we suspend it and have the last WR wake it up. 1291f7917c00SJeff Kirsher */ 1292f7917c00SJeff Kirsher static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr) 1293f7917c00SJeff Kirsher { 1294f7917c00SJeff Kirsher reclaim_completed_tx_imm(&q->q); 1295f7917c00SJeff Kirsher if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { 1296e2ac9628SHariprasad Shenai wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F); 1297f7917c00SJeff Kirsher q->q.stops++; 1298f7917c00SJeff Kirsher q->full = 1; 1299f7917c00SJeff Kirsher } 1300f7917c00SJeff Kirsher } 1301f7917c00SJeff Kirsher 1302f7917c00SJeff Kirsher /** 1303f7917c00SJeff Kirsher * ctrl_xmit - send a packet through an SGE control Tx queue 1304f7917c00SJeff Kirsher * @q: the control queue 1305f7917c00SJeff Kirsher * @skb: the packet 1306f7917c00SJeff Kirsher * 1307f7917c00SJeff Kirsher * Send a packet through an SGE control Tx queue. Packets sent through 1308f7917c00SJeff Kirsher * a control queue must fit entirely as immediate data. 1309f7917c00SJeff Kirsher */ 1310f7917c00SJeff Kirsher static int ctrl_xmit(struct sge_ctrl_txq *q, struct sk_buff *skb) 1311f7917c00SJeff Kirsher { 1312f7917c00SJeff Kirsher unsigned int ndesc; 1313f7917c00SJeff Kirsher struct fw_wr_hdr *wr; 1314f7917c00SJeff Kirsher 1315f7917c00SJeff Kirsher if (unlikely(!is_imm(skb))) { 1316f7917c00SJeff Kirsher WARN_ON(1); 1317f7917c00SJeff Kirsher dev_kfree_skb(skb); 1318f7917c00SJeff Kirsher return NET_XMIT_DROP; 1319f7917c00SJeff Kirsher } 1320f7917c00SJeff Kirsher 1321f7917c00SJeff Kirsher ndesc = DIV_ROUND_UP(skb->len, sizeof(struct tx_desc)); 1322f7917c00SJeff Kirsher spin_lock(&q->sendq.lock); 1323f7917c00SJeff Kirsher 1324f7917c00SJeff Kirsher if (unlikely(q->full)) { 1325f7917c00SJeff Kirsher skb->priority = ndesc; /* save for restart */ 1326f7917c00SJeff Kirsher __skb_queue_tail(&q->sendq, skb); 1327f7917c00SJeff Kirsher spin_unlock(&q->sendq.lock); 1328f7917c00SJeff Kirsher return NET_XMIT_CN; 1329f7917c00SJeff Kirsher } 1330f7917c00SJeff Kirsher 1331f7917c00SJeff Kirsher wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx]; 1332f7917c00SJeff Kirsher inline_tx_skb(skb, &q->q, wr); 1333f7917c00SJeff Kirsher 1334f7917c00SJeff Kirsher txq_advance(&q->q, ndesc); 1335f7917c00SJeff Kirsher if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) 1336f7917c00SJeff Kirsher ctrlq_check_stop(q, wr); 1337f7917c00SJeff Kirsher 1338f7917c00SJeff Kirsher ring_tx_db(q->adap, &q->q, ndesc); 1339f7917c00SJeff Kirsher spin_unlock(&q->sendq.lock); 1340f7917c00SJeff Kirsher 1341f7917c00SJeff Kirsher kfree_skb(skb); 1342f7917c00SJeff Kirsher return NET_XMIT_SUCCESS; 1343f7917c00SJeff Kirsher } 1344f7917c00SJeff Kirsher 1345f7917c00SJeff Kirsher /** 1346f7917c00SJeff Kirsher * restart_ctrlq - restart a suspended control queue 1347f7917c00SJeff Kirsher * @data: the control queue to restart 1348f7917c00SJeff Kirsher * 1349f7917c00SJeff Kirsher * Resumes transmission on a suspended Tx control queue. 1350f7917c00SJeff Kirsher */ 1351f7917c00SJeff Kirsher static void restart_ctrlq(unsigned long data) 1352f7917c00SJeff Kirsher { 1353f7917c00SJeff Kirsher struct sk_buff *skb; 1354f7917c00SJeff Kirsher unsigned int written = 0; 1355f7917c00SJeff Kirsher struct sge_ctrl_txq *q = (struct sge_ctrl_txq *)data; 1356f7917c00SJeff Kirsher 1357f7917c00SJeff Kirsher spin_lock(&q->sendq.lock); 1358f7917c00SJeff Kirsher reclaim_completed_tx_imm(&q->q); 1359f7917c00SJeff Kirsher BUG_ON(txq_avail(&q->q) < TXQ_STOP_THRES); /* q should be empty */ 1360f7917c00SJeff Kirsher 1361f7917c00SJeff Kirsher while ((skb = __skb_dequeue(&q->sendq)) != NULL) { 1362f7917c00SJeff Kirsher struct fw_wr_hdr *wr; 1363f7917c00SJeff Kirsher unsigned int ndesc = skb->priority; /* previously saved */ 1364f7917c00SJeff Kirsher 1365f7917c00SJeff Kirsher /* 1366f7917c00SJeff Kirsher * Write descriptors and free skbs outside the lock to limit 1367f7917c00SJeff Kirsher * wait times. q->full is still set so new skbs will be queued. 1368f7917c00SJeff Kirsher */ 1369f7917c00SJeff Kirsher spin_unlock(&q->sendq.lock); 1370f7917c00SJeff Kirsher 1371f7917c00SJeff Kirsher wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx]; 1372f7917c00SJeff Kirsher inline_tx_skb(skb, &q->q, wr); 1373f7917c00SJeff Kirsher kfree_skb(skb); 1374f7917c00SJeff Kirsher 1375f7917c00SJeff Kirsher written += ndesc; 1376f7917c00SJeff Kirsher txq_advance(&q->q, ndesc); 1377f7917c00SJeff Kirsher if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { 1378f7917c00SJeff Kirsher unsigned long old = q->q.stops; 1379f7917c00SJeff Kirsher 1380f7917c00SJeff Kirsher ctrlq_check_stop(q, wr); 1381f7917c00SJeff Kirsher if (q->q.stops != old) { /* suspended anew */ 1382f7917c00SJeff Kirsher spin_lock(&q->sendq.lock); 1383f7917c00SJeff Kirsher goto ringdb; 1384f7917c00SJeff Kirsher } 1385f7917c00SJeff Kirsher } 1386f7917c00SJeff Kirsher if (written > 16) { 1387f7917c00SJeff Kirsher ring_tx_db(q->adap, &q->q, written); 1388f7917c00SJeff Kirsher written = 0; 1389f7917c00SJeff Kirsher } 1390f7917c00SJeff Kirsher spin_lock(&q->sendq.lock); 1391f7917c00SJeff Kirsher } 1392f7917c00SJeff Kirsher q->full = 0; 1393f7917c00SJeff Kirsher ringdb: if (written) 1394f7917c00SJeff Kirsher ring_tx_db(q->adap, &q->q, written); 1395f7917c00SJeff Kirsher spin_unlock(&q->sendq.lock); 1396f7917c00SJeff Kirsher } 1397f7917c00SJeff Kirsher 1398f7917c00SJeff Kirsher /** 1399f7917c00SJeff Kirsher * t4_mgmt_tx - send a management message 1400f7917c00SJeff Kirsher * @adap: the adapter 1401f7917c00SJeff Kirsher * @skb: the packet containing the management message 1402f7917c00SJeff Kirsher * 1403f7917c00SJeff Kirsher * Send a management message through control queue 0. 1404f7917c00SJeff Kirsher */ 1405f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb) 1406f7917c00SJeff Kirsher { 1407f7917c00SJeff Kirsher int ret; 1408f7917c00SJeff Kirsher 1409f7917c00SJeff Kirsher local_bh_disable(); 1410f7917c00SJeff Kirsher ret = ctrl_xmit(&adap->sge.ctrlq[0], skb); 1411f7917c00SJeff Kirsher local_bh_enable(); 1412f7917c00SJeff Kirsher return ret; 1413f7917c00SJeff Kirsher } 1414f7917c00SJeff Kirsher 1415f7917c00SJeff Kirsher /** 1416f7917c00SJeff Kirsher * is_ofld_imm - check whether a packet can be sent as immediate data 1417f7917c00SJeff Kirsher * @skb: the packet 1418f7917c00SJeff Kirsher * 1419f7917c00SJeff Kirsher * Returns true if a packet can be sent as an offload WR with immediate 1420f7917c00SJeff Kirsher * data. We currently use the same limit as for Ethernet packets. 1421f7917c00SJeff Kirsher */ 1422f7917c00SJeff Kirsher static inline int is_ofld_imm(const struct sk_buff *skb) 1423f7917c00SJeff Kirsher { 1424f7917c00SJeff Kirsher return skb->len <= MAX_IMM_TX_PKT_LEN; 1425f7917c00SJeff Kirsher } 1426f7917c00SJeff Kirsher 1427f7917c00SJeff Kirsher /** 1428f7917c00SJeff Kirsher * calc_tx_flits_ofld - calculate # of flits for an offload packet 1429f7917c00SJeff Kirsher * @skb: the packet 1430f7917c00SJeff Kirsher * 1431f7917c00SJeff Kirsher * Returns the number of flits needed for the given offload packet. 1432f7917c00SJeff Kirsher * These packets are already fully constructed and no additional headers 1433f7917c00SJeff Kirsher * will be added. 1434f7917c00SJeff Kirsher */ 1435f7917c00SJeff Kirsher static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb) 1436f7917c00SJeff Kirsher { 1437f7917c00SJeff Kirsher unsigned int flits, cnt; 1438f7917c00SJeff Kirsher 1439f7917c00SJeff Kirsher if (is_ofld_imm(skb)) 1440f7917c00SJeff Kirsher return DIV_ROUND_UP(skb->len, 8); 1441f7917c00SJeff Kirsher 1442f7917c00SJeff Kirsher flits = skb_transport_offset(skb) / 8U; /* headers */ 1443f7917c00SJeff Kirsher cnt = skb_shinfo(skb)->nr_frags; 144415dd16c2SLi RongQing if (skb_tail_pointer(skb) != skb_transport_header(skb)) 1445f7917c00SJeff Kirsher cnt++; 1446f7917c00SJeff Kirsher return flits + sgl_len(cnt); 1447f7917c00SJeff Kirsher } 1448f7917c00SJeff Kirsher 1449f7917c00SJeff Kirsher /** 1450f7917c00SJeff Kirsher * txq_stop_maperr - stop a Tx queue due to I/O MMU exhaustion 1451f7917c00SJeff Kirsher * @adap: the adapter 1452f7917c00SJeff Kirsher * @q: the queue to stop 1453f7917c00SJeff Kirsher * 1454f7917c00SJeff Kirsher * Mark a Tx queue stopped due to I/O MMU exhaustion and resulting 1455f7917c00SJeff Kirsher * inability to map packets. A periodic timer attempts to restart 1456f7917c00SJeff Kirsher * queues so marked. 1457f7917c00SJeff Kirsher */ 1458f7917c00SJeff Kirsher static void txq_stop_maperr(struct sge_ofld_txq *q) 1459f7917c00SJeff Kirsher { 1460f7917c00SJeff Kirsher q->mapping_err++; 1461f7917c00SJeff Kirsher q->q.stops++; 1462f7917c00SJeff Kirsher set_bit(q->q.cntxt_id - q->adap->sge.egr_start, 1463f7917c00SJeff Kirsher q->adap->sge.txq_maperr); 1464f7917c00SJeff Kirsher } 1465f7917c00SJeff Kirsher 1466f7917c00SJeff Kirsher /** 1467f7917c00SJeff Kirsher * ofldtxq_stop - stop an offload Tx queue that has become full 1468f7917c00SJeff Kirsher * @q: the queue to stop 1469f7917c00SJeff Kirsher * @skb: the packet causing the queue to become full 1470f7917c00SJeff Kirsher * 1471f7917c00SJeff Kirsher * Stops an offload Tx queue that has become full and modifies the packet 1472f7917c00SJeff Kirsher * being written to request a wakeup. 1473f7917c00SJeff Kirsher */ 1474f7917c00SJeff Kirsher static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb) 1475f7917c00SJeff Kirsher { 1476f7917c00SJeff Kirsher struct fw_wr_hdr *wr = (struct fw_wr_hdr *)skb->data; 1477f7917c00SJeff Kirsher 1478e2ac9628SHariprasad Shenai wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F); 1479f7917c00SJeff Kirsher q->q.stops++; 1480f7917c00SJeff Kirsher q->full = 1; 1481f7917c00SJeff Kirsher } 1482f7917c00SJeff Kirsher 1483f7917c00SJeff Kirsher /** 1484f7917c00SJeff Kirsher * service_ofldq - restart a suspended offload queue 1485f7917c00SJeff Kirsher * @q: the offload queue 1486f7917c00SJeff Kirsher * 1487f7917c00SJeff Kirsher * Services an offload Tx queue by moving packets from its packet queue 1488f7917c00SJeff Kirsher * to the HW Tx ring. The function starts and ends with the queue locked. 1489f7917c00SJeff Kirsher */ 1490f7917c00SJeff Kirsher static void service_ofldq(struct sge_ofld_txq *q) 1491f7917c00SJeff Kirsher { 1492f7917c00SJeff Kirsher u64 *pos; 1493f7917c00SJeff Kirsher int credits; 1494f7917c00SJeff Kirsher struct sk_buff *skb; 1495f7917c00SJeff Kirsher unsigned int written = 0; 1496f7917c00SJeff Kirsher unsigned int flits, ndesc; 1497f7917c00SJeff Kirsher 1498f7917c00SJeff Kirsher while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) { 1499f7917c00SJeff Kirsher /* 1500f7917c00SJeff Kirsher * We drop the lock but leave skb on sendq, thus retaining 1501f7917c00SJeff Kirsher * exclusive access to the state of the queue. 1502f7917c00SJeff Kirsher */ 1503f7917c00SJeff Kirsher spin_unlock(&q->sendq.lock); 1504f7917c00SJeff Kirsher 1505f7917c00SJeff Kirsher reclaim_completed_tx(q->adap, &q->q, false); 1506f7917c00SJeff Kirsher 1507f7917c00SJeff Kirsher flits = skb->priority; /* previously saved */ 1508f7917c00SJeff Kirsher ndesc = flits_to_desc(flits); 1509f7917c00SJeff Kirsher credits = txq_avail(&q->q) - ndesc; 1510f7917c00SJeff Kirsher BUG_ON(credits < 0); 1511f7917c00SJeff Kirsher if (unlikely(credits < TXQ_STOP_THRES)) 1512f7917c00SJeff Kirsher ofldtxq_stop(q, skb); 1513f7917c00SJeff Kirsher 1514f7917c00SJeff Kirsher pos = (u64 *)&q->q.desc[q->q.pidx]; 1515f7917c00SJeff Kirsher if (is_ofld_imm(skb)) 1516f7917c00SJeff Kirsher inline_tx_skb(skb, &q->q, pos); 1517f7917c00SJeff Kirsher else if (map_skb(q->adap->pdev_dev, skb, 1518f7917c00SJeff Kirsher (dma_addr_t *)skb->head)) { 1519f7917c00SJeff Kirsher txq_stop_maperr(q); 1520f7917c00SJeff Kirsher spin_lock(&q->sendq.lock); 1521f7917c00SJeff Kirsher break; 1522f7917c00SJeff Kirsher } else { 1523f7917c00SJeff Kirsher int last_desc, hdr_len = skb_transport_offset(skb); 1524f7917c00SJeff Kirsher 1525f7917c00SJeff Kirsher memcpy(pos, skb->data, hdr_len); 1526f7917c00SJeff Kirsher write_sgl(skb, &q->q, (void *)pos + hdr_len, 1527f7917c00SJeff Kirsher pos + flits, hdr_len, 1528f7917c00SJeff Kirsher (dma_addr_t *)skb->head); 1529f7917c00SJeff Kirsher #ifdef CONFIG_NEED_DMA_MAP_STATE 1530f7917c00SJeff Kirsher skb->dev = q->adap->port[0]; 1531f7917c00SJeff Kirsher skb->destructor = deferred_unmap_destructor; 1532f7917c00SJeff Kirsher #endif 1533f7917c00SJeff Kirsher last_desc = q->q.pidx + ndesc - 1; 1534f7917c00SJeff Kirsher if (last_desc >= q->q.size) 1535f7917c00SJeff Kirsher last_desc -= q->q.size; 1536f7917c00SJeff Kirsher q->q.sdesc[last_desc].skb = skb; 1537f7917c00SJeff Kirsher } 1538f7917c00SJeff Kirsher 1539f7917c00SJeff Kirsher txq_advance(&q->q, ndesc); 1540f7917c00SJeff Kirsher written += ndesc; 1541f7917c00SJeff Kirsher if (unlikely(written > 32)) { 1542f7917c00SJeff Kirsher ring_tx_db(q->adap, &q->q, written); 1543f7917c00SJeff Kirsher written = 0; 1544f7917c00SJeff Kirsher } 1545f7917c00SJeff Kirsher 1546f7917c00SJeff Kirsher spin_lock(&q->sendq.lock); 1547f7917c00SJeff Kirsher __skb_unlink(skb, &q->sendq); 1548f7917c00SJeff Kirsher if (is_ofld_imm(skb)) 1549f7917c00SJeff Kirsher kfree_skb(skb); 1550f7917c00SJeff Kirsher } 1551f7917c00SJeff Kirsher if (likely(written)) 1552f7917c00SJeff Kirsher ring_tx_db(q->adap, &q->q, written); 1553f7917c00SJeff Kirsher } 1554f7917c00SJeff Kirsher 1555f7917c00SJeff Kirsher /** 1556f7917c00SJeff Kirsher * ofld_xmit - send a packet through an offload queue 1557f7917c00SJeff Kirsher * @q: the Tx offload queue 1558f7917c00SJeff Kirsher * @skb: the packet 1559f7917c00SJeff Kirsher * 1560f7917c00SJeff Kirsher * Send an offload packet through an SGE offload queue. 1561f7917c00SJeff Kirsher */ 1562f7917c00SJeff Kirsher static int ofld_xmit(struct sge_ofld_txq *q, struct sk_buff *skb) 1563f7917c00SJeff Kirsher { 1564f7917c00SJeff Kirsher skb->priority = calc_tx_flits_ofld(skb); /* save for restart */ 1565f7917c00SJeff Kirsher spin_lock(&q->sendq.lock); 1566f7917c00SJeff Kirsher __skb_queue_tail(&q->sendq, skb); 1567f7917c00SJeff Kirsher if (q->sendq.qlen == 1) 1568f7917c00SJeff Kirsher service_ofldq(q); 1569f7917c00SJeff Kirsher spin_unlock(&q->sendq.lock); 1570f7917c00SJeff Kirsher return NET_XMIT_SUCCESS; 1571f7917c00SJeff Kirsher } 1572f7917c00SJeff Kirsher 1573f7917c00SJeff Kirsher /** 1574f7917c00SJeff Kirsher * restart_ofldq - restart a suspended offload queue 1575f7917c00SJeff Kirsher * @data: the offload queue to restart 1576f7917c00SJeff Kirsher * 1577f7917c00SJeff Kirsher * Resumes transmission on a suspended Tx offload queue. 1578f7917c00SJeff Kirsher */ 1579f7917c00SJeff Kirsher static void restart_ofldq(unsigned long data) 1580f7917c00SJeff Kirsher { 1581f7917c00SJeff Kirsher struct sge_ofld_txq *q = (struct sge_ofld_txq *)data; 1582f7917c00SJeff Kirsher 1583f7917c00SJeff Kirsher spin_lock(&q->sendq.lock); 1584f7917c00SJeff Kirsher q->full = 0; /* the queue actually is completely empty now */ 1585f7917c00SJeff Kirsher service_ofldq(q); 1586f7917c00SJeff Kirsher spin_unlock(&q->sendq.lock); 1587f7917c00SJeff Kirsher } 1588f7917c00SJeff Kirsher 1589f7917c00SJeff Kirsher /** 1590f7917c00SJeff Kirsher * skb_txq - return the Tx queue an offload packet should use 1591f7917c00SJeff Kirsher * @skb: the packet 1592f7917c00SJeff Kirsher * 1593f7917c00SJeff Kirsher * Returns the Tx queue an offload packet should use as indicated by bits 1594f7917c00SJeff Kirsher * 1-15 in the packet's queue_mapping. 1595f7917c00SJeff Kirsher */ 1596f7917c00SJeff Kirsher static inline unsigned int skb_txq(const struct sk_buff *skb) 1597f7917c00SJeff Kirsher { 1598f7917c00SJeff Kirsher return skb->queue_mapping >> 1; 1599f7917c00SJeff Kirsher } 1600f7917c00SJeff Kirsher 1601f7917c00SJeff Kirsher /** 1602f7917c00SJeff Kirsher * is_ctrl_pkt - return whether an offload packet is a control packet 1603f7917c00SJeff Kirsher * @skb: the packet 1604f7917c00SJeff Kirsher * 1605f7917c00SJeff Kirsher * Returns whether an offload packet should use an OFLD or a CTRL 1606f7917c00SJeff Kirsher * Tx queue as indicated by bit 0 in the packet's queue_mapping. 1607f7917c00SJeff Kirsher */ 1608f7917c00SJeff Kirsher static inline unsigned int is_ctrl_pkt(const struct sk_buff *skb) 1609f7917c00SJeff Kirsher { 1610f7917c00SJeff Kirsher return skb->queue_mapping & 1; 1611f7917c00SJeff Kirsher } 1612f7917c00SJeff Kirsher 1613f7917c00SJeff Kirsher static inline int ofld_send(struct adapter *adap, struct sk_buff *skb) 1614f7917c00SJeff Kirsher { 1615f7917c00SJeff Kirsher unsigned int idx = skb_txq(skb); 1616f7917c00SJeff Kirsher 16174fe44dd7SKumar Sanghvi if (unlikely(is_ctrl_pkt(skb))) { 16184fe44dd7SKumar Sanghvi /* Single ctrl queue is a requirement for LE workaround path */ 16194fe44dd7SKumar Sanghvi if (adap->tids.nsftids) 16204fe44dd7SKumar Sanghvi idx = 0; 1621f7917c00SJeff Kirsher return ctrl_xmit(&adap->sge.ctrlq[idx], skb); 16224fe44dd7SKumar Sanghvi } 1623f7917c00SJeff Kirsher return ofld_xmit(&adap->sge.ofldtxq[idx], skb); 1624f7917c00SJeff Kirsher } 1625f7917c00SJeff Kirsher 1626f7917c00SJeff Kirsher /** 1627f7917c00SJeff Kirsher * t4_ofld_send - send an offload packet 1628f7917c00SJeff Kirsher * @adap: the adapter 1629f7917c00SJeff Kirsher * @skb: the packet 1630f7917c00SJeff Kirsher * 1631f7917c00SJeff Kirsher * Sends an offload packet. We use the packet queue_mapping to select the 1632f7917c00SJeff Kirsher * appropriate Tx queue as follows: bit 0 indicates whether the packet 1633f7917c00SJeff Kirsher * should be sent as regular or control, bits 1-15 select the queue. 1634f7917c00SJeff Kirsher */ 1635f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb) 1636f7917c00SJeff Kirsher { 1637f7917c00SJeff Kirsher int ret; 1638f7917c00SJeff Kirsher 1639f7917c00SJeff Kirsher local_bh_disable(); 1640f7917c00SJeff Kirsher ret = ofld_send(adap, skb); 1641f7917c00SJeff Kirsher local_bh_enable(); 1642f7917c00SJeff Kirsher return ret; 1643f7917c00SJeff Kirsher } 1644f7917c00SJeff Kirsher 1645f7917c00SJeff Kirsher /** 1646f7917c00SJeff Kirsher * cxgb4_ofld_send - send an offload packet 1647f7917c00SJeff Kirsher * @dev: the net device 1648f7917c00SJeff Kirsher * @skb: the packet 1649f7917c00SJeff Kirsher * 1650f7917c00SJeff Kirsher * Sends an offload packet. This is an exported version of @t4_ofld_send, 1651f7917c00SJeff Kirsher * intended for ULDs. 1652f7917c00SJeff Kirsher */ 1653f7917c00SJeff Kirsher int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb) 1654f7917c00SJeff Kirsher { 1655f7917c00SJeff Kirsher return t4_ofld_send(netdev2adap(dev), skb); 1656f7917c00SJeff Kirsher } 1657f7917c00SJeff Kirsher EXPORT_SYMBOL(cxgb4_ofld_send); 1658f7917c00SJeff Kirsher 1659e91b0f24SIan Campbell static inline void copy_frags(struct sk_buff *skb, 1660f7917c00SJeff Kirsher const struct pkt_gl *gl, unsigned int offset) 1661f7917c00SJeff Kirsher { 1662e91b0f24SIan Campbell int i; 1663f7917c00SJeff Kirsher 1664f7917c00SJeff Kirsher /* usually there's just one frag */ 1665e91b0f24SIan Campbell __skb_fill_page_desc(skb, 0, gl->frags[0].page, 1666e91b0f24SIan Campbell gl->frags[0].offset + offset, 1667e91b0f24SIan Campbell gl->frags[0].size - offset); 1668e91b0f24SIan Campbell skb_shinfo(skb)->nr_frags = gl->nfrags; 1669e91b0f24SIan Campbell for (i = 1; i < gl->nfrags; i++) 1670e91b0f24SIan Campbell __skb_fill_page_desc(skb, i, gl->frags[i].page, 1671e91b0f24SIan Campbell gl->frags[i].offset, 1672e91b0f24SIan Campbell gl->frags[i].size); 1673f7917c00SJeff Kirsher 1674f7917c00SJeff Kirsher /* get a reference to the last page, we don't own it */ 1675e91b0f24SIan Campbell get_page(gl->frags[gl->nfrags - 1].page); 1676f7917c00SJeff Kirsher } 1677f7917c00SJeff Kirsher 1678f7917c00SJeff Kirsher /** 1679f7917c00SJeff Kirsher * cxgb4_pktgl_to_skb - build an sk_buff from a packet gather list 1680f7917c00SJeff Kirsher * @gl: the gather list 1681f7917c00SJeff Kirsher * @skb_len: size of sk_buff main body if it carries fragments 1682f7917c00SJeff Kirsher * @pull_len: amount of data to move to the sk_buff's main body 1683f7917c00SJeff Kirsher * 1684f7917c00SJeff Kirsher * Builds an sk_buff from the given packet gather list. Returns the 1685f7917c00SJeff Kirsher * sk_buff or %NULL if sk_buff allocation failed. 1686f7917c00SJeff Kirsher */ 1687f7917c00SJeff Kirsher struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl, 1688f7917c00SJeff Kirsher unsigned int skb_len, unsigned int pull_len) 1689f7917c00SJeff Kirsher { 1690f7917c00SJeff Kirsher struct sk_buff *skb; 1691f7917c00SJeff Kirsher 1692f7917c00SJeff Kirsher /* 1693f7917c00SJeff Kirsher * Below we rely on RX_COPY_THRES being less than the smallest Rx buffer 1694f7917c00SJeff Kirsher * size, which is expected since buffers are at least PAGE_SIZEd. 1695f7917c00SJeff Kirsher * In this case packets up to RX_COPY_THRES have only one fragment. 1696f7917c00SJeff Kirsher */ 1697f7917c00SJeff Kirsher if (gl->tot_len <= RX_COPY_THRES) { 1698f7917c00SJeff Kirsher skb = dev_alloc_skb(gl->tot_len); 1699f7917c00SJeff Kirsher if (unlikely(!skb)) 1700f7917c00SJeff Kirsher goto out; 1701f7917c00SJeff Kirsher __skb_put(skb, gl->tot_len); 1702f7917c00SJeff Kirsher skb_copy_to_linear_data(skb, gl->va, gl->tot_len); 1703f7917c00SJeff Kirsher } else { 1704f7917c00SJeff Kirsher skb = dev_alloc_skb(skb_len); 1705f7917c00SJeff Kirsher if (unlikely(!skb)) 1706f7917c00SJeff Kirsher goto out; 1707f7917c00SJeff Kirsher __skb_put(skb, pull_len); 1708f7917c00SJeff Kirsher skb_copy_to_linear_data(skb, gl->va, pull_len); 1709f7917c00SJeff Kirsher 1710e91b0f24SIan Campbell copy_frags(skb, gl, pull_len); 1711f7917c00SJeff Kirsher skb->len = gl->tot_len; 1712f7917c00SJeff Kirsher skb->data_len = skb->len - pull_len; 1713f7917c00SJeff Kirsher skb->truesize += skb->data_len; 1714f7917c00SJeff Kirsher } 1715f7917c00SJeff Kirsher out: return skb; 1716f7917c00SJeff Kirsher } 1717f7917c00SJeff Kirsher EXPORT_SYMBOL(cxgb4_pktgl_to_skb); 1718f7917c00SJeff Kirsher 1719f7917c00SJeff Kirsher /** 1720f7917c00SJeff Kirsher * t4_pktgl_free - free a packet gather list 1721f7917c00SJeff Kirsher * @gl: the gather list 1722f7917c00SJeff Kirsher * 1723f7917c00SJeff Kirsher * Releases the pages of a packet gather list. We do not own the last 1724f7917c00SJeff Kirsher * page on the list and do not free it. 1725f7917c00SJeff Kirsher */ 1726f7917c00SJeff Kirsher static void t4_pktgl_free(const struct pkt_gl *gl) 1727f7917c00SJeff Kirsher { 1728f7917c00SJeff Kirsher int n; 1729e91b0f24SIan Campbell const struct page_frag *p; 1730f7917c00SJeff Kirsher 1731f7917c00SJeff Kirsher for (p = gl->frags, n = gl->nfrags - 1; n--; p++) 1732f7917c00SJeff Kirsher put_page(p->page); 1733f7917c00SJeff Kirsher } 1734f7917c00SJeff Kirsher 1735f7917c00SJeff Kirsher /* 1736f7917c00SJeff Kirsher * Process an MPS trace packet. Give it an unused protocol number so it won't 1737f7917c00SJeff Kirsher * be delivered to anyone and send it to the stack for capture. 1738f7917c00SJeff Kirsher */ 1739f7917c00SJeff Kirsher static noinline int handle_trace_pkt(struct adapter *adap, 1740f7917c00SJeff Kirsher const struct pkt_gl *gl) 1741f7917c00SJeff Kirsher { 1742f7917c00SJeff Kirsher struct sk_buff *skb; 1743f7917c00SJeff Kirsher 1744f7917c00SJeff Kirsher skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN); 1745f7917c00SJeff Kirsher if (unlikely(!skb)) { 1746f7917c00SJeff Kirsher t4_pktgl_free(gl); 1747f7917c00SJeff Kirsher return 0; 1748f7917c00SJeff Kirsher } 1749f7917c00SJeff Kirsher 1750d14807ddSHariprasad Shenai if (is_t4(adap->params.chip)) 17510a57a536SSantosh Rastapur __skb_pull(skb, sizeof(struct cpl_trace_pkt)); 17520a57a536SSantosh Rastapur else 17530a57a536SSantosh Rastapur __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt)); 17540a57a536SSantosh Rastapur 1755f7917c00SJeff Kirsher skb_reset_mac_header(skb); 1756f7917c00SJeff Kirsher skb->protocol = htons(0xffff); 1757f7917c00SJeff Kirsher skb->dev = adap->port[0]; 1758f7917c00SJeff Kirsher netif_receive_skb(skb); 1759f7917c00SJeff Kirsher return 0; 1760f7917c00SJeff Kirsher } 1761f7917c00SJeff Kirsher 1762f7917c00SJeff Kirsher static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl, 1763f7917c00SJeff Kirsher const struct cpl_rx_pkt *pkt) 1764f7917c00SJeff Kirsher { 176552367a76SVipul Pandya struct adapter *adapter = rxq->rspq.adap; 176652367a76SVipul Pandya struct sge *s = &adapter->sge; 1767f7917c00SJeff Kirsher int ret; 1768f7917c00SJeff Kirsher struct sk_buff *skb; 1769f7917c00SJeff Kirsher 1770f7917c00SJeff Kirsher skb = napi_get_frags(&rxq->rspq.napi); 1771f7917c00SJeff Kirsher if (unlikely(!skb)) { 1772f7917c00SJeff Kirsher t4_pktgl_free(gl); 1773f7917c00SJeff Kirsher rxq->stats.rx_drops++; 1774f7917c00SJeff Kirsher return; 1775f7917c00SJeff Kirsher } 1776f7917c00SJeff Kirsher 177752367a76SVipul Pandya copy_frags(skb, gl, s->pktshift); 177852367a76SVipul Pandya skb->len = gl->tot_len - s->pktshift; 1779f7917c00SJeff Kirsher skb->data_len = skb->len; 1780f7917c00SJeff Kirsher skb->truesize += skb->data_len; 1781f7917c00SJeff Kirsher skb->ip_summed = CHECKSUM_UNNECESSARY; 1782f7917c00SJeff Kirsher skb_record_rx_queue(skb, rxq->rspq.idx); 17833a336cb1SHariprasad Shenai skb_mark_napi_id(skb, &rxq->rspq.napi); 1784f7917c00SJeff Kirsher if (rxq->rspq.netdev->features & NETIF_F_RXHASH) 17858264989cSTom Herbert skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val, 17868264989cSTom Herbert PKT_HASH_TYPE_L3); 1787f7917c00SJeff Kirsher 1788f7917c00SJeff Kirsher if (unlikely(pkt->vlan_ex)) { 178986a9bad3SPatrick McHardy __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); 1790f7917c00SJeff Kirsher rxq->stats.vlan_ex++; 1791f7917c00SJeff Kirsher } 1792f7917c00SJeff Kirsher ret = napi_gro_frags(&rxq->rspq.napi); 1793f7917c00SJeff Kirsher if (ret == GRO_HELD) 1794f7917c00SJeff Kirsher rxq->stats.lro_pkts++; 1795f7917c00SJeff Kirsher else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE) 1796f7917c00SJeff Kirsher rxq->stats.lro_merged++; 1797f7917c00SJeff Kirsher rxq->stats.pkts++; 1798f7917c00SJeff Kirsher rxq->stats.rx_cso++; 1799f7917c00SJeff Kirsher } 1800f7917c00SJeff Kirsher 1801f7917c00SJeff Kirsher /** 1802f7917c00SJeff Kirsher * t4_ethrx_handler - process an ingress ethernet packet 1803f7917c00SJeff Kirsher * @q: the response queue that received the packet 1804f7917c00SJeff Kirsher * @rsp: the response queue descriptor holding the RX_PKT message 1805f7917c00SJeff Kirsher * @si: the gather list of packet fragments 1806f7917c00SJeff Kirsher * 1807f7917c00SJeff Kirsher * Process an ingress ethernet packet and deliver it to the stack. 1808f7917c00SJeff Kirsher */ 1809f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1810f7917c00SJeff Kirsher const struct pkt_gl *si) 1811f7917c00SJeff Kirsher { 1812f7917c00SJeff Kirsher bool csum_ok; 1813f7917c00SJeff Kirsher struct sk_buff *skb; 1814f7917c00SJeff Kirsher const struct cpl_rx_pkt *pkt; 1815f7917c00SJeff Kirsher struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); 181652367a76SVipul Pandya struct sge *s = &q->adap->sge; 1817d14807ddSHariprasad Shenai int cpl_trace_pkt = is_t4(q->adap->params.chip) ? 18180a57a536SSantosh Rastapur CPL_TRACE_PKT : CPL_TRACE_PKT_T5; 181984a200b3SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 182084a200b3SVarun Prakash struct port_info *pi; 182184a200b3SVarun Prakash #endif 1822f7917c00SJeff Kirsher 18230a57a536SSantosh Rastapur if (unlikely(*(u8 *)rsp == cpl_trace_pkt)) 1824f7917c00SJeff Kirsher return handle_trace_pkt(q->adap, si); 1825f7917c00SJeff Kirsher 1826f7917c00SJeff Kirsher pkt = (const struct cpl_rx_pkt *)rsp; 1827cca2822dSHariprasad Shenai csum_ok = pkt->csum_calc && !pkt->err_vec && 1828cca2822dSHariprasad Shenai (q->netdev->features & NETIF_F_RXCSUM); 1829bdc590b9SHariprasad Shenai if ((pkt->l2info & htonl(RXF_TCP_F)) && 18303a336cb1SHariprasad Shenai !(cxgb_poll_busy_polling(q)) && 1831f7917c00SJeff Kirsher (q->netdev->features & NETIF_F_GRO) && csum_ok && !pkt->ip_frag) { 1832f7917c00SJeff Kirsher do_gro(rxq, si, pkt); 1833f7917c00SJeff Kirsher return 0; 1834f7917c00SJeff Kirsher } 1835f7917c00SJeff Kirsher 1836f7917c00SJeff Kirsher skb = cxgb4_pktgl_to_skb(si, RX_PKT_SKB_LEN, RX_PULL_LEN); 1837f7917c00SJeff Kirsher if (unlikely(!skb)) { 1838f7917c00SJeff Kirsher t4_pktgl_free(si); 1839f7917c00SJeff Kirsher rxq->stats.rx_drops++; 1840f7917c00SJeff Kirsher return 0; 1841f7917c00SJeff Kirsher } 1842f7917c00SJeff Kirsher 184352367a76SVipul Pandya __skb_pull(skb, s->pktshift); /* remove ethernet header padding */ 1844f7917c00SJeff Kirsher skb->protocol = eth_type_trans(skb, q->netdev); 1845f7917c00SJeff Kirsher skb_record_rx_queue(skb, q->idx); 1846f7917c00SJeff Kirsher if (skb->dev->features & NETIF_F_RXHASH) 18478264989cSTom Herbert skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val, 18488264989cSTom Herbert PKT_HASH_TYPE_L3); 1849f7917c00SJeff Kirsher 1850f7917c00SJeff Kirsher rxq->stats.pkts++; 1851f7917c00SJeff Kirsher 1852bdc590b9SHariprasad Shenai if (csum_ok && (pkt->l2info & htonl(RXF_UDP_F | RXF_TCP_F))) { 1853f7917c00SJeff Kirsher if (!pkt->ip_frag) { 1854f7917c00SJeff Kirsher skb->ip_summed = CHECKSUM_UNNECESSARY; 1855f7917c00SJeff Kirsher rxq->stats.rx_cso++; 1856bdc590b9SHariprasad Shenai } else if (pkt->l2info & htonl(RXF_IP_F)) { 1857f7917c00SJeff Kirsher __sum16 c = (__force __sum16)pkt->csum; 1858f7917c00SJeff Kirsher skb->csum = csum_unfold(c); 1859f7917c00SJeff Kirsher skb->ip_summed = CHECKSUM_COMPLETE; 1860f7917c00SJeff Kirsher rxq->stats.rx_cso++; 1861f7917c00SJeff Kirsher } 186284a200b3SVarun Prakash } else { 1863f7917c00SJeff Kirsher skb_checksum_none_assert(skb); 186484a200b3SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 186584a200b3SVarun Prakash #define CPL_RX_PKT_FLAGS (RXF_PSH_F | RXF_SYN_F | RXF_UDP_F | \ 186684a200b3SVarun Prakash RXF_TCP_F | RXF_IP_F | RXF_IP6_F | RXF_LRO_F) 186784a200b3SVarun Prakash 186884a200b3SVarun Prakash pi = netdev_priv(skb->dev); 186984a200b3SVarun Prakash if (!(pkt->l2info & cpu_to_be32(CPL_RX_PKT_FLAGS))) { 187084a200b3SVarun Prakash if ((pkt->l2info & cpu_to_be32(RXF_FCOE_F)) && 187184a200b3SVarun Prakash (pi->fcoe.flags & CXGB_FCOE_ENABLED)) { 187284a200b3SVarun Prakash if (!(pkt->err_vec & cpu_to_be16(RXERR_CSUM_F))) 187384a200b3SVarun Prakash skb->ip_summed = CHECKSUM_UNNECESSARY; 187484a200b3SVarun Prakash } 187584a200b3SVarun Prakash } 187684a200b3SVarun Prakash 187784a200b3SVarun Prakash #undef CPL_RX_PKT_FLAGS 187884a200b3SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 187984a200b3SVarun Prakash } 1880f7917c00SJeff Kirsher 1881f7917c00SJeff Kirsher if (unlikely(pkt->vlan_ex)) { 188286a9bad3SPatrick McHardy __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); 1883f7917c00SJeff Kirsher rxq->stats.vlan_ex++; 1884f7917c00SJeff Kirsher } 18853a336cb1SHariprasad Shenai skb_mark_napi_id(skb, &q->napi); 1886f7917c00SJeff Kirsher netif_receive_skb(skb); 1887f7917c00SJeff Kirsher return 0; 1888f7917c00SJeff Kirsher } 1889f7917c00SJeff Kirsher 1890f7917c00SJeff Kirsher /** 1891f7917c00SJeff Kirsher * restore_rx_bufs - put back a packet's Rx buffers 1892f7917c00SJeff Kirsher * @si: the packet gather list 1893f7917c00SJeff Kirsher * @q: the SGE free list 1894f7917c00SJeff Kirsher * @frags: number of FL buffers to restore 1895f7917c00SJeff Kirsher * 1896f7917c00SJeff Kirsher * Puts back on an FL the Rx buffers associated with @si. The buffers 1897f7917c00SJeff Kirsher * have already been unmapped and are left unmapped, we mark them so to 1898f7917c00SJeff Kirsher * prevent further unmapping attempts. 1899f7917c00SJeff Kirsher * 1900f7917c00SJeff Kirsher * This function undoes a series of @unmap_rx_buf calls when we find out 1901f7917c00SJeff Kirsher * that the current packet can't be processed right away afterall and we 1902f7917c00SJeff Kirsher * need to come back to it later. This is a very rare event and there's 1903f7917c00SJeff Kirsher * no effort to make this particularly efficient. 1904f7917c00SJeff Kirsher */ 1905f7917c00SJeff Kirsher static void restore_rx_bufs(const struct pkt_gl *si, struct sge_fl *q, 1906f7917c00SJeff Kirsher int frags) 1907f7917c00SJeff Kirsher { 1908f7917c00SJeff Kirsher struct rx_sw_desc *d; 1909f7917c00SJeff Kirsher 1910f7917c00SJeff Kirsher while (frags--) { 1911f7917c00SJeff Kirsher if (q->cidx == 0) 1912f7917c00SJeff Kirsher q->cidx = q->size - 1; 1913f7917c00SJeff Kirsher else 1914f7917c00SJeff Kirsher q->cidx--; 1915f7917c00SJeff Kirsher d = &q->sdesc[q->cidx]; 1916f7917c00SJeff Kirsher d->page = si->frags[frags].page; 1917f7917c00SJeff Kirsher d->dma_addr |= RX_UNMAPPED_BUF; 1918f7917c00SJeff Kirsher q->avail++; 1919f7917c00SJeff Kirsher } 1920f7917c00SJeff Kirsher } 1921f7917c00SJeff Kirsher 1922f7917c00SJeff Kirsher /** 1923f7917c00SJeff Kirsher * is_new_response - check if a response is newly written 1924f7917c00SJeff Kirsher * @r: the response descriptor 1925f7917c00SJeff Kirsher * @q: the response queue 1926f7917c00SJeff Kirsher * 1927f7917c00SJeff Kirsher * Returns true if a response descriptor contains a yet unprocessed 1928f7917c00SJeff Kirsher * response. 1929f7917c00SJeff Kirsher */ 1930f7917c00SJeff Kirsher static inline bool is_new_response(const struct rsp_ctrl *r, 1931f7917c00SJeff Kirsher const struct sge_rspq *q) 1932f7917c00SJeff Kirsher { 1933f7917c00SJeff Kirsher return RSPD_GEN(r->type_gen) == q->gen; 1934f7917c00SJeff Kirsher } 1935f7917c00SJeff Kirsher 1936f7917c00SJeff Kirsher /** 1937f7917c00SJeff Kirsher * rspq_next - advance to the next entry in a response queue 1938f7917c00SJeff Kirsher * @q: the queue 1939f7917c00SJeff Kirsher * 1940f7917c00SJeff Kirsher * Updates the state of a response queue to advance it to the next entry. 1941f7917c00SJeff Kirsher */ 1942f7917c00SJeff Kirsher static inline void rspq_next(struct sge_rspq *q) 1943f7917c00SJeff Kirsher { 1944f7917c00SJeff Kirsher q->cur_desc = (void *)q->cur_desc + q->iqe_len; 1945f7917c00SJeff Kirsher if (unlikely(++q->cidx == q->size)) { 1946f7917c00SJeff Kirsher q->cidx = 0; 1947f7917c00SJeff Kirsher q->gen ^= 1; 1948f7917c00SJeff Kirsher q->cur_desc = q->desc; 1949f7917c00SJeff Kirsher } 1950f7917c00SJeff Kirsher } 1951f7917c00SJeff Kirsher 1952f7917c00SJeff Kirsher /** 1953f7917c00SJeff Kirsher * process_responses - process responses from an SGE response queue 1954f7917c00SJeff Kirsher * @q: the ingress queue to process 1955f7917c00SJeff Kirsher * @budget: how many responses can be processed in this round 1956f7917c00SJeff Kirsher * 1957f7917c00SJeff Kirsher * Process responses from an SGE response queue up to the supplied budget. 1958f7917c00SJeff Kirsher * Responses include received packets as well as control messages from FW 1959f7917c00SJeff Kirsher * or HW. 1960f7917c00SJeff Kirsher * 1961f7917c00SJeff Kirsher * Additionally choose the interrupt holdoff time for the next interrupt 1962f7917c00SJeff Kirsher * on this queue. If the system is under memory shortage use a fairly 1963f7917c00SJeff Kirsher * long delay to help recovery. 1964f7917c00SJeff Kirsher */ 1965f7917c00SJeff Kirsher static int process_responses(struct sge_rspq *q, int budget) 1966f7917c00SJeff Kirsher { 1967f7917c00SJeff Kirsher int ret, rsp_type; 1968f7917c00SJeff Kirsher int budget_left = budget; 1969f7917c00SJeff Kirsher const struct rsp_ctrl *rc; 1970f7917c00SJeff Kirsher struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); 197152367a76SVipul Pandya struct adapter *adapter = q->adap; 197252367a76SVipul Pandya struct sge *s = &adapter->sge; 1973f7917c00SJeff Kirsher 1974f7917c00SJeff Kirsher while (likely(budget_left)) { 1975f7917c00SJeff Kirsher rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc)); 1976f7917c00SJeff Kirsher if (!is_new_response(rc, q)) 1977f7917c00SJeff Kirsher break; 1978f7917c00SJeff Kirsher 1979019be1cfSAlexander Duyck dma_rmb(); 1980f7917c00SJeff Kirsher rsp_type = RSPD_TYPE(rc->type_gen); 1981f7917c00SJeff Kirsher if (likely(rsp_type == RSP_TYPE_FLBUF)) { 1982e91b0f24SIan Campbell struct page_frag *fp; 1983f7917c00SJeff Kirsher struct pkt_gl si; 1984f7917c00SJeff Kirsher const struct rx_sw_desc *rsd; 1985f7917c00SJeff Kirsher u32 len = ntohl(rc->pldbuflen_qid), bufsz, frags; 1986f7917c00SJeff Kirsher 1987f7917c00SJeff Kirsher if (len & RSPD_NEWBUF) { 1988f7917c00SJeff Kirsher if (likely(q->offset > 0)) { 1989f7917c00SJeff Kirsher free_rx_bufs(q->adap, &rxq->fl, 1); 1990f7917c00SJeff Kirsher q->offset = 0; 1991f7917c00SJeff Kirsher } 1992f7917c00SJeff Kirsher len = RSPD_LEN(len); 1993f7917c00SJeff Kirsher } 1994f7917c00SJeff Kirsher si.tot_len = len; 1995f7917c00SJeff Kirsher 1996f7917c00SJeff Kirsher /* gather packet fragments */ 1997f7917c00SJeff Kirsher for (frags = 0, fp = si.frags; ; frags++, fp++) { 1998f7917c00SJeff Kirsher rsd = &rxq->fl.sdesc[rxq->fl.cidx]; 199952367a76SVipul Pandya bufsz = get_buf_size(adapter, rsd); 2000f7917c00SJeff Kirsher fp->page = rsd->page; 2001e91b0f24SIan Campbell fp->offset = q->offset; 2002e91b0f24SIan Campbell fp->size = min(bufsz, len); 2003e91b0f24SIan Campbell len -= fp->size; 2004f7917c00SJeff Kirsher if (!len) 2005f7917c00SJeff Kirsher break; 2006f7917c00SJeff Kirsher unmap_rx_buf(q->adap, &rxq->fl); 2007f7917c00SJeff Kirsher } 2008f7917c00SJeff Kirsher 2009f7917c00SJeff Kirsher /* 2010f7917c00SJeff Kirsher * Last buffer remains mapped so explicitly make it 2011f7917c00SJeff Kirsher * coherent for CPU access. 2012f7917c00SJeff Kirsher */ 2013f7917c00SJeff Kirsher dma_sync_single_for_cpu(q->adap->pdev_dev, 2014f7917c00SJeff Kirsher get_buf_addr(rsd), 2015e91b0f24SIan Campbell fp->size, DMA_FROM_DEVICE); 2016f7917c00SJeff Kirsher 2017f7917c00SJeff Kirsher si.va = page_address(si.frags[0].page) + 2018e91b0f24SIan Campbell si.frags[0].offset; 2019f7917c00SJeff Kirsher prefetch(si.va); 2020f7917c00SJeff Kirsher 2021f7917c00SJeff Kirsher si.nfrags = frags + 1; 2022f7917c00SJeff Kirsher ret = q->handler(q, q->cur_desc, &si); 2023f7917c00SJeff Kirsher if (likely(ret == 0)) 202452367a76SVipul Pandya q->offset += ALIGN(fp->size, s->fl_align); 2025f7917c00SJeff Kirsher else 2026f7917c00SJeff Kirsher restore_rx_bufs(&si, &rxq->fl, frags); 2027f7917c00SJeff Kirsher } else if (likely(rsp_type == RSP_TYPE_CPL)) { 2028f7917c00SJeff Kirsher ret = q->handler(q, q->cur_desc, NULL); 2029f7917c00SJeff Kirsher } else { 2030f7917c00SJeff Kirsher ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN); 2031f7917c00SJeff Kirsher } 2032f7917c00SJeff Kirsher 2033f7917c00SJeff Kirsher if (unlikely(ret)) { 2034f7917c00SJeff Kirsher /* couldn't process descriptor, back off for recovery */ 2035f7917c00SJeff Kirsher q->next_intr_params = QINTR_TIMER_IDX(NOMEM_TMR_IDX); 2036f7917c00SJeff Kirsher break; 2037f7917c00SJeff Kirsher } 2038f7917c00SJeff Kirsher 2039f7917c00SJeff Kirsher rspq_next(q); 2040f7917c00SJeff Kirsher budget_left--; 2041f7917c00SJeff Kirsher } 2042f7917c00SJeff Kirsher 2043f7917c00SJeff Kirsher if (q->offset >= 0 && rxq->fl.size - rxq->fl.avail >= 16) 2044f7917c00SJeff Kirsher __refill_fl(q->adap, &rxq->fl); 2045f7917c00SJeff Kirsher return budget - budget_left; 2046f7917c00SJeff Kirsher } 2047f7917c00SJeff Kirsher 20483a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 20493a336cb1SHariprasad Shenai int cxgb_busy_poll(struct napi_struct *napi) 20503a336cb1SHariprasad Shenai { 20513a336cb1SHariprasad Shenai struct sge_rspq *q = container_of(napi, struct sge_rspq, napi); 20523a336cb1SHariprasad Shenai unsigned int params, work_done; 20533a336cb1SHariprasad Shenai u32 val; 20543a336cb1SHariprasad Shenai 20553a336cb1SHariprasad Shenai if (!cxgb_poll_lock_poll(q)) 20563a336cb1SHariprasad Shenai return LL_FLUSH_BUSY; 20573a336cb1SHariprasad Shenai 20583a336cb1SHariprasad Shenai work_done = process_responses(q, 4); 20593a336cb1SHariprasad Shenai params = QINTR_TIMER_IDX(TIMERREG_COUNTER0_X) | QINTR_CNT_EN; 20603a336cb1SHariprasad Shenai q->next_intr_params = params; 20613a336cb1SHariprasad Shenai val = CIDXINC_V(work_done) | SEINTARM_V(params); 20623a336cb1SHariprasad Shenai 20633a336cb1SHariprasad Shenai /* If we don't have access to the new User GTS (T5+), use the old 20643a336cb1SHariprasad Shenai * doorbell mechanism; otherwise use the new BAR2 mechanism. 20653a336cb1SHariprasad Shenai */ 20663a336cb1SHariprasad Shenai if (unlikely(!q->bar2_addr)) 20673a336cb1SHariprasad Shenai t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A), 20683a336cb1SHariprasad Shenai val | INGRESSQID_V((u32)q->cntxt_id)); 20693a336cb1SHariprasad Shenai else { 20703a336cb1SHariprasad Shenai writel(val | INGRESSQID_V(q->bar2_qid), 20713a336cb1SHariprasad Shenai q->bar2_addr + SGE_UDB_GTS); 20723a336cb1SHariprasad Shenai wmb(); 20733a336cb1SHariprasad Shenai } 20743a336cb1SHariprasad Shenai 20753a336cb1SHariprasad Shenai cxgb_poll_unlock_poll(q); 20763a336cb1SHariprasad Shenai return work_done; 20773a336cb1SHariprasad Shenai } 20783a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 20793a336cb1SHariprasad Shenai 2080f7917c00SJeff Kirsher /** 2081f7917c00SJeff Kirsher * napi_rx_handler - the NAPI handler for Rx processing 2082f7917c00SJeff Kirsher * @napi: the napi instance 2083f7917c00SJeff Kirsher * @budget: how many packets we can process in this round 2084f7917c00SJeff Kirsher * 2085f7917c00SJeff Kirsher * Handler for new data events when using NAPI. This does not need any 2086f7917c00SJeff Kirsher * locking or protection from interrupts as data interrupts are off at 2087f7917c00SJeff Kirsher * this point and other adapter interrupts do not interfere (the latter 2088f7917c00SJeff Kirsher * in not a concern at all with MSI-X as non-data interrupts then have 2089f7917c00SJeff Kirsher * a separate handler). 2090f7917c00SJeff Kirsher */ 2091f7917c00SJeff Kirsher static int napi_rx_handler(struct napi_struct *napi, int budget) 2092f7917c00SJeff Kirsher { 2093f7917c00SJeff Kirsher unsigned int params; 2094f7917c00SJeff Kirsher struct sge_rspq *q = container_of(napi, struct sge_rspq, napi); 20953a336cb1SHariprasad Shenai int work_done; 2096d63a6dcfSHariprasad Shenai u32 val; 2097f7917c00SJeff Kirsher 20983a336cb1SHariprasad Shenai if (!cxgb_poll_lock_napi(q)) 20993a336cb1SHariprasad Shenai return budget; 21003a336cb1SHariprasad Shenai 21013a336cb1SHariprasad Shenai work_done = process_responses(q, budget); 2102f7917c00SJeff Kirsher if (likely(work_done < budget)) { 2103e553ec3fSHariprasad Shenai int timer_index; 2104e553ec3fSHariprasad Shenai 2105f7917c00SJeff Kirsher napi_complete(napi); 2106e553ec3fSHariprasad Shenai timer_index = QINTR_TIMER_IDX_GET(q->next_intr_params); 2107e553ec3fSHariprasad Shenai 2108e553ec3fSHariprasad Shenai if (q->adaptive_rx) { 2109e553ec3fSHariprasad Shenai if (work_done > max(timer_pkt_quota[timer_index], 2110e553ec3fSHariprasad Shenai MIN_NAPI_WORK)) 2111e553ec3fSHariprasad Shenai timer_index = (timer_index + 1); 2112e553ec3fSHariprasad Shenai else 2113e553ec3fSHariprasad Shenai timer_index = timer_index - 1; 2114e553ec3fSHariprasad Shenai 2115e553ec3fSHariprasad Shenai timer_index = clamp(timer_index, 0, SGE_TIMERREGS - 1); 2116e553ec3fSHariprasad Shenai q->next_intr_params = QINTR_TIMER_IDX(timer_index) | 2117e553ec3fSHariprasad Shenai V_QINTR_CNT_EN; 2118e553ec3fSHariprasad Shenai params = q->next_intr_params; 2119e553ec3fSHariprasad Shenai } else { 2120f7917c00SJeff Kirsher params = q->next_intr_params; 2121f7917c00SJeff Kirsher q->next_intr_params = q->intr_params; 2122e553ec3fSHariprasad Shenai } 2123f7917c00SJeff Kirsher } else 2124f7917c00SJeff Kirsher params = QINTR_TIMER_IDX(7); 2125f7917c00SJeff Kirsher 2126f612b815SHariprasad Shenai val = CIDXINC_V(work_done) | SEINTARM_V(params); 2127df64e4d3SHariprasad Shenai 2128df64e4d3SHariprasad Shenai /* If we don't have access to the new User GTS (T5+), use the old 2129df64e4d3SHariprasad Shenai * doorbell mechanism; otherwise use the new BAR2 mechanism. 2130df64e4d3SHariprasad Shenai */ 2131df64e4d3SHariprasad Shenai if (unlikely(q->bar2_addr == NULL)) { 2132f612b815SHariprasad Shenai t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A), 2133f612b815SHariprasad Shenai val | INGRESSQID_V((u32)q->cntxt_id)); 2134d63a6dcfSHariprasad Shenai } else { 2135f612b815SHariprasad Shenai writel(val | INGRESSQID_V(q->bar2_qid), 2136df64e4d3SHariprasad Shenai q->bar2_addr + SGE_UDB_GTS); 2137d63a6dcfSHariprasad Shenai wmb(); 2138d63a6dcfSHariprasad Shenai } 21393a336cb1SHariprasad Shenai cxgb_poll_unlock_napi(q); 2140f7917c00SJeff Kirsher return work_done; 2141f7917c00SJeff Kirsher } 2142f7917c00SJeff Kirsher 2143f7917c00SJeff Kirsher /* 2144f7917c00SJeff Kirsher * The MSI-X interrupt handler for an SGE response queue. 2145f7917c00SJeff Kirsher */ 2146f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie) 2147f7917c00SJeff Kirsher { 2148f7917c00SJeff Kirsher struct sge_rspq *q = cookie; 2149f7917c00SJeff Kirsher 2150f7917c00SJeff Kirsher napi_schedule(&q->napi); 2151f7917c00SJeff Kirsher return IRQ_HANDLED; 2152f7917c00SJeff Kirsher } 2153f7917c00SJeff Kirsher 2154f7917c00SJeff Kirsher /* 2155f7917c00SJeff Kirsher * Process the indirect interrupt entries in the interrupt queue and kick off 2156f7917c00SJeff Kirsher * NAPI for each queue that has generated an entry. 2157f7917c00SJeff Kirsher */ 2158f7917c00SJeff Kirsher static unsigned int process_intrq(struct adapter *adap) 2159f7917c00SJeff Kirsher { 2160f7917c00SJeff Kirsher unsigned int credits; 2161f7917c00SJeff Kirsher const struct rsp_ctrl *rc; 2162f7917c00SJeff Kirsher struct sge_rspq *q = &adap->sge.intrq; 2163d63a6dcfSHariprasad Shenai u32 val; 2164f7917c00SJeff Kirsher 2165f7917c00SJeff Kirsher spin_lock(&adap->sge.intrq_lock); 2166f7917c00SJeff Kirsher for (credits = 0; ; credits++) { 2167f7917c00SJeff Kirsher rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc)); 2168f7917c00SJeff Kirsher if (!is_new_response(rc, q)) 2169f7917c00SJeff Kirsher break; 2170f7917c00SJeff Kirsher 2171019be1cfSAlexander Duyck dma_rmb(); 2172f7917c00SJeff Kirsher if (RSPD_TYPE(rc->type_gen) == RSP_TYPE_INTR) { 2173f7917c00SJeff Kirsher unsigned int qid = ntohl(rc->pldbuflen_qid); 2174f7917c00SJeff Kirsher 2175f7917c00SJeff Kirsher qid -= adap->sge.ingr_start; 2176f7917c00SJeff Kirsher napi_schedule(&adap->sge.ingr_map[qid]->napi); 2177f7917c00SJeff Kirsher } 2178f7917c00SJeff Kirsher 2179f7917c00SJeff Kirsher rspq_next(q); 2180f7917c00SJeff Kirsher } 2181f7917c00SJeff Kirsher 2182f612b815SHariprasad Shenai val = CIDXINC_V(credits) | SEINTARM_V(q->intr_params); 2183df64e4d3SHariprasad Shenai 2184df64e4d3SHariprasad Shenai /* If we don't have access to the new User GTS (T5+), use the old 2185df64e4d3SHariprasad Shenai * doorbell mechanism; otherwise use the new BAR2 mechanism. 2186df64e4d3SHariprasad Shenai */ 2187df64e4d3SHariprasad Shenai if (unlikely(q->bar2_addr == NULL)) { 2188f612b815SHariprasad Shenai t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), 2189f612b815SHariprasad Shenai val | INGRESSQID_V(q->cntxt_id)); 2190d63a6dcfSHariprasad Shenai } else { 2191f612b815SHariprasad Shenai writel(val | INGRESSQID_V(q->bar2_qid), 2192df64e4d3SHariprasad Shenai q->bar2_addr + SGE_UDB_GTS); 2193d63a6dcfSHariprasad Shenai wmb(); 2194d63a6dcfSHariprasad Shenai } 2195f7917c00SJeff Kirsher spin_unlock(&adap->sge.intrq_lock); 2196f7917c00SJeff Kirsher return credits; 2197f7917c00SJeff Kirsher } 2198f7917c00SJeff Kirsher 2199f7917c00SJeff Kirsher /* 2200f7917c00SJeff Kirsher * The MSI interrupt handler, which handles data events from SGE response queues 2201f7917c00SJeff Kirsher * as well as error and other async events as they all use the same MSI vector. 2202f7917c00SJeff Kirsher */ 2203f7917c00SJeff Kirsher static irqreturn_t t4_intr_msi(int irq, void *cookie) 2204f7917c00SJeff Kirsher { 2205f7917c00SJeff Kirsher struct adapter *adap = cookie; 2206f7917c00SJeff Kirsher 2207f7917c00SJeff Kirsher t4_slow_intr_handler(adap); 2208f7917c00SJeff Kirsher process_intrq(adap); 2209f7917c00SJeff Kirsher return IRQ_HANDLED; 2210f7917c00SJeff Kirsher } 2211f7917c00SJeff Kirsher 2212f7917c00SJeff Kirsher /* 2213f7917c00SJeff Kirsher * Interrupt handler for legacy INTx interrupts. 2214f7917c00SJeff Kirsher * Handles data events from SGE response queues as well as error and other 2215f7917c00SJeff Kirsher * async events as they all use the same interrupt line. 2216f7917c00SJeff Kirsher */ 2217f7917c00SJeff Kirsher static irqreturn_t t4_intr_intx(int irq, void *cookie) 2218f7917c00SJeff Kirsher { 2219f7917c00SJeff Kirsher struct adapter *adap = cookie; 2220f7917c00SJeff Kirsher 2221f061de42SHariprasad Shenai t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0); 2222f7917c00SJeff Kirsher if (t4_slow_intr_handler(adap) | process_intrq(adap)) 2223f7917c00SJeff Kirsher return IRQ_HANDLED; 2224f7917c00SJeff Kirsher return IRQ_NONE; /* probably shared interrupt */ 2225f7917c00SJeff Kirsher } 2226f7917c00SJeff Kirsher 2227f7917c00SJeff Kirsher /** 2228f7917c00SJeff Kirsher * t4_intr_handler - select the top-level interrupt handler 2229f7917c00SJeff Kirsher * @adap: the adapter 2230f7917c00SJeff Kirsher * 2231f7917c00SJeff Kirsher * Selects the top-level interrupt handler based on the type of interrupts 2232f7917c00SJeff Kirsher * (MSI-X, MSI, or INTx). 2233f7917c00SJeff Kirsher */ 2234f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap) 2235f7917c00SJeff Kirsher { 2236f7917c00SJeff Kirsher if (adap->flags & USING_MSIX) 2237f7917c00SJeff Kirsher return t4_sge_intr_msix; 2238f7917c00SJeff Kirsher if (adap->flags & USING_MSI) 2239f7917c00SJeff Kirsher return t4_intr_msi; 2240f7917c00SJeff Kirsher return t4_intr_intx; 2241f7917c00SJeff Kirsher } 2242f7917c00SJeff Kirsher 2243f7917c00SJeff Kirsher static void sge_rx_timer_cb(unsigned long data) 2244f7917c00SJeff Kirsher { 2245f7917c00SJeff Kirsher unsigned long m; 22460f4d201fSKumar Sanghvi unsigned int i, idma_same_state_cnt[2]; 2247f7917c00SJeff Kirsher struct adapter *adap = (struct adapter *)data; 2248f7917c00SJeff Kirsher struct sge *s = &adap->sge; 2249f7917c00SJeff Kirsher 22504b8e27a8SHariprasad Shenai for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++) 2251f7917c00SJeff Kirsher for (m = s->starving_fl[i]; m; m &= m - 1) { 2252f7917c00SJeff Kirsher struct sge_eth_rxq *rxq; 2253f7917c00SJeff Kirsher unsigned int id = __ffs(m) + i * BITS_PER_LONG; 2254f7917c00SJeff Kirsher struct sge_fl *fl = s->egr_map[id]; 2255f7917c00SJeff Kirsher 2256f7917c00SJeff Kirsher clear_bit(id, s->starving_fl); 22574e857c58SPeter Zijlstra smp_mb__after_atomic(); 2258f7917c00SJeff Kirsher 2259c098b026SHariprasad Shenai if (fl_starving(adap, fl)) { 2260f7917c00SJeff Kirsher rxq = container_of(fl, struct sge_eth_rxq, fl); 2261f7917c00SJeff Kirsher if (napi_reschedule(&rxq->rspq.napi)) 2262f7917c00SJeff Kirsher fl->starving++; 2263f7917c00SJeff Kirsher else 2264f7917c00SJeff Kirsher set_bit(id, s->starving_fl); 2265f7917c00SJeff Kirsher } 2266f7917c00SJeff Kirsher } 2267f7917c00SJeff Kirsher 2268f061de42SHariprasad Shenai t4_write_reg(adap, SGE_DEBUG_INDEX_A, 13); 2269f061de42SHariprasad Shenai idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH_A); 2270f061de42SHariprasad Shenai idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A); 2271f7917c00SJeff Kirsher 22720f4d201fSKumar Sanghvi for (i = 0; i < 2; i++) { 22730f4d201fSKumar Sanghvi u32 debug0, debug11; 22740f4d201fSKumar Sanghvi 22750f4d201fSKumar Sanghvi /* If the Ingress DMA Same State Counter ("timer") is less 22760f4d201fSKumar Sanghvi * than 1s, then we can reset our synthesized Stall Timer and 22770f4d201fSKumar Sanghvi * continue. If we have previously emitted warnings about a 22780f4d201fSKumar Sanghvi * potential stalled Ingress Queue, issue a note indicating 22790f4d201fSKumar Sanghvi * that the Ingress Queue has resumed forward progress. 22800f4d201fSKumar Sanghvi */ 22810f4d201fSKumar Sanghvi if (idma_same_state_cnt[i] < s->idma_1s_thresh) { 22820f4d201fSKumar Sanghvi if (s->idma_stalled[i] >= SGE_IDMA_WARN_THRESH) 22830f4d201fSKumar Sanghvi CH_WARN(adap, "SGE idma%d, queue%u,resumed after %d sec\n", 22840f4d201fSKumar Sanghvi i, s->idma_qid[i], 22850f4d201fSKumar Sanghvi s->idma_stalled[i]/HZ); 22860f4d201fSKumar Sanghvi s->idma_stalled[i] = 0; 2287f7917c00SJeff Kirsher continue; 22880f4d201fSKumar Sanghvi } 22890f4d201fSKumar Sanghvi 22900f4d201fSKumar Sanghvi /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 22910f4d201fSKumar Sanghvi * domain. The first time we get here it'll be because we 22920f4d201fSKumar Sanghvi * passed the 1s Threshold; each additional time it'll be 22930f4d201fSKumar Sanghvi * because the RX Timer Callback is being fired on its regular 22940f4d201fSKumar Sanghvi * schedule. 22950f4d201fSKumar Sanghvi * 22960f4d201fSKumar Sanghvi * If the stall is below our Potential Hung Ingress Queue 22970f4d201fSKumar Sanghvi * Warning Threshold, continue. 22980f4d201fSKumar Sanghvi */ 22990f4d201fSKumar Sanghvi if (s->idma_stalled[i] == 0) 23000f4d201fSKumar Sanghvi s->idma_stalled[i] = HZ; 23010f4d201fSKumar Sanghvi else 23020f4d201fSKumar Sanghvi s->idma_stalled[i] += RX_QCHECK_PERIOD; 23030f4d201fSKumar Sanghvi 23040f4d201fSKumar Sanghvi if (s->idma_stalled[i] < SGE_IDMA_WARN_THRESH) 23050f4d201fSKumar Sanghvi continue; 23060f4d201fSKumar Sanghvi 23070f4d201fSKumar Sanghvi /* We'll issue a warning every SGE_IDMA_WARN_REPEAT Hz */ 23080f4d201fSKumar Sanghvi if (((s->idma_stalled[i] - HZ) % SGE_IDMA_WARN_REPEAT) != 0) 23090f4d201fSKumar Sanghvi continue; 23100f4d201fSKumar Sanghvi 23110f4d201fSKumar Sanghvi /* Read and save the SGE IDMA State and Queue ID information. 23120f4d201fSKumar Sanghvi * We do this every time in case it changes across time ... 23130f4d201fSKumar Sanghvi */ 2314f061de42SHariprasad Shenai t4_write_reg(adap, SGE_DEBUG_INDEX_A, 0); 2315f061de42SHariprasad Shenai debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A); 23160f4d201fSKumar Sanghvi s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 23170f4d201fSKumar Sanghvi 2318f061de42SHariprasad Shenai t4_write_reg(adap, SGE_DEBUG_INDEX_A, 11); 2319f061de42SHariprasad Shenai debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A); 23200f4d201fSKumar Sanghvi s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 23210f4d201fSKumar Sanghvi 23220f4d201fSKumar Sanghvi CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n", 23230f4d201fSKumar Sanghvi i, s->idma_qid[i], s->idma_state[i], 23240f4d201fSKumar Sanghvi s->idma_stalled[i]/HZ, debug0, debug11); 23250f4d201fSKumar Sanghvi t4_sge_decode_idma_state(adap, s->idma_state[i]); 23260f4d201fSKumar Sanghvi } 2327f7917c00SJeff Kirsher 2328f7917c00SJeff Kirsher mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD); 2329f7917c00SJeff Kirsher } 2330f7917c00SJeff Kirsher 2331f7917c00SJeff Kirsher static void sge_tx_timer_cb(unsigned long data) 2332f7917c00SJeff Kirsher { 2333f7917c00SJeff Kirsher unsigned long m; 2334f7917c00SJeff Kirsher unsigned int i, budget; 2335f7917c00SJeff Kirsher struct adapter *adap = (struct adapter *)data; 2336f7917c00SJeff Kirsher struct sge *s = &adap->sge; 2337f7917c00SJeff Kirsher 23384b8e27a8SHariprasad Shenai for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++) 2339f7917c00SJeff Kirsher for (m = s->txq_maperr[i]; m; m &= m - 1) { 2340f7917c00SJeff Kirsher unsigned long id = __ffs(m) + i * BITS_PER_LONG; 2341f7917c00SJeff Kirsher struct sge_ofld_txq *txq = s->egr_map[id]; 2342f7917c00SJeff Kirsher 2343f7917c00SJeff Kirsher clear_bit(id, s->txq_maperr); 2344f7917c00SJeff Kirsher tasklet_schedule(&txq->qresume_tsk); 2345f7917c00SJeff Kirsher } 2346f7917c00SJeff Kirsher 2347f7917c00SJeff Kirsher budget = MAX_TIMER_TX_RECLAIM; 2348f7917c00SJeff Kirsher i = s->ethtxq_rover; 2349f7917c00SJeff Kirsher do { 2350f7917c00SJeff Kirsher struct sge_eth_txq *q = &s->ethtxq[i]; 2351f7917c00SJeff Kirsher 2352f7917c00SJeff Kirsher if (q->q.in_use && 2353f7917c00SJeff Kirsher time_after_eq(jiffies, q->txq->trans_start + HZ / 100) && 2354f7917c00SJeff Kirsher __netif_tx_trylock(q->txq)) { 2355f7917c00SJeff Kirsher int avail = reclaimable(&q->q); 2356f7917c00SJeff Kirsher 2357f7917c00SJeff Kirsher if (avail) { 2358f7917c00SJeff Kirsher if (avail > budget) 2359f7917c00SJeff Kirsher avail = budget; 2360f7917c00SJeff Kirsher 2361f7917c00SJeff Kirsher free_tx_desc(adap, &q->q, avail, true); 2362f7917c00SJeff Kirsher q->q.in_use -= avail; 2363f7917c00SJeff Kirsher budget -= avail; 2364f7917c00SJeff Kirsher } 2365f7917c00SJeff Kirsher __netif_tx_unlock(q->txq); 2366f7917c00SJeff Kirsher } 2367f7917c00SJeff Kirsher 2368f7917c00SJeff Kirsher if (++i >= s->ethqsets) 2369f7917c00SJeff Kirsher i = 0; 2370f7917c00SJeff Kirsher } while (budget && i != s->ethtxq_rover); 2371f7917c00SJeff Kirsher s->ethtxq_rover = i; 2372f7917c00SJeff Kirsher mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2)); 2373f7917c00SJeff Kirsher } 2374f7917c00SJeff Kirsher 2375d63a6dcfSHariprasad Shenai /** 2376df64e4d3SHariprasad Shenai * bar2_address - return the BAR2 address for an SGE Queue's Registers 2377df64e4d3SHariprasad Shenai * @adapter: the adapter 2378df64e4d3SHariprasad Shenai * @qid: the SGE Queue ID 2379df64e4d3SHariprasad Shenai * @qtype: the SGE Queue Type (Egress or Ingress) 2380df64e4d3SHariprasad Shenai * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 2381d63a6dcfSHariprasad Shenai * 2382df64e4d3SHariprasad Shenai * Returns the BAR2 address for the SGE Queue Registers associated with 2383df64e4d3SHariprasad Shenai * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also 2384df64e4d3SHariprasad Shenai * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE 2385df64e4d3SHariprasad Shenai * Queue Registers. If the BAR2 Queue ID is 0, then "Inferred Queue ID" 2386df64e4d3SHariprasad Shenai * Registers are supported (e.g. the Write Combining Doorbell Buffer). 2387d63a6dcfSHariprasad Shenai */ 2388df64e4d3SHariprasad Shenai static void __iomem *bar2_address(struct adapter *adapter, 2389df64e4d3SHariprasad Shenai unsigned int qid, 2390df64e4d3SHariprasad Shenai enum t4_bar2_qtype qtype, 2391df64e4d3SHariprasad Shenai unsigned int *pbar2_qid) 2392d63a6dcfSHariprasad Shenai { 2393df64e4d3SHariprasad Shenai u64 bar2_qoffset; 2394df64e4d3SHariprasad Shenai int ret; 2395d63a6dcfSHariprasad Shenai 2396dd0bcc0bSStephen Rothwell ret = cxgb4_t4_bar2_sge_qregs(adapter, qid, qtype, 2397df64e4d3SHariprasad Shenai &bar2_qoffset, pbar2_qid); 2398df64e4d3SHariprasad Shenai if (ret) 2399df64e4d3SHariprasad Shenai return NULL; 2400d63a6dcfSHariprasad Shenai 2401df64e4d3SHariprasad Shenai return adapter->bar2 + bar2_qoffset; 2402d63a6dcfSHariprasad Shenai } 2403d63a6dcfSHariprasad Shenai 2404f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 2405f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 2406f7917c00SJeff Kirsher struct sge_fl *fl, rspq_handler_t hnd) 2407f7917c00SJeff Kirsher { 2408f7917c00SJeff Kirsher int ret, flsz = 0; 2409f7917c00SJeff Kirsher struct fw_iq_cmd c; 241052367a76SVipul Pandya struct sge *s = &adap->sge; 2411f7917c00SJeff Kirsher struct port_info *pi = netdev_priv(dev); 2412f7917c00SJeff Kirsher 2413f7917c00SJeff Kirsher /* Size needs to be multiple of 16, including status entry. */ 2414f7917c00SJeff Kirsher iq->size = roundup(iq->size, 16); 2415f7917c00SJeff Kirsher 2416f7917c00SJeff Kirsher iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0, 2417f7917c00SJeff Kirsher &iq->phys_addr, NULL, 0, NUMA_NO_NODE); 2418f7917c00SJeff Kirsher if (!iq->desc) 2419f7917c00SJeff Kirsher return -ENOMEM; 2420f7917c00SJeff Kirsher 2421f7917c00SJeff Kirsher memset(&c, 0, sizeof(c)); 2422e2ac9628SHariprasad Shenai c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F | 2423e2ac9628SHariprasad Shenai FW_CMD_WRITE_F | FW_CMD_EXEC_F | 24246e4b51a6SHariprasad Shenai FW_IQ_CMD_PFN_V(adap->fn) | FW_IQ_CMD_VFN_V(0)); 24256e4b51a6SHariprasad Shenai c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F | FW_IQ_CMD_IQSTART_F | 2426f7917c00SJeff Kirsher FW_LEN16(c)); 24276e4b51a6SHariprasad Shenai c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) | 24286e4b51a6SHariprasad Shenai FW_IQ_CMD_IQASYNCH_V(fwevtq) | FW_IQ_CMD_VIID_V(pi->viid) | 24296e4b51a6SHariprasad Shenai FW_IQ_CMD_IQANDST_V(intr_idx < 0) | FW_IQ_CMD_IQANUD_V(1) | 24306e4b51a6SHariprasad Shenai FW_IQ_CMD_IQANDSTINDEX_V(intr_idx >= 0 ? intr_idx : 2431f7917c00SJeff Kirsher -intr_idx - 1)); 24326e4b51a6SHariprasad Shenai c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(pi->tx_chan) | 24336e4b51a6SHariprasad Shenai FW_IQ_CMD_IQGTSMODE_F | 24346e4b51a6SHariprasad Shenai FW_IQ_CMD_IQINTCNTTHRESH_V(iq->pktcnt_idx) | 24356e4b51a6SHariprasad Shenai FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4)); 2436f7917c00SJeff Kirsher c.iqsize = htons(iq->size); 2437f7917c00SJeff Kirsher c.iqaddr = cpu_to_be64(iq->phys_addr); 2438f7917c00SJeff Kirsher 2439f7917c00SJeff Kirsher if (fl) { 2440f7917c00SJeff Kirsher fl->size = roundup(fl->size, 8); 2441f7917c00SJeff Kirsher fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64), 2442f7917c00SJeff Kirsher sizeof(struct rx_sw_desc), &fl->addr, 244352367a76SVipul Pandya &fl->sdesc, s->stat_len, NUMA_NO_NODE); 2444f7917c00SJeff Kirsher if (!fl->desc) 2445f7917c00SJeff Kirsher goto fl_nomem; 2446f7917c00SJeff Kirsher 244752367a76SVipul Pandya flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc); 24486e4b51a6SHariprasad Shenai c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN_F | 24496e4b51a6SHariprasad Shenai FW_IQ_CMD_FL0FETCHRO_F | 24506e4b51a6SHariprasad Shenai FW_IQ_CMD_FL0DATARO_F | 24516e4b51a6SHariprasad Shenai FW_IQ_CMD_FL0PADEN_F); 24526e4b51a6SHariprasad Shenai c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN_V(2) | 24536e4b51a6SHariprasad Shenai FW_IQ_CMD_FL0FBMAX_V(3)); 2454f7917c00SJeff Kirsher c.fl0size = htons(flsz); 2455f7917c00SJeff Kirsher c.fl0addr = cpu_to_be64(fl->addr); 2456f7917c00SJeff Kirsher } 2457f7917c00SJeff Kirsher 2458f7917c00SJeff Kirsher ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); 2459f7917c00SJeff Kirsher if (ret) 2460f7917c00SJeff Kirsher goto err; 2461f7917c00SJeff Kirsher 2462f7917c00SJeff Kirsher netif_napi_add(dev, &iq->napi, napi_rx_handler, 64); 24633a336cb1SHariprasad Shenai napi_hash_add(&iq->napi); 2464f7917c00SJeff Kirsher iq->cur_desc = iq->desc; 2465f7917c00SJeff Kirsher iq->cidx = 0; 2466f7917c00SJeff Kirsher iq->gen = 1; 2467f7917c00SJeff Kirsher iq->next_intr_params = iq->intr_params; 2468f7917c00SJeff Kirsher iq->cntxt_id = ntohs(c.iqid); 2469f7917c00SJeff Kirsher iq->abs_id = ntohs(c.physiqid); 2470df64e4d3SHariprasad Shenai iq->bar2_addr = bar2_address(adap, 2471df64e4d3SHariprasad Shenai iq->cntxt_id, 2472df64e4d3SHariprasad Shenai T4_BAR2_QTYPE_INGRESS, 2473df64e4d3SHariprasad Shenai &iq->bar2_qid); 2474f7917c00SJeff Kirsher iq->size--; /* subtract status entry */ 2475f7917c00SJeff Kirsher iq->netdev = dev; 2476f7917c00SJeff Kirsher iq->handler = hnd; 2477f7917c00SJeff Kirsher 2478f7917c00SJeff Kirsher /* set offset to -1 to distinguish ingress queues without FL */ 2479f7917c00SJeff Kirsher iq->offset = fl ? 0 : -1; 2480f7917c00SJeff Kirsher 2481f7917c00SJeff Kirsher adap->sge.ingr_map[iq->cntxt_id - adap->sge.ingr_start] = iq; 2482f7917c00SJeff Kirsher 2483f7917c00SJeff Kirsher if (fl) { 2484f7917c00SJeff Kirsher fl->cntxt_id = ntohs(c.fl0id); 2485f7917c00SJeff Kirsher fl->avail = fl->pend_cred = 0; 2486f7917c00SJeff Kirsher fl->pidx = fl->cidx = 0; 2487f7917c00SJeff Kirsher fl->alloc_failed = fl->large_alloc_failed = fl->starving = 0; 2488f7917c00SJeff Kirsher adap->sge.egr_map[fl->cntxt_id - adap->sge.egr_start] = fl; 2489d63a6dcfSHariprasad Shenai 2490df64e4d3SHariprasad Shenai /* Note, we must initialize the BAR2 Free List User Doorbell 2491df64e4d3SHariprasad Shenai * information before refilling the Free List! 2492d63a6dcfSHariprasad Shenai */ 2493df64e4d3SHariprasad Shenai fl->bar2_addr = bar2_address(adap, 2494df64e4d3SHariprasad Shenai fl->cntxt_id, 2495df64e4d3SHariprasad Shenai T4_BAR2_QTYPE_EGRESS, 2496df64e4d3SHariprasad Shenai &fl->bar2_qid); 2497f7917c00SJeff Kirsher refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL); 2498f7917c00SJeff Kirsher } 2499f7917c00SJeff Kirsher return 0; 2500f7917c00SJeff Kirsher 2501f7917c00SJeff Kirsher fl_nomem: 2502f7917c00SJeff Kirsher ret = -ENOMEM; 2503f7917c00SJeff Kirsher err: 2504f7917c00SJeff Kirsher if (iq->desc) { 2505f7917c00SJeff Kirsher dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len, 2506f7917c00SJeff Kirsher iq->desc, iq->phys_addr); 2507f7917c00SJeff Kirsher iq->desc = NULL; 2508f7917c00SJeff Kirsher } 2509f7917c00SJeff Kirsher if (fl && fl->desc) { 2510f7917c00SJeff Kirsher kfree(fl->sdesc); 2511f7917c00SJeff Kirsher fl->sdesc = NULL; 2512f7917c00SJeff Kirsher dma_free_coherent(adap->pdev_dev, flsz * sizeof(struct tx_desc), 2513f7917c00SJeff Kirsher fl->desc, fl->addr); 2514f7917c00SJeff Kirsher fl->desc = NULL; 2515f7917c00SJeff Kirsher } 2516f7917c00SJeff Kirsher return ret; 2517f7917c00SJeff Kirsher } 2518f7917c00SJeff Kirsher 2519f7917c00SJeff Kirsher static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id) 2520f7917c00SJeff Kirsher { 252122adfe0aSSantosh Rastapur q->cntxt_id = id; 2522df64e4d3SHariprasad Shenai q->bar2_addr = bar2_address(adap, 2523df64e4d3SHariprasad Shenai q->cntxt_id, 2524df64e4d3SHariprasad Shenai T4_BAR2_QTYPE_EGRESS, 2525df64e4d3SHariprasad Shenai &q->bar2_qid); 2526f7917c00SJeff Kirsher q->in_use = 0; 2527f7917c00SJeff Kirsher q->cidx = q->pidx = 0; 2528f7917c00SJeff Kirsher q->stops = q->restarts = 0; 2529f7917c00SJeff Kirsher q->stat = (void *)&q->desc[q->size]; 25303069ee9bSVipul Pandya spin_lock_init(&q->db_lock); 2531f7917c00SJeff Kirsher adap->sge.egr_map[id - adap->sge.egr_start] = q; 2532f7917c00SJeff Kirsher } 2533f7917c00SJeff Kirsher 2534f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 2535f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 2536f7917c00SJeff Kirsher unsigned int iqid) 2537f7917c00SJeff Kirsher { 2538f7917c00SJeff Kirsher int ret, nentries; 2539f7917c00SJeff Kirsher struct fw_eq_eth_cmd c; 254052367a76SVipul Pandya struct sge *s = &adap->sge; 2541f7917c00SJeff Kirsher struct port_info *pi = netdev_priv(dev); 2542f7917c00SJeff Kirsher 2543f7917c00SJeff Kirsher /* Add status entries */ 254452367a76SVipul Pandya nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); 2545f7917c00SJeff Kirsher 2546f7917c00SJeff Kirsher txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size, 2547f7917c00SJeff Kirsher sizeof(struct tx_desc), sizeof(struct tx_sw_desc), 254852367a76SVipul Pandya &txq->q.phys_addr, &txq->q.sdesc, s->stat_len, 2549f7917c00SJeff Kirsher netdev_queue_numa_node_read(netdevq)); 2550f7917c00SJeff Kirsher if (!txq->q.desc) 2551f7917c00SJeff Kirsher return -ENOMEM; 2552f7917c00SJeff Kirsher 2553f7917c00SJeff Kirsher memset(&c, 0, sizeof(c)); 2554e2ac9628SHariprasad Shenai c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F | 2555e2ac9628SHariprasad Shenai FW_CMD_WRITE_F | FW_CMD_EXEC_F | 25566e4b51a6SHariprasad Shenai FW_EQ_ETH_CMD_PFN_V(adap->fn) | 25576e4b51a6SHariprasad Shenai FW_EQ_ETH_CMD_VFN_V(0)); 25586e4b51a6SHariprasad Shenai c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F | 25596e4b51a6SHariprasad Shenai FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c)); 25606e4b51a6SHariprasad Shenai c.viid_pkd = htonl(FW_EQ_ETH_CMD_AUTOEQUEQE_F | 25616e4b51a6SHariprasad Shenai FW_EQ_ETH_CMD_VIID_V(pi->viid)); 25626e4b51a6SHariprasad Shenai c.fetchszm_to_iqid = htonl(FW_EQ_ETH_CMD_HOSTFCMODE_V(2) | 25636e4b51a6SHariprasad Shenai FW_EQ_ETH_CMD_PCIECHN_V(pi->tx_chan) | 25646e4b51a6SHariprasad Shenai FW_EQ_ETH_CMD_FETCHRO_V(1) | 25656e4b51a6SHariprasad Shenai FW_EQ_ETH_CMD_IQID_V(iqid)); 25666e4b51a6SHariprasad Shenai c.dcaen_to_eqsize = htonl(FW_EQ_ETH_CMD_FBMIN_V(2) | 25676e4b51a6SHariprasad Shenai FW_EQ_ETH_CMD_FBMAX_V(3) | 25686e4b51a6SHariprasad Shenai FW_EQ_ETH_CMD_CIDXFTHRESH_V(5) | 25696e4b51a6SHariprasad Shenai FW_EQ_ETH_CMD_EQSIZE_V(nentries)); 2570f7917c00SJeff Kirsher c.eqaddr = cpu_to_be64(txq->q.phys_addr); 2571f7917c00SJeff Kirsher 2572f7917c00SJeff Kirsher ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); 2573f7917c00SJeff Kirsher if (ret) { 2574f7917c00SJeff Kirsher kfree(txq->q.sdesc); 2575f7917c00SJeff Kirsher txq->q.sdesc = NULL; 2576f7917c00SJeff Kirsher dma_free_coherent(adap->pdev_dev, 2577f7917c00SJeff Kirsher nentries * sizeof(struct tx_desc), 2578f7917c00SJeff Kirsher txq->q.desc, txq->q.phys_addr); 2579f7917c00SJeff Kirsher txq->q.desc = NULL; 2580f7917c00SJeff Kirsher return ret; 2581f7917c00SJeff Kirsher } 2582f7917c00SJeff Kirsher 25836e4b51a6SHariprasad Shenai init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_G(ntohl(c.eqid_pkd))); 2584f7917c00SJeff Kirsher txq->txq = netdevq; 2585f7917c00SJeff Kirsher txq->tso = txq->tx_cso = txq->vlan_ins = 0; 2586f7917c00SJeff Kirsher txq->mapping_err = 0; 2587f7917c00SJeff Kirsher return 0; 2588f7917c00SJeff Kirsher } 2589f7917c00SJeff Kirsher 2590f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 2591f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 2592f7917c00SJeff Kirsher unsigned int cmplqid) 2593f7917c00SJeff Kirsher { 2594f7917c00SJeff Kirsher int ret, nentries; 2595f7917c00SJeff Kirsher struct fw_eq_ctrl_cmd c; 259652367a76SVipul Pandya struct sge *s = &adap->sge; 2597f7917c00SJeff Kirsher struct port_info *pi = netdev_priv(dev); 2598f7917c00SJeff Kirsher 2599f7917c00SJeff Kirsher /* Add status entries */ 260052367a76SVipul Pandya nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); 2601f7917c00SJeff Kirsher 2602f7917c00SJeff Kirsher txq->q.desc = alloc_ring(adap->pdev_dev, nentries, 2603f7917c00SJeff Kirsher sizeof(struct tx_desc), 0, &txq->q.phys_addr, 2604f7917c00SJeff Kirsher NULL, 0, NUMA_NO_NODE); 2605f7917c00SJeff Kirsher if (!txq->q.desc) 2606f7917c00SJeff Kirsher return -ENOMEM; 2607f7917c00SJeff Kirsher 2608e2ac9628SHariprasad Shenai c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F | 2609e2ac9628SHariprasad Shenai FW_CMD_WRITE_F | FW_CMD_EXEC_F | 26106e4b51a6SHariprasad Shenai FW_EQ_CTRL_CMD_PFN_V(adap->fn) | 26116e4b51a6SHariprasad Shenai FW_EQ_CTRL_CMD_VFN_V(0)); 26126e4b51a6SHariprasad Shenai c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F | 26136e4b51a6SHariprasad Shenai FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c)); 26146e4b51a6SHariprasad Shenai c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID_V(cmplqid)); 2615f7917c00SJeff Kirsher c.physeqid_pkd = htonl(0); 26166e4b51a6SHariprasad Shenai c.fetchszm_to_iqid = htonl(FW_EQ_CTRL_CMD_HOSTFCMODE_V(2) | 26176e4b51a6SHariprasad Shenai FW_EQ_CTRL_CMD_PCIECHN_V(pi->tx_chan) | 26186e4b51a6SHariprasad Shenai FW_EQ_CTRL_CMD_FETCHRO_F | 26196e4b51a6SHariprasad Shenai FW_EQ_CTRL_CMD_IQID_V(iqid)); 26206e4b51a6SHariprasad Shenai c.dcaen_to_eqsize = htonl(FW_EQ_CTRL_CMD_FBMIN_V(2) | 26216e4b51a6SHariprasad Shenai FW_EQ_CTRL_CMD_FBMAX_V(3) | 26226e4b51a6SHariprasad Shenai FW_EQ_CTRL_CMD_CIDXFTHRESH_V(5) | 26236e4b51a6SHariprasad Shenai FW_EQ_CTRL_CMD_EQSIZE_V(nentries)); 2624f7917c00SJeff Kirsher c.eqaddr = cpu_to_be64(txq->q.phys_addr); 2625f7917c00SJeff Kirsher 2626f7917c00SJeff Kirsher ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); 2627f7917c00SJeff Kirsher if (ret) { 2628f7917c00SJeff Kirsher dma_free_coherent(adap->pdev_dev, 2629f7917c00SJeff Kirsher nentries * sizeof(struct tx_desc), 2630f7917c00SJeff Kirsher txq->q.desc, txq->q.phys_addr); 2631f7917c00SJeff Kirsher txq->q.desc = NULL; 2632f7917c00SJeff Kirsher return ret; 2633f7917c00SJeff Kirsher } 2634f7917c00SJeff Kirsher 26356e4b51a6SHariprasad Shenai init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_G(ntohl(c.cmpliqid_eqid))); 2636f7917c00SJeff Kirsher txq->adap = adap; 2637f7917c00SJeff Kirsher skb_queue_head_init(&txq->sendq); 2638f7917c00SJeff Kirsher tasklet_init(&txq->qresume_tsk, restart_ctrlq, (unsigned long)txq); 2639f7917c00SJeff Kirsher txq->full = 0; 2640f7917c00SJeff Kirsher return 0; 2641f7917c00SJeff Kirsher } 2642f7917c00SJeff Kirsher 2643f7917c00SJeff Kirsher int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 2644f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid) 2645f7917c00SJeff Kirsher { 2646f7917c00SJeff Kirsher int ret, nentries; 2647f7917c00SJeff Kirsher struct fw_eq_ofld_cmd c; 264852367a76SVipul Pandya struct sge *s = &adap->sge; 2649f7917c00SJeff Kirsher struct port_info *pi = netdev_priv(dev); 2650f7917c00SJeff Kirsher 2651f7917c00SJeff Kirsher /* Add status entries */ 265252367a76SVipul Pandya nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); 2653f7917c00SJeff Kirsher 2654f7917c00SJeff Kirsher txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size, 2655f7917c00SJeff Kirsher sizeof(struct tx_desc), sizeof(struct tx_sw_desc), 265652367a76SVipul Pandya &txq->q.phys_addr, &txq->q.sdesc, s->stat_len, 2657f7917c00SJeff Kirsher NUMA_NO_NODE); 2658f7917c00SJeff Kirsher if (!txq->q.desc) 2659f7917c00SJeff Kirsher return -ENOMEM; 2660f7917c00SJeff Kirsher 2661f7917c00SJeff Kirsher memset(&c, 0, sizeof(c)); 2662e2ac9628SHariprasad Shenai c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F | 2663e2ac9628SHariprasad Shenai FW_CMD_WRITE_F | FW_CMD_EXEC_F | 26646e4b51a6SHariprasad Shenai FW_EQ_OFLD_CMD_PFN_V(adap->fn) | 26656e4b51a6SHariprasad Shenai FW_EQ_OFLD_CMD_VFN_V(0)); 26666e4b51a6SHariprasad Shenai c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F | 26676e4b51a6SHariprasad Shenai FW_EQ_OFLD_CMD_EQSTART_F | FW_LEN16(c)); 26686e4b51a6SHariprasad Shenai c.fetchszm_to_iqid = htonl(FW_EQ_OFLD_CMD_HOSTFCMODE_V(2) | 26696e4b51a6SHariprasad Shenai FW_EQ_OFLD_CMD_PCIECHN_V(pi->tx_chan) | 26706e4b51a6SHariprasad Shenai FW_EQ_OFLD_CMD_FETCHRO_F | 26716e4b51a6SHariprasad Shenai FW_EQ_OFLD_CMD_IQID_V(iqid)); 26726e4b51a6SHariprasad Shenai c.dcaen_to_eqsize = htonl(FW_EQ_OFLD_CMD_FBMIN_V(2) | 26736e4b51a6SHariprasad Shenai FW_EQ_OFLD_CMD_FBMAX_V(3) | 26746e4b51a6SHariprasad Shenai FW_EQ_OFLD_CMD_CIDXFTHRESH_V(5) | 26756e4b51a6SHariprasad Shenai FW_EQ_OFLD_CMD_EQSIZE_V(nentries)); 2676f7917c00SJeff Kirsher c.eqaddr = cpu_to_be64(txq->q.phys_addr); 2677f7917c00SJeff Kirsher 2678f7917c00SJeff Kirsher ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c); 2679f7917c00SJeff Kirsher if (ret) { 2680f7917c00SJeff Kirsher kfree(txq->q.sdesc); 2681f7917c00SJeff Kirsher txq->q.sdesc = NULL; 2682f7917c00SJeff Kirsher dma_free_coherent(adap->pdev_dev, 2683f7917c00SJeff Kirsher nentries * sizeof(struct tx_desc), 2684f7917c00SJeff Kirsher txq->q.desc, txq->q.phys_addr); 2685f7917c00SJeff Kirsher txq->q.desc = NULL; 2686f7917c00SJeff Kirsher return ret; 2687f7917c00SJeff Kirsher } 2688f7917c00SJeff Kirsher 26896e4b51a6SHariprasad Shenai init_txq(adap, &txq->q, FW_EQ_OFLD_CMD_EQID_G(ntohl(c.eqid_pkd))); 2690f7917c00SJeff Kirsher txq->adap = adap; 2691f7917c00SJeff Kirsher skb_queue_head_init(&txq->sendq); 2692f7917c00SJeff Kirsher tasklet_init(&txq->qresume_tsk, restart_ofldq, (unsigned long)txq); 2693f7917c00SJeff Kirsher txq->full = 0; 2694f7917c00SJeff Kirsher txq->mapping_err = 0; 2695f7917c00SJeff Kirsher return 0; 2696f7917c00SJeff Kirsher } 2697f7917c00SJeff Kirsher 2698f7917c00SJeff Kirsher static void free_txq(struct adapter *adap, struct sge_txq *q) 2699f7917c00SJeff Kirsher { 270052367a76SVipul Pandya struct sge *s = &adap->sge; 270152367a76SVipul Pandya 2702f7917c00SJeff Kirsher dma_free_coherent(adap->pdev_dev, 270352367a76SVipul Pandya q->size * sizeof(struct tx_desc) + s->stat_len, 2704f7917c00SJeff Kirsher q->desc, q->phys_addr); 2705f7917c00SJeff Kirsher q->cntxt_id = 0; 2706f7917c00SJeff Kirsher q->sdesc = NULL; 2707f7917c00SJeff Kirsher q->desc = NULL; 2708f7917c00SJeff Kirsher } 2709f7917c00SJeff Kirsher 2710f7917c00SJeff Kirsher static void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, 2711f7917c00SJeff Kirsher struct sge_fl *fl) 2712f7917c00SJeff Kirsher { 271352367a76SVipul Pandya struct sge *s = &adap->sge; 2714f7917c00SJeff Kirsher unsigned int fl_id = fl ? fl->cntxt_id : 0xffff; 2715f7917c00SJeff Kirsher 2716f7917c00SJeff Kirsher adap->sge.ingr_map[rq->cntxt_id - adap->sge.ingr_start] = NULL; 2717f7917c00SJeff Kirsher t4_iq_free(adap, adap->fn, adap->fn, 0, FW_IQ_TYPE_FL_INT_CAP, 2718f7917c00SJeff Kirsher rq->cntxt_id, fl_id, 0xffff); 2719f7917c00SJeff Kirsher dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len, 2720f7917c00SJeff Kirsher rq->desc, rq->phys_addr); 27213a336cb1SHariprasad Shenai napi_hash_del(&rq->napi); 2722f7917c00SJeff Kirsher netif_napi_del(&rq->napi); 2723f7917c00SJeff Kirsher rq->netdev = NULL; 2724f7917c00SJeff Kirsher rq->cntxt_id = rq->abs_id = 0; 2725f7917c00SJeff Kirsher rq->desc = NULL; 2726f7917c00SJeff Kirsher 2727f7917c00SJeff Kirsher if (fl) { 2728f7917c00SJeff Kirsher free_rx_bufs(adap, fl, fl->avail); 272952367a76SVipul Pandya dma_free_coherent(adap->pdev_dev, fl->size * 8 + s->stat_len, 2730f7917c00SJeff Kirsher fl->desc, fl->addr); 2731f7917c00SJeff Kirsher kfree(fl->sdesc); 2732f7917c00SJeff Kirsher fl->sdesc = NULL; 2733f7917c00SJeff Kirsher fl->cntxt_id = 0; 2734f7917c00SJeff Kirsher fl->desc = NULL; 2735f7917c00SJeff Kirsher } 2736f7917c00SJeff Kirsher } 2737f7917c00SJeff Kirsher 2738f7917c00SJeff Kirsher /** 27395fa76694SHariprasad Shenai * t4_free_ofld_rxqs - free a block of consecutive Rx queues 27405fa76694SHariprasad Shenai * @adap: the adapter 27415fa76694SHariprasad Shenai * @n: number of queues 27425fa76694SHariprasad Shenai * @q: pointer to first queue 27435fa76694SHariprasad Shenai * 27445fa76694SHariprasad Shenai * Release the resources of a consecutive block of offload Rx queues. 27455fa76694SHariprasad Shenai */ 27465fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q) 27475fa76694SHariprasad Shenai { 27485fa76694SHariprasad Shenai for ( ; n; n--, q++) 27495fa76694SHariprasad Shenai if (q->rspq.desc) 27505fa76694SHariprasad Shenai free_rspq_fl(adap, &q->rspq, 27515fa76694SHariprasad Shenai q->fl.size ? &q->fl : NULL); 27525fa76694SHariprasad Shenai } 27535fa76694SHariprasad Shenai 27545fa76694SHariprasad Shenai /** 2755f7917c00SJeff Kirsher * t4_free_sge_resources - free SGE resources 2756f7917c00SJeff Kirsher * @adap: the adapter 2757f7917c00SJeff Kirsher * 2758f7917c00SJeff Kirsher * Frees resources used by the SGE queue sets. 2759f7917c00SJeff Kirsher */ 2760f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap) 2761f7917c00SJeff Kirsher { 2762f7917c00SJeff Kirsher int i; 2763f7917c00SJeff Kirsher struct sge_eth_rxq *eq = adap->sge.ethrxq; 2764f7917c00SJeff Kirsher struct sge_eth_txq *etq = adap->sge.ethtxq; 2765f7917c00SJeff Kirsher 2766f7917c00SJeff Kirsher /* clean up Ethernet Tx/Rx queues */ 2767f7917c00SJeff Kirsher for (i = 0; i < adap->sge.ethqsets; i++, eq++, etq++) { 2768f7917c00SJeff Kirsher if (eq->rspq.desc) 27695fa76694SHariprasad Shenai free_rspq_fl(adap, &eq->rspq, 27705fa76694SHariprasad Shenai eq->fl.size ? &eq->fl : NULL); 2771f7917c00SJeff Kirsher if (etq->q.desc) { 2772f7917c00SJeff Kirsher t4_eth_eq_free(adap, adap->fn, adap->fn, 0, 2773f7917c00SJeff Kirsher etq->q.cntxt_id); 2774f7917c00SJeff Kirsher free_tx_desc(adap, &etq->q, etq->q.in_use, true); 2775f7917c00SJeff Kirsher kfree(etq->q.sdesc); 2776f7917c00SJeff Kirsher free_txq(adap, &etq->q); 2777f7917c00SJeff Kirsher } 2778f7917c00SJeff Kirsher } 2779f7917c00SJeff Kirsher 2780f7917c00SJeff Kirsher /* clean up RDMA and iSCSI Rx queues */ 27815fa76694SHariprasad Shenai t4_free_ofld_rxqs(adap, adap->sge.ofldqsets, adap->sge.ofldrxq); 27825fa76694SHariprasad Shenai t4_free_ofld_rxqs(adap, adap->sge.rdmaqs, adap->sge.rdmarxq); 27835fa76694SHariprasad Shenai t4_free_ofld_rxqs(adap, adap->sge.rdmaciqs, adap->sge.rdmaciq); 2784f7917c00SJeff Kirsher 2785f7917c00SJeff Kirsher /* clean up offload Tx queues */ 2786f7917c00SJeff Kirsher for (i = 0; i < ARRAY_SIZE(adap->sge.ofldtxq); i++) { 2787f7917c00SJeff Kirsher struct sge_ofld_txq *q = &adap->sge.ofldtxq[i]; 2788f7917c00SJeff Kirsher 2789f7917c00SJeff Kirsher if (q->q.desc) { 2790f7917c00SJeff Kirsher tasklet_kill(&q->qresume_tsk); 2791f7917c00SJeff Kirsher t4_ofld_eq_free(adap, adap->fn, adap->fn, 0, 2792f7917c00SJeff Kirsher q->q.cntxt_id); 2793f7917c00SJeff Kirsher free_tx_desc(adap, &q->q, q->q.in_use, false); 2794f7917c00SJeff Kirsher kfree(q->q.sdesc); 2795f7917c00SJeff Kirsher __skb_queue_purge(&q->sendq); 2796f7917c00SJeff Kirsher free_txq(adap, &q->q); 2797f7917c00SJeff Kirsher } 2798f7917c00SJeff Kirsher } 2799f7917c00SJeff Kirsher 2800f7917c00SJeff Kirsher /* clean up control Tx queues */ 2801f7917c00SJeff Kirsher for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) { 2802f7917c00SJeff Kirsher struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i]; 2803f7917c00SJeff Kirsher 2804f7917c00SJeff Kirsher if (cq->q.desc) { 2805f7917c00SJeff Kirsher tasklet_kill(&cq->qresume_tsk); 2806f7917c00SJeff Kirsher t4_ctrl_eq_free(adap, adap->fn, adap->fn, 0, 2807f7917c00SJeff Kirsher cq->q.cntxt_id); 2808f7917c00SJeff Kirsher __skb_queue_purge(&cq->sendq); 2809f7917c00SJeff Kirsher free_txq(adap, &cq->q); 2810f7917c00SJeff Kirsher } 2811f7917c00SJeff Kirsher } 2812f7917c00SJeff Kirsher 2813f7917c00SJeff Kirsher if (adap->sge.fw_evtq.desc) 2814f7917c00SJeff Kirsher free_rspq_fl(adap, &adap->sge.fw_evtq, NULL); 2815f7917c00SJeff Kirsher 2816f7917c00SJeff Kirsher if (adap->sge.intrq.desc) 2817f7917c00SJeff Kirsher free_rspq_fl(adap, &adap->sge.intrq, NULL); 2818f7917c00SJeff Kirsher 2819f7917c00SJeff Kirsher /* clear the reverse egress queue map */ 28204b8e27a8SHariprasad Shenai memset(adap->sge.egr_map, 0, 28214b8e27a8SHariprasad Shenai adap->sge.egr_sz * sizeof(*adap->sge.egr_map)); 2822f7917c00SJeff Kirsher } 2823f7917c00SJeff Kirsher 2824f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap) 2825f7917c00SJeff Kirsher { 2826f7917c00SJeff Kirsher adap->sge.ethtxq_rover = 0; 2827f7917c00SJeff Kirsher mod_timer(&adap->sge.rx_timer, jiffies + RX_QCHECK_PERIOD); 2828f7917c00SJeff Kirsher mod_timer(&adap->sge.tx_timer, jiffies + TX_QCHECK_PERIOD); 2829f7917c00SJeff Kirsher } 2830f7917c00SJeff Kirsher 2831f7917c00SJeff Kirsher /** 2832f7917c00SJeff Kirsher * t4_sge_stop - disable SGE operation 2833f7917c00SJeff Kirsher * @adap: the adapter 2834f7917c00SJeff Kirsher * 2835f7917c00SJeff Kirsher * Stop tasklets and timers associated with the DMA engine. Note that 2836f7917c00SJeff Kirsher * this is effective only if measures have been taken to disable any HW 2837f7917c00SJeff Kirsher * events that may restart them. 2838f7917c00SJeff Kirsher */ 2839f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap) 2840f7917c00SJeff Kirsher { 2841f7917c00SJeff Kirsher int i; 2842f7917c00SJeff Kirsher struct sge *s = &adap->sge; 2843f7917c00SJeff Kirsher 2844f7917c00SJeff Kirsher if (in_interrupt()) /* actions below require waiting */ 2845f7917c00SJeff Kirsher return; 2846f7917c00SJeff Kirsher 2847f7917c00SJeff Kirsher if (s->rx_timer.function) 2848f7917c00SJeff Kirsher del_timer_sync(&s->rx_timer); 2849f7917c00SJeff Kirsher if (s->tx_timer.function) 2850f7917c00SJeff Kirsher del_timer_sync(&s->tx_timer); 2851f7917c00SJeff Kirsher 2852f7917c00SJeff Kirsher for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) { 2853f7917c00SJeff Kirsher struct sge_ofld_txq *q = &s->ofldtxq[i]; 2854f7917c00SJeff Kirsher 2855f7917c00SJeff Kirsher if (q->q.desc) 2856f7917c00SJeff Kirsher tasklet_kill(&q->qresume_tsk); 2857f7917c00SJeff Kirsher } 2858f7917c00SJeff Kirsher for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) { 2859f7917c00SJeff Kirsher struct sge_ctrl_txq *cq = &s->ctrlq[i]; 2860f7917c00SJeff Kirsher 2861f7917c00SJeff Kirsher if (cq->q.desc) 2862f7917c00SJeff Kirsher tasklet_kill(&cq->qresume_tsk); 2863f7917c00SJeff Kirsher } 2864f7917c00SJeff Kirsher } 2865f7917c00SJeff Kirsher 2866f7917c00SJeff Kirsher /** 286706640310SHariprasad Shenai * t4_sge_init_soft - grab core SGE values needed by SGE code 2868f7917c00SJeff Kirsher * @adap: the adapter 2869f7917c00SJeff Kirsher * 287006640310SHariprasad Shenai * We need to grab the SGE operating parameters that we need to have 287106640310SHariprasad Shenai * in order to do our job and make sure we can live with them. 2872f7917c00SJeff Kirsher */ 2873f7917c00SJeff Kirsher 287452367a76SVipul Pandya static int t4_sge_init_soft(struct adapter *adap) 287552367a76SVipul Pandya { 287652367a76SVipul Pandya struct sge *s = &adap->sge; 287752367a76SVipul Pandya u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu; 287852367a76SVipul Pandya u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5; 287952367a76SVipul Pandya u32 ingress_rx_threshold; 288052367a76SVipul Pandya 288152367a76SVipul Pandya /* 288252367a76SVipul Pandya * Verify that CPL messages are going to the Ingress Queue for 288352367a76SVipul Pandya * process_responses() and that only packet data is going to the 288452367a76SVipul Pandya * Free Lists. 288552367a76SVipul Pandya */ 2886f612b815SHariprasad Shenai if ((t4_read_reg(adap, SGE_CONTROL_A) & RXPKTCPLMODE_F) != 2887f612b815SHariprasad Shenai RXPKTCPLMODE_V(RXPKTCPLMODE_SPLIT_X)) { 288852367a76SVipul Pandya dev_err(adap->pdev_dev, "bad SGE CPL MODE\n"); 288952367a76SVipul Pandya return -EINVAL; 289052367a76SVipul Pandya } 289152367a76SVipul Pandya 289252367a76SVipul Pandya /* 289352367a76SVipul Pandya * Validate the Host Buffer Register Array indices that we want to 289452367a76SVipul Pandya * use ... 289552367a76SVipul Pandya * 289652367a76SVipul Pandya * XXX Note that we should really read through the Host Buffer Size 289752367a76SVipul Pandya * XXX register array and find the indices of the Buffer Sizes which 289852367a76SVipul Pandya * XXX meet our needs! 289952367a76SVipul Pandya */ 290052367a76SVipul Pandya #define READ_FL_BUF(x) \ 2901f612b815SHariprasad Shenai t4_read_reg(adap, SGE_FL_BUFFER_SIZE0_A+(x)*sizeof(u32)) 290252367a76SVipul Pandya 290352367a76SVipul Pandya fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF); 290452367a76SVipul Pandya fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF); 290552367a76SVipul Pandya fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF); 290652367a76SVipul Pandya fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF); 290752367a76SVipul Pandya 290892ddcc7bSKumar Sanghvi /* We only bother using the Large Page logic if the Large Page Buffer 290992ddcc7bSKumar Sanghvi * is larger than our Page Size Buffer. 291092ddcc7bSKumar Sanghvi */ 291192ddcc7bSKumar Sanghvi if (fl_large_pg <= fl_small_pg) 291292ddcc7bSKumar Sanghvi fl_large_pg = 0; 291392ddcc7bSKumar Sanghvi 291452367a76SVipul Pandya #undef READ_FL_BUF 291552367a76SVipul Pandya 291692ddcc7bSKumar Sanghvi /* The Page Size Buffer must be exactly equal to our Page Size and the 291792ddcc7bSKumar Sanghvi * Large Page Size Buffer should be 0 (per above) or a power of 2. 291892ddcc7bSKumar Sanghvi */ 291952367a76SVipul Pandya if (fl_small_pg != PAGE_SIZE || 292092ddcc7bSKumar Sanghvi (fl_large_pg & (fl_large_pg-1)) != 0) { 292152367a76SVipul Pandya dev_err(adap->pdev_dev, "bad SGE FL page buffer sizes [%d, %d]\n", 292252367a76SVipul Pandya fl_small_pg, fl_large_pg); 292352367a76SVipul Pandya return -EINVAL; 292452367a76SVipul Pandya } 292552367a76SVipul Pandya if (fl_large_pg) 292652367a76SVipul Pandya s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT; 292752367a76SVipul Pandya 292852367a76SVipul Pandya if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap) || 292952367a76SVipul Pandya fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) { 293052367a76SVipul Pandya dev_err(adap->pdev_dev, "bad SGE FL MTU sizes [%d, %d]\n", 293152367a76SVipul Pandya fl_small_mtu, fl_large_mtu); 293252367a76SVipul Pandya return -EINVAL; 293352367a76SVipul Pandya } 293452367a76SVipul Pandya 293552367a76SVipul Pandya /* 293652367a76SVipul Pandya * Retrieve our RX interrupt holdoff timer values and counter 293752367a76SVipul Pandya * threshold values from the SGE parameters. 293852367a76SVipul Pandya */ 2939f061de42SHariprasad Shenai timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A); 2940f061de42SHariprasad Shenai timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A); 2941f061de42SHariprasad Shenai timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A); 294252367a76SVipul Pandya s->timer_val[0] = core_ticks_to_us(adap, 2943f061de42SHariprasad Shenai TIMERVALUE0_G(timer_value_0_and_1)); 294452367a76SVipul Pandya s->timer_val[1] = core_ticks_to_us(adap, 2945f061de42SHariprasad Shenai TIMERVALUE1_G(timer_value_0_and_1)); 294652367a76SVipul Pandya s->timer_val[2] = core_ticks_to_us(adap, 2947f061de42SHariprasad Shenai TIMERVALUE2_G(timer_value_2_and_3)); 294852367a76SVipul Pandya s->timer_val[3] = core_ticks_to_us(adap, 2949f061de42SHariprasad Shenai TIMERVALUE3_G(timer_value_2_and_3)); 295052367a76SVipul Pandya s->timer_val[4] = core_ticks_to_us(adap, 2951f061de42SHariprasad Shenai TIMERVALUE4_G(timer_value_4_and_5)); 295252367a76SVipul Pandya s->timer_val[5] = core_ticks_to_us(adap, 2953f061de42SHariprasad Shenai TIMERVALUE5_G(timer_value_4_and_5)); 295452367a76SVipul Pandya 2955f612b815SHariprasad Shenai ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A); 2956f612b815SHariprasad Shenai s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold); 2957f612b815SHariprasad Shenai s->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold); 2958f612b815SHariprasad Shenai s->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold); 2959f612b815SHariprasad Shenai s->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold); 296052367a76SVipul Pandya 296152367a76SVipul Pandya return 0; 296252367a76SVipul Pandya } 296352367a76SVipul Pandya 296406640310SHariprasad Shenai /** 296506640310SHariprasad Shenai * t4_sge_init - initialize SGE 296606640310SHariprasad Shenai * @adap: the adapter 296706640310SHariprasad Shenai * 296806640310SHariprasad Shenai * Perform low-level SGE code initialization needed every time after a 296906640310SHariprasad Shenai * chip reset. 297052367a76SVipul Pandya */ 297152367a76SVipul Pandya int t4_sge_init(struct adapter *adap) 297252367a76SVipul Pandya { 297352367a76SVipul Pandya struct sge *s = &adap->sge; 2974ce8f407aSHariprasad Shenai u32 sge_control, sge_control2, sge_conm_ctrl; 2975ce8f407aSHariprasad Shenai unsigned int ingpadboundary, ingpackboundary; 2976c2b955e0SKumar Sanghvi int ret, egress_threshold; 297752367a76SVipul Pandya 297852367a76SVipul Pandya /* 297952367a76SVipul Pandya * Ingress Padding Boundary and Egress Status Page Size are set up by 298052367a76SVipul Pandya * t4_fixup_host_params(). 298152367a76SVipul Pandya */ 2982f612b815SHariprasad Shenai sge_control = t4_read_reg(adap, SGE_CONTROL_A); 2983f612b815SHariprasad Shenai s->pktshift = PKTSHIFT_G(sge_control); 2984f612b815SHariprasad Shenai s->stat_len = (sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64; 2985ce8f407aSHariprasad Shenai 2986ce8f407aSHariprasad Shenai /* T4 uses a single control field to specify both the PCIe Padding and 2987ce8f407aSHariprasad Shenai * Packing Boundary. T5 introduced the ability to specify these 2988ce8f407aSHariprasad Shenai * separately. The actual Ingress Packet Data alignment boundary 2989ce8f407aSHariprasad Shenai * within Packed Buffer Mode is the maximum of these two 2990ce8f407aSHariprasad Shenai * specifications. 2991ce8f407aSHariprasad Shenai */ 2992f612b815SHariprasad Shenai ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + 2993f612b815SHariprasad Shenai INGPADBOUNDARY_SHIFT_X); 2994ce8f407aSHariprasad Shenai if (is_t4(adap->params.chip)) { 2995ce8f407aSHariprasad Shenai s->fl_align = ingpadboundary; 2996ce8f407aSHariprasad Shenai } else { 2997ce8f407aSHariprasad Shenai /* T5 has a different interpretation of one of the PCIe Packing 2998ce8f407aSHariprasad Shenai * Boundary values. 2999ce8f407aSHariprasad Shenai */ 3000ce8f407aSHariprasad Shenai sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A); 3001ce8f407aSHariprasad Shenai ingpackboundary = INGPACKBOUNDARY_G(sge_control2); 3002ce8f407aSHariprasad Shenai if (ingpackboundary == INGPACKBOUNDARY_16B_X) 3003ce8f407aSHariprasad Shenai ingpackboundary = 16; 3004ce8f407aSHariprasad Shenai else 3005ce8f407aSHariprasad Shenai ingpackboundary = 1 << (ingpackboundary + 3006ce8f407aSHariprasad Shenai INGPACKBOUNDARY_SHIFT_X); 3007ce8f407aSHariprasad Shenai 3008ce8f407aSHariprasad Shenai s->fl_align = max(ingpadboundary, ingpackboundary); 3009ce8f407aSHariprasad Shenai } 301052367a76SVipul Pandya 301152367a76SVipul Pandya ret = t4_sge_init_soft(adap); 301252367a76SVipul Pandya if (ret < 0) 301352367a76SVipul Pandya return ret; 301452367a76SVipul Pandya 301552367a76SVipul Pandya /* 301652367a76SVipul Pandya * A FL with <= fl_starve_thres buffers is starving and a periodic 301752367a76SVipul Pandya * timer will attempt to refill it. This needs to be larger than the 301852367a76SVipul Pandya * SGE's Egress Congestion Threshold. If it isn't, then we can get 301952367a76SVipul Pandya * stuck waiting for new packets while the SGE is waiting for us to 302052367a76SVipul Pandya * give it more Free List entries. (Note that the SGE's Egress 3021c2b955e0SKumar Sanghvi * Congestion Threshold is in units of 2 Free List pointers.) For T4, 3022c2b955e0SKumar Sanghvi * there was only a single field to control this. For T5 there's the 3023c2b955e0SKumar Sanghvi * original field which now only applies to Unpacked Mode Free List 3024c2b955e0SKumar Sanghvi * buffers and a new field which only applies to Packed Mode Free List 3025c2b955e0SKumar Sanghvi * buffers. 302652367a76SVipul Pandya */ 3027f612b815SHariprasad Shenai sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A); 3028c2b955e0SKumar Sanghvi if (is_t4(adap->params.chip)) 3029f612b815SHariprasad Shenai egress_threshold = EGRTHRESHOLD_G(sge_conm_ctrl); 3030c2b955e0SKumar Sanghvi else 3031f612b815SHariprasad Shenai egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl); 3032c2b955e0SKumar Sanghvi s->fl_starve_thres = 2*egress_threshold + 1; 303352367a76SVipul Pandya 3034f7917c00SJeff Kirsher setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap); 3035f7917c00SJeff Kirsher setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adap); 30360f4d201fSKumar Sanghvi s->idma_1s_thresh = core_ticks_per_usec(adap) * 1000000; /* 1 s */ 30370f4d201fSKumar Sanghvi s->idma_stalled[0] = 0; 30380f4d201fSKumar Sanghvi s->idma_stalled[1] = 0; 3039f7917c00SJeff Kirsher spin_lock_init(&s->intrq_lock); 304052367a76SVipul Pandya 304152367a76SVipul Pandya return 0; 3042f7917c00SJeff Kirsher } 3043