1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_ULD_H 36 #define __CXGB4_ULD_H 37 38 #include <linux/cache.h> 39 #include <linux/spinlock.h> 40 #include <linux/skbuff.h> 41 #include <linux/inetdevice.h> 42 #include <linux/atomic.h> 43 #include "cxgb4.h" 44 45 #define MAX_ULD_QSETS 16 46 47 /* CPL message priority levels */ 48 enum { 49 CPL_PRIORITY_DATA = 0, /* data messages */ 50 CPL_PRIORITY_SETUP = 1, /* connection setup messages */ 51 CPL_PRIORITY_TEARDOWN = 0, /* connection teardown messages */ 52 CPL_PRIORITY_LISTEN = 1, /* listen start/stop messages */ 53 CPL_PRIORITY_ACK = 1, /* RX ACK messages */ 54 CPL_PRIORITY_CONTROL = 1 /* control messages */ 55 }; 56 57 #define INIT_TP_WR(w, tid) do { \ 58 (w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_TP_WR) | \ 59 FW_WR_IMMDLEN_V(sizeof(*w) - sizeof(w->wr))); \ 60 (w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*w), 16)) | \ 61 FW_WR_FLOWID_V(tid)); \ 62 (w)->wr.wr_lo = cpu_to_be64(0); \ 63 } while (0) 64 65 #define INIT_TP_WR_CPL(w, cpl, tid) do { \ 66 INIT_TP_WR(w, tid); \ 67 OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \ 68 } while (0) 69 70 #define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \ 71 (w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_ULPTX_WR) | \ 72 FW_WR_ATOMIC_V(atomic)); \ 73 (w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(wrlen, 16)) | \ 74 FW_WR_FLOWID_V(tid)); \ 75 (w)->wr.wr_lo = cpu_to_be64(0); \ 76 } while (0) 77 78 /* Special asynchronous notification message */ 79 #define CXGB4_MSG_AN ((void *)1) 80 #define TX_ULD(uld)(((uld) != CXGB4_ULD_CRYPTO) ? CXGB4_TX_OFLD :\ 81 CXGB4_TX_CRYPTO) 82 83 struct serv_entry { 84 void *data; 85 }; 86 87 union aopen_entry { 88 void *data; 89 union aopen_entry *next; 90 }; 91 92 /* 93 * Holds the size, base address, free list start, etc of the TID, server TID, 94 * and active-open TID tables. The tables themselves are allocated dynamically. 95 */ 96 struct tid_info { 97 void **tid_tab; 98 unsigned int ntids; 99 100 struct serv_entry *stid_tab; 101 unsigned long *stid_bmap; 102 unsigned int nstids; 103 unsigned int stid_base; 104 unsigned int hash_base; 105 106 union aopen_entry *atid_tab; 107 unsigned int natids; 108 unsigned int atid_base; 109 110 struct filter_entry *ftid_tab; 111 unsigned long *ftid_bmap; 112 unsigned int nftids; 113 unsigned int ftid_base; 114 unsigned int aftid_base; 115 unsigned int aftid_end; 116 /* Server filter region */ 117 unsigned int sftid_base; 118 unsigned int nsftids; 119 120 spinlock_t atid_lock ____cacheline_aligned_in_smp; 121 union aopen_entry *afree; 122 unsigned int atids_in_use; 123 124 spinlock_t stid_lock; 125 unsigned int stids_in_use; 126 unsigned int sftids_in_use; 127 128 /* TIDs in the TCAM */ 129 atomic_t tids_in_use; 130 /* TIDs in the HASH */ 131 atomic_t hash_tids_in_use; 132 /* lock for setting/clearing filter bitmap */ 133 spinlock_t ftid_lock; 134 }; 135 136 static inline void *lookup_tid(const struct tid_info *t, unsigned int tid) 137 { 138 return tid < t->ntids ? t->tid_tab[tid] : NULL; 139 } 140 141 static inline void *lookup_atid(const struct tid_info *t, unsigned int atid) 142 { 143 return atid < t->natids ? t->atid_tab[atid].data : NULL; 144 } 145 146 static inline void *lookup_stid(const struct tid_info *t, unsigned int stid) 147 { 148 /* Is it a server filter TID? */ 149 if (t->nsftids && (stid >= t->sftid_base)) { 150 stid -= t->sftid_base; 151 stid += t->nstids; 152 } else { 153 stid -= t->stid_base; 154 } 155 156 return stid < (t->nstids + t->nsftids) ? t->stid_tab[stid].data : NULL; 157 } 158 159 static inline void cxgb4_insert_tid(struct tid_info *t, void *data, 160 unsigned int tid) 161 { 162 t->tid_tab[tid] = data; 163 if (t->hash_base && (tid >= t->hash_base)) 164 atomic_inc(&t->hash_tids_in_use); 165 else 166 atomic_inc(&t->tids_in_use); 167 } 168 169 int cxgb4_alloc_atid(struct tid_info *t, void *data); 170 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data); 171 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data); 172 void cxgb4_free_atid(struct tid_info *t, unsigned int atid); 173 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family); 174 void cxgb4_remove_tid(struct tid_info *t, unsigned int qid, unsigned int tid); 175 176 struct in6_addr; 177 178 int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 179 __be32 sip, __be16 sport, __be16 vlan, 180 unsigned int queue); 181 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 182 const struct in6_addr *sip, __be16 sport, 183 unsigned int queue); 184 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 185 unsigned int queue, bool ipv6); 186 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 187 __be32 sip, __be16 sport, __be16 vlan, 188 unsigned int queue, 189 unsigned char port, unsigned char mask); 190 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 191 unsigned int queue, bool ipv6); 192 193 /* Filter operation context to allow callers of cxgb4_set_filter() and 194 * cxgb4_del_filter() to wait for an asynchronous completion. 195 */ 196 struct filter_ctx { 197 struct completion completion; /* completion rendezvous */ 198 void *closure; /* caller's opaque information */ 199 int result; /* result of operation */ 200 u32 tid; /* to store tid */ 201 }; 202 203 struct ch_filter_specification; 204 205 int __cxgb4_set_filter(struct net_device *dev, int filter_id, 206 struct ch_filter_specification *fs, 207 struct filter_ctx *ctx); 208 int __cxgb4_del_filter(struct net_device *dev, int filter_id, 209 struct filter_ctx *ctx); 210 int cxgb4_set_filter(struct net_device *dev, int filter_id, 211 struct ch_filter_specification *fs); 212 int cxgb4_del_filter(struct net_device *dev, int filter_id); 213 214 static inline void set_wr_txq(struct sk_buff *skb, int prio, int queue) 215 { 216 skb_set_queue_mapping(skb, (queue << 1) | prio); 217 } 218 219 enum cxgb4_uld { 220 CXGB4_ULD_INIT, 221 CXGB4_ULD_RDMA, 222 CXGB4_ULD_ISCSI, 223 CXGB4_ULD_ISCSIT, 224 CXGB4_ULD_CRYPTO, 225 CXGB4_ULD_MAX 226 }; 227 228 enum cxgb4_tx_uld { 229 CXGB4_TX_OFLD, 230 CXGB4_TX_CRYPTO, 231 CXGB4_TX_MAX 232 }; 233 234 enum cxgb4_txq_type { 235 CXGB4_TXQ_ETH, 236 CXGB4_TXQ_ULD, 237 CXGB4_TXQ_CTRL, 238 CXGB4_TXQ_MAX 239 }; 240 241 enum cxgb4_state { 242 CXGB4_STATE_UP, 243 CXGB4_STATE_START_RECOVERY, 244 CXGB4_STATE_DOWN, 245 CXGB4_STATE_DETACH 246 }; 247 248 enum cxgb4_control { 249 CXGB4_CONTROL_DB_FULL, 250 CXGB4_CONTROL_DB_EMPTY, 251 CXGB4_CONTROL_DB_DROP, 252 }; 253 254 struct pci_dev; 255 struct l2t_data; 256 struct net_device; 257 struct pkt_gl; 258 struct tp_tcp_stats; 259 struct t4_lro_mgr; 260 261 struct cxgb4_range { 262 unsigned int start; 263 unsigned int size; 264 }; 265 266 struct cxgb4_virt_res { /* virtualized HW resources */ 267 struct cxgb4_range ddp; 268 struct cxgb4_range iscsi; 269 struct cxgb4_range stag; 270 struct cxgb4_range rq; 271 struct cxgb4_range pbl; 272 struct cxgb4_range qp; 273 struct cxgb4_range cq; 274 struct cxgb4_range ocq; 275 }; 276 277 #define OCQ_WIN_OFFSET(pdev, vres) \ 278 (pci_resource_len((pdev), 2) - roundup_pow_of_two((vres)->ocq.size)) 279 280 /* 281 * Block of information the LLD provides to ULDs attaching to a device. 282 */ 283 struct cxgb4_lld_info { 284 struct pci_dev *pdev; /* associated PCI device */ 285 struct l2t_data *l2t; /* L2 table */ 286 struct tid_info *tids; /* TID table */ 287 struct net_device **ports; /* device ports */ 288 const struct cxgb4_virt_res *vr; /* assorted HW resources */ 289 const unsigned short *mtus; /* MTU table */ 290 const unsigned short *rxq_ids; /* the ULD's Rx queue ids */ 291 const unsigned short *ciq_ids; /* the ULD's concentrator IQ ids */ 292 unsigned short nrxq; /* # of Rx queues */ 293 unsigned short ntxq; /* # of Tx queues */ 294 unsigned short nciq; /* # of concentrator IQ */ 295 unsigned char nchan:4; /* # of channels */ 296 unsigned char nports:4; /* # of ports */ 297 unsigned char wr_cred; /* WR 16-byte credits */ 298 unsigned char adapter_type; /* type of adapter */ 299 unsigned char fw_api_ver; /* FW API version */ 300 unsigned int fw_vers; /* FW version */ 301 unsigned int iscsi_iolen; /* iSCSI max I/O length */ 302 unsigned int cclk_ps; /* Core clock period in psec */ 303 unsigned short udb_density; /* # of user DB/page */ 304 unsigned short ucq_density; /* # of user CQs/page */ 305 unsigned short filt_mode; /* filter optional components */ 306 unsigned short tx_modq[NCHAN]; /* maps each tx channel to a */ 307 /* scheduler queue */ 308 void __iomem *gts_reg; /* address of GTS register */ 309 void __iomem *db_reg; /* address of kernel doorbell */ 310 int dbfifo_int_thresh; /* doorbell fifo int threshold */ 311 unsigned int sge_ingpadboundary; /* SGE ingress padding boundary */ 312 unsigned int sge_egrstatuspagesize; /* SGE egress status page size */ 313 unsigned int sge_pktshift; /* Padding between CPL and */ 314 /* packet data */ 315 unsigned int pf; /* Physical Function we're using */ 316 bool enable_fw_ofld_conn; /* Enable connection through fw */ 317 /* WR */ 318 unsigned int max_ordird_qp; /* Max ORD/IRD depth per RDMA QP */ 319 unsigned int max_ird_adapter; /* Max IRD memory per adapter */ 320 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 321 unsigned int iscsi_tagmask; /* iscsi ddp tag mask */ 322 unsigned int iscsi_pgsz_order; /* iscsi ddp page size orders */ 323 unsigned int iscsi_llimit; /* chip's iscsi region llimit */ 324 void **iscsi_ppm; /* iscsi page pod manager */ 325 int nodeid; /* device numa node id */ 326 bool fr_nsmr_tpte_wr_support; /* FW supports FR_NSMR_TPTE_WR */ 327 }; 328 329 struct cxgb4_uld_info { 330 const char *name; 331 void *handle; 332 unsigned int nrxq; 333 unsigned int rxq_size; 334 unsigned int ntxq; 335 bool ciq; 336 bool lro; 337 void *(*add)(const struct cxgb4_lld_info *p); 338 int (*rx_handler)(void *handle, const __be64 *rsp, 339 const struct pkt_gl *gl); 340 int (*state_change)(void *handle, enum cxgb4_state new_state); 341 int (*control)(void *handle, enum cxgb4_control control, ...); 342 int (*lro_rx_handler)(void *handle, const __be64 *rsp, 343 const struct pkt_gl *gl, 344 struct t4_lro_mgr *lro_mgr, 345 struct napi_struct *napi); 346 void (*lro_flush)(struct t4_lro_mgr *); 347 }; 348 349 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p); 350 int cxgb4_unregister_uld(enum cxgb4_uld type); 351 int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb); 352 int cxgb4_crypto_send(struct net_device *dev, struct sk_buff *skb); 353 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo); 354 unsigned int cxgb4_port_chan(const struct net_device *dev); 355 unsigned int cxgb4_port_viid(const struct net_device *dev); 356 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid); 357 unsigned int cxgb4_port_idx(const struct net_device *dev); 358 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 359 unsigned int *idx); 360 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 361 unsigned short header_size, 362 unsigned short data_size_max, 363 unsigned short data_size_align, 364 unsigned int *mtu_idxp); 365 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 366 struct tp_tcp_stats *v6); 367 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 368 const unsigned int *pgsz_order); 369 struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl, 370 unsigned int skb_len, unsigned int pull_len); 371 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, u16 size); 372 int cxgb4_flush_eq_cache(struct net_device *dev); 373 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte); 374 u64 cxgb4_read_sge_timestamp(struct net_device *dev); 375 376 enum cxgb4_bar2_qtype { CXGB4_BAR2_QTYPE_EGRESS, CXGB4_BAR2_QTYPE_INGRESS }; 377 int cxgb4_bar2_sge_qregs(struct net_device *dev, 378 unsigned int qid, 379 enum cxgb4_bar2_qtype qtype, 380 int user, 381 u64 *pbar2_qoffset, 382 unsigned int *pbar2_qid); 383 384 #endif /* !__CXGB4_ULD_H */ 385