1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_ULD_H 36 #define __CXGB4_ULD_H 37 38 #include <linux/cache.h> 39 #include <linux/spinlock.h> 40 #include <linux/skbuff.h> 41 #include <linux/inetdevice.h> 42 #include <linux/atomic.h> 43 #include "cxgb4.h" 44 45 #define MAX_ULD_QSETS 16 46 47 /* CPL message priority levels */ 48 enum { 49 CPL_PRIORITY_DATA = 0, /* data messages */ 50 CPL_PRIORITY_SETUP = 1, /* connection setup messages */ 51 CPL_PRIORITY_TEARDOWN = 0, /* connection teardown messages */ 52 CPL_PRIORITY_LISTEN = 1, /* listen start/stop messages */ 53 CPL_PRIORITY_ACK = 1, /* RX ACK messages */ 54 CPL_PRIORITY_CONTROL = 1 /* control messages */ 55 }; 56 57 #define INIT_TP_WR(w, tid) do { \ 58 (w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_TP_WR) | \ 59 FW_WR_IMMDLEN_V(sizeof(*w) - sizeof(w->wr))); \ 60 (w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*w), 16)) | \ 61 FW_WR_FLOWID_V(tid)); \ 62 (w)->wr.wr_lo = cpu_to_be64(0); \ 63 } while (0) 64 65 #define INIT_TP_WR_CPL(w, cpl, tid) do { \ 66 INIT_TP_WR(w, tid); \ 67 OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \ 68 } while (0) 69 70 #define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \ 71 (w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_ULPTX_WR) | \ 72 FW_WR_ATOMIC_V(atomic)); \ 73 (w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(wrlen, 16)) | \ 74 FW_WR_FLOWID_V(tid)); \ 75 (w)->wr.wr_lo = cpu_to_be64(0); \ 76 } while (0) 77 78 /* Special asynchronous notification message */ 79 #define CXGB4_MSG_AN ((void *)1) 80 #define TX_ULD(uld)(((uld) != CXGB4_ULD_CRYPTO) ? CXGB4_TX_OFLD :\ 81 CXGB4_TX_CRYPTO) 82 83 struct serv_entry { 84 void *data; 85 }; 86 87 union aopen_entry { 88 void *data; 89 union aopen_entry *next; 90 }; 91 92 struct eotid_entry { 93 void *data; 94 }; 95 96 /* 97 * Holds the size, base address, free list start, etc of the TID, server TID, 98 * and active-open TID tables. The tables themselves are allocated dynamically. 99 */ 100 struct tid_info { 101 void **tid_tab; 102 unsigned int ntids; 103 104 struct serv_entry *stid_tab; 105 unsigned long *stid_bmap; 106 unsigned int nstids; 107 unsigned int stid_base; 108 unsigned int hash_base; 109 110 union aopen_entry *atid_tab; 111 unsigned int natids; 112 unsigned int atid_base; 113 114 struct filter_entry *hpftid_tab; 115 unsigned long *hpftid_bmap; 116 unsigned int nhpftids; 117 unsigned int hpftid_base; 118 119 struct filter_entry *ftid_tab; 120 unsigned long *ftid_bmap; 121 unsigned int nftids; 122 unsigned int ftid_base; 123 unsigned int aftid_base; 124 unsigned int aftid_end; 125 /* Server filter region */ 126 unsigned int sftid_base; 127 unsigned int nsftids; 128 129 spinlock_t atid_lock ____cacheline_aligned_in_smp; 130 union aopen_entry *afree; 131 unsigned int atids_in_use; 132 133 spinlock_t stid_lock; 134 unsigned int stids_in_use; 135 unsigned int v6_stids_in_use; 136 unsigned int sftids_in_use; 137 138 /* ETHOFLD range */ 139 struct eotid_entry *eotid_tab; 140 unsigned long *eotid_bmap; 141 unsigned int eotid_base; 142 unsigned int neotids; 143 144 /* TIDs in the TCAM */ 145 atomic_t tids_in_use; 146 /* TIDs in the HASH */ 147 atomic_t hash_tids_in_use; 148 atomic_t conns_in_use; 149 /* lock for setting/clearing filter bitmap */ 150 spinlock_t ftid_lock; 151 }; 152 153 static inline void *lookup_tid(const struct tid_info *t, unsigned int tid) 154 { 155 return tid < t->ntids ? t->tid_tab[tid] : NULL; 156 } 157 158 static inline void *lookup_atid(const struct tid_info *t, unsigned int atid) 159 { 160 return atid < t->natids ? t->atid_tab[atid].data : NULL; 161 } 162 163 static inline void *lookup_stid(const struct tid_info *t, unsigned int stid) 164 { 165 /* Is it a server filter TID? */ 166 if (t->nsftids && (stid >= t->sftid_base)) { 167 stid -= t->sftid_base; 168 stid += t->nstids; 169 } else { 170 stid -= t->stid_base; 171 } 172 173 return stid < (t->nstids + t->nsftids) ? t->stid_tab[stid].data : NULL; 174 } 175 176 static inline void cxgb4_insert_tid(struct tid_info *t, void *data, 177 unsigned int tid, unsigned short family) 178 { 179 t->tid_tab[tid] = data; 180 if (t->hash_base && (tid >= t->hash_base)) { 181 if (family == AF_INET6) 182 atomic_add(2, &t->hash_tids_in_use); 183 else 184 atomic_inc(&t->hash_tids_in_use); 185 } else { 186 if (family == AF_INET6) 187 atomic_add(2, &t->tids_in_use); 188 else 189 atomic_inc(&t->tids_in_use); 190 } 191 atomic_inc(&t->conns_in_use); 192 } 193 194 static inline struct eotid_entry *cxgb4_lookup_eotid(struct tid_info *t, 195 u32 eotid) 196 { 197 return eotid < t->neotids ? &t->eotid_tab[eotid] : NULL; 198 } 199 200 static inline int cxgb4_get_free_eotid(struct tid_info *t) 201 { 202 int eotid; 203 204 eotid = find_first_zero_bit(t->eotid_bmap, t->neotids); 205 if (eotid >= t->neotids) 206 eotid = -1; 207 208 return eotid; 209 } 210 211 static inline void cxgb4_alloc_eotid(struct tid_info *t, u32 eotid, void *data) 212 { 213 set_bit(eotid, t->eotid_bmap); 214 t->eotid_tab[eotid].data = data; 215 } 216 217 static inline void cxgb4_free_eotid(struct tid_info *t, u32 eotid) 218 { 219 clear_bit(eotid, t->eotid_bmap); 220 t->eotid_tab[eotid].data = NULL; 221 } 222 223 int cxgb4_alloc_atid(struct tid_info *t, void *data); 224 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data); 225 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data); 226 void cxgb4_free_atid(struct tid_info *t, unsigned int atid); 227 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family); 228 void cxgb4_remove_tid(struct tid_info *t, unsigned int qid, unsigned int tid, 229 unsigned short family); 230 struct in6_addr; 231 232 int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 233 __be32 sip, __be16 sport, __be16 vlan, 234 unsigned int queue); 235 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 236 const struct in6_addr *sip, __be16 sport, 237 unsigned int queue); 238 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 239 unsigned int queue, bool ipv6); 240 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 241 __be32 sip, __be16 sport, __be16 vlan, 242 unsigned int queue, 243 unsigned char port, unsigned char mask); 244 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 245 unsigned int queue, bool ipv6); 246 247 /* Filter operation context to allow callers of cxgb4_set_filter() and 248 * cxgb4_del_filter() to wait for an asynchronous completion. 249 */ 250 struct filter_ctx { 251 struct completion completion; /* completion rendezvous */ 252 void *closure; /* caller's opaque information */ 253 int result; /* result of operation */ 254 u32 tid; /* to store tid */ 255 }; 256 257 struct ch_filter_specification; 258 259 int cxgb4_get_free_ftid(struct net_device *dev, int family); 260 int __cxgb4_set_filter(struct net_device *dev, int filter_id, 261 struct ch_filter_specification *fs, 262 struct filter_ctx *ctx); 263 int __cxgb4_del_filter(struct net_device *dev, int filter_id, 264 struct ch_filter_specification *fs, 265 struct filter_ctx *ctx); 266 int cxgb4_set_filter(struct net_device *dev, int filter_id, 267 struct ch_filter_specification *fs); 268 int cxgb4_del_filter(struct net_device *dev, int filter_id, 269 struct ch_filter_specification *fs); 270 int cxgb4_get_filter_counters(struct net_device *dev, unsigned int fidx, 271 u64 *hitcnt, u64 *bytecnt, bool hash); 272 273 static inline void set_wr_txq(struct sk_buff *skb, int prio, int queue) 274 { 275 skb_set_queue_mapping(skb, (queue << 1) | prio); 276 } 277 278 enum cxgb4_uld { 279 CXGB4_ULD_INIT, 280 CXGB4_ULD_RDMA, 281 CXGB4_ULD_ISCSI, 282 CXGB4_ULD_ISCSIT, 283 CXGB4_ULD_CRYPTO, 284 CXGB4_ULD_TLS, 285 CXGB4_ULD_MAX 286 }; 287 288 enum cxgb4_tx_uld { 289 CXGB4_TX_OFLD, 290 CXGB4_TX_CRYPTO, 291 CXGB4_TX_MAX 292 }; 293 294 enum cxgb4_txq_type { 295 CXGB4_TXQ_ETH, 296 CXGB4_TXQ_ULD, 297 CXGB4_TXQ_CTRL, 298 CXGB4_TXQ_MAX 299 }; 300 301 enum cxgb4_state { 302 CXGB4_STATE_UP, 303 CXGB4_STATE_START_RECOVERY, 304 CXGB4_STATE_DOWN, 305 CXGB4_STATE_DETACH, 306 CXGB4_STATE_FATAL_ERROR 307 }; 308 309 enum cxgb4_control { 310 CXGB4_CONTROL_DB_FULL, 311 CXGB4_CONTROL_DB_EMPTY, 312 CXGB4_CONTROL_DB_DROP, 313 }; 314 315 struct pci_dev; 316 struct l2t_data; 317 struct net_device; 318 struct pkt_gl; 319 struct tp_tcp_stats; 320 struct t4_lro_mgr; 321 322 struct cxgb4_range { 323 unsigned int start; 324 unsigned int size; 325 }; 326 327 struct cxgb4_virt_res { /* virtualized HW resources */ 328 struct cxgb4_range ddp; 329 struct cxgb4_range iscsi; 330 struct cxgb4_range stag; 331 struct cxgb4_range rq; 332 struct cxgb4_range srq; 333 struct cxgb4_range pbl; 334 struct cxgb4_range qp; 335 struct cxgb4_range cq; 336 struct cxgb4_range ocq; 337 struct cxgb4_range key; 338 unsigned int ncrypto_fc; 339 struct cxgb4_range ppod_edram; 340 }; 341 342 struct chcr_stats_debug { 343 atomic_t cipher_rqst; 344 atomic_t digest_rqst; 345 atomic_t aead_rqst; 346 atomic_t complete; 347 atomic_t error; 348 atomic_t fallback; 349 atomic_t ipsec_cnt; 350 atomic_t tls_pdu_tx; 351 atomic_t tls_pdu_rx; 352 atomic_t tls_key; 353 }; 354 355 #define OCQ_WIN_OFFSET(pdev, vres) \ 356 (pci_resource_len((pdev), 2) - roundup_pow_of_two((vres)->ocq.size)) 357 358 /* 359 * Block of information the LLD provides to ULDs attaching to a device. 360 */ 361 struct cxgb4_lld_info { 362 struct pci_dev *pdev; /* associated PCI device */ 363 struct l2t_data *l2t; /* L2 table */ 364 struct tid_info *tids; /* TID table */ 365 struct net_device **ports; /* device ports */ 366 const struct cxgb4_virt_res *vr; /* assorted HW resources */ 367 const unsigned short *mtus; /* MTU table */ 368 const unsigned short *rxq_ids; /* the ULD's Rx queue ids */ 369 const unsigned short *ciq_ids; /* the ULD's concentrator IQ ids */ 370 unsigned short nrxq; /* # of Rx queues */ 371 unsigned short ntxq; /* # of Tx queues */ 372 unsigned short nciq; /* # of concentrator IQ */ 373 unsigned char nchan:4; /* # of channels */ 374 unsigned char nports:4; /* # of ports */ 375 unsigned char wr_cred; /* WR 16-byte credits */ 376 unsigned char adapter_type; /* type of adapter */ 377 unsigned char fw_api_ver; /* FW API version */ 378 unsigned char crypto; /* crypto support */ 379 unsigned int fw_vers; /* FW version */ 380 unsigned int iscsi_iolen; /* iSCSI max I/O length */ 381 unsigned int cclk_ps; /* Core clock period in psec */ 382 unsigned short udb_density; /* # of user DB/page */ 383 unsigned short ucq_density; /* # of user CQs/page */ 384 unsigned int sge_host_page_size; /* SGE host page size */ 385 unsigned short filt_mode; /* filter optional components */ 386 unsigned short tx_modq[NCHAN]; /* maps each tx channel to a */ 387 /* scheduler queue */ 388 void __iomem *gts_reg; /* address of GTS register */ 389 void __iomem *db_reg; /* address of kernel doorbell */ 390 int dbfifo_int_thresh; /* doorbell fifo int threshold */ 391 unsigned int sge_ingpadboundary; /* SGE ingress padding boundary */ 392 unsigned int sge_egrstatuspagesize; /* SGE egress status page size */ 393 unsigned int sge_pktshift; /* Padding between CPL and */ 394 /* packet data */ 395 unsigned int pf; /* Physical Function we're using */ 396 bool enable_fw_ofld_conn; /* Enable connection through fw */ 397 /* WR */ 398 unsigned int max_ordird_qp; /* Max ORD/IRD depth per RDMA QP */ 399 unsigned int max_ird_adapter; /* Max IRD memory per adapter */ 400 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 401 unsigned int iscsi_tagmask; /* iscsi ddp tag mask */ 402 unsigned int iscsi_pgsz_order; /* iscsi ddp page size orders */ 403 unsigned int iscsi_llimit; /* chip's iscsi region llimit */ 404 unsigned int ulp_crypto; /* crypto lookaside support */ 405 void **iscsi_ppm; /* iscsi page pod manager */ 406 int nodeid; /* device numa node id */ 407 bool fr_nsmr_tpte_wr_support; /* FW supports FR_NSMR_TPTE_WR */ 408 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 409 bool write_cmpl_support; /* FW supports WRITE_CMPL WR */ 410 }; 411 412 struct cxgb4_uld_info { 413 char name[IFNAMSIZ]; 414 void *handle; 415 unsigned int nrxq; 416 unsigned int rxq_size; 417 unsigned int ntxq; 418 bool ciq; 419 bool lro; 420 void *(*add)(const struct cxgb4_lld_info *p); 421 int (*rx_handler)(void *handle, const __be64 *rsp, 422 const struct pkt_gl *gl); 423 int (*state_change)(void *handle, enum cxgb4_state new_state); 424 int (*control)(void *handle, enum cxgb4_control control, ...); 425 int (*lro_rx_handler)(void *handle, const __be64 *rsp, 426 const struct pkt_gl *gl, 427 struct t4_lro_mgr *lro_mgr, 428 struct napi_struct *napi); 429 void (*lro_flush)(struct t4_lro_mgr *); 430 int (*tx_handler)(struct sk_buff *skb, struct net_device *dev); 431 }; 432 433 void cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p); 434 int cxgb4_unregister_uld(enum cxgb4_uld type); 435 int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb); 436 int cxgb4_immdata_send(struct net_device *dev, unsigned int idx, 437 const void *src, unsigned int len); 438 int cxgb4_crypto_send(struct net_device *dev, struct sk_buff *skb); 439 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo); 440 unsigned int cxgb4_port_chan(const struct net_device *dev); 441 unsigned int cxgb4_port_e2cchan(const struct net_device *dev); 442 unsigned int cxgb4_port_viid(const struct net_device *dev); 443 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid); 444 unsigned int cxgb4_port_idx(const struct net_device *dev); 445 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 446 unsigned int *idx); 447 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 448 unsigned short header_size, 449 unsigned short data_size_max, 450 unsigned short data_size_align, 451 unsigned int *mtu_idxp); 452 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 453 struct tp_tcp_stats *v6); 454 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 455 const unsigned int *pgsz_order); 456 struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl, 457 unsigned int skb_len, unsigned int pull_len); 458 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, u16 size); 459 int cxgb4_flush_eq_cache(struct net_device *dev); 460 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte); 461 u64 cxgb4_read_sge_timestamp(struct net_device *dev); 462 463 enum cxgb4_bar2_qtype { CXGB4_BAR2_QTYPE_EGRESS, CXGB4_BAR2_QTYPE_INGRESS }; 464 int cxgb4_bar2_sge_qregs(struct net_device *dev, 465 unsigned int qid, 466 enum cxgb4_bar2_qtype qtype, 467 int user, 468 u64 *pbar2_qoffset, 469 unsigned int *pbar2_qid); 470 471 #endif /* !__CXGB4_ULD_H */ 472