1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/seq_file.h> 36 #include <linux/debugfs.h> 37 #include <linux/string_helpers.h> 38 #include <linux/sort.h> 39 #include <linux/ctype.h> 40 41 #include "cxgb4.h" 42 #include "t4_regs.h" 43 #include "t4_values.h" 44 #include "t4fw_api.h" 45 #include "cxgb4_debugfs.h" 46 #include "clip_tbl.h" 47 #include "l2t.h" 48 49 /* generic seq_file support for showing a table of size rows x width. */ 50 static void *seq_tab_get_idx(struct seq_tab *tb, loff_t pos) 51 { 52 pos -= tb->skip_first; 53 return pos >= tb->rows ? NULL : &tb->data[pos * tb->width]; 54 } 55 56 static void *seq_tab_start(struct seq_file *seq, loff_t *pos) 57 { 58 struct seq_tab *tb = seq->private; 59 60 if (tb->skip_first && *pos == 0) 61 return SEQ_START_TOKEN; 62 63 return seq_tab_get_idx(tb, *pos); 64 } 65 66 static void *seq_tab_next(struct seq_file *seq, void *v, loff_t *pos) 67 { 68 v = seq_tab_get_idx(seq->private, *pos + 1); 69 if (v) 70 ++*pos; 71 return v; 72 } 73 74 static void seq_tab_stop(struct seq_file *seq, void *v) 75 { 76 } 77 78 static int seq_tab_show(struct seq_file *seq, void *v) 79 { 80 const struct seq_tab *tb = seq->private; 81 82 return tb->show(seq, v, ((char *)v - tb->data) / tb->width); 83 } 84 85 static const struct seq_operations seq_tab_ops = { 86 .start = seq_tab_start, 87 .next = seq_tab_next, 88 .stop = seq_tab_stop, 89 .show = seq_tab_show 90 }; 91 92 struct seq_tab *seq_open_tab(struct file *f, unsigned int rows, 93 unsigned int width, unsigned int have_header, 94 int (*show)(struct seq_file *seq, void *v, int i)) 95 { 96 struct seq_tab *p; 97 98 p = __seq_open_private(f, &seq_tab_ops, sizeof(*p) + rows * width); 99 if (p) { 100 p->show = show; 101 p->rows = rows; 102 p->width = width; 103 p->skip_first = have_header != 0; 104 } 105 return p; 106 } 107 108 /* Trim the size of a seq_tab to the supplied number of rows. The operation is 109 * irreversible. 110 */ 111 static int seq_tab_trim(struct seq_tab *p, unsigned int new_rows) 112 { 113 if (new_rows > p->rows) 114 return -EINVAL; 115 p->rows = new_rows; 116 return 0; 117 } 118 119 static int cim_la_show(struct seq_file *seq, void *v, int idx) 120 { 121 if (v == SEQ_START_TOKEN) 122 seq_puts(seq, "Status Data PC LS0Stat LS0Addr " 123 " LS0Data\n"); 124 else { 125 const u32 *p = v; 126 127 seq_printf(seq, 128 " %02x %x%07x %x%07x %08x %08x %08x%08x%08x%08x\n", 129 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 130 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 131 p[6], p[7]); 132 } 133 return 0; 134 } 135 136 static int cim_la_show_3in1(struct seq_file *seq, void *v, int idx) 137 { 138 if (v == SEQ_START_TOKEN) { 139 seq_puts(seq, "Status Data PC\n"); 140 } else { 141 const u32 *p = v; 142 143 seq_printf(seq, " %02x %08x %08x\n", p[5] & 0xff, p[6], 144 p[7]); 145 seq_printf(seq, " %02x %02x%06x %02x%06x\n", 146 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 147 p[4] & 0xff, p[5] >> 8); 148 seq_printf(seq, " %02x %x%07x %x%07x\n", (p[0] >> 4) & 0xff, 149 p[0] & 0xf, p[1] >> 4, p[1] & 0xf, p[2] >> 4); 150 } 151 return 0; 152 } 153 154 static int cim_la_open(struct inode *inode, struct file *file) 155 { 156 int ret; 157 unsigned int cfg; 158 struct seq_tab *p; 159 struct adapter *adap = inode->i_private; 160 161 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg); 162 if (ret) 163 return ret; 164 165 p = seq_open_tab(file, adap->params.cim_la_size / 8, 8 * sizeof(u32), 1, 166 cfg & UPDBGLACAPTPCONLY_F ? 167 cim_la_show_3in1 : cim_la_show); 168 if (!p) 169 return -ENOMEM; 170 171 ret = t4_cim_read_la(adap, (u32 *)p->data, NULL); 172 if (ret) 173 seq_release_private(inode, file); 174 return ret; 175 } 176 177 static const struct file_operations cim_la_fops = { 178 .owner = THIS_MODULE, 179 .open = cim_la_open, 180 .read = seq_read, 181 .llseek = seq_lseek, 182 .release = seq_release_private 183 }; 184 185 static int cim_pif_la_show(struct seq_file *seq, void *v, int idx) 186 { 187 const u32 *p = v; 188 189 if (v == SEQ_START_TOKEN) { 190 seq_puts(seq, "Cntl ID DataBE Addr Data\n"); 191 } else if (idx < CIM_PIFLA_SIZE) { 192 seq_printf(seq, " %02x %02x %04x %08x %08x%08x%08x%08x\n", 193 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, 194 p[5] & 0xffff, p[4], p[3], p[2], p[1], p[0]); 195 } else { 196 if (idx == CIM_PIFLA_SIZE) 197 seq_puts(seq, "\nCntl ID Data\n"); 198 seq_printf(seq, " %02x %02x %08x%08x%08x%08x\n", 199 (p[4] >> 6) & 0xff, p[4] & 0x3f, 200 p[3], p[2], p[1], p[0]); 201 } 202 return 0; 203 } 204 205 static int cim_pif_la_open(struct inode *inode, struct file *file) 206 { 207 struct seq_tab *p; 208 struct adapter *adap = inode->i_private; 209 210 p = seq_open_tab(file, 2 * CIM_PIFLA_SIZE, 6 * sizeof(u32), 1, 211 cim_pif_la_show); 212 if (!p) 213 return -ENOMEM; 214 215 t4_cim_read_pif_la(adap, (u32 *)p->data, 216 (u32 *)p->data + 6 * CIM_PIFLA_SIZE, NULL, NULL); 217 return 0; 218 } 219 220 static const struct file_operations cim_pif_la_fops = { 221 .owner = THIS_MODULE, 222 .open = cim_pif_la_open, 223 .read = seq_read, 224 .llseek = seq_lseek, 225 .release = seq_release_private 226 }; 227 228 static int cim_ma_la_show(struct seq_file *seq, void *v, int idx) 229 { 230 const u32 *p = v; 231 232 if (v == SEQ_START_TOKEN) { 233 seq_puts(seq, "\n"); 234 } else if (idx < CIM_MALA_SIZE) { 235 seq_printf(seq, "%02x%08x%08x%08x%08x\n", 236 p[4], p[3], p[2], p[1], p[0]); 237 } else { 238 if (idx == CIM_MALA_SIZE) 239 seq_puts(seq, 240 "\nCnt ID Tag UE Data RDY VLD\n"); 241 seq_printf(seq, "%3u %2u %x %u %08x%08x %u %u\n", 242 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 243 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 244 (p[1] >> 2) | ((p[2] & 3) << 30), 245 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 246 p[0] & 1); 247 } 248 return 0; 249 } 250 251 static int cim_ma_la_open(struct inode *inode, struct file *file) 252 { 253 struct seq_tab *p; 254 struct adapter *adap = inode->i_private; 255 256 p = seq_open_tab(file, 2 * CIM_MALA_SIZE, 5 * sizeof(u32), 1, 257 cim_ma_la_show); 258 if (!p) 259 return -ENOMEM; 260 261 t4_cim_read_ma_la(adap, (u32 *)p->data, 262 (u32 *)p->data + 5 * CIM_MALA_SIZE); 263 return 0; 264 } 265 266 static const struct file_operations cim_ma_la_fops = { 267 .owner = THIS_MODULE, 268 .open = cim_ma_la_open, 269 .read = seq_read, 270 .llseek = seq_lseek, 271 .release = seq_release_private 272 }; 273 274 static int cim_qcfg_show(struct seq_file *seq, void *v) 275 { 276 static const char * const qname[] = { 277 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", 278 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", 279 "SGE0-RX", "SGE1-RX" 280 }; 281 282 int i; 283 struct adapter *adap = seq->private; 284 u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 285 u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 286 u32 stat[(4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5))]; 287 u16 thres[CIM_NUM_IBQ]; 288 u32 obq_wr_t4[2 * CIM_NUM_OBQ], *wr; 289 u32 obq_wr_t5[2 * CIM_NUM_OBQ_T5]; 290 u32 *p = stat; 291 int cim_num_obq = is_t4(adap->params.chip) ? 292 CIM_NUM_OBQ : CIM_NUM_OBQ_T5; 293 294 i = t4_cim_read(adap, is_t4(adap->params.chip) ? UP_IBQ_0_RDADDR_A : 295 UP_IBQ_0_SHADOW_RDADDR_A, 296 ARRAY_SIZE(stat), stat); 297 if (!i) { 298 if (is_t4(adap->params.chip)) { 299 i = t4_cim_read(adap, UP_OBQ_0_REALADDR_A, 300 ARRAY_SIZE(obq_wr_t4), obq_wr_t4); 301 wr = obq_wr_t4; 302 } else { 303 i = t4_cim_read(adap, UP_OBQ_0_SHADOW_REALADDR_A, 304 ARRAY_SIZE(obq_wr_t5), obq_wr_t5); 305 wr = obq_wr_t5; 306 } 307 } 308 if (i) 309 return i; 310 311 t4_read_cimq_cfg(adap, base, size, thres); 312 313 seq_printf(seq, 314 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail\n"); 315 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 316 seq_printf(seq, "%7s %5x %5u %5u %6x %4x %4u %4u %5u\n", 317 qname[i], base[i], size[i], thres[i], 318 IBQRDADDR_G(p[0]), IBQWRADDR_G(p[1]), 319 QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]), 320 QUEREMFLITS_G(p[2]) * 16); 321 for ( ; i < CIM_NUM_IBQ + cim_num_obq; i++, p += 4, wr += 2) 322 seq_printf(seq, "%7s %5x %5u %12x %4x %4u %4u %5u\n", 323 qname[i], base[i], size[i], 324 QUERDADDR_G(p[0]) & 0x3fff, wr[0] - base[i], 325 QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]), 326 QUEREMFLITS_G(p[2]) * 16); 327 return 0; 328 } 329 330 static int cim_qcfg_open(struct inode *inode, struct file *file) 331 { 332 return single_open(file, cim_qcfg_show, inode->i_private); 333 } 334 335 static const struct file_operations cim_qcfg_fops = { 336 .owner = THIS_MODULE, 337 .open = cim_qcfg_open, 338 .read = seq_read, 339 .llseek = seq_lseek, 340 .release = single_release, 341 }; 342 343 static int cimq_show(struct seq_file *seq, void *v, int idx) 344 { 345 const u32 *p = v; 346 347 seq_printf(seq, "%#06x: %08x %08x %08x %08x\n", idx * 16, p[0], p[1], 348 p[2], p[3]); 349 return 0; 350 } 351 352 static int cim_ibq_open(struct inode *inode, struct file *file) 353 { 354 int ret; 355 struct seq_tab *p; 356 unsigned int qid = (uintptr_t)inode->i_private & 7; 357 struct adapter *adap = inode->i_private - qid; 358 359 p = seq_open_tab(file, CIM_IBQ_SIZE, 4 * sizeof(u32), 0, cimq_show); 360 if (!p) 361 return -ENOMEM; 362 363 ret = t4_read_cim_ibq(adap, qid, (u32 *)p->data, CIM_IBQ_SIZE * 4); 364 if (ret < 0) 365 seq_release_private(inode, file); 366 else 367 ret = 0; 368 return ret; 369 } 370 371 static const struct file_operations cim_ibq_fops = { 372 .owner = THIS_MODULE, 373 .open = cim_ibq_open, 374 .read = seq_read, 375 .llseek = seq_lseek, 376 .release = seq_release_private 377 }; 378 379 static int cim_obq_open(struct inode *inode, struct file *file) 380 { 381 int ret; 382 struct seq_tab *p; 383 unsigned int qid = (uintptr_t)inode->i_private & 7; 384 struct adapter *adap = inode->i_private - qid; 385 386 p = seq_open_tab(file, 6 * CIM_OBQ_SIZE, 4 * sizeof(u32), 0, cimq_show); 387 if (!p) 388 return -ENOMEM; 389 390 ret = t4_read_cim_obq(adap, qid, (u32 *)p->data, 6 * CIM_OBQ_SIZE * 4); 391 if (ret < 0) { 392 seq_release_private(inode, file); 393 } else { 394 seq_tab_trim(p, ret / 4); 395 ret = 0; 396 } 397 return ret; 398 } 399 400 static const struct file_operations cim_obq_fops = { 401 .owner = THIS_MODULE, 402 .open = cim_obq_open, 403 .read = seq_read, 404 .llseek = seq_lseek, 405 .release = seq_release_private 406 }; 407 408 struct field_desc { 409 const char *name; 410 unsigned int start; 411 unsigned int width; 412 }; 413 414 static void field_desc_show(struct seq_file *seq, u64 v, 415 const struct field_desc *p) 416 { 417 char buf[32]; 418 int line_size = 0; 419 420 while (p->name) { 421 u64 mask = (1ULL << p->width) - 1; 422 int len = scnprintf(buf, sizeof(buf), "%s: %llu", p->name, 423 ((unsigned long long)v >> p->start) & mask); 424 425 if (line_size + len >= 79) { 426 line_size = 8; 427 seq_puts(seq, "\n "); 428 } 429 seq_printf(seq, "%s ", buf); 430 line_size += len + 1; 431 p++; 432 } 433 seq_putc(seq, '\n'); 434 } 435 436 static struct field_desc tp_la0[] = { 437 { "RcfOpCodeOut", 60, 4 }, 438 { "State", 56, 4 }, 439 { "WcfState", 52, 4 }, 440 { "RcfOpcSrcOut", 50, 2 }, 441 { "CRxError", 49, 1 }, 442 { "ERxError", 48, 1 }, 443 { "SanityFailed", 47, 1 }, 444 { "SpuriousMsg", 46, 1 }, 445 { "FlushInputMsg", 45, 1 }, 446 { "FlushInputCpl", 44, 1 }, 447 { "RssUpBit", 43, 1 }, 448 { "RssFilterHit", 42, 1 }, 449 { "Tid", 32, 10 }, 450 { "InitTcb", 31, 1 }, 451 { "LineNumber", 24, 7 }, 452 { "Emsg", 23, 1 }, 453 { "EdataOut", 22, 1 }, 454 { "Cmsg", 21, 1 }, 455 { "CdataOut", 20, 1 }, 456 { "EreadPdu", 19, 1 }, 457 { "CreadPdu", 18, 1 }, 458 { "TunnelPkt", 17, 1 }, 459 { "RcfPeerFin", 16, 1 }, 460 { "RcfReasonOut", 12, 4 }, 461 { "TxCchannel", 10, 2 }, 462 { "RcfTxChannel", 8, 2 }, 463 { "RxEchannel", 6, 2 }, 464 { "RcfRxChannel", 5, 1 }, 465 { "RcfDataOutSrdy", 4, 1 }, 466 { "RxDvld", 3, 1 }, 467 { "RxOoDvld", 2, 1 }, 468 { "RxCongestion", 1, 1 }, 469 { "TxCongestion", 0, 1 }, 470 { NULL } 471 }; 472 473 static int tp_la_show(struct seq_file *seq, void *v, int idx) 474 { 475 const u64 *p = v; 476 477 field_desc_show(seq, *p, tp_la0); 478 return 0; 479 } 480 481 static int tp_la_show2(struct seq_file *seq, void *v, int idx) 482 { 483 const u64 *p = v; 484 485 if (idx) 486 seq_putc(seq, '\n'); 487 field_desc_show(seq, p[0], tp_la0); 488 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 489 field_desc_show(seq, p[1], tp_la0); 490 return 0; 491 } 492 493 static int tp_la_show3(struct seq_file *seq, void *v, int idx) 494 { 495 static struct field_desc tp_la1[] = { 496 { "CplCmdIn", 56, 8 }, 497 { "CplCmdOut", 48, 8 }, 498 { "ESynOut", 47, 1 }, 499 { "EAckOut", 46, 1 }, 500 { "EFinOut", 45, 1 }, 501 { "ERstOut", 44, 1 }, 502 { "SynIn", 43, 1 }, 503 { "AckIn", 42, 1 }, 504 { "FinIn", 41, 1 }, 505 { "RstIn", 40, 1 }, 506 { "DataIn", 39, 1 }, 507 { "DataInVld", 38, 1 }, 508 { "PadIn", 37, 1 }, 509 { "RxBufEmpty", 36, 1 }, 510 { "RxDdp", 35, 1 }, 511 { "RxFbCongestion", 34, 1 }, 512 { "TxFbCongestion", 33, 1 }, 513 { "TxPktSumSrdy", 32, 1 }, 514 { "RcfUlpType", 28, 4 }, 515 { "Eread", 27, 1 }, 516 { "Ebypass", 26, 1 }, 517 { "Esave", 25, 1 }, 518 { "Static0", 24, 1 }, 519 { "Cread", 23, 1 }, 520 { "Cbypass", 22, 1 }, 521 { "Csave", 21, 1 }, 522 { "CPktOut", 20, 1 }, 523 { "RxPagePoolFull", 18, 2 }, 524 { "RxLpbkPkt", 17, 1 }, 525 { "TxLpbkPkt", 16, 1 }, 526 { "RxVfValid", 15, 1 }, 527 { "SynLearned", 14, 1 }, 528 { "SetDelEntry", 13, 1 }, 529 { "SetInvEntry", 12, 1 }, 530 { "CpcmdDvld", 11, 1 }, 531 { "CpcmdSave", 10, 1 }, 532 { "RxPstructsFull", 8, 2 }, 533 { "EpcmdDvld", 7, 1 }, 534 { "EpcmdFlush", 6, 1 }, 535 { "EpcmdTrimPrefix", 5, 1 }, 536 { "EpcmdTrimPostfix", 4, 1 }, 537 { "ERssIp4Pkt", 3, 1 }, 538 { "ERssIp6Pkt", 2, 1 }, 539 { "ERssTcpUdpPkt", 1, 1 }, 540 { "ERssFceFipPkt", 0, 1 }, 541 { NULL } 542 }; 543 static struct field_desc tp_la2[] = { 544 { "CplCmdIn", 56, 8 }, 545 { "MpsVfVld", 55, 1 }, 546 { "MpsPf", 52, 3 }, 547 { "MpsVf", 44, 8 }, 548 { "SynIn", 43, 1 }, 549 { "AckIn", 42, 1 }, 550 { "FinIn", 41, 1 }, 551 { "RstIn", 40, 1 }, 552 { "DataIn", 39, 1 }, 553 { "DataInVld", 38, 1 }, 554 { "PadIn", 37, 1 }, 555 { "RxBufEmpty", 36, 1 }, 556 { "RxDdp", 35, 1 }, 557 { "RxFbCongestion", 34, 1 }, 558 { "TxFbCongestion", 33, 1 }, 559 { "TxPktSumSrdy", 32, 1 }, 560 { "RcfUlpType", 28, 4 }, 561 { "Eread", 27, 1 }, 562 { "Ebypass", 26, 1 }, 563 { "Esave", 25, 1 }, 564 { "Static0", 24, 1 }, 565 { "Cread", 23, 1 }, 566 { "Cbypass", 22, 1 }, 567 { "Csave", 21, 1 }, 568 { "CPktOut", 20, 1 }, 569 { "RxPagePoolFull", 18, 2 }, 570 { "RxLpbkPkt", 17, 1 }, 571 { "TxLpbkPkt", 16, 1 }, 572 { "RxVfValid", 15, 1 }, 573 { "SynLearned", 14, 1 }, 574 { "SetDelEntry", 13, 1 }, 575 { "SetInvEntry", 12, 1 }, 576 { "CpcmdDvld", 11, 1 }, 577 { "CpcmdSave", 10, 1 }, 578 { "RxPstructsFull", 8, 2 }, 579 { "EpcmdDvld", 7, 1 }, 580 { "EpcmdFlush", 6, 1 }, 581 { "EpcmdTrimPrefix", 5, 1 }, 582 { "EpcmdTrimPostfix", 4, 1 }, 583 { "ERssIp4Pkt", 3, 1 }, 584 { "ERssIp6Pkt", 2, 1 }, 585 { "ERssTcpUdpPkt", 1, 1 }, 586 { "ERssFceFipPkt", 0, 1 }, 587 { NULL } 588 }; 589 const u64 *p = v; 590 591 if (idx) 592 seq_putc(seq, '\n'); 593 field_desc_show(seq, p[0], tp_la0); 594 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 595 field_desc_show(seq, p[1], (p[0] & BIT(17)) ? tp_la2 : tp_la1); 596 return 0; 597 } 598 599 static int tp_la_open(struct inode *inode, struct file *file) 600 { 601 struct seq_tab *p; 602 struct adapter *adap = inode->i_private; 603 604 switch (DBGLAMODE_G(t4_read_reg(adap, TP_DBG_LA_CONFIG_A))) { 605 case 2: 606 p = seq_open_tab(file, TPLA_SIZE / 2, 2 * sizeof(u64), 0, 607 tp_la_show2); 608 break; 609 case 3: 610 p = seq_open_tab(file, TPLA_SIZE / 2, 2 * sizeof(u64), 0, 611 tp_la_show3); 612 break; 613 default: 614 p = seq_open_tab(file, TPLA_SIZE, sizeof(u64), 0, tp_la_show); 615 } 616 if (!p) 617 return -ENOMEM; 618 619 t4_tp_read_la(adap, (u64 *)p->data, NULL); 620 return 0; 621 } 622 623 static ssize_t tp_la_write(struct file *file, const char __user *buf, 624 size_t count, loff_t *pos) 625 { 626 int err; 627 char s[32]; 628 unsigned long val; 629 size_t size = min(sizeof(s) - 1, count); 630 struct adapter *adap = file_inode(file)->i_private; 631 632 if (copy_from_user(s, buf, size)) 633 return -EFAULT; 634 s[size] = '\0'; 635 err = kstrtoul(s, 0, &val); 636 if (err) 637 return err; 638 if (val > 0xffff) 639 return -EINVAL; 640 adap->params.tp.la_mask = val << 16; 641 t4_set_reg_field(adap, TP_DBG_LA_CONFIG_A, 0xffff0000U, 642 adap->params.tp.la_mask); 643 return count; 644 } 645 646 static const struct file_operations tp_la_fops = { 647 .owner = THIS_MODULE, 648 .open = tp_la_open, 649 .read = seq_read, 650 .llseek = seq_lseek, 651 .release = seq_release_private, 652 .write = tp_la_write 653 }; 654 655 static int ulprx_la_show(struct seq_file *seq, void *v, int idx) 656 { 657 const u32 *p = v; 658 659 if (v == SEQ_START_TOKEN) 660 seq_puts(seq, " Pcmd Type Message" 661 " Data\n"); 662 else 663 seq_printf(seq, "%08x%08x %4x %08x %08x%08x%08x%08x\n", 664 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 665 return 0; 666 } 667 668 static int ulprx_la_open(struct inode *inode, struct file *file) 669 { 670 struct seq_tab *p; 671 struct adapter *adap = inode->i_private; 672 673 p = seq_open_tab(file, ULPRX_LA_SIZE, 8 * sizeof(u32), 1, 674 ulprx_la_show); 675 if (!p) 676 return -ENOMEM; 677 678 t4_ulprx_read_la(adap, (u32 *)p->data); 679 return 0; 680 } 681 682 static const struct file_operations ulprx_la_fops = { 683 .owner = THIS_MODULE, 684 .open = ulprx_la_open, 685 .read = seq_read, 686 .llseek = seq_lseek, 687 .release = seq_release_private 688 }; 689 690 /* Show the PM memory stats. These stats include: 691 * 692 * TX: 693 * Read: memory read operation 694 * Write Bypass: cut-through 695 * Bypass + mem: cut-through and save copy 696 * 697 * RX: 698 * Read: memory read 699 * Write Bypass: cut-through 700 * Flush: payload trim or drop 701 */ 702 static int pm_stats_show(struct seq_file *seq, void *v) 703 { 704 static const char * const tx_pm_stats[] = { 705 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:" 706 }; 707 static const char * const rx_pm_stats[] = { 708 "Read:", "Write bypass:", "Write mem:", "Flush:" 709 }; 710 711 int i; 712 u32 tx_cnt[PM_NSTATS], rx_cnt[PM_NSTATS]; 713 u64 tx_cyc[PM_NSTATS], rx_cyc[PM_NSTATS]; 714 struct adapter *adap = seq->private; 715 716 t4_pmtx_get_stats(adap, tx_cnt, tx_cyc); 717 t4_pmrx_get_stats(adap, rx_cnt, rx_cyc); 718 719 seq_printf(seq, "%13s %10s %20s\n", " ", "Tx pcmds", "Tx bytes"); 720 for (i = 0; i < PM_NSTATS - 1; i++) 721 seq_printf(seq, "%-13s %10u %20llu\n", 722 tx_pm_stats[i], tx_cnt[i], tx_cyc[i]); 723 724 seq_printf(seq, "%13s %10s %20s\n", " ", "Rx pcmds", "Rx bytes"); 725 for (i = 0; i < PM_NSTATS - 1; i++) 726 seq_printf(seq, "%-13s %10u %20llu\n", 727 rx_pm_stats[i], rx_cnt[i], rx_cyc[i]); 728 return 0; 729 } 730 731 static int pm_stats_open(struct inode *inode, struct file *file) 732 { 733 return single_open(file, pm_stats_show, inode->i_private); 734 } 735 736 static ssize_t pm_stats_clear(struct file *file, const char __user *buf, 737 size_t count, loff_t *pos) 738 { 739 struct adapter *adap = file_inode(file)->i_private; 740 741 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, 0); 742 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, 0); 743 return count; 744 } 745 746 static const struct file_operations pm_stats_debugfs_fops = { 747 .owner = THIS_MODULE, 748 .open = pm_stats_open, 749 .read = seq_read, 750 .llseek = seq_lseek, 751 .release = single_release, 752 .write = pm_stats_clear 753 }; 754 755 static int tx_rate_show(struct seq_file *seq, void *v) 756 { 757 u64 nrate[NCHAN], orate[NCHAN]; 758 struct adapter *adap = seq->private; 759 760 t4_get_chan_txrate(adap, nrate, orate); 761 if (adap->params.arch.nchan == NCHAN) { 762 seq_puts(seq, " channel 0 channel 1 " 763 "channel 2 channel 3\n"); 764 seq_printf(seq, "NIC B/s: %10llu %10llu %10llu %10llu\n", 765 (unsigned long long)nrate[0], 766 (unsigned long long)nrate[1], 767 (unsigned long long)nrate[2], 768 (unsigned long long)nrate[3]); 769 seq_printf(seq, "Offload B/s: %10llu %10llu %10llu %10llu\n", 770 (unsigned long long)orate[0], 771 (unsigned long long)orate[1], 772 (unsigned long long)orate[2], 773 (unsigned long long)orate[3]); 774 } else { 775 seq_puts(seq, " channel 0 channel 1\n"); 776 seq_printf(seq, "NIC B/s: %10llu %10llu\n", 777 (unsigned long long)nrate[0], 778 (unsigned long long)nrate[1]); 779 seq_printf(seq, "Offload B/s: %10llu %10llu\n", 780 (unsigned long long)orate[0], 781 (unsigned long long)orate[1]); 782 } 783 return 0; 784 } 785 786 DEFINE_SIMPLE_DEBUGFS_FILE(tx_rate); 787 788 static int cctrl_tbl_show(struct seq_file *seq, void *v) 789 { 790 static const char * const dec_fac[] = { 791 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 792 "0.9375" }; 793 794 int i; 795 u16 (*incr)[NCCTRL_WIN]; 796 struct adapter *adap = seq->private; 797 798 incr = kmalloc(sizeof(*incr) * NMTUS, GFP_KERNEL); 799 if (!incr) 800 return -ENOMEM; 801 802 t4_read_cong_tbl(adap, incr); 803 804 for (i = 0; i < NCCTRL_WIN; ++i) { 805 seq_printf(seq, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 806 incr[0][i], incr[1][i], incr[2][i], incr[3][i], 807 incr[4][i], incr[5][i], incr[6][i], incr[7][i]); 808 seq_printf(seq, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 809 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 810 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 811 adap->params.a_wnd[i], 812 dec_fac[adap->params.b_wnd[i]]); 813 } 814 815 kfree(incr); 816 return 0; 817 } 818 819 DEFINE_SIMPLE_DEBUGFS_FILE(cctrl_tbl); 820 821 /* Format a value in a unit that differs from the value's native unit by the 822 * given factor. 823 */ 824 static char *unit_conv(char *buf, size_t len, unsigned int val, 825 unsigned int factor) 826 { 827 unsigned int rem = val % factor; 828 829 if (rem == 0) { 830 snprintf(buf, len, "%u", val / factor); 831 } else { 832 while (rem % 10 == 0) 833 rem /= 10; 834 snprintf(buf, len, "%u.%u", val / factor, rem); 835 } 836 return buf; 837 } 838 839 static int clk_show(struct seq_file *seq, void *v) 840 { 841 char buf[32]; 842 struct adapter *adap = seq->private; 843 unsigned int cclk_ps = 1000000000 / adap->params.vpd.cclk; /* in ps */ 844 u32 res = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); 845 unsigned int tre = TIMERRESOLUTION_G(res); 846 unsigned int dack_re = DELAYEDACKRESOLUTION_G(res); 847 unsigned long long tp_tick_us = (cclk_ps << tre) / 1000000; /* in us */ 848 849 seq_printf(seq, "Core clock period: %s ns\n", 850 unit_conv(buf, sizeof(buf), cclk_ps, 1000)); 851 seq_printf(seq, "TP timer tick: %s us\n", 852 unit_conv(buf, sizeof(buf), (cclk_ps << tre), 1000000)); 853 seq_printf(seq, "TCP timestamp tick: %s us\n", 854 unit_conv(buf, sizeof(buf), 855 (cclk_ps << TIMESTAMPRESOLUTION_G(res)), 1000000)); 856 seq_printf(seq, "DACK tick: %s us\n", 857 unit_conv(buf, sizeof(buf), (cclk_ps << dack_re), 1000000)); 858 seq_printf(seq, "DACK timer: %u us\n", 859 ((cclk_ps << dack_re) / 1000000) * 860 t4_read_reg(adap, TP_DACK_TIMER_A)); 861 seq_printf(seq, "Retransmit min: %llu us\n", 862 tp_tick_us * t4_read_reg(adap, TP_RXT_MIN_A)); 863 seq_printf(seq, "Retransmit max: %llu us\n", 864 tp_tick_us * t4_read_reg(adap, TP_RXT_MAX_A)); 865 seq_printf(seq, "Persist timer min: %llu us\n", 866 tp_tick_us * t4_read_reg(adap, TP_PERS_MIN_A)); 867 seq_printf(seq, "Persist timer max: %llu us\n", 868 tp_tick_us * t4_read_reg(adap, TP_PERS_MAX_A)); 869 seq_printf(seq, "Keepalive idle timer: %llu us\n", 870 tp_tick_us * t4_read_reg(adap, TP_KEEP_IDLE_A)); 871 seq_printf(seq, "Keepalive interval: %llu us\n", 872 tp_tick_us * t4_read_reg(adap, TP_KEEP_INTVL_A)); 873 seq_printf(seq, "Initial SRTT: %llu us\n", 874 tp_tick_us * INITSRTT_G(t4_read_reg(adap, TP_INIT_SRTT_A))); 875 seq_printf(seq, "FINWAIT2 timer: %llu us\n", 876 tp_tick_us * t4_read_reg(adap, TP_FINWAIT2_TIMER_A)); 877 878 return 0; 879 } 880 881 DEFINE_SIMPLE_DEBUGFS_FILE(clk); 882 883 /* Firmware Device Log dump. */ 884 static const char * const devlog_level_strings[] = { 885 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 886 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 887 [FW_DEVLOG_LEVEL_ERR] = "ERR", 888 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 889 [FW_DEVLOG_LEVEL_INFO] = "INFO", 890 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 891 }; 892 893 static const char * const devlog_facility_strings[] = { 894 [FW_DEVLOG_FACILITY_CORE] = "CORE", 895 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 896 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 897 [FW_DEVLOG_FACILITY_RES] = "RES", 898 [FW_DEVLOG_FACILITY_HW] = "HW", 899 [FW_DEVLOG_FACILITY_FLR] = "FLR", 900 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 901 [FW_DEVLOG_FACILITY_PHY] = "PHY", 902 [FW_DEVLOG_FACILITY_MAC] = "MAC", 903 [FW_DEVLOG_FACILITY_PORT] = "PORT", 904 [FW_DEVLOG_FACILITY_VI] = "VI", 905 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 906 [FW_DEVLOG_FACILITY_ACL] = "ACL", 907 [FW_DEVLOG_FACILITY_TM] = "TM", 908 [FW_DEVLOG_FACILITY_QFC] = "QFC", 909 [FW_DEVLOG_FACILITY_DCB] = "DCB", 910 [FW_DEVLOG_FACILITY_ETH] = "ETH", 911 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 912 [FW_DEVLOG_FACILITY_RI] = "RI", 913 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 914 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 915 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 916 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE" 917 }; 918 919 /* Information gathered by Device Log Open routine for the display routine. 920 */ 921 struct devlog_info { 922 unsigned int nentries; /* number of entries in log[] */ 923 unsigned int first; /* first [temporal] entry in log[] */ 924 struct fw_devlog_e log[0]; /* Firmware Device Log */ 925 }; 926 927 /* Dump a Firmaware Device Log entry. 928 */ 929 static int devlog_show(struct seq_file *seq, void *v) 930 { 931 if (v == SEQ_START_TOKEN) 932 seq_printf(seq, "%10s %15s %8s %8s %s\n", 933 "Seq#", "Tstamp", "Level", "Facility", "Message"); 934 else { 935 struct devlog_info *dinfo = seq->private; 936 int fidx = (uintptr_t)v - 2; 937 unsigned long index; 938 struct fw_devlog_e *e; 939 940 /* Get a pointer to the log entry to display. Skip unused log 941 * entries. 942 */ 943 index = dinfo->first + fidx; 944 if (index >= dinfo->nentries) 945 index -= dinfo->nentries; 946 e = &dinfo->log[index]; 947 if (e->timestamp == 0) 948 return 0; 949 950 /* Print the message. This depends on the firmware using 951 * exactly the same formating strings as the kernel so we may 952 * eventually have to put a format interpreter in here ... 953 */ 954 seq_printf(seq, "%10d %15llu %8s %8s ", 955 be32_to_cpu(e->seqno), 956 be64_to_cpu(e->timestamp), 957 (e->level < ARRAY_SIZE(devlog_level_strings) 958 ? devlog_level_strings[e->level] 959 : "UNKNOWN"), 960 (e->facility < ARRAY_SIZE(devlog_facility_strings) 961 ? devlog_facility_strings[e->facility] 962 : "UNKNOWN")); 963 seq_printf(seq, e->fmt, 964 be32_to_cpu(e->params[0]), 965 be32_to_cpu(e->params[1]), 966 be32_to_cpu(e->params[2]), 967 be32_to_cpu(e->params[3]), 968 be32_to_cpu(e->params[4]), 969 be32_to_cpu(e->params[5]), 970 be32_to_cpu(e->params[6]), 971 be32_to_cpu(e->params[7])); 972 } 973 return 0; 974 } 975 976 /* Sequential File Operations for Device Log. 977 */ 978 static inline void *devlog_get_idx(struct devlog_info *dinfo, loff_t pos) 979 { 980 if (pos > dinfo->nentries) 981 return NULL; 982 983 return (void *)(uintptr_t)(pos + 1); 984 } 985 986 static void *devlog_start(struct seq_file *seq, loff_t *pos) 987 { 988 struct devlog_info *dinfo = seq->private; 989 990 return (*pos 991 ? devlog_get_idx(dinfo, *pos) 992 : SEQ_START_TOKEN); 993 } 994 995 static void *devlog_next(struct seq_file *seq, void *v, loff_t *pos) 996 { 997 struct devlog_info *dinfo = seq->private; 998 999 (*pos)++; 1000 return devlog_get_idx(dinfo, *pos); 1001 } 1002 1003 static void devlog_stop(struct seq_file *seq, void *v) 1004 { 1005 } 1006 1007 static const struct seq_operations devlog_seq_ops = { 1008 .start = devlog_start, 1009 .next = devlog_next, 1010 .stop = devlog_stop, 1011 .show = devlog_show 1012 }; 1013 1014 /* Set up for reading the firmware's device log. We read the entire log here 1015 * and then display it incrementally in devlog_show(). 1016 */ 1017 static int devlog_open(struct inode *inode, struct file *file) 1018 { 1019 struct adapter *adap = inode->i_private; 1020 struct devlog_params *dparams = &adap->params.devlog; 1021 struct devlog_info *dinfo; 1022 unsigned int index; 1023 u32 fseqno; 1024 int ret; 1025 1026 /* If we don't know where the log is we can't do anything. 1027 */ 1028 if (dparams->start == 0) 1029 return -ENXIO; 1030 1031 /* Allocate the space to read in the firmware's device log and set up 1032 * for the iterated call to our display function. 1033 */ 1034 dinfo = __seq_open_private(file, &devlog_seq_ops, 1035 sizeof(*dinfo) + dparams->size); 1036 if (!dinfo) 1037 return -ENOMEM; 1038 1039 /* Record the basic log buffer information and read in the raw log. 1040 */ 1041 dinfo->nentries = (dparams->size / sizeof(struct fw_devlog_e)); 1042 dinfo->first = 0; 1043 spin_lock(&adap->win0_lock); 1044 ret = t4_memory_rw(adap, adap->params.drv_memwin, dparams->memtype, 1045 dparams->start, dparams->size, (__be32 *)dinfo->log, 1046 T4_MEMORY_READ); 1047 spin_unlock(&adap->win0_lock); 1048 if (ret) { 1049 seq_release_private(inode, file); 1050 return ret; 1051 } 1052 1053 /* Find the earliest (lowest Sequence Number) log entry in the 1054 * circular Device Log. 1055 */ 1056 for (fseqno = ~((u32)0), index = 0; index < dinfo->nentries; index++) { 1057 struct fw_devlog_e *e = &dinfo->log[index]; 1058 __u32 seqno; 1059 1060 if (e->timestamp == 0) 1061 continue; 1062 1063 seqno = be32_to_cpu(e->seqno); 1064 if (seqno < fseqno) { 1065 fseqno = seqno; 1066 dinfo->first = index; 1067 } 1068 } 1069 return 0; 1070 } 1071 1072 static const struct file_operations devlog_fops = { 1073 .owner = THIS_MODULE, 1074 .open = devlog_open, 1075 .read = seq_read, 1076 .llseek = seq_lseek, 1077 .release = seq_release_private 1078 }; 1079 1080 static int mbox_show(struct seq_file *seq, void *v) 1081 { 1082 static const char * const owner[] = { "none", "FW", "driver", 1083 "unknown" }; 1084 1085 int i; 1086 unsigned int mbox = (uintptr_t)seq->private & 7; 1087 struct adapter *adap = seq->private - mbox; 1088 void __iomem *addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A); 1089 unsigned int ctrl_reg = (is_t4(adap->params.chip) 1090 ? CIM_PF_MAILBOX_CTRL_A 1091 : CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A); 1092 void __iomem *ctrl = adap->regs + PF_REG(mbox, ctrl_reg); 1093 1094 i = MBOWNER_G(readl(ctrl)); 1095 seq_printf(seq, "mailbox owned by %s\n\n", owner[i]); 1096 1097 for (i = 0; i < MBOX_LEN; i += 8) 1098 seq_printf(seq, "%016llx\n", 1099 (unsigned long long)readq(addr + i)); 1100 return 0; 1101 } 1102 1103 static int mbox_open(struct inode *inode, struct file *file) 1104 { 1105 return single_open(file, mbox_show, inode->i_private); 1106 } 1107 1108 static ssize_t mbox_write(struct file *file, const char __user *buf, 1109 size_t count, loff_t *pos) 1110 { 1111 int i; 1112 char c = '\n', s[256]; 1113 unsigned long long data[8]; 1114 const struct inode *ino; 1115 unsigned int mbox; 1116 struct adapter *adap; 1117 void __iomem *addr; 1118 void __iomem *ctrl; 1119 1120 if (count > sizeof(s) - 1 || !count) 1121 return -EINVAL; 1122 if (copy_from_user(s, buf, count)) 1123 return -EFAULT; 1124 s[count] = '\0'; 1125 1126 if (sscanf(s, "%llx %llx %llx %llx %llx %llx %llx %llx%c", &data[0], 1127 &data[1], &data[2], &data[3], &data[4], &data[5], &data[6], 1128 &data[7], &c) < 8 || c != '\n') 1129 return -EINVAL; 1130 1131 ino = file_inode(file); 1132 mbox = (uintptr_t)ino->i_private & 7; 1133 adap = ino->i_private - mbox; 1134 addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A); 1135 ctrl = addr + MBOX_LEN; 1136 1137 if (MBOWNER_G(readl(ctrl)) != X_MBOWNER_PL) 1138 return -EBUSY; 1139 1140 for (i = 0; i < 8; i++) 1141 writeq(data[i], addr + 8 * i); 1142 1143 writel(MBMSGVALID_F | MBOWNER_V(X_MBOWNER_FW), ctrl); 1144 return count; 1145 } 1146 1147 static const struct file_operations mbox_debugfs_fops = { 1148 .owner = THIS_MODULE, 1149 .open = mbox_open, 1150 .read = seq_read, 1151 .llseek = seq_lseek, 1152 .release = single_release, 1153 .write = mbox_write 1154 }; 1155 1156 static ssize_t flash_read(struct file *file, char __user *buf, size_t count, 1157 loff_t *ppos) 1158 { 1159 loff_t pos = *ppos; 1160 loff_t avail = file_inode(file)->i_size; 1161 struct adapter *adap = file->private_data; 1162 1163 if (pos < 0) 1164 return -EINVAL; 1165 if (pos >= avail) 1166 return 0; 1167 if (count > avail - pos) 1168 count = avail - pos; 1169 1170 while (count) { 1171 size_t len; 1172 int ret, ofst; 1173 u8 data[256]; 1174 1175 ofst = pos & 3; 1176 len = min(count + ofst, sizeof(data)); 1177 ret = t4_read_flash(adap, pos - ofst, (len + 3) / 4, 1178 (u32 *)data, 1); 1179 if (ret) 1180 return ret; 1181 1182 len -= ofst; 1183 if (copy_to_user(buf, data + ofst, len)) 1184 return -EFAULT; 1185 1186 buf += len; 1187 pos += len; 1188 count -= len; 1189 } 1190 count = pos - *ppos; 1191 *ppos = pos; 1192 return count; 1193 } 1194 1195 static const struct file_operations flash_debugfs_fops = { 1196 .owner = THIS_MODULE, 1197 .open = mem_open, 1198 .read = flash_read, 1199 }; 1200 1201 static inline void tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask) 1202 { 1203 *mask = x | y; 1204 y = (__force u64)cpu_to_be64(y); 1205 memcpy(addr, (char *)&y + 2, ETH_ALEN); 1206 } 1207 1208 static int mps_tcam_show(struct seq_file *seq, void *v) 1209 { 1210 struct adapter *adap = seq->private; 1211 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip); 1212 1213 if (v == SEQ_START_TOKEN) { 1214 if (adap->params.arch.mps_rplc_size > 128) 1215 seq_puts(seq, "Idx Ethernet address Mask " 1216 "Vld Ports PF VF " 1217 "Replication " 1218 " P0 P1 P2 P3 ML\n"); 1219 else 1220 seq_puts(seq, "Idx Ethernet address Mask " 1221 "Vld Ports PF VF Replication" 1222 " P0 P1 P2 P3 ML\n"); 1223 } else { 1224 u64 mask; 1225 u8 addr[ETH_ALEN]; 1226 bool replicate; 1227 unsigned int idx = (uintptr_t)v - 2; 1228 u64 tcamy, tcamx, val; 1229 u32 cls_lo, cls_hi, ctl; 1230 u32 rplc[8] = {0}; 1231 1232 if (chip_ver > CHELSIO_T5) { 1233 /* CtlCmdType - 0: Read, 1: Write 1234 * CtlTcamSel - 0: TCAM0, 1: TCAM1 1235 * CtlXYBitSel- 0: Y bit, 1: X bit 1236 */ 1237 1238 /* Read tcamy */ 1239 ctl = CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0); 1240 if (idx < 256) 1241 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0); 1242 else 1243 ctl |= CTLTCAMINDEX_V(idx - 256) | 1244 CTLTCAMSEL_V(1); 1245 t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1246 val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A); 1247 tcamy = DMACH_G(val) << 32; 1248 tcamy |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A); 1249 1250 /* Read tcamx. Change the control param */ 1251 ctl |= CTLXYBITSEL_V(1); 1252 t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1253 val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A); 1254 tcamx = DMACH_G(val) << 32; 1255 tcamx |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A); 1256 } else { 1257 tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx)); 1258 tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx)); 1259 } 1260 1261 cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx)); 1262 cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx)); 1263 1264 if (tcamx & tcamy) { 1265 seq_printf(seq, "%3u -\n", idx); 1266 goto out; 1267 } 1268 1269 rplc[0] = rplc[1] = rplc[2] = rplc[3] = 0; 1270 if (chip_ver > CHELSIO_T5) 1271 replicate = (cls_lo & T6_REPLICATE_F); 1272 else 1273 replicate = (cls_lo & REPLICATE_F); 1274 1275 if (replicate) { 1276 struct fw_ldst_cmd ldst_cmd; 1277 int ret; 1278 struct fw_ldst_mps_rplc mps_rplc; 1279 u32 ldst_addrspc; 1280 1281 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 1282 ldst_addrspc = 1283 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS); 1284 ldst_cmd.op_to_addrspace = 1285 htonl(FW_CMD_OP_V(FW_LDST_CMD) | 1286 FW_CMD_REQUEST_F | 1287 FW_CMD_READ_F | 1288 ldst_addrspc); 1289 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd)); 1290 ldst_cmd.u.mps.rplc.fid_idx = 1291 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) | 1292 FW_LDST_CMD_IDX_V(idx)); 1293 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, 1294 sizeof(ldst_cmd), &ldst_cmd); 1295 if (ret) 1296 dev_warn(adap->pdev_dev, "Can't read MPS " 1297 "replication map for idx %d: %d\n", 1298 idx, -ret); 1299 else { 1300 mps_rplc = ldst_cmd.u.mps.rplc; 1301 rplc[0] = ntohl(mps_rplc.rplc31_0); 1302 rplc[1] = ntohl(mps_rplc.rplc63_32); 1303 rplc[2] = ntohl(mps_rplc.rplc95_64); 1304 rplc[3] = ntohl(mps_rplc.rplc127_96); 1305 if (adap->params.arch.mps_rplc_size > 128) { 1306 rplc[4] = ntohl(mps_rplc.rplc159_128); 1307 rplc[5] = ntohl(mps_rplc.rplc191_160); 1308 rplc[6] = ntohl(mps_rplc.rplc223_192); 1309 rplc[7] = ntohl(mps_rplc.rplc255_224); 1310 } 1311 } 1312 } 1313 1314 tcamxy2valmask(tcamx, tcamy, addr, &mask); 1315 if (chip_ver > CHELSIO_T5) 1316 seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x " 1317 "%012llx%3c %#x%4u%4d", 1318 idx, addr[0], addr[1], addr[2], addr[3], 1319 addr[4], addr[5], (unsigned long long)mask, 1320 (cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N', 1321 PORTMAP_G(cls_hi), 1322 T6_PF_G(cls_lo), 1323 (cls_lo & T6_VF_VALID_F) ? 1324 T6_VF_G(cls_lo) : -1); 1325 else 1326 seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x " 1327 "%012llx%3c %#x%4u%4d", 1328 idx, addr[0], addr[1], addr[2], addr[3], 1329 addr[4], addr[5], (unsigned long long)mask, 1330 (cls_lo & SRAM_VLD_F) ? 'Y' : 'N', 1331 PORTMAP_G(cls_hi), 1332 PF_G(cls_lo), 1333 (cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1); 1334 1335 if (replicate) { 1336 if (adap->params.arch.mps_rplc_size > 128) 1337 seq_printf(seq, " %08x %08x %08x %08x " 1338 "%08x %08x %08x %08x", 1339 rplc[7], rplc[6], rplc[5], rplc[4], 1340 rplc[3], rplc[2], rplc[1], rplc[0]); 1341 else 1342 seq_printf(seq, " %08x %08x %08x %08x", 1343 rplc[3], rplc[2], rplc[1], rplc[0]); 1344 } else { 1345 if (adap->params.arch.mps_rplc_size > 128) 1346 seq_printf(seq, "%72c", ' '); 1347 else 1348 seq_printf(seq, "%36c", ' '); 1349 } 1350 1351 if (chip_ver > CHELSIO_T5) 1352 seq_printf(seq, "%4u%3u%3u%3u %#x\n", 1353 T6_SRAM_PRIO0_G(cls_lo), 1354 T6_SRAM_PRIO1_G(cls_lo), 1355 T6_SRAM_PRIO2_G(cls_lo), 1356 T6_SRAM_PRIO3_G(cls_lo), 1357 (cls_lo >> T6_MULTILISTEN0_S) & 0xf); 1358 else 1359 seq_printf(seq, "%4u%3u%3u%3u %#x\n", 1360 SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo), 1361 SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo), 1362 (cls_lo >> MULTILISTEN0_S) & 0xf); 1363 } 1364 out: return 0; 1365 } 1366 1367 static inline void *mps_tcam_get_idx(struct seq_file *seq, loff_t pos) 1368 { 1369 struct adapter *adap = seq->private; 1370 int max_mac_addr = is_t4(adap->params.chip) ? 1371 NUM_MPS_CLS_SRAM_L_INSTANCES : 1372 NUM_MPS_T5_CLS_SRAM_L_INSTANCES; 1373 return ((pos <= max_mac_addr) ? (void *)(uintptr_t)(pos + 1) : NULL); 1374 } 1375 1376 static void *mps_tcam_start(struct seq_file *seq, loff_t *pos) 1377 { 1378 return *pos ? mps_tcam_get_idx(seq, *pos) : SEQ_START_TOKEN; 1379 } 1380 1381 static void *mps_tcam_next(struct seq_file *seq, void *v, loff_t *pos) 1382 { 1383 ++*pos; 1384 return mps_tcam_get_idx(seq, *pos); 1385 } 1386 1387 static void mps_tcam_stop(struct seq_file *seq, void *v) 1388 { 1389 } 1390 1391 static const struct seq_operations mps_tcam_seq_ops = { 1392 .start = mps_tcam_start, 1393 .next = mps_tcam_next, 1394 .stop = mps_tcam_stop, 1395 .show = mps_tcam_show 1396 }; 1397 1398 static int mps_tcam_open(struct inode *inode, struct file *file) 1399 { 1400 int res = seq_open(file, &mps_tcam_seq_ops); 1401 1402 if (!res) { 1403 struct seq_file *seq = file->private_data; 1404 1405 seq->private = inode->i_private; 1406 } 1407 return res; 1408 } 1409 1410 static const struct file_operations mps_tcam_debugfs_fops = { 1411 .owner = THIS_MODULE, 1412 .open = mps_tcam_open, 1413 .read = seq_read, 1414 .llseek = seq_lseek, 1415 .release = seq_release, 1416 }; 1417 1418 /* Display various sensor information. 1419 */ 1420 static int sensors_show(struct seq_file *seq, void *v) 1421 { 1422 struct adapter *adap = seq->private; 1423 u32 param[7], val[7]; 1424 int ret; 1425 1426 /* Note that if the sensors haven't been initialized and turned on 1427 * we'll get values of 0, so treat those as "<unknown>" ... 1428 */ 1429 param[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 1430 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DIAG) | 1431 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_DIAG_TMP)); 1432 param[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 1433 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DIAG) | 1434 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_DIAG_VDD)); 1435 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 1436 param, val); 1437 1438 if (ret < 0 || val[0] == 0) 1439 seq_puts(seq, "Temperature: <unknown>\n"); 1440 else 1441 seq_printf(seq, "Temperature: %dC\n", val[0]); 1442 1443 if (ret < 0 || val[1] == 0) 1444 seq_puts(seq, "Core VDD: <unknown>\n"); 1445 else 1446 seq_printf(seq, "Core VDD: %dmV\n", val[1]); 1447 1448 return 0; 1449 } 1450 1451 DEFINE_SIMPLE_DEBUGFS_FILE(sensors); 1452 1453 #if IS_ENABLED(CONFIG_IPV6) 1454 static int clip_tbl_open(struct inode *inode, struct file *file) 1455 { 1456 return single_open(file, clip_tbl_show, inode->i_private); 1457 } 1458 1459 static const struct file_operations clip_tbl_debugfs_fops = { 1460 .owner = THIS_MODULE, 1461 .open = clip_tbl_open, 1462 .read = seq_read, 1463 .llseek = seq_lseek, 1464 .release = single_release 1465 }; 1466 #endif 1467 1468 /*RSS Table. 1469 */ 1470 1471 static int rss_show(struct seq_file *seq, void *v, int idx) 1472 { 1473 u16 *entry = v; 1474 1475 seq_printf(seq, "%4d: %4u %4u %4u %4u %4u %4u %4u %4u\n", 1476 idx * 8, entry[0], entry[1], entry[2], entry[3], entry[4], 1477 entry[5], entry[6], entry[7]); 1478 return 0; 1479 } 1480 1481 static int rss_open(struct inode *inode, struct file *file) 1482 { 1483 int ret; 1484 struct seq_tab *p; 1485 struct adapter *adap = inode->i_private; 1486 1487 p = seq_open_tab(file, RSS_NENTRIES / 8, 8 * sizeof(u16), 0, rss_show); 1488 if (!p) 1489 return -ENOMEM; 1490 1491 ret = t4_read_rss(adap, (u16 *)p->data); 1492 if (ret) 1493 seq_release_private(inode, file); 1494 1495 return ret; 1496 } 1497 1498 static const struct file_operations rss_debugfs_fops = { 1499 .owner = THIS_MODULE, 1500 .open = rss_open, 1501 .read = seq_read, 1502 .llseek = seq_lseek, 1503 .release = seq_release_private 1504 }; 1505 1506 /* RSS Configuration. 1507 */ 1508 1509 /* Small utility function to return the strings "yes" or "no" if the supplied 1510 * argument is non-zero. 1511 */ 1512 static const char *yesno(int x) 1513 { 1514 static const char *yes = "yes"; 1515 static const char *no = "no"; 1516 1517 return x ? yes : no; 1518 } 1519 1520 static int rss_config_show(struct seq_file *seq, void *v) 1521 { 1522 struct adapter *adapter = seq->private; 1523 static const char * const keymode[] = { 1524 "global", 1525 "global and per-VF scramble", 1526 "per-PF and per-VF scramble", 1527 "per-VF and per-VF scramble", 1528 }; 1529 u32 rssconf; 1530 1531 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_A); 1532 seq_printf(seq, "TP_RSS_CONFIG: %#x\n", rssconf); 1533 seq_printf(seq, " Tnl4TupEnIpv6: %3s\n", yesno(rssconf & 1534 TNL4TUPENIPV6_F)); 1535 seq_printf(seq, " Tnl2TupEnIpv6: %3s\n", yesno(rssconf & 1536 TNL2TUPENIPV6_F)); 1537 seq_printf(seq, " Tnl4TupEnIpv4: %3s\n", yesno(rssconf & 1538 TNL4TUPENIPV4_F)); 1539 seq_printf(seq, " Tnl2TupEnIpv4: %3s\n", yesno(rssconf & 1540 TNL2TUPENIPV4_F)); 1541 seq_printf(seq, " TnlTcpSel: %3s\n", yesno(rssconf & TNLTCPSEL_F)); 1542 seq_printf(seq, " TnlIp6Sel: %3s\n", yesno(rssconf & TNLIP6SEL_F)); 1543 seq_printf(seq, " TnlVrtSel: %3s\n", yesno(rssconf & TNLVRTSEL_F)); 1544 seq_printf(seq, " TnlMapEn: %3s\n", yesno(rssconf & TNLMAPEN_F)); 1545 seq_printf(seq, " OfdHashSave: %3s\n", yesno(rssconf & 1546 OFDHASHSAVE_F)); 1547 seq_printf(seq, " OfdVrtSel: %3s\n", yesno(rssconf & OFDVRTSEL_F)); 1548 seq_printf(seq, " OfdMapEn: %3s\n", yesno(rssconf & OFDMAPEN_F)); 1549 seq_printf(seq, " OfdLkpEn: %3s\n", yesno(rssconf & OFDLKPEN_F)); 1550 seq_printf(seq, " Syn4TupEnIpv6: %3s\n", yesno(rssconf & 1551 SYN4TUPENIPV6_F)); 1552 seq_printf(seq, " Syn2TupEnIpv6: %3s\n", yesno(rssconf & 1553 SYN2TUPENIPV6_F)); 1554 seq_printf(seq, " Syn4TupEnIpv4: %3s\n", yesno(rssconf & 1555 SYN4TUPENIPV4_F)); 1556 seq_printf(seq, " Syn2TupEnIpv4: %3s\n", yesno(rssconf & 1557 SYN2TUPENIPV4_F)); 1558 seq_printf(seq, " Syn4TupEnIpv6: %3s\n", yesno(rssconf & 1559 SYN4TUPENIPV6_F)); 1560 seq_printf(seq, " SynIp6Sel: %3s\n", yesno(rssconf & SYNIP6SEL_F)); 1561 seq_printf(seq, " SynVrt6Sel: %3s\n", yesno(rssconf & SYNVRTSEL_F)); 1562 seq_printf(seq, " SynMapEn: %3s\n", yesno(rssconf & SYNMAPEN_F)); 1563 seq_printf(seq, " SynLkpEn: %3s\n", yesno(rssconf & SYNLKPEN_F)); 1564 seq_printf(seq, " ChnEn: %3s\n", yesno(rssconf & 1565 CHANNELENABLE_F)); 1566 seq_printf(seq, " PrtEn: %3s\n", yesno(rssconf & 1567 PORTENABLE_F)); 1568 seq_printf(seq, " TnlAllLkp: %3s\n", yesno(rssconf & 1569 TNLALLLOOKUP_F)); 1570 seq_printf(seq, " VrtEn: %3s\n", yesno(rssconf & 1571 VIRTENABLE_F)); 1572 seq_printf(seq, " CngEn: %3s\n", yesno(rssconf & 1573 CONGESTIONENABLE_F)); 1574 seq_printf(seq, " HashToeplitz: %3s\n", yesno(rssconf & 1575 HASHTOEPLITZ_F)); 1576 seq_printf(seq, " Udp4En: %3s\n", yesno(rssconf & UDPENABLE_F)); 1577 seq_printf(seq, " Disable: %3s\n", yesno(rssconf & DISABLE_F)); 1578 1579 seq_puts(seq, "\n"); 1580 1581 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_TNL_A); 1582 seq_printf(seq, "TP_RSS_CONFIG_TNL: %#x\n", rssconf); 1583 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf)); 1584 seq_printf(seq, " MaskFilter: %3d\n", MASKFILTER_G(rssconf)); 1585 if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) { 1586 seq_printf(seq, " HashAll: %3s\n", 1587 yesno(rssconf & HASHALL_F)); 1588 seq_printf(seq, " HashEth: %3s\n", 1589 yesno(rssconf & HASHETH_F)); 1590 } 1591 seq_printf(seq, " UseWireCh: %3s\n", yesno(rssconf & USEWIRECH_F)); 1592 1593 seq_puts(seq, "\n"); 1594 1595 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_OFD_A); 1596 seq_printf(seq, "TP_RSS_CONFIG_OFD: %#x\n", rssconf); 1597 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf)); 1598 seq_printf(seq, " RRCplMapEn: %3s\n", yesno(rssconf & 1599 RRCPLMAPEN_F)); 1600 seq_printf(seq, " RRCplQueWidth: %3d\n", RRCPLQUEWIDTH_G(rssconf)); 1601 1602 seq_puts(seq, "\n"); 1603 1604 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_SYN_A); 1605 seq_printf(seq, "TP_RSS_CONFIG_SYN: %#x\n", rssconf); 1606 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf)); 1607 seq_printf(seq, " UseWireCh: %3s\n", yesno(rssconf & USEWIRECH_F)); 1608 1609 seq_puts(seq, "\n"); 1610 1611 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A); 1612 seq_printf(seq, "TP_RSS_CONFIG_VRT: %#x\n", rssconf); 1613 if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) { 1614 seq_printf(seq, " KeyWrAddrX: %3d\n", 1615 KEYWRADDRX_G(rssconf)); 1616 seq_printf(seq, " KeyExtend: %3s\n", 1617 yesno(rssconf & KEYEXTEND_F)); 1618 } 1619 seq_printf(seq, " VfRdRg: %3s\n", yesno(rssconf & VFRDRG_F)); 1620 seq_printf(seq, " VfRdEn: %3s\n", yesno(rssconf & VFRDEN_F)); 1621 seq_printf(seq, " VfPerrEn: %3s\n", yesno(rssconf & VFPERREN_F)); 1622 seq_printf(seq, " KeyPerrEn: %3s\n", yesno(rssconf & KEYPERREN_F)); 1623 seq_printf(seq, " DisVfVlan: %3s\n", yesno(rssconf & 1624 DISABLEVLAN_F)); 1625 seq_printf(seq, " EnUpSwt: %3s\n", yesno(rssconf & ENABLEUP0_F)); 1626 seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf)); 1627 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) 1628 seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf)); 1629 else 1630 seq_printf(seq, " VfWrAddr: %3d\n", 1631 T6_VFWRADDR_G(rssconf)); 1632 seq_printf(seq, " KeyMode: %s\n", keymode[KEYMODE_G(rssconf)]); 1633 seq_printf(seq, " VfWrEn: %3s\n", yesno(rssconf & VFWREN_F)); 1634 seq_printf(seq, " KeyWrEn: %3s\n", yesno(rssconf & KEYWREN_F)); 1635 seq_printf(seq, " KeyWrAddr: %3d\n", KEYWRADDR_G(rssconf)); 1636 1637 seq_puts(seq, "\n"); 1638 1639 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_CNG_A); 1640 seq_printf(seq, "TP_RSS_CONFIG_CNG: %#x\n", rssconf); 1641 seq_printf(seq, " ChnCount3: %3s\n", yesno(rssconf & CHNCOUNT3_F)); 1642 seq_printf(seq, " ChnCount2: %3s\n", yesno(rssconf & CHNCOUNT2_F)); 1643 seq_printf(seq, " ChnCount1: %3s\n", yesno(rssconf & CHNCOUNT1_F)); 1644 seq_printf(seq, " ChnCount0: %3s\n", yesno(rssconf & CHNCOUNT0_F)); 1645 seq_printf(seq, " ChnUndFlow3: %3s\n", yesno(rssconf & 1646 CHNUNDFLOW3_F)); 1647 seq_printf(seq, " ChnUndFlow2: %3s\n", yesno(rssconf & 1648 CHNUNDFLOW2_F)); 1649 seq_printf(seq, " ChnUndFlow1: %3s\n", yesno(rssconf & 1650 CHNUNDFLOW1_F)); 1651 seq_printf(seq, " ChnUndFlow0: %3s\n", yesno(rssconf & 1652 CHNUNDFLOW0_F)); 1653 seq_printf(seq, " RstChn3: %3s\n", yesno(rssconf & RSTCHN3_F)); 1654 seq_printf(seq, " RstChn2: %3s\n", yesno(rssconf & RSTCHN2_F)); 1655 seq_printf(seq, " RstChn1: %3s\n", yesno(rssconf & RSTCHN1_F)); 1656 seq_printf(seq, " RstChn0: %3s\n", yesno(rssconf & RSTCHN0_F)); 1657 seq_printf(seq, " UpdVld: %3s\n", yesno(rssconf & UPDVLD_F)); 1658 seq_printf(seq, " Xoff: %3s\n", yesno(rssconf & XOFF_F)); 1659 seq_printf(seq, " UpdChn3: %3s\n", yesno(rssconf & UPDCHN3_F)); 1660 seq_printf(seq, " UpdChn2: %3s\n", yesno(rssconf & UPDCHN2_F)); 1661 seq_printf(seq, " UpdChn1: %3s\n", yesno(rssconf & UPDCHN1_F)); 1662 seq_printf(seq, " UpdChn0: %3s\n", yesno(rssconf & UPDCHN0_F)); 1663 seq_printf(seq, " Queue: %3d\n", QUEUE_G(rssconf)); 1664 1665 return 0; 1666 } 1667 1668 DEFINE_SIMPLE_DEBUGFS_FILE(rss_config); 1669 1670 /* RSS Secret Key. 1671 */ 1672 1673 static int rss_key_show(struct seq_file *seq, void *v) 1674 { 1675 u32 key[10]; 1676 1677 t4_read_rss_key(seq->private, key); 1678 seq_printf(seq, "%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x\n", 1679 key[9], key[8], key[7], key[6], key[5], key[4], key[3], 1680 key[2], key[1], key[0]); 1681 return 0; 1682 } 1683 1684 static int rss_key_open(struct inode *inode, struct file *file) 1685 { 1686 return single_open(file, rss_key_show, inode->i_private); 1687 } 1688 1689 static ssize_t rss_key_write(struct file *file, const char __user *buf, 1690 size_t count, loff_t *pos) 1691 { 1692 int i, j; 1693 u32 key[10]; 1694 char s[100], *p; 1695 struct adapter *adap = file_inode(file)->i_private; 1696 1697 if (count > sizeof(s) - 1) 1698 return -EINVAL; 1699 if (copy_from_user(s, buf, count)) 1700 return -EFAULT; 1701 for (i = count; i > 0 && isspace(s[i - 1]); i--) 1702 ; 1703 s[i] = '\0'; 1704 1705 for (p = s, i = 9; i >= 0; i--) { 1706 key[i] = 0; 1707 for (j = 0; j < 8; j++, p++) { 1708 if (!isxdigit(*p)) 1709 return -EINVAL; 1710 key[i] = (key[i] << 4) | hex2val(*p); 1711 } 1712 } 1713 1714 t4_write_rss_key(adap, key, -1); 1715 return count; 1716 } 1717 1718 static const struct file_operations rss_key_debugfs_fops = { 1719 .owner = THIS_MODULE, 1720 .open = rss_key_open, 1721 .read = seq_read, 1722 .llseek = seq_lseek, 1723 .release = single_release, 1724 .write = rss_key_write 1725 }; 1726 1727 /* PF RSS Configuration. 1728 */ 1729 1730 struct rss_pf_conf { 1731 u32 rss_pf_map; 1732 u32 rss_pf_mask; 1733 u32 rss_pf_config; 1734 }; 1735 1736 static int rss_pf_config_show(struct seq_file *seq, void *v, int idx) 1737 { 1738 struct rss_pf_conf *pfconf; 1739 1740 if (v == SEQ_START_TOKEN) { 1741 /* use the 0th entry to dump the PF Map Index Size */ 1742 pfconf = seq->private + offsetof(struct seq_tab, data); 1743 seq_printf(seq, "PF Map Index Size = %d\n\n", 1744 LKPIDXSIZE_G(pfconf->rss_pf_map)); 1745 1746 seq_puts(seq, " RSS PF VF Hash Tuple Enable Default\n"); 1747 seq_puts(seq, " Enable IPF Mask Mask IPv6 IPv4 UDP Queue\n"); 1748 seq_puts(seq, " PF Map Chn Prt Map Size Size Four Two Four Two Four Ch1 Ch0\n"); 1749 } else { 1750 #define G_PFnLKPIDX(map, n) \ 1751 (((map) >> PF1LKPIDX_S*(n)) & PF0LKPIDX_M) 1752 #define G_PFnMSKSIZE(mask, n) \ 1753 (((mask) >> PF1MSKSIZE_S*(n)) & PF1MSKSIZE_M) 1754 1755 pfconf = v; 1756 seq_printf(seq, "%3d %3s %3s %3s %3d %3d %3d %3s %3s %3s %3s %3s %3d %3d\n", 1757 idx, 1758 yesno(pfconf->rss_pf_config & MAPENABLE_F), 1759 yesno(pfconf->rss_pf_config & CHNENABLE_F), 1760 yesno(pfconf->rss_pf_config & PRTENABLE_F), 1761 G_PFnLKPIDX(pfconf->rss_pf_map, idx), 1762 G_PFnMSKSIZE(pfconf->rss_pf_mask, idx), 1763 IVFWIDTH_G(pfconf->rss_pf_config), 1764 yesno(pfconf->rss_pf_config & IP6FOURTUPEN_F), 1765 yesno(pfconf->rss_pf_config & IP6TWOTUPEN_F), 1766 yesno(pfconf->rss_pf_config & IP4FOURTUPEN_F), 1767 yesno(pfconf->rss_pf_config & IP4TWOTUPEN_F), 1768 yesno(pfconf->rss_pf_config & UDPFOURTUPEN_F), 1769 CH1DEFAULTQUEUE_G(pfconf->rss_pf_config), 1770 CH0DEFAULTQUEUE_G(pfconf->rss_pf_config)); 1771 1772 #undef G_PFnLKPIDX 1773 #undef G_PFnMSKSIZE 1774 } 1775 return 0; 1776 } 1777 1778 static int rss_pf_config_open(struct inode *inode, struct file *file) 1779 { 1780 struct adapter *adapter = inode->i_private; 1781 struct seq_tab *p; 1782 u32 rss_pf_map, rss_pf_mask; 1783 struct rss_pf_conf *pfconf; 1784 int pf; 1785 1786 p = seq_open_tab(file, 8, sizeof(*pfconf), 1, rss_pf_config_show); 1787 if (!p) 1788 return -ENOMEM; 1789 1790 pfconf = (struct rss_pf_conf *)p->data; 1791 rss_pf_map = t4_read_rss_pf_map(adapter); 1792 rss_pf_mask = t4_read_rss_pf_mask(adapter); 1793 for (pf = 0; pf < 8; pf++) { 1794 pfconf[pf].rss_pf_map = rss_pf_map; 1795 pfconf[pf].rss_pf_mask = rss_pf_mask; 1796 t4_read_rss_pf_config(adapter, pf, &pfconf[pf].rss_pf_config); 1797 } 1798 return 0; 1799 } 1800 1801 static const struct file_operations rss_pf_config_debugfs_fops = { 1802 .owner = THIS_MODULE, 1803 .open = rss_pf_config_open, 1804 .read = seq_read, 1805 .llseek = seq_lseek, 1806 .release = seq_release_private 1807 }; 1808 1809 /* VF RSS Configuration. 1810 */ 1811 1812 struct rss_vf_conf { 1813 u32 rss_vf_vfl; 1814 u32 rss_vf_vfh; 1815 }; 1816 1817 static int rss_vf_config_show(struct seq_file *seq, void *v, int idx) 1818 { 1819 if (v == SEQ_START_TOKEN) { 1820 seq_puts(seq, " RSS Hash Tuple Enable\n"); 1821 seq_puts(seq, " Enable IVF Dis Enb IPv6 IPv4 UDP Def Secret Key\n"); 1822 seq_puts(seq, " VF Chn Prt Map VLAN uP Four Two Four Two Four Que Idx Hash\n"); 1823 } else { 1824 struct rss_vf_conf *vfconf = v; 1825 1826 seq_printf(seq, "%3d %3s %3s %3d %3s %3s %3s %3s %3s %3s %3s %4d %3d %#10x\n", 1827 idx, 1828 yesno(vfconf->rss_vf_vfh & VFCHNEN_F), 1829 yesno(vfconf->rss_vf_vfh & VFPRTEN_F), 1830 VFLKPIDX_G(vfconf->rss_vf_vfh), 1831 yesno(vfconf->rss_vf_vfh & VFVLNEX_F), 1832 yesno(vfconf->rss_vf_vfh & VFUPEN_F), 1833 yesno(vfconf->rss_vf_vfh & VFIP4FOURTUPEN_F), 1834 yesno(vfconf->rss_vf_vfh & VFIP6TWOTUPEN_F), 1835 yesno(vfconf->rss_vf_vfh & VFIP4FOURTUPEN_F), 1836 yesno(vfconf->rss_vf_vfh & VFIP4TWOTUPEN_F), 1837 yesno(vfconf->rss_vf_vfh & ENABLEUDPHASH_F), 1838 DEFAULTQUEUE_G(vfconf->rss_vf_vfh), 1839 KEYINDEX_G(vfconf->rss_vf_vfh), 1840 vfconf->rss_vf_vfl); 1841 } 1842 return 0; 1843 } 1844 1845 static int rss_vf_config_open(struct inode *inode, struct file *file) 1846 { 1847 struct adapter *adapter = inode->i_private; 1848 struct seq_tab *p; 1849 struct rss_vf_conf *vfconf; 1850 int vf, vfcount = adapter->params.arch.vfcount; 1851 1852 p = seq_open_tab(file, vfcount, sizeof(*vfconf), 1, rss_vf_config_show); 1853 if (!p) 1854 return -ENOMEM; 1855 1856 vfconf = (struct rss_vf_conf *)p->data; 1857 for (vf = 0; vf < vfcount; vf++) { 1858 t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl, 1859 &vfconf[vf].rss_vf_vfh); 1860 } 1861 return 0; 1862 } 1863 1864 static const struct file_operations rss_vf_config_debugfs_fops = { 1865 .owner = THIS_MODULE, 1866 .open = rss_vf_config_open, 1867 .read = seq_read, 1868 .llseek = seq_lseek, 1869 .release = seq_release_private 1870 }; 1871 1872 /** 1873 * ethqset2pinfo - return port_info of an Ethernet Queue Set 1874 * @adap: the adapter 1875 * @qset: Ethernet Queue Set 1876 */ 1877 static inline struct port_info *ethqset2pinfo(struct adapter *adap, int qset) 1878 { 1879 int pidx; 1880 1881 for_each_port(adap, pidx) { 1882 struct port_info *pi = adap2pinfo(adap, pidx); 1883 1884 if (qset >= pi->first_qset && 1885 qset < pi->first_qset + pi->nqsets) 1886 return pi; 1887 } 1888 1889 /* should never happen! */ 1890 BUG_ON(1); 1891 return NULL; 1892 } 1893 1894 static int sge_qinfo_show(struct seq_file *seq, void *v) 1895 { 1896 struct adapter *adap = seq->private; 1897 int eth_entries = DIV_ROUND_UP(adap->sge.ethqsets, 4); 1898 int toe_entries = DIV_ROUND_UP(adap->sge.ofldqsets, 4); 1899 int rdma_entries = DIV_ROUND_UP(adap->sge.rdmaqs, 4); 1900 int ciq_entries = DIV_ROUND_UP(adap->sge.rdmaciqs, 4); 1901 int ctrl_entries = DIV_ROUND_UP(MAX_CTRL_QUEUES, 4); 1902 int i, r = (uintptr_t)v - 1; 1903 int toe_idx = r - eth_entries; 1904 int rdma_idx = toe_idx - toe_entries; 1905 int ciq_idx = rdma_idx - rdma_entries; 1906 int ctrl_idx = ciq_idx - ciq_entries; 1907 int fq_idx = ctrl_idx - ctrl_entries; 1908 1909 if (r) 1910 seq_putc(seq, '\n'); 1911 1912 #define S3(fmt_spec, s, v) \ 1913 do { \ 1914 seq_printf(seq, "%-12s", s); \ 1915 for (i = 0; i < n; ++i) \ 1916 seq_printf(seq, " %16" fmt_spec, v); \ 1917 seq_putc(seq, '\n'); \ 1918 } while (0) 1919 #define S(s, v) S3("s", s, v) 1920 #define T(s, v) S3("u", s, tx[i].v) 1921 #define R(s, v) S3("u", s, rx[i].v) 1922 1923 if (r < eth_entries) { 1924 int base_qset = r * 4; 1925 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[base_qset]; 1926 const struct sge_eth_txq *tx = &adap->sge.ethtxq[base_qset]; 1927 int n = min(4, adap->sge.ethqsets - 4 * r); 1928 1929 S("QType:", "Ethernet"); 1930 S("Interface:", 1931 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A"); 1932 T("TxQ ID:", q.cntxt_id); 1933 T("TxQ size:", q.size); 1934 T("TxQ inuse:", q.in_use); 1935 T("TxQ CIDX:", q.cidx); 1936 T("TxQ PIDX:", q.pidx); 1937 #ifdef CONFIG_CHELSIO_T4_DCB 1938 T("DCB Prio:", dcb_prio); 1939 S3("u", "DCB PGID:", 1940 (ethqset2pinfo(adap, base_qset + i)->dcb.pgid >> 1941 4*(7-tx[i].dcb_prio)) & 0xf); 1942 S3("u", "DCB PFC:", 1943 (ethqset2pinfo(adap, base_qset + i)->dcb.pfcen >> 1944 1*(7-tx[i].dcb_prio)) & 0x1); 1945 #endif 1946 R("RspQ ID:", rspq.abs_id); 1947 R("RspQ size:", rspq.size); 1948 R("RspQE size:", rspq.iqe_len); 1949 R("RspQ CIDX:", rspq.cidx); 1950 R("RspQ Gen:", rspq.gen); 1951 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 1952 S3("u", "Intr pktcnt:", 1953 adap->sge.counter_val[rx[i].rspq.pktcnt_idx]); 1954 R("FL ID:", fl.cntxt_id); 1955 R("FL size:", fl.size - 8); 1956 R("FL pend:", fl.pend_cred); 1957 R("FL avail:", fl.avail); 1958 R("FL PIDX:", fl.pidx); 1959 R("FL CIDX:", fl.cidx); 1960 } else if (toe_idx < toe_entries) { 1961 const struct sge_ofld_rxq *rx = &adap->sge.ofldrxq[toe_idx * 4]; 1962 const struct sge_ofld_txq *tx = &adap->sge.ofldtxq[toe_idx * 4]; 1963 int n = min(4, adap->sge.ofldqsets - 4 * toe_idx); 1964 1965 S("QType:", "TOE"); 1966 T("TxQ ID:", q.cntxt_id); 1967 T("TxQ size:", q.size); 1968 T("TxQ inuse:", q.in_use); 1969 T("TxQ CIDX:", q.cidx); 1970 T("TxQ PIDX:", q.pidx); 1971 R("RspQ ID:", rspq.abs_id); 1972 R("RspQ size:", rspq.size); 1973 R("RspQE size:", rspq.iqe_len); 1974 R("RspQ CIDX:", rspq.cidx); 1975 R("RspQ Gen:", rspq.gen); 1976 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 1977 S3("u", "Intr pktcnt:", 1978 adap->sge.counter_val[rx[i].rspq.pktcnt_idx]); 1979 R("FL ID:", fl.cntxt_id); 1980 R("FL size:", fl.size - 8); 1981 R("FL pend:", fl.pend_cred); 1982 R("FL avail:", fl.avail); 1983 R("FL PIDX:", fl.pidx); 1984 R("FL CIDX:", fl.cidx); 1985 } else if (rdma_idx < rdma_entries) { 1986 const struct sge_ofld_rxq *rx = 1987 &adap->sge.rdmarxq[rdma_idx * 4]; 1988 int n = min(4, adap->sge.rdmaqs - 4 * rdma_idx); 1989 1990 S("QType:", "RDMA-CPL"); 1991 S("Interface:", 1992 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A"); 1993 R("RspQ ID:", rspq.abs_id); 1994 R("RspQ size:", rspq.size); 1995 R("RspQE size:", rspq.iqe_len); 1996 R("RspQ CIDX:", rspq.cidx); 1997 R("RspQ Gen:", rspq.gen); 1998 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 1999 S3("u", "Intr pktcnt:", 2000 adap->sge.counter_val[rx[i].rspq.pktcnt_idx]); 2001 R("FL ID:", fl.cntxt_id); 2002 R("FL size:", fl.size - 8); 2003 R("FL pend:", fl.pend_cred); 2004 R("FL avail:", fl.avail); 2005 R("FL PIDX:", fl.pidx); 2006 R("FL CIDX:", fl.cidx); 2007 } else if (ciq_idx < ciq_entries) { 2008 const struct sge_ofld_rxq *rx = &adap->sge.rdmaciq[ciq_idx * 4]; 2009 int n = min(4, adap->sge.rdmaciqs - 4 * ciq_idx); 2010 2011 S("QType:", "RDMA-CIQ"); 2012 S("Interface:", 2013 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A"); 2014 R("RspQ ID:", rspq.abs_id); 2015 R("RspQ size:", rspq.size); 2016 R("RspQE size:", rspq.iqe_len); 2017 R("RspQ CIDX:", rspq.cidx); 2018 R("RspQ Gen:", rspq.gen); 2019 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 2020 S3("u", "Intr pktcnt:", 2021 adap->sge.counter_val[rx[i].rspq.pktcnt_idx]); 2022 } else if (ctrl_idx < ctrl_entries) { 2023 const struct sge_ctrl_txq *tx = &adap->sge.ctrlq[ctrl_idx * 4]; 2024 int n = min(4, adap->params.nports - 4 * ctrl_idx); 2025 2026 S("QType:", "Control"); 2027 T("TxQ ID:", q.cntxt_id); 2028 T("TxQ size:", q.size); 2029 T("TxQ inuse:", q.in_use); 2030 T("TxQ CIDX:", q.cidx); 2031 T("TxQ PIDX:", q.pidx); 2032 } else if (fq_idx == 0) { 2033 const struct sge_rspq *evtq = &adap->sge.fw_evtq; 2034 2035 seq_printf(seq, "%-12s %16s\n", "QType:", "FW event queue"); 2036 seq_printf(seq, "%-12s %16u\n", "RspQ ID:", evtq->abs_id); 2037 seq_printf(seq, "%-12s %16u\n", "RspQ size:", evtq->size); 2038 seq_printf(seq, "%-12s %16u\n", "RspQE size:", evtq->iqe_len); 2039 seq_printf(seq, "%-12s %16u\n", "RspQ CIDX:", evtq->cidx); 2040 seq_printf(seq, "%-12s %16u\n", "RspQ Gen:", evtq->gen); 2041 seq_printf(seq, "%-12s %16u\n", "Intr delay:", 2042 qtimer_val(adap, evtq)); 2043 seq_printf(seq, "%-12s %16u\n", "Intr pktcnt:", 2044 adap->sge.counter_val[evtq->pktcnt_idx]); 2045 } 2046 #undef R 2047 #undef T 2048 #undef S 2049 #undef S3 2050 return 0; 2051 } 2052 2053 static int sge_queue_entries(const struct adapter *adap) 2054 { 2055 return DIV_ROUND_UP(adap->sge.ethqsets, 4) + 2056 DIV_ROUND_UP(adap->sge.ofldqsets, 4) + 2057 DIV_ROUND_UP(adap->sge.rdmaqs, 4) + 2058 DIV_ROUND_UP(adap->sge.rdmaciqs, 4) + 2059 DIV_ROUND_UP(MAX_CTRL_QUEUES, 4) + 1; 2060 } 2061 2062 static void *sge_queue_start(struct seq_file *seq, loff_t *pos) 2063 { 2064 int entries = sge_queue_entries(seq->private); 2065 2066 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL; 2067 } 2068 2069 static void sge_queue_stop(struct seq_file *seq, void *v) 2070 { 2071 } 2072 2073 static void *sge_queue_next(struct seq_file *seq, void *v, loff_t *pos) 2074 { 2075 int entries = sge_queue_entries(seq->private); 2076 2077 ++*pos; 2078 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL; 2079 } 2080 2081 static const struct seq_operations sge_qinfo_seq_ops = { 2082 .start = sge_queue_start, 2083 .next = sge_queue_next, 2084 .stop = sge_queue_stop, 2085 .show = sge_qinfo_show 2086 }; 2087 2088 static int sge_qinfo_open(struct inode *inode, struct file *file) 2089 { 2090 int res = seq_open(file, &sge_qinfo_seq_ops); 2091 2092 if (!res) { 2093 struct seq_file *seq = file->private_data; 2094 2095 seq->private = inode->i_private; 2096 } 2097 return res; 2098 } 2099 2100 static const struct file_operations sge_qinfo_debugfs_fops = { 2101 .owner = THIS_MODULE, 2102 .open = sge_qinfo_open, 2103 .read = seq_read, 2104 .llseek = seq_lseek, 2105 .release = seq_release, 2106 }; 2107 2108 int mem_open(struct inode *inode, struct file *file) 2109 { 2110 unsigned int mem; 2111 struct adapter *adap; 2112 2113 file->private_data = inode->i_private; 2114 2115 mem = (uintptr_t)file->private_data & 0x3; 2116 adap = file->private_data - mem; 2117 2118 (void)t4_fwcache(adap, FW_PARAM_DEV_FWCACHE_FLUSH); 2119 2120 return 0; 2121 } 2122 2123 static ssize_t mem_read(struct file *file, char __user *buf, size_t count, 2124 loff_t *ppos) 2125 { 2126 loff_t pos = *ppos; 2127 loff_t avail = file_inode(file)->i_size; 2128 unsigned int mem = (uintptr_t)file->private_data & 3; 2129 struct adapter *adap = file->private_data - mem; 2130 __be32 *data; 2131 int ret; 2132 2133 if (pos < 0) 2134 return -EINVAL; 2135 if (pos >= avail) 2136 return 0; 2137 if (count > avail - pos) 2138 count = avail - pos; 2139 2140 data = t4_alloc_mem(count); 2141 if (!data) 2142 return -ENOMEM; 2143 2144 spin_lock(&adap->win0_lock); 2145 ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ); 2146 spin_unlock(&adap->win0_lock); 2147 if (ret) { 2148 t4_free_mem(data); 2149 return ret; 2150 } 2151 ret = copy_to_user(buf, data, count); 2152 2153 t4_free_mem(data); 2154 if (ret) 2155 return -EFAULT; 2156 2157 *ppos = pos + count; 2158 return count; 2159 } 2160 static const struct file_operations mem_debugfs_fops = { 2161 .owner = THIS_MODULE, 2162 .open = simple_open, 2163 .read = mem_read, 2164 .llseek = default_llseek, 2165 }; 2166 2167 static void add_debugfs_mem(struct adapter *adap, const char *name, 2168 unsigned int idx, unsigned int size_mb) 2169 { 2170 debugfs_create_file_size(name, S_IRUSR, adap->debugfs_root, 2171 (void *)adap + idx, &mem_debugfs_fops, 2172 size_mb << 20); 2173 } 2174 2175 static int blocked_fl_open(struct inode *inode, struct file *file) 2176 { 2177 file->private_data = inode->i_private; 2178 return 0; 2179 } 2180 2181 static ssize_t blocked_fl_read(struct file *filp, char __user *ubuf, 2182 size_t count, loff_t *ppos) 2183 { 2184 int len; 2185 const struct adapter *adap = filp->private_data; 2186 char *buf; 2187 ssize_t size = (adap->sge.egr_sz + 3) / 4 + 2188 adap->sge.egr_sz / 32 + 2; /* includes ,/\n/\0 */ 2189 2190 buf = kzalloc(size, GFP_KERNEL); 2191 if (!buf) 2192 return -ENOMEM; 2193 2194 len = snprintf(buf, size - 1, "%*pb\n", 2195 adap->sge.egr_sz, adap->sge.blocked_fl); 2196 len += sprintf(buf + len, "\n"); 2197 size = simple_read_from_buffer(ubuf, count, ppos, buf, len); 2198 t4_free_mem(buf); 2199 return size; 2200 } 2201 2202 static ssize_t blocked_fl_write(struct file *filp, const char __user *ubuf, 2203 size_t count, loff_t *ppos) 2204 { 2205 int err; 2206 unsigned long *t; 2207 struct adapter *adap = filp->private_data; 2208 2209 t = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), sizeof(long), GFP_KERNEL); 2210 if (!t) 2211 return -ENOMEM; 2212 2213 err = bitmap_parse_user(ubuf, count, t, adap->sge.egr_sz); 2214 if (err) 2215 return err; 2216 2217 bitmap_copy(adap->sge.blocked_fl, t, adap->sge.egr_sz); 2218 t4_free_mem(t); 2219 return count; 2220 } 2221 2222 static const struct file_operations blocked_fl_fops = { 2223 .owner = THIS_MODULE, 2224 .open = blocked_fl_open, 2225 .read = blocked_fl_read, 2226 .write = blocked_fl_write, 2227 .llseek = generic_file_llseek, 2228 }; 2229 2230 /* Add an array of Debug FS files. 2231 */ 2232 void add_debugfs_files(struct adapter *adap, 2233 struct t4_debugfs_entry *files, 2234 unsigned int nfiles) 2235 { 2236 int i; 2237 2238 /* debugfs support is best effort */ 2239 for (i = 0; i < nfiles; i++) 2240 debugfs_create_file(files[i].name, files[i].mode, 2241 adap->debugfs_root, 2242 (void *)adap + files[i].data, 2243 files[i].ops); 2244 } 2245 2246 int t4_setup_debugfs(struct adapter *adap) 2247 { 2248 int i; 2249 u32 size = 0; 2250 struct dentry *de; 2251 2252 static struct t4_debugfs_entry t4_debugfs_files[] = { 2253 { "cim_la", &cim_la_fops, S_IRUSR, 0 }, 2254 { "cim_pif_la", &cim_pif_la_fops, S_IRUSR, 0 }, 2255 { "cim_ma_la", &cim_ma_la_fops, S_IRUSR, 0 }, 2256 { "cim_qcfg", &cim_qcfg_fops, S_IRUSR, 0 }, 2257 { "clk", &clk_debugfs_fops, S_IRUSR, 0 }, 2258 { "devlog", &devlog_fops, S_IRUSR, 0 }, 2259 { "mbox0", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 0 }, 2260 { "mbox1", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 1 }, 2261 { "mbox2", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 2 }, 2262 { "mbox3", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 3 }, 2263 { "mbox4", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 4 }, 2264 { "mbox5", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 5 }, 2265 { "mbox6", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 6 }, 2266 { "mbox7", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 7 }, 2267 { "l2t", &t4_l2t_fops, S_IRUSR, 0}, 2268 { "mps_tcam", &mps_tcam_debugfs_fops, S_IRUSR, 0 }, 2269 { "rss", &rss_debugfs_fops, S_IRUSR, 0 }, 2270 { "rss_config", &rss_config_debugfs_fops, S_IRUSR, 0 }, 2271 { "rss_key", &rss_key_debugfs_fops, S_IRUSR, 0 }, 2272 { "rss_pf_config", &rss_pf_config_debugfs_fops, S_IRUSR, 0 }, 2273 { "rss_vf_config", &rss_vf_config_debugfs_fops, S_IRUSR, 0 }, 2274 { "sge_qinfo", &sge_qinfo_debugfs_fops, S_IRUSR, 0 }, 2275 { "ibq_tp0", &cim_ibq_fops, S_IRUSR, 0 }, 2276 { "ibq_tp1", &cim_ibq_fops, S_IRUSR, 1 }, 2277 { "ibq_ulp", &cim_ibq_fops, S_IRUSR, 2 }, 2278 { "ibq_sge0", &cim_ibq_fops, S_IRUSR, 3 }, 2279 { "ibq_sge1", &cim_ibq_fops, S_IRUSR, 4 }, 2280 { "ibq_ncsi", &cim_ibq_fops, S_IRUSR, 5 }, 2281 { "obq_ulp0", &cim_obq_fops, S_IRUSR, 0 }, 2282 { "obq_ulp1", &cim_obq_fops, S_IRUSR, 1 }, 2283 { "obq_ulp2", &cim_obq_fops, S_IRUSR, 2 }, 2284 { "obq_ulp3", &cim_obq_fops, S_IRUSR, 3 }, 2285 { "obq_sge", &cim_obq_fops, S_IRUSR, 4 }, 2286 { "obq_ncsi", &cim_obq_fops, S_IRUSR, 5 }, 2287 { "tp_la", &tp_la_fops, S_IRUSR, 0 }, 2288 { "ulprx_la", &ulprx_la_fops, S_IRUSR, 0 }, 2289 { "sensors", &sensors_debugfs_fops, S_IRUSR, 0 }, 2290 { "pm_stats", &pm_stats_debugfs_fops, S_IRUSR, 0 }, 2291 { "tx_rate", &tx_rate_debugfs_fops, S_IRUSR, 0 }, 2292 { "cctrl", &cctrl_tbl_debugfs_fops, S_IRUSR, 0 }, 2293 #if IS_ENABLED(CONFIG_IPV6) 2294 { "clip_tbl", &clip_tbl_debugfs_fops, S_IRUSR, 0 }, 2295 #endif 2296 { "blocked_fl", &blocked_fl_fops, S_IRUSR | S_IWUSR, 0 }, 2297 }; 2298 2299 /* Debug FS nodes common to all T5 and later adapters. 2300 */ 2301 static struct t4_debugfs_entry t5_debugfs_files[] = { 2302 { "obq_sge_rx_q0", &cim_obq_fops, S_IRUSR, 6 }, 2303 { "obq_sge_rx_q1", &cim_obq_fops, S_IRUSR, 7 }, 2304 }; 2305 2306 add_debugfs_files(adap, 2307 t4_debugfs_files, 2308 ARRAY_SIZE(t4_debugfs_files)); 2309 if (!is_t4(adap->params.chip)) 2310 add_debugfs_files(adap, 2311 t5_debugfs_files, 2312 ARRAY_SIZE(t5_debugfs_files)); 2313 2314 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 2315 if (i & EDRAM0_ENABLE_F) { 2316 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 2317 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM0_SIZE_G(size)); 2318 } 2319 if (i & EDRAM1_ENABLE_F) { 2320 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 2321 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size)); 2322 } 2323 if (is_t5(adap->params.chip)) { 2324 if (i & EXT_MEM0_ENABLE_F) { 2325 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 2326 add_debugfs_mem(adap, "mc0", MEM_MC0, 2327 EXT_MEM0_SIZE_G(size)); 2328 } 2329 if (i & EXT_MEM1_ENABLE_F) { 2330 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 2331 add_debugfs_mem(adap, "mc1", MEM_MC1, 2332 EXT_MEM1_SIZE_G(size)); 2333 } 2334 } else { 2335 if (i & EXT_MEM_ENABLE_F) { 2336 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A); 2337 add_debugfs_mem(adap, "mc", MEM_MC, 2338 EXT_MEM_SIZE_G(size)); 2339 } 2340 } 2341 2342 de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap, 2343 &flash_debugfs_fops, adap->params.sf_size); 2344 2345 return 0; 2346 } 2347