1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/seq_file.h> 36 #include <linux/debugfs.h> 37 #include <linux/string_helpers.h> 38 #include <linux/sort.h> 39 #include <linux/ctype.h> 40 41 #include "cxgb4.h" 42 #include "t4_regs.h" 43 #include "t4_values.h" 44 #include "t4fw_api.h" 45 #include "cxgb4_debugfs.h" 46 #include "clip_tbl.h" 47 #include "l2t.h" 48 #include "cudbg_if.h" 49 #include "cudbg_lib_common.h" 50 #include "cudbg_entity.h" 51 #include "cudbg_lib.h" 52 53 /* generic seq_file support for showing a table of size rows x width. */ 54 static void *seq_tab_get_idx(struct seq_tab *tb, loff_t pos) 55 { 56 pos -= tb->skip_first; 57 return pos >= tb->rows ? NULL : &tb->data[pos * tb->width]; 58 } 59 60 static void *seq_tab_start(struct seq_file *seq, loff_t *pos) 61 { 62 struct seq_tab *tb = seq->private; 63 64 if (tb->skip_first && *pos == 0) 65 return SEQ_START_TOKEN; 66 67 return seq_tab_get_idx(tb, *pos); 68 } 69 70 static void *seq_tab_next(struct seq_file *seq, void *v, loff_t *pos) 71 { 72 v = seq_tab_get_idx(seq->private, *pos + 1); 73 ++(*pos); 74 return v; 75 } 76 77 static void seq_tab_stop(struct seq_file *seq, void *v) 78 { 79 } 80 81 static int seq_tab_show(struct seq_file *seq, void *v) 82 { 83 const struct seq_tab *tb = seq->private; 84 85 return tb->show(seq, v, ((char *)v - tb->data) / tb->width); 86 } 87 88 static const struct seq_operations seq_tab_ops = { 89 .start = seq_tab_start, 90 .next = seq_tab_next, 91 .stop = seq_tab_stop, 92 .show = seq_tab_show 93 }; 94 95 struct seq_tab *seq_open_tab(struct file *f, unsigned int rows, 96 unsigned int width, unsigned int have_header, 97 int (*show)(struct seq_file *seq, void *v, int i)) 98 { 99 struct seq_tab *p; 100 101 p = __seq_open_private(f, &seq_tab_ops, sizeof(*p) + rows * width); 102 if (p) { 103 p->show = show; 104 p->rows = rows; 105 p->width = width; 106 p->skip_first = have_header != 0; 107 } 108 return p; 109 } 110 111 /* Trim the size of a seq_tab to the supplied number of rows. The operation is 112 * irreversible. 113 */ 114 static int seq_tab_trim(struct seq_tab *p, unsigned int new_rows) 115 { 116 if (new_rows > p->rows) 117 return -EINVAL; 118 p->rows = new_rows; 119 return 0; 120 } 121 122 static int cim_la_show(struct seq_file *seq, void *v, int idx) 123 { 124 if (v == SEQ_START_TOKEN) 125 seq_puts(seq, "Status Data PC LS0Stat LS0Addr " 126 " LS0Data\n"); 127 else { 128 const u32 *p = v; 129 130 seq_printf(seq, 131 " %02x %x%07x %x%07x %08x %08x %08x%08x%08x%08x\n", 132 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 133 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 134 p[6], p[7]); 135 } 136 return 0; 137 } 138 139 static int cim_la_show_3in1(struct seq_file *seq, void *v, int idx) 140 { 141 if (v == SEQ_START_TOKEN) { 142 seq_puts(seq, "Status Data PC\n"); 143 } else { 144 const u32 *p = v; 145 146 seq_printf(seq, " %02x %08x %08x\n", p[5] & 0xff, p[6], 147 p[7]); 148 seq_printf(seq, " %02x %02x%06x %02x%06x\n", 149 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 150 p[4] & 0xff, p[5] >> 8); 151 seq_printf(seq, " %02x %x%07x %x%07x\n", (p[0] >> 4) & 0xff, 152 p[0] & 0xf, p[1] >> 4, p[1] & 0xf, p[2] >> 4); 153 } 154 return 0; 155 } 156 157 static int cim_la_show_t6(struct seq_file *seq, void *v, int idx) 158 { 159 if (v == SEQ_START_TOKEN) { 160 seq_puts(seq, "Status Inst Data PC LS0Stat " 161 "LS0Addr LS0Data LS1Stat LS1Addr LS1Data\n"); 162 } else { 163 const u32 *p = v; 164 165 seq_printf(seq, " %02x %04x%04x %04x%04x %04x%04x %08x %08x %08x %08x %08x %08x\n", 166 (p[9] >> 16) & 0xff, /* Status */ 167 p[9] & 0xffff, p[8] >> 16, /* Inst */ 168 p[8] & 0xffff, p[7] >> 16, /* Data */ 169 p[7] & 0xffff, p[6] >> 16, /* PC */ 170 p[2], p[1], p[0], /* LS0 Stat, Addr and Data */ 171 p[5], p[4], p[3]); /* LS1 Stat, Addr and Data */ 172 } 173 return 0; 174 } 175 176 static int cim_la_show_pc_t6(struct seq_file *seq, void *v, int idx) 177 { 178 if (v == SEQ_START_TOKEN) { 179 seq_puts(seq, "Status Inst Data PC\n"); 180 } else { 181 const u32 *p = v; 182 183 seq_printf(seq, " %02x %08x %08x %08x\n", 184 p[3] & 0xff, p[2], p[1], p[0]); 185 seq_printf(seq, " %02x %02x%06x %02x%06x %02x%06x\n", 186 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 187 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 188 seq_printf(seq, " %02x %04x%04x %04x%04x %04x%04x\n", 189 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 190 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 191 p[6] >> 16); 192 } 193 return 0; 194 } 195 196 static int cim_la_open(struct inode *inode, struct file *file) 197 { 198 int ret; 199 unsigned int cfg; 200 struct seq_tab *p; 201 struct adapter *adap = inode->i_private; 202 203 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg); 204 if (ret) 205 return ret; 206 207 if (is_t6(adap->params.chip)) { 208 /* +1 to account for integer division of CIMLA_SIZE/10 */ 209 p = seq_open_tab(file, (adap->params.cim_la_size / 10) + 1, 210 10 * sizeof(u32), 1, 211 cfg & UPDBGLACAPTPCONLY_F ? 212 cim_la_show_pc_t6 : cim_la_show_t6); 213 } else { 214 p = seq_open_tab(file, adap->params.cim_la_size / 8, 215 8 * sizeof(u32), 1, 216 cfg & UPDBGLACAPTPCONLY_F ? cim_la_show_3in1 : 217 cim_la_show); 218 } 219 if (!p) 220 return -ENOMEM; 221 222 ret = t4_cim_read_la(adap, (u32 *)p->data, NULL); 223 if (ret) 224 seq_release_private(inode, file); 225 return ret; 226 } 227 228 static const struct file_operations cim_la_fops = { 229 .owner = THIS_MODULE, 230 .open = cim_la_open, 231 .read = seq_read, 232 .llseek = seq_lseek, 233 .release = seq_release_private 234 }; 235 236 static int cim_pif_la_show(struct seq_file *seq, void *v, int idx) 237 { 238 const u32 *p = v; 239 240 if (v == SEQ_START_TOKEN) { 241 seq_puts(seq, "Cntl ID DataBE Addr Data\n"); 242 } else if (idx < CIM_PIFLA_SIZE) { 243 seq_printf(seq, " %02x %02x %04x %08x %08x%08x%08x%08x\n", 244 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, 245 p[5] & 0xffff, p[4], p[3], p[2], p[1], p[0]); 246 } else { 247 if (idx == CIM_PIFLA_SIZE) 248 seq_puts(seq, "\nCntl ID Data\n"); 249 seq_printf(seq, " %02x %02x %08x%08x%08x%08x\n", 250 (p[4] >> 6) & 0xff, p[4] & 0x3f, 251 p[3], p[2], p[1], p[0]); 252 } 253 return 0; 254 } 255 256 static int cim_pif_la_open(struct inode *inode, struct file *file) 257 { 258 struct seq_tab *p; 259 struct adapter *adap = inode->i_private; 260 261 p = seq_open_tab(file, 2 * CIM_PIFLA_SIZE, 6 * sizeof(u32), 1, 262 cim_pif_la_show); 263 if (!p) 264 return -ENOMEM; 265 266 t4_cim_read_pif_la(adap, (u32 *)p->data, 267 (u32 *)p->data + 6 * CIM_PIFLA_SIZE, NULL, NULL); 268 return 0; 269 } 270 271 static const struct file_operations cim_pif_la_fops = { 272 .owner = THIS_MODULE, 273 .open = cim_pif_la_open, 274 .read = seq_read, 275 .llseek = seq_lseek, 276 .release = seq_release_private 277 }; 278 279 static int cim_ma_la_show(struct seq_file *seq, void *v, int idx) 280 { 281 const u32 *p = v; 282 283 if (v == SEQ_START_TOKEN) { 284 seq_puts(seq, "\n"); 285 } else if (idx < CIM_MALA_SIZE) { 286 seq_printf(seq, "%02x%08x%08x%08x%08x\n", 287 p[4], p[3], p[2], p[1], p[0]); 288 } else { 289 if (idx == CIM_MALA_SIZE) 290 seq_puts(seq, 291 "\nCnt ID Tag UE Data RDY VLD\n"); 292 seq_printf(seq, "%3u %2u %x %u %08x%08x %u %u\n", 293 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 294 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 295 (p[1] >> 2) | ((p[2] & 3) << 30), 296 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 297 p[0] & 1); 298 } 299 return 0; 300 } 301 302 static int cim_ma_la_open(struct inode *inode, struct file *file) 303 { 304 struct seq_tab *p; 305 struct adapter *adap = inode->i_private; 306 307 p = seq_open_tab(file, 2 * CIM_MALA_SIZE, 5 * sizeof(u32), 1, 308 cim_ma_la_show); 309 if (!p) 310 return -ENOMEM; 311 312 t4_cim_read_ma_la(adap, (u32 *)p->data, 313 (u32 *)p->data + 5 * CIM_MALA_SIZE); 314 return 0; 315 } 316 317 static const struct file_operations cim_ma_la_fops = { 318 .owner = THIS_MODULE, 319 .open = cim_ma_la_open, 320 .read = seq_read, 321 .llseek = seq_lseek, 322 .release = seq_release_private 323 }; 324 325 static int cim_qcfg_show(struct seq_file *seq, void *v) 326 { 327 static const char * const qname[] = { 328 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", 329 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", 330 "SGE0-RX", "SGE1-RX" 331 }; 332 333 int i; 334 struct adapter *adap = seq->private; 335 u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 336 u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 337 u32 stat[(4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5))]; 338 u16 thres[CIM_NUM_IBQ]; 339 u32 obq_wr_t4[2 * CIM_NUM_OBQ], *wr; 340 u32 obq_wr_t5[2 * CIM_NUM_OBQ_T5]; 341 u32 *p = stat; 342 int cim_num_obq = is_t4(adap->params.chip) ? 343 CIM_NUM_OBQ : CIM_NUM_OBQ_T5; 344 345 i = t4_cim_read(adap, is_t4(adap->params.chip) ? UP_IBQ_0_RDADDR_A : 346 UP_IBQ_0_SHADOW_RDADDR_A, 347 ARRAY_SIZE(stat), stat); 348 if (!i) { 349 if (is_t4(adap->params.chip)) { 350 i = t4_cim_read(adap, UP_OBQ_0_REALADDR_A, 351 ARRAY_SIZE(obq_wr_t4), obq_wr_t4); 352 wr = obq_wr_t4; 353 } else { 354 i = t4_cim_read(adap, UP_OBQ_0_SHADOW_REALADDR_A, 355 ARRAY_SIZE(obq_wr_t5), obq_wr_t5); 356 wr = obq_wr_t5; 357 } 358 } 359 if (i) 360 return i; 361 362 t4_read_cimq_cfg(adap, base, size, thres); 363 364 seq_printf(seq, 365 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail\n"); 366 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 367 seq_printf(seq, "%7s %5x %5u %5u %6x %4x %4u %4u %5u\n", 368 qname[i], base[i], size[i], thres[i], 369 IBQRDADDR_G(p[0]), IBQWRADDR_G(p[1]), 370 QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]), 371 QUEREMFLITS_G(p[2]) * 16); 372 for ( ; i < CIM_NUM_IBQ + cim_num_obq; i++, p += 4, wr += 2) 373 seq_printf(seq, "%7s %5x %5u %12x %4x %4u %4u %5u\n", 374 qname[i], base[i], size[i], 375 QUERDADDR_G(p[0]) & 0x3fff, wr[0] - base[i], 376 QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]), 377 QUEREMFLITS_G(p[2]) * 16); 378 return 0; 379 } 380 DEFINE_SHOW_ATTRIBUTE(cim_qcfg); 381 382 static int cimq_show(struct seq_file *seq, void *v, int idx) 383 { 384 const u32 *p = v; 385 386 seq_printf(seq, "%#06x: %08x %08x %08x %08x\n", idx * 16, p[0], p[1], 387 p[2], p[3]); 388 return 0; 389 } 390 391 static int cim_ibq_open(struct inode *inode, struct file *file) 392 { 393 int ret; 394 struct seq_tab *p; 395 unsigned int qid = (uintptr_t)inode->i_private & 7; 396 struct adapter *adap = inode->i_private - qid; 397 398 p = seq_open_tab(file, CIM_IBQ_SIZE, 4 * sizeof(u32), 0, cimq_show); 399 if (!p) 400 return -ENOMEM; 401 402 ret = t4_read_cim_ibq(adap, qid, (u32 *)p->data, CIM_IBQ_SIZE * 4); 403 if (ret < 0) 404 seq_release_private(inode, file); 405 else 406 ret = 0; 407 return ret; 408 } 409 410 static const struct file_operations cim_ibq_fops = { 411 .owner = THIS_MODULE, 412 .open = cim_ibq_open, 413 .read = seq_read, 414 .llseek = seq_lseek, 415 .release = seq_release_private 416 }; 417 418 static int cim_obq_open(struct inode *inode, struct file *file) 419 { 420 int ret; 421 struct seq_tab *p; 422 unsigned int qid = (uintptr_t)inode->i_private & 7; 423 struct adapter *adap = inode->i_private - qid; 424 425 p = seq_open_tab(file, 6 * CIM_OBQ_SIZE, 4 * sizeof(u32), 0, cimq_show); 426 if (!p) 427 return -ENOMEM; 428 429 ret = t4_read_cim_obq(adap, qid, (u32 *)p->data, 6 * CIM_OBQ_SIZE * 4); 430 if (ret < 0) { 431 seq_release_private(inode, file); 432 } else { 433 seq_tab_trim(p, ret / 4); 434 ret = 0; 435 } 436 return ret; 437 } 438 439 static const struct file_operations cim_obq_fops = { 440 .owner = THIS_MODULE, 441 .open = cim_obq_open, 442 .read = seq_read, 443 .llseek = seq_lseek, 444 .release = seq_release_private 445 }; 446 447 struct field_desc { 448 const char *name; 449 unsigned int start; 450 unsigned int width; 451 }; 452 453 static void field_desc_show(struct seq_file *seq, u64 v, 454 const struct field_desc *p) 455 { 456 char buf[32]; 457 int line_size = 0; 458 459 while (p->name) { 460 u64 mask = (1ULL << p->width) - 1; 461 int len = scnprintf(buf, sizeof(buf), "%s: %llu", p->name, 462 ((unsigned long long)v >> p->start) & mask); 463 464 if (line_size + len >= 79) { 465 line_size = 8; 466 seq_puts(seq, "\n "); 467 } 468 seq_printf(seq, "%s ", buf); 469 line_size += len + 1; 470 p++; 471 } 472 seq_putc(seq, '\n'); 473 } 474 475 static struct field_desc tp_la0[] = { 476 { "RcfOpCodeOut", 60, 4 }, 477 { "State", 56, 4 }, 478 { "WcfState", 52, 4 }, 479 { "RcfOpcSrcOut", 50, 2 }, 480 { "CRxError", 49, 1 }, 481 { "ERxError", 48, 1 }, 482 { "SanityFailed", 47, 1 }, 483 { "SpuriousMsg", 46, 1 }, 484 { "FlushInputMsg", 45, 1 }, 485 { "FlushInputCpl", 44, 1 }, 486 { "RssUpBit", 43, 1 }, 487 { "RssFilterHit", 42, 1 }, 488 { "Tid", 32, 10 }, 489 { "InitTcb", 31, 1 }, 490 { "LineNumber", 24, 7 }, 491 { "Emsg", 23, 1 }, 492 { "EdataOut", 22, 1 }, 493 { "Cmsg", 21, 1 }, 494 { "CdataOut", 20, 1 }, 495 { "EreadPdu", 19, 1 }, 496 { "CreadPdu", 18, 1 }, 497 { "TunnelPkt", 17, 1 }, 498 { "RcfPeerFin", 16, 1 }, 499 { "RcfReasonOut", 12, 4 }, 500 { "TxCchannel", 10, 2 }, 501 { "RcfTxChannel", 8, 2 }, 502 { "RxEchannel", 6, 2 }, 503 { "RcfRxChannel", 5, 1 }, 504 { "RcfDataOutSrdy", 4, 1 }, 505 { "RxDvld", 3, 1 }, 506 { "RxOoDvld", 2, 1 }, 507 { "RxCongestion", 1, 1 }, 508 { "TxCongestion", 0, 1 }, 509 { NULL } 510 }; 511 512 static int tp_la_show(struct seq_file *seq, void *v, int idx) 513 { 514 const u64 *p = v; 515 516 field_desc_show(seq, *p, tp_la0); 517 return 0; 518 } 519 520 static int tp_la_show2(struct seq_file *seq, void *v, int idx) 521 { 522 const u64 *p = v; 523 524 if (idx) 525 seq_putc(seq, '\n'); 526 field_desc_show(seq, p[0], tp_la0); 527 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 528 field_desc_show(seq, p[1], tp_la0); 529 return 0; 530 } 531 532 static int tp_la_show3(struct seq_file *seq, void *v, int idx) 533 { 534 static struct field_desc tp_la1[] = { 535 { "CplCmdIn", 56, 8 }, 536 { "CplCmdOut", 48, 8 }, 537 { "ESynOut", 47, 1 }, 538 { "EAckOut", 46, 1 }, 539 { "EFinOut", 45, 1 }, 540 { "ERstOut", 44, 1 }, 541 { "SynIn", 43, 1 }, 542 { "AckIn", 42, 1 }, 543 { "FinIn", 41, 1 }, 544 { "RstIn", 40, 1 }, 545 { "DataIn", 39, 1 }, 546 { "DataInVld", 38, 1 }, 547 { "PadIn", 37, 1 }, 548 { "RxBufEmpty", 36, 1 }, 549 { "RxDdp", 35, 1 }, 550 { "RxFbCongestion", 34, 1 }, 551 { "TxFbCongestion", 33, 1 }, 552 { "TxPktSumSrdy", 32, 1 }, 553 { "RcfUlpType", 28, 4 }, 554 { "Eread", 27, 1 }, 555 { "Ebypass", 26, 1 }, 556 { "Esave", 25, 1 }, 557 { "Static0", 24, 1 }, 558 { "Cread", 23, 1 }, 559 { "Cbypass", 22, 1 }, 560 { "Csave", 21, 1 }, 561 { "CPktOut", 20, 1 }, 562 { "RxPagePoolFull", 18, 2 }, 563 { "RxLpbkPkt", 17, 1 }, 564 { "TxLpbkPkt", 16, 1 }, 565 { "RxVfValid", 15, 1 }, 566 { "SynLearned", 14, 1 }, 567 { "SetDelEntry", 13, 1 }, 568 { "SetInvEntry", 12, 1 }, 569 { "CpcmdDvld", 11, 1 }, 570 { "CpcmdSave", 10, 1 }, 571 { "RxPstructsFull", 8, 2 }, 572 { "EpcmdDvld", 7, 1 }, 573 { "EpcmdFlush", 6, 1 }, 574 { "EpcmdTrimPrefix", 5, 1 }, 575 { "EpcmdTrimPostfix", 4, 1 }, 576 { "ERssIp4Pkt", 3, 1 }, 577 { "ERssIp6Pkt", 2, 1 }, 578 { "ERssTcpUdpPkt", 1, 1 }, 579 { "ERssFceFipPkt", 0, 1 }, 580 { NULL } 581 }; 582 static struct field_desc tp_la2[] = { 583 { "CplCmdIn", 56, 8 }, 584 { "MpsVfVld", 55, 1 }, 585 { "MpsPf", 52, 3 }, 586 { "MpsVf", 44, 8 }, 587 { "SynIn", 43, 1 }, 588 { "AckIn", 42, 1 }, 589 { "FinIn", 41, 1 }, 590 { "RstIn", 40, 1 }, 591 { "DataIn", 39, 1 }, 592 { "DataInVld", 38, 1 }, 593 { "PadIn", 37, 1 }, 594 { "RxBufEmpty", 36, 1 }, 595 { "RxDdp", 35, 1 }, 596 { "RxFbCongestion", 34, 1 }, 597 { "TxFbCongestion", 33, 1 }, 598 { "TxPktSumSrdy", 32, 1 }, 599 { "RcfUlpType", 28, 4 }, 600 { "Eread", 27, 1 }, 601 { "Ebypass", 26, 1 }, 602 { "Esave", 25, 1 }, 603 { "Static0", 24, 1 }, 604 { "Cread", 23, 1 }, 605 { "Cbypass", 22, 1 }, 606 { "Csave", 21, 1 }, 607 { "CPktOut", 20, 1 }, 608 { "RxPagePoolFull", 18, 2 }, 609 { "RxLpbkPkt", 17, 1 }, 610 { "TxLpbkPkt", 16, 1 }, 611 { "RxVfValid", 15, 1 }, 612 { "SynLearned", 14, 1 }, 613 { "SetDelEntry", 13, 1 }, 614 { "SetInvEntry", 12, 1 }, 615 { "CpcmdDvld", 11, 1 }, 616 { "CpcmdSave", 10, 1 }, 617 { "RxPstructsFull", 8, 2 }, 618 { "EpcmdDvld", 7, 1 }, 619 { "EpcmdFlush", 6, 1 }, 620 { "EpcmdTrimPrefix", 5, 1 }, 621 { "EpcmdTrimPostfix", 4, 1 }, 622 { "ERssIp4Pkt", 3, 1 }, 623 { "ERssIp6Pkt", 2, 1 }, 624 { "ERssTcpUdpPkt", 1, 1 }, 625 { "ERssFceFipPkt", 0, 1 }, 626 { NULL } 627 }; 628 const u64 *p = v; 629 630 if (idx) 631 seq_putc(seq, '\n'); 632 field_desc_show(seq, p[0], tp_la0); 633 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 634 field_desc_show(seq, p[1], (p[0] & BIT(17)) ? tp_la2 : tp_la1); 635 return 0; 636 } 637 638 static int tp_la_open(struct inode *inode, struct file *file) 639 { 640 struct seq_tab *p; 641 struct adapter *adap = inode->i_private; 642 643 switch (DBGLAMODE_G(t4_read_reg(adap, TP_DBG_LA_CONFIG_A))) { 644 case 2: 645 p = seq_open_tab(file, TPLA_SIZE / 2, 2 * sizeof(u64), 0, 646 tp_la_show2); 647 break; 648 case 3: 649 p = seq_open_tab(file, TPLA_SIZE / 2, 2 * sizeof(u64), 0, 650 tp_la_show3); 651 break; 652 default: 653 p = seq_open_tab(file, TPLA_SIZE, sizeof(u64), 0, tp_la_show); 654 } 655 if (!p) 656 return -ENOMEM; 657 658 t4_tp_read_la(adap, (u64 *)p->data, NULL); 659 return 0; 660 } 661 662 static ssize_t tp_la_write(struct file *file, const char __user *buf, 663 size_t count, loff_t *pos) 664 { 665 int err; 666 char s[32]; 667 unsigned long val; 668 size_t size = min(sizeof(s) - 1, count); 669 struct adapter *adap = file_inode(file)->i_private; 670 671 if (copy_from_user(s, buf, size)) 672 return -EFAULT; 673 s[size] = '\0'; 674 err = kstrtoul(s, 0, &val); 675 if (err) 676 return err; 677 if (val > 0xffff) 678 return -EINVAL; 679 adap->params.tp.la_mask = val << 16; 680 t4_set_reg_field(adap, TP_DBG_LA_CONFIG_A, 0xffff0000U, 681 adap->params.tp.la_mask); 682 return count; 683 } 684 685 static const struct file_operations tp_la_fops = { 686 .owner = THIS_MODULE, 687 .open = tp_la_open, 688 .read = seq_read, 689 .llseek = seq_lseek, 690 .release = seq_release_private, 691 .write = tp_la_write 692 }; 693 694 static int ulprx_la_show(struct seq_file *seq, void *v, int idx) 695 { 696 const u32 *p = v; 697 698 if (v == SEQ_START_TOKEN) 699 seq_puts(seq, " Pcmd Type Message" 700 " Data\n"); 701 else 702 seq_printf(seq, "%08x%08x %4x %08x %08x%08x%08x%08x\n", 703 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 704 return 0; 705 } 706 707 static int ulprx_la_open(struct inode *inode, struct file *file) 708 { 709 struct seq_tab *p; 710 struct adapter *adap = inode->i_private; 711 712 p = seq_open_tab(file, ULPRX_LA_SIZE, 8 * sizeof(u32), 1, 713 ulprx_la_show); 714 if (!p) 715 return -ENOMEM; 716 717 t4_ulprx_read_la(adap, (u32 *)p->data); 718 return 0; 719 } 720 721 static const struct file_operations ulprx_la_fops = { 722 .owner = THIS_MODULE, 723 .open = ulprx_la_open, 724 .read = seq_read, 725 .llseek = seq_lseek, 726 .release = seq_release_private 727 }; 728 729 /* Show the PM memory stats. These stats include: 730 * 731 * TX: 732 * Read: memory read operation 733 * Write Bypass: cut-through 734 * Bypass + mem: cut-through and save copy 735 * 736 * RX: 737 * Read: memory read 738 * Write Bypass: cut-through 739 * Flush: payload trim or drop 740 */ 741 static int pm_stats_show(struct seq_file *seq, void *v) 742 { 743 static const char * const tx_pm_stats[] = { 744 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:" 745 }; 746 static const char * const rx_pm_stats[] = { 747 "Read:", "Write bypass:", "Write mem:", "Flush:" 748 }; 749 750 int i; 751 u32 tx_cnt[T6_PM_NSTATS], rx_cnt[T6_PM_NSTATS]; 752 u64 tx_cyc[T6_PM_NSTATS], rx_cyc[T6_PM_NSTATS]; 753 struct adapter *adap = seq->private; 754 755 t4_pmtx_get_stats(adap, tx_cnt, tx_cyc); 756 t4_pmrx_get_stats(adap, rx_cnt, rx_cyc); 757 758 seq_printf(seq, "%13s %10s %20s\n", " ", "Tx pcmds", "Tx bytes"); 759 for (i = 0; i < PM_NSTATS - 1; i++) 760 seq_printf(seq, "%-13s %10u %20llu\n", 761 tx_pm_stats[i], tx_cnt[i], tx_cyc[i]); 762 763 seq_printf(seq, "%13s %10s %20s\n", " ", "Rx pcmds", "Rx bytes"); 764 for (i = 0; i < PM_NSTATS - 1; i++) 765 seq_printf(seq, "%-13s %10u %20llu\n", 766 rx_pm_stats[i], rx_cnt[i], rx_cyc[i]); 767 768 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 769 /* In T5 the granularity of the total wait is too fine. 770 * It is not useful as it reaches the max value too fast. 771 * Hence display this Input FIFO wait for T6 onwards. 772 */ 773 seq_printf(seq, "%13s %10s %20s\n", 774 " ", "Total wait", "Total Occupancy"); 775 seq_printf(seq, "Tx FIFO wait %10u %20llu\n", 776 tx_cnt[i], tx_cyc[i]); 777 seq_printf(seq, "Rx FIFO wait %10u %20llu\n", 778 rx_cnt[i], rx_cyc[i]); 779 780 /* Skip index 6 as there is nothing useful ihere */ 781 i += 2; 782 783 /* At index 7, a new stat for read latency (count, total wait) 784 * is added. 785 */ 786 seq_printf(seq, "%13s %10s %20s\n", 787 " ", "Reads", "Total wait"); 788 seq_printf(seq, "Tx latency %10u %20llu\n", 789 tx_cnt[i], tx_cyc[i]); 790 seq_printf(seq, "Rx latency %10u %20llu\n", 791 rx_cnt[i], rx_cyc[i]); 792 } 793 return 0; 794 } 795 796 static int pm_stats_open(struct inode *inode, struct file *file) 797 { 798 return single_open(file, pm_stats_show, inode->i_private); 799 } 800 801 static ssize_t pm_stats_clear(struct file *file, const char __user *buf, 802 size_t count, loff_t *pos) 803 { 804 struct adapter *adap = file_inode(file)->i_private; 805 806 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, 0); 807 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, 0); 808 return count; 809 } 810 811 static const struct file_operations pm_stats_debugfs_fops = { 812 .owner = THIS_MODULE, 813 .open = pm_stats_open, 814 .read = seq_read, 815 .llseek = seq_lseek, 816 .release = single_release, 817 .write = pm_stats_clear 818 }; 819 820 static int tx_rate_show(struct seq_file *seq, void *v) 821 { 822 u64 nrate[NCHAN], orate[NCHAN]; 823 struct adapter *adap = seq->private; 824 825 t4_get_chan_txrate(adap, nrate, orate); 826 if (adap->params.arch.nchan == NCHAN) { 827 seq_puts(seq, " channel 0 channel 1 " 828 "channel 2 channel 3\n"); 829 seq_printf(seq, "NIC B/s: %10llu %10llu %10llu %10llu\n", 830 (unsigned long long)nrate[0], 831 (unsigned long long)nrate[1], 832 (unsigned long long)nrate[2], 833 (unsigned long long)nrate[3]); 834 seq_printf(seq, "Offload B/s: %10llu %10llu %10llu %10llu\n", 835 (unsigned long long)orate[0], 836 (unsigned long long)orate[1], 837 (unsigned long long)orate[2], 838 (unsigned long long)orate[3]); 839 } else { 840 seq_puts(seq, " channel 0 channel 1\n"); 841 seq_printf(seq, "NIC B/s: %10llu %10llu\n", 842 (unsigned long long)nrate[0], 843 (unsigned long long)nrate[1]); 844 seq_printf(seq, "Offload B/s: %10llu %10llu\n", 845 (unsigned long long)orate[0], 846 (unsigned long long)orate[1]); 847 } 848 return 0; 849 } 850 DEFINE_SHOW_ATTRIBUTE(tx_rate); 851 852 static int cctrl_tbl_show(struct seq_file *seq, void *v) 853 { 854 static const char * const dec_fac[] = { 855 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 856 "0.9375" }; 857 858 int i; 859 u16 (*incr)[NCCTRL_WIN]; 860 struct adapter *adap = seq->private; 861 862 incr = kmalloc_array(NMTUS, sizeof(*incr), GFP_KERNEL); 863 if (!incr) 864 return -ENOMEM; 865 866 t4_read_cong_tbl(adap, incr); 867 868 for (i = 0; i < NCCTRL_WIN; ++i) { 869 seq_printf(seq, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 870 incr[0][i], incr[1][i], incr[2][i], incr[3][i], 871 incr[4][i], incr[5][i], incr[6][i], incr[7][i]); 872 seq_printf(seq, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 873 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 874 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 875 adap->params.a_wnd[i], 876 dec_fac[adap->params.b_wnd[i]]); 877 } 878 879 kfree(incr); 880 return 0; 881 } 882 DEFINE_SHOW_ATTRIBUTE(cctrl_tbl); 883 884 /* Format a value in a unit that differs from the value's native unit by the 885 * given factor. 886 */ 887 static char *unit_conv(char *buf, size_t len, unsigned int val, 888 unsigned int factor) 889 { 890 unsigned int rem = val % factor; 891 892 if (rem == 0) { 893 snprintf(buf, len, "%u", val / factor); 894 } else { 895 while (rem % 10 == 0) 896 rem /= 10; 897 snprintf(buf, len, "%u.%u", val / factor, rem); 898 } 899 return buf; 900 } 901 902 static int clk_show(struct seq_file *seq, void *v) 903 { 904 char buf[32]; 905 struct adapter *adap = seq->private; 906 unsigned int cclk_ps = 1000000000 / adap->params.vpd.cclk; /* in ps */ 907 u32 res = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); 908 unsigned int tre = TIMERRESOLUTION_G(res); 909 unsigned int dack_re = DELAYEDACKRESOLUTION_G(res); 910 unsigned long long tp_tick_us = (cclk_ps << tre) / 1000000; /* in us */ 911 912 seq_printf(seq, "Core clock period: %s ns\n", 913 unit_conv(buf, sizeof(buf), cclk_ps, 1000)); 914 seq_printf(seq, "TP timer tick: %s us\n", 915 unit_conv(buf, sizeof(buf), (cclk_ps << tre), 1000000)); 916 seq_printf(seq, "TCP timestamp tick: %s us\n", 917 unit_conv(buf, sizeof(buf), 918 (cclk_ps << TIMESTAMPRESOLUTION_G(res)), 1000000)); 919 seq_printf(seq, "DACK tick: %s us\n", 920 unit_conv(buf, sizeof(buf), (cclk_ps << dack_re), 1000000)); 921 seq_printf(seq, "DACK timer: %u us\n", 922 ((cclk_ps << dack_re) / 1000000) * 923 t4_read_reg(adap, TP_DACK_TIMER_A)); 924 seq_printf(seq, "Retransmit min: %llu us\n", 925 tp_tick_us * t4_read_reg(adap, TP_RXT_MIN_A)); 926 seq_printf(seq, "Retransmit max: %llu us\n", 927 tp_tick_us * t4_read_reg(adap, TP_RXT_MAX_A)); 928 seq_printf(seq, "Persist timer min: %llu us\n", 929 tp_tick_us * t4_read_reg(adap, TP_PERS_MIN_A)); 930 seq_printf(seq, "Persist timer max: %llu us\n", 931 tp_tick_us * t4_read_reg(adap, TP_PERS_MAX_A)); 932 seq_printf(seq, "Keepalive idle timer: %llu us\n", 933 tp_tick_us * t4_read_reg(adap, TP_KEEP_IDLE_A)); 934 seq_printf(seq, "Keepalive interval: %llu us\n", 935 tp_tick_us * t4_read_reg(adap, TP_KEEP_INTVL_A)); 936 seq_printf(seq, "Initial SRTT: %llu us\n", 937 tp_tick_us * INITSRTT_G(t4_read_reg(adap, TP_INIT_SRTT_A))); 938 seq_printf(seq, "FINWAIT2 timer: %llu us\n", 939 tp_tick_us * t4_read_reg(adap, TP_FINWAIT2_TIMER_A)); 940 941 return 0; 942 } 943 DEFINE_SHOW_ATTRIBUTE(clk); 944 945 /* Firmware Device Log dump. */ 946 static const char * const devlog_level_strings[] = { 947 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 948 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 949 [FW_DEVLOG_LEVEL_ERR] = "ERR", 950 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 951 [FW_DEVLOG_LEVEL_INFO] = "INFO", 952 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 953 }; 954 955 static const char * const devlog_facility_strings[] = { 956 [FW_DEVLOG_FACILITY_CORE] = "CORE", 957 [FW_DEVLOG_FACILITY_CF] = "CF", 958 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 959 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 960 [FW_DEVLOG_FACILITY_RES] = "RES", 961 [FW_DEVLOG_FACILITY_HW] = "HW", 962 [FW_DEVLOG_FACILITY_FLR] = "FLR", 963 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 964 [FW_DEVLOG_FACILITY_PHY] = "PHY", 965 [FW_DEVLOG_FACILITY_MAC] = "MAC", 966 [FW_DEVLOG_FACILITY_PORT] = "PORT", 967 [FW_DEVLOG_FACILITY_VI] = "VI", 968 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 969 [FW_DEVLOG_FACILITY_ACL] = "ACL", 970 [FW_DEVLOG_FACILITY_TM] = "TM", 971 [FW_DEVLOG_FACILITY_QFC] = "QFC", 972 [FW_DEVLOG_FACILITY_DCB] = "DCB", 973 [FW_DEVLOG_FACILITY_ETH] = "ETH", 974 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 975 [FW_DEVLOG_FACILITY_RI] = "RI", 976 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 977 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 978 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 979 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE" 980 }; 981 982 /* Information gathered by Device Log Open routine for the display routine. 983 */ 984 struct devlog_info { 985 unsigned int nentries; /* number of entries in log[] */ 986 unsigned int first; /* first [temporal] entry in log[] */ 987 struct fw_devlog_e log[0]; /* Firmware Device Log */ 988 }; 989 990 /* Dump a Firmaware Device Log entry. 991 */ 992 static int devlog_show(struct seq_file *seq, void *v) 993 { 994 if (v == SEQ_START_TOKEN) 995 seq_printf(seq, "%10s %15s %8s %8s %s\n", 996 "Seq#", "Tstamp", "Level", "Facility", "Message"); 997 else { 998 struct devlog_info *dinfo = seq->private; 999 int fidx = (uintptr_t)v - 2; 1000 unsigned long index; 1001 struct fw_devlog_e *e; 1002 1003 /* Get a pointer to the log entry to display. Skip unused log 1004 * entries. 1005 */ 1006 index = dinfo->first + fidx; 1007 if (index >= dinfo->nentries) 1008 index -= dinfo->nentries; 1009 e = &dinfo->log[index]; 1010 if (e->timestamp == 0) 1011 return 0; 1012 1013 /* Print the message. This depends on the firmware using 1014 * exactly the same formating strings as the kernel so we may 1015 * eventually have to put a format interpreter in here ... 1016 */ 1017 seq_printf(seq, "%10d %15llu %8s %8s ", 1018 be32_to_cpu(e->seqno), 1019 be64_to_cpu(e->timestamp), 1020 (e->level < ARRAY_SIZE(devlog_level_strings) 1021 ? devlog_level_strings[e->level] 1022 : "UNKNOWN"), 1023 (e->facility < ARRAY_SIZE(devlog_facility_strings) 1024 ? devlog_facility_strings[e->facility] 1025 : "UNKNOWN")); 1026 seq_printf(seq, e->fmt, 1027 be32_to_cpu(e->params[0]), 1028 be32_to_cpu(e->params[1]), 1029 be32_to_cpu(e->params[2]), 1030 be32_to_cpu(e->params[3]), 1031 be32_to_cpu(e->params[4]), 1032 be32_to_cpu(e->params[5]), 1033 be32_to_cpu(e->params[6]), 1034 be32_to_cpu(e->params[7])); 1035 } 1036 return 0; 1037 } 1038 1039 /* Sequential File Operations for Device Log. 1040 */ 1041 static inline void *devlog_get_idx(struct devlog_info *dinfo, loff_t pos) 1042 { 1043 if (pos > dinfo->nentries) 1044 return NULL; 1045 1046 return (void *)(uintptr_t)(pos + 1); 1047 } 1048 1049 static void *devlog_start(struct seq_file *seq, loff_t *pos) 1050 { 1051 struct devlog_info *dinfo = seq->private; 1052 1053 return (*pos 1054 ? devlog_get_idx(dinfo, *pos) 1055 : SEQ_START_TOKEN); 1056 } 1057 1058 static void *devlog_next(struct seq_file *seq, void *v, loff_t *pos) 1059 { 1060 struct devlog_info *dinfo = seq->private; 1061 1062 (*pos)++; 1063 return devlog_get_idx(dinfo, *pos); 1064 } 1065 1066 static void devlog_stop(struct seq_file *seq, void *v) 1067 { 1068 } 1069 1070 static const struct seq_operations devlog_seq_ops = { 1071 .start = devlog_start, 1072 .next = devlog_next, 1073 .stop = devlog_stop, 1074 .show = devlog_show 1075 }; 1076 1077 /* Set up for reading the firmware's device log. We read the entire log here 1078 * and then display it incrementally in devlog_show(). 1079 */ 1080 static int devlog_open(struct inode *inode, struct file *file) 1081 { 1082 struct adapter *adap = inode->i_private; 1083 struct devlog_params *dparams = &adap->params.devlog; 1084 struct devlog_info *dinfo; 1085 unsigned int index; 1086 u32 fseqno; 1087 int ret; 1088 1089 /* If we don't know where the log is we can't do anything. 1090 */ 1091 if (dparams->start == 0) 1092 return -ENXIO; 1093 1094 /* Allocate the space to read in the firmware's device log and set up 1095 * for the iterated call to our display function. 1096 */ 1097 dinfo = __seq_open_private(file, &devlog_seq_ops, 1098 sizeof(*dinfo) + dparams->size); 1099 if (!dinfo) 1100 return -ENOMEM; 1101 1102 /* Record the basic log buffer information and read in the raw log. 1103 */ 1104 dinfo->nentries = (dparams->size / sizeof(struct fw_devlog_e)); 1105 dinfo->first = 0; 1106 spin_lock(&adap->win0_lock); 1107 ret = t4_memory_rw(adap, adap->params.drv_memwin, dparams->memtype, 1108 dparams->start, dparams->size, (__be32 *)dinfo->log, 1109 T4_MEMORY_READ); 1110 spin_unlock(&adap->win0_lock); 1111 if (ret) { 1112 seq_release_private(inode, file); 1113 return ret; 1114 } 1115 1116 /* Find the earliest (lowest Sequence Number) log entry in the 1117 * circular Device Log. 1118 */ 1119 for (fseqno = ~((u32)0), index = 0; index < dinfo->nentries; index++) { 1120 struct fw_devlog_e *e = &dinfo->log[index]; 1121 __u32 seqno; 1122 1123 if (e->timestamp == 0) 1124 continue; 1125 1126 seqno = be32_to_cpu(e->seqno); 1127 if (seqno < fseqno) { 1128 fseqno = seqno; 1129 dinfo->first = index; 1130 } 1131 } 1132 return 0; 1133 } 1134 1135 static const struct file_operations devlog_fops = { 1136 .owner = THIS_MODULE, 1137 .open = devlog_open, 1138 .read = seq_read, 1139 .llseek = seq_lseek, 1140 .release = seq_release_private 1141 }; 1142 1143 /* Show Firmware Mailbox Command/Reply Log 1144 * 1145 * Note that we don't do any locking when dumping the Firmware Mailbox Log so 1146 * it's possible that we can catch things during a log update and therefore 1147 * see partially corrupted log entries. But it's probably Good Enough(tm). 1148 * If we ever decide that we want to make sure that we're dumping a coherent 1149 * log, we'd need to perform locking in the mailbox logging and in 1150 * mboxlog_open() where we'd need to grab the entire mailbox log in one go 1151 * like we do for the Firmware Device Log. 1152 */ 1153 static int mboxlog_show(struct seq_file *seq, void *v) 1154 { 1155 struct adapter *adapter = seq->private; 1156 struct mbox_cmd_log *log = adapter->mbox_log; 1157 struct mbox_cmd *entry; 1158 int entry_idx, i; 1159 1160 if (v == SEQ_START_TOKEN) { 1161 seq_printf(seq, 1162 "%10s %15s %5s %5s %s\n", 1163 "Seq#", "Tstamp", "Atime", "Etime", 1164 "Command/Reply"); 1165 return 0; 1166 } 1167 1168 entry_idx = log->cursor + ((uintptr_t)v - 2); 1169 if (entry_idx >= log->size) 1170 entry_idx -= log->size; 1171 entry = mbox_cmd_log_entry(log, entry_idx); 1172 1173 /* skip over unused entries */ 1174 if (entry->timestamp == 0) 1175 return 0; 1176 1177 seq_printf(seq, "%10u %15llu %5d %5d", 1178 entry->seqno, entry->timestamp, 1179 entry->access, entry->execute); 1180 for (i = 0; i < MBOX_LEN / 8; i++) { 1181 u64 flit = entry->cmd[i]; 1182 u32 hi = (u32)(flit >> 32); 1183 u32 lo = (u32)flit; 1184 1185 seq_printf(seq, " %08x %08x", hi, lo); 1186 } 1187 seq_puts(seq, "\n"); 1188 return 0; 1189 } 1190 1191 static inline void *mboxlog_get_idx(struct seq_file *seq, loff_t pos) 1192 { 1193 struct adapter *adapter = seq->private; 1194 struct mbox_cmd_log *log = adapter->mbox_log; 1195 1196 return ((pos <= log->size) ? (void *)(uintptr_t)(pos + 1) : NULL); 1197 } 1198 1199 static void *mboxlog_start(struct seq_file *seq, loff_t *pos) 1200 { 1201 return *pos ? mboxlog_get_idx(seq, *pos) : SEQ_START_TOKEN; 1202 } 1203 1204 static void *mboxlog_next(struct seq_file *seq, void *v, loff_t *pos) 1205 { 1206 ++*pos; 1207 return mboxlog_get_idx(seq, *pos); 1208 } 1209 1210 static void mboxlog_stop(struct seq_file *seq, void *v) 1211 { 1212 } 1213 1214 static const struct seq_operations mboxlog_seq_ops = { 1215 .start = mboxlog_start, 1216 .next = mboxlog_next, 1217 .stop = mboxlog_stop, 1218 .show = mboxlog_show 1219 }; 1220 1221 static int mboxlog_open(struct inode *inode, struct file *file) 1222 { 1223 int res = seq_open(file, &mboxlog_seq_ops); 1224 1225 if (!res) { 1226 struct seq_file *seq = file->private_data; 1227 1228 seq->private = inode->i_private; 1229 } 1230 return res; 1231 } 1232 1233 static const struct file_operations mboxlog_fops = { 1234 .owner = THIS_MODULE, 1235 .open = mboxlog_open, 1236 .read = seq_read, 1237 .llseek = seq_lseek, 1238 .release = seq_release, 1239 }; 1240 1241 static int mbox_show(struct seq_file *seq, void *v) 1242 { 1243 static const char * const owner[] = { "none", "FW", "driver", 1244 "unknown", "<unread>" }; 1245 1246 int i; 1247 unsigned int mbox = (uintptr_t)seq->private & 7; 1248 struct adapter *adap = seq->private - mbox; 1249 void __iomem *addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A); 1250 1251 /* For T4 we don't have a shadow copy of the Mailbox Control register. 1252 * And since reading that real register causes a side effect of 1253 * granting ownership, we're best of simply not reading it at all. 1254 */ 1255 if (is_t4(adap->params.chip)) { 1256 i = 4; /* index of "<unread>" */ 1257 } else { 1258 unsigned int ctrl_reg = CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A; 1259 void __iomem *ctrl = adap->regs + PF_REG(mbox, ctrl_reg); 1260 1261 i = MBOWNER_G(readl(ctrl)); 1262 } 1263 1264 seq_printf(seq, "mailbox owned by %s\n\n", owner[i]); 1265 1266 for (i = 0; i < MBOX_LEN; i += 8) 1267 seq_printf(seq, "%016llx\n", 1268 (unsigned long long)readq(addr + i)); 1269 return 0; 1270 } 1271 1272 static int mbox_open(struct inode *inode, struct file *file) 1273 { 1274 return single_open(file, mbox_show, inode->i_private); 1275 } 1276 1277 static ssize_t mbox_write(struct file *file, const char __user *buf, 1278 size_t count, loff_t *pos) 1279 { 1280 int i; 1281 char c = '\n', s[256]; 1282 unsigned long long data[8]; 1283 const struct inode *ino; 1284 unsigned int mbox; 1285 struct adapter *adap; 1286 void __iomem *addr; 1287 void __iomem *ctrl; 1288 1289 if (count > sizeof(s) - 1 || !count) 1290 return -EINVAL; 1291 if (copy_from_user(s, buf, count)) 1292 return -EFAULT; 1293 s[count] = '\0'; 1294 1295 if (sscanf(s, "%llx %llx %llx %llx %llx %llx %llx %llx%c", &data[0], 1296 &data[1], &data[2], &data[3], &data[4], &data[5], &data[6], 1297 &data[7], &c) < 8 || c != '\n') 1298 return -EINVAL; 1299 1300 ino = file_inode(file); 1301 mbox = (uintptr_t)ino->i_private & 7; 1302 adap = ino->i_private - mbox; 1303 addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A); 1304 ctrl = addr + MBOX_LEN; 1305 1306 if (MBOWNER_G(readl(ctrl)) != X_MBOWNER_PL) 1307 return -EBUSY; 1308 1309 for (i = 0; i < 8; i++) 1310 writeq(data[i], addr + 8 * i); 1311 1312 writel(MBMSGVALID_F | MBOWNER_V(X_MBOWNER_FW), ctrl); 1313 return count; 1314 } 1315 1316 static const struct file_operations mbox_debugfs_fops = { 1317 .owner = THIS_MODULE, 1318 .open = mbox_open, 1319 .read = seq_read, 1320 .llseek = seq_lseek, 1321 .release = single_release, 1322 .write = mbox_write 1323 }; 1324 1325 static int mps_trc_show(struct seq_file *seq, void *v) 1326 { 1327 int enabled, i; 1328 struct trace_params tp; 1329 unsigned int trcidx = (uintptr_t)seq->private & 3; 1330 struct adapter *adap = seq->private - trcidx; 1331 1332 t4_get_trace_filter(adap, &tp, trcidx, &enabled); 1333 if (!enabled) { 1334 seq_puts(seq, "tracer is disabled\n"); 1335 return 0; 1336 } 1337 1338 if (tp.skip_ofst * 8 >= TRACE_LEN) { 1339 dev_err(adap->pdev_dev, "illegal trace pattern skip offset\n"); 1340 return -EINVAL; 1341 } 1342 if (tp.port < 8) { 1343 i = adap->chan_map[tp.port & 3]; 1344 if (i >= MAX_NPORTS) { 1345 dev_err(adap->pdev_dev, "tracer %u is assigned " 1346 "to non-existing port\n", trcidx); 1347 return -EINVAL; 1348 } 1349 seq_printf(seq, "tracer is capturing %s %s, ", 1350 adap->port[i]->name, tp.port < 4 ? "Rx" : "Tx"); 1351 } else 1352 seq_printf(seq, "tracer is capturing loopback %d, ", 1353 tp.port - 8); 1354 seq_printf(seq, "snap length: %u, min length: %u\n", tp.snap_len, 1355 tp.min_len); 1356 seq_printf(seq, "packets captured %smatch filter\n", 1357 tp.invert ? "do not " : ""); 1358 1359 if (tp.skip_ofst) { 1360 seq_puts(seq, "filter pattern: "); 1361 for (i = 0; i < tp.skip_ofst * 2; i += 2) 1362 seq_printf(seq, "%08x%08x", tp.data[i], tp.data[i + 1]); 1363 seq_putc(seq, '/'); 1364 for (i = 0; i < tp.skip_ofst * 2; i += 2) 1365 seq_printf(seq, "%08x%08x", tp.mask[i], tp.mask[i + 1]); 1366 seq_puts(seq, "@0\n"); 1367 } 1368 1369 seq_puts(seq, "filter pattern: "); 1370 for (i = tp.skip_ofst * 2; i < TRACE_LEN / 4; i += 2) 1371 seq_printf(seq, "%08x%08x", tp.data[i], tp.data[i + 1]); 1372 seq_putc(seq, '/'); 1373 for (i = tp.skip_ofst * 2; i < TRACE_LEN / 4; i += 2) 1374 seq_printf(seq, "%08x%08x", tp.mask[i], tp.mask[i + 1]); 1375 seq_printf(seq, "@%u\n", (tp.skip_ofst + tp.skip_len) * 8); 1376 return 0; 1377 } 1378 1379 static int mps_trc_open(struct inode *inode, struct file *file) 1380 { 1381 return single_open(file, mps_trc_show, inode->i_private); 1382 } 1383 1384 static unsigned int xdigit2int(unsigned char c) 1385 { 1386 return isdigit(c) ? c - '0' : tolower(c) - 'a' + 10; 1387 } 1388 1389 #define TRC_PORT_NONE 0xff 1390 #define TRC_RSS_ENABLE 0x33 1391 #define TRC_RSS_DISABLE 0x13 1392 1393 /* Set an MPS trace filter. Syntax is: 1394 * 1395 * disable 1396 * 1397 * to disable tracing, or 1398 * 1399 * interface qid=<qid no> [snaplen=<val>] [minlen=<val>] [not] [<pattern>]... 1400 * 1401 * where interface is one of rxN, txN, or loopbackN, N = 0..3, qid can be one 1402 * of the NIC's response qid obtained from sge_qinfo and pattern has the form 1403 * 1404 * <pattern data>[/<pattern mask>][@<anchor>] 1405 * 1406 * Up to 2 filter patterns can be specified. If 2 are supplied the first one 1407 * must be anchored at 0. An omitted mask is taken as a mask of 1s, an omitted 1408 * anchor is taken as 0. 1409 */ 1410 static ssize_t mps_trc_write(struct file *file, const char __user *buf, 1411 size_t count, loff_t *pos) 1412 { 1413 int i, enable, ret; 1414 u32 *data, *mask; 1415 struct trace_params tp; 1416 const struct inode *ino; 1417 unsigned int trcidx; 1418 char *s, *p, *word, *end; 1419 struct adapter *adap; 1420 u32 j; 1421 1422 ino = file_inode(file); 1423 trcidx = (uintptr_t)ino->i_private & 3; 1424 adap = ino->i_private - trcidx; 1425 1426 /* Don't accept input more than 1K, can't be anything valid except lots 1427 * of whitespace. Well, use less. 1428 */ 1429 if (count > 1024) 1430 return -EFBIG; 1431 p = s = kzalloc(count + 1, GFP_USER); 1432 if (!s) 1433 return -ENOMEM; 1434 if (copy_from_user(s, buf, count)) { 1435 count = -EFAULT; 1436 goto out; 1437 } 1438 1439 if (s[count - 1] == '\n') 1440 s[count - 1] = '\0'; 1441 1442 enable = strcmp("disable", s) != 0; 1443 if (!enable) 1444 goto apply; 1445 1446 /* enable or disable trace multi rss filter */ 1447 if (adap->trace_rss) 1448 t4_write_reg(adap, MPS_TRC_CFG_A, TRC_RSS_ENABLE); 1449 else 1450 t4_write_reg(adap, MPS_TRC_CFG_A, TRC_RSS_DISABLE); 1451 1452 memset(&tp, 0, sizeof(tp)); 1453 tp.port = TRC_PORT_NONE; 1454 i = 0; /* counts pattern nibbles */ 1455 1456 while (p) { 1457 while (isspace(*p)) 1458 p++; 1459 word = strsep(&p, " "); 1460 if (!*word) 1461 break; 1462 1463 if (!strncmp(word, "qid=", 4)) { 1464 end = (char *)word + 4; 1465 ret = kstrtouint(end, 10, &j); 1466 if (ret) 1467 goto out; 1468 if (!adap->trace_rss) { 1469 t4_write_reg(adap, MPS_T5_TRC_RSS_CONTROL_A, j); 1470 continue; 1471 } 1472 1473 switch (trcidx) { 1474 case 0: 1475 t4_write_reg(adap, MPS_TRC_RSS_CONTROL_A, j); 1476 break; 1477 case 1: 1478 t4_write_reg(adap, 1479 MPS_TRC_FILTER1_RSS_CONTROL_A, j); 1480 break; 1481 case 2: 1482 t4_write_reg(adap, 1483 MPS_TRC_FILTER2_RSS_CONTROL_A, j); 1484 break; 1485 case 3: 1486 t4_write_reg(adap, 1487 MPS_TRC_FILTER3_RSS_CONTROL_A, j); 1488 break; 1489 } 1490 continue; 1491 } 1492 if (!strncmp(word, "snaplen=", 8)) { 1493 end = (char *)word + 8; 1494 ret = kstrtouint(end, 10, &j); 1495 if (ret || j > 9600) { 1496 inval: count = -EINVAL; 1497 goto out; 1498 } 1499 tp.snap_len = j; 1500 continue; 1501 } 1502 if (!strncmp(word, "minlen=", 7)) { 1503 end = (char *)word + 7; 1504 ret = kstrtouint(end, 10, &j); 1505 if (ret || j > TFMINPKTSIZE_M) 1506 goto inval; 1507 tp.min_len = j; 1508 continue; 1509 } 1510 if (!strcmp(word, "not")) { 1511 tp.invert = !tp.invert; 1512 continue; 1513 } 1514 if (!strncmp(word, "loopback", 8) && tp.port == TRC_PORT_NONE) { 1515 if (word[8] < '0' || word[8] > '3' || word[9]) 1516 goto inval; 1517 tp.port = word[8] - '0' + 8; 1518 continue; 1519 } 1520 if (!strncmp(word, "tx", 2) && tp.port == TRC_PORT_NONE) { 1521 if (word[2] < '0' || word[2] > '3' || word[3]) 1522 goto inval; 1523 tp.port = word[2] - '0' + 4; 1524 if (adap->chan_map[tp.port & 3] >= MAX_NPORTS) 1525 goto inval; 1526 continue; 1527 } 1528 if (!strncmp(word, "rx", 2) && tp.port == TRC_PORT_NONE) { 1529 if (word[2] < '0' || word[2] > '3' || word[3]) 1530 goto inval; 1531 tp.port = word[2] - '0'; 1532 if (adap->chan_map[tp.port] >= MAX_NPORTS) 1533 goto inval; 1534 continue; 1535 } 1536 if (!isxdigit(*word)) 1537 goto inval; 1538 1539 /* we have found a trace pattern */ 1540 if (i) { /* split pattern */ 1541 if (tp.skip_len) /* too many splits */ 1542 goto inval; 1543 tp.skip_ofst = i / 16; 1544 } 1545 1546 data = &tp.data[i / 8]; 1547 mask = &tp.mask[i / 8]; 1548 j = i; 1549 1550 while (isxdigit(*word)) { 1551 if (i >= TRACE_LEN * 2) { 1552 count = -EFBIG; 1553 goto out; 1554 } 1555 *data = (*data << 4) + xdigit2int(*word++); 1556 if (++i % 8 == 0) 1557 data++; 1558 } 1559 if (*word == '/') { 1560 word++; 1561 while (isxdigit(*word)) { 1562 if (j >= i) /* mask longer than data */ 1563 goto inval; 1564 *mask = (*mask << 4) + xdigit2int(*word++); 1565 if (++j % 8 == 0) 1566 mask++; 1567 } 1568 if (i != j) /* mask shorter than data */ 1569 goto inval; 1570 } else { /* no mask, use all 1s */ 1571 for ( ; i - j >= 8; j += 8) 1572 *mask++ = 0xffffffff; 1573 if (i % 8) 1574 *mask = (1 << (i % 8) * 4) - 1; 1575 } 1576 if (*word == '@') { 1577 end = (char *)word + 1; 1578 ret = kstrtouint(end, 10, &j); 1579 if (*end && *end != '\n') 1580 goto inval; 1581 if (j & 7) /* doesn't start at multiple of 8 */ 1582 goto inval; 1583 j /= 8; 1584 if (j < tp.skip_ofst) /* overlaps earlier pattern */ 1585 goto inval; 1586 if (j - tp.skip_ofst > 31) /* skip too big */ 1587 goto inval; 1588 tp.skip_len = j - tp.skip_ofst; 1589 } 1590 if (i % 8) { 1591 *data <<= (8 - i % 8) * 4; 1592 *mask <<= (8 - i % 8) * 4; 1593 i = (i + 15) & ~15; /* 8-byte align */ 1594 } 1595 } 1596 1597 if (tp.port == TRC_PORT_NONE) 1598 goto inval; 1599 1600 apply: 1601 i = t4_set_trace_filter(adap, &tp, trcidx, enable); 1602 if (i) 1603 count = i; 1604 out: 1605 kfree(s); 1606 return count; 1607 } 1608 1609 static const struct file_operations mps_trc_debugfs_fops = { 1610 .owner = THIS_MODULE, 1611 .open = mps_trc_open, 1612 .read = seq_read, 1613 .llseek = seq_lseek, 1614 .release = single_release, 1615 .write = mps_trc_write 1616 }; 1617 1618 static ssize_t flash_read(struct file *file, char __user *buf, size_t count, 1619 loff_t *ppos) 1620 { 1621 loff_t pos = *ppos; 1622 loff_t avail = file_inode(file)->i_size; 1623 struct adapter *adap = file->private_data; 1624 1625 if (pos < 0) 1626 return -EINVAL; 1627 if (pos >= avail) 1628 return 0; 1629 if (count > avail - pos) 1630 count = avail - pos; 1631 1632 while (count) { 1633 size_t len; 1634 int ret, ofst; 1635 u8 data[256]; 1636 1637 ofst = pos & 3; 1638 len = min(count + ofst, sizeof(data)); 1639 ret = t4_read_flash(adap, pos - ofst, (len + 3) / 4, 1640 (u32 *)data, 1); 1641 if (ret) 1642 return ret; 1643 1644 len -= ofst; 1645 if (copy_to_user(buf, data + ofst, len)) 1646 return -EFAULT; 1647 1648 buf += len; 1649 pos += len; 1650 count -= len; 1651 } 1652 count = pos - *ppos; 1653 *ppos = pos; 1654 return count; 1655 } 1656 1657 static const struct file_operations flash_debugfs_fops = { 1658 .owner = THIS_MODULE, 1659 .open = mem_open, 1660 .read = flash_read, 1661 .llseek = default_llseek, 1662 }; 1663 1664 static inline void tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask) 1665 { 1666 *mask = x | y; 1667 y = (__force u64)cpu_to_be64(y); 1668 memcpy(addr, (char *)&y + 2, ETH_ALEN); 1669 } 1670 1671 static int mps_tcam_show(struct seq_file *seq, void *v) 1672 { 1673 struct adapter *adap = seq->private; 1674 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip); 1675 if (v == SEQ_START_TOKEN) { 1676 if (chip_ver > CHELSIO_T5) { 1677 seq_puts(seq, "Idx Ethernet address Mask " 1678 " VNI Mask IVLAN Vld " 1679 "DIP_Hit Lookup Port " 1680 "Vld Ports PF VF " 1681 "Replication " 1682 " P0 P1 P2 P3 ML\n"); 1683 } else { 1684 if (adap->params.arch.mps_rplc_size > 128) 1685 seq_puts(seq, "Idx Ethernet address Mask " 1686 "Vld Ports PF VF " 1687 "Replication " 1688 " P0 P1 P2 P3 ML\n"); 1689 else 1690 seq_puts(seq, "Idx Ethernet address Mask " 1691 "Vld Ports PF VF Replication" 1692 " P0 P1 P2 P3 ML\n"); 1693 } 1694 } else { 1695 u64 mask; 1696 u8 addr[ETH_ALEN]; 1697 bool replicate, dip_hit = false, vlan_vld = false; 1698 unsigned int idx = (uintptr_t)v - 2; 1699 u64 tcamy, tcamx, val; 1700 u32 cls_lo, cls_hi, ctl, data2, vnix = 0, vniy = 0; 1701 u32 rplc[8] = {0}; 1702 u8 lookup_type = 0, port_num = 0; 1703 u16 ivlan = 0; 1704 1705 if (chip_ver > CHELSIO_T5) { 1706 /* CtlCmdType - 0: Read, 1: Write 1707 * CtlTcamSel - 0: TCAM0, 1: TCAM1 1708 * CtlXYBitSel- 0: Y bit, 1: X bit 1709 */ 1710 1711 /* Read tcamy */ 1712 ctl = CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0); 1713 if (idx < 256) 1714 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0); 1715 else 1716 ctl |= CTLTCAMINDEX_V(idx - 256) | 1717 CTLTCAMSEL_V(1); 1718 t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1719 val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A); 1720 tcamy = DMACH_G(val) << 32; 1721 tcamy |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A); 1722 data2 = t4_read_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A); 1723 lookup_type = DATALKPTYPE_G(data2); 1724 /* 0 - Outer header, 1 - Inner header 1725 * [71:48] bit locations are overloaded for 1726 * outer vs. inner lookup types. 1727 */ 1728 if (lookup_type && (lookup_type != DATALKPTYPE_M)) { 1729 /* Inner header VNI */ 1730 vniy = (data2 & DATAVIDH2_F) | 1731 (DATAVIDH1_G(data2) << 16) | VIDL_G(val); 1732 dip_hit = data2 & DATADIPHIT_F; 1733 } else { 1734 vlan_vld = data2 & DATAVIDH2_F; 1735 ivlan = VIDL_G(val); 1736 } 1737 port_num = DATAPORTNUM_G(data2); 1738 1739 /* Read tcamx. Change the control param */ 1740 vnix = 0; 1741 ctl |= CTLXYBITSEL_V(1); 1742 t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1743 val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A); 1744 tcamx = DMACH_G(val) << 32; 1745 tcamx |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A); 1746 data2 = t4_read_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A); 1747 if (lookup_type && (lookup_type != DATALKPTYPE_M)) { 1748 /* Inner header VNI mask */ 1749 vnix = (data2 & DATAVIDH2_F) | 1750 (DATAVIDH1_G(data2) << 16) | VIDL_G(val); 1751 } 1752 } else { 1753 tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx)); 1754 tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx)); 1755 } 1756 1757 cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx)); 1758 cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx)); 1759 1760 if (tcamx & tcamy) { 1761 seq_printf(seq, "%3u -\n", idx); 1762 goto out; 1763 } 1764 1765 rplc[0] = rplc[1] = rplc[2] = rplc[3] = 0; 1766 if (chip_ver > CHELSIO_T5) 1767 replicate = (cls_lo & T6_REPLICATE_F); 1768 else 1769 replicate = (cls_lo & REPLICATE_F); 1770 1771 if (replicate) { 1772 struct fw_ldst_cmd ldst_cmd; 1773 int ret; 1774 struct fw_ldst_mps_rplc mps_rplc; 1775 u32 ldst_addrspc; 1776 1777 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 1778 ldst_addrspc = 1779 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS); 1780 ldst_cmd.op_to_addrspace = 1781 htonl(FW_CMD_OP_V(FW_LDST_CMD) | 1782 FW_CMD_REQUEST_F | 1783 FW_CMD_READ_F | 1784 ldst_addrspc); 1785 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd)); 1786 ldst_cmd.u.mps.rplc.fid_idx = 1787 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) | 1788 FW_LDST_CMD_IDX_V(idx)); 1789 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, 1790 sizeof(ldst_cmd), &ldst_cmd); 1791 if (ret) 1792 dev_warn(adap->pdev_dev, "Can't read MPS " 1793 "replication map for idx %d: %d\n", 1794 idx, -ret); 1795 else { 1796 mps_rplc = ldst_cmd.u.mps.rplc; 1797 rplc[0] = ntohl(mps_rplc.rplc31_0); 1798 rplc[1] = ntohl(mps_rplc.rplc63_32); 1799 rplc[2] = ntohl(mps_rplc.rplc95_64); 1800 rplc[3] = ntohl(mps_rplc.rplc127_96); 1801 if (adap->params.arch.mps_rplc_size > 128) { 1802 rplc[4] = ntohl(mps_rplc.rplc159_128); 1803 rplc[5] = ntohl(mps_rplc.rplc191_160); 1804 rplc[6] = ntohl(mps_rplc.rplc223_192); 1805 rplc[7] = ntohl(mps_rplc.rplc255_224); 1806 } 1807 } 1808 } 1809 1810 tcamxy2valmask(tcamx, tcamy, addr, &mask); 1811 if (chip_ver > CHELSIO_T5) { 1812 /* Inner header lookup */ 1813 if (lookup_type && (lookup_type != DATALKPTYPE_M)) { 1814 seq_printf(seq, 1815 "%3u %02x:%02x:%02x:%02x:%02x:%02x " 1816 "%012llx %06x %06x - - %3c" 1817 " 'I' %4x " 1818 "%3c %#x%4u%4d", idx, addr[0], 1819 addr[1], addr[2], addr[3], 1820 addr[4], addr[5], 1821 (unsigned long long)mask, 1822 vniy, (vnix | vniy), 1823 dip_hit ? 'Y' : 'N', 1824 port_num, 1825 (cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N', 1826 PORTMAP_G(cls_hi), 1827 T6_PF_G(cls_lo), 1828 (cls_lo & T6_VF_VALID_F) ? 1829 T6_VF_G(cls_lo) : -1); 1830 } else { 1831 seq_printf(seq, 1832 "%3u %02x:%02x:%02x:%02x:%02x:%02x " 1833 "%012llx - - ", 1834 idx, addr[0], addr[1], addr[2], 1835 addr[3], addr[4], addr[5], 1836 (unsigned long long)mask); 1837 1838 if (vlan_vld) 1839 seq_printf(seq, "%4u Y ", ivlan); 1840 else 1841 seq_puts(seq, " - N "); 1842 1843 seq_printf(seq, 1844 "- %3c %4x %3c %#x%4u%4d", 1845 lookup_type ? 'I' : 'O', port_num, 1846 (cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N', 1847 PORTMAP_G(cls_hi), 1848 T6_PF_G(cls_lo), 1849 (cls_lo & T6_VF_VALID_F) ? 1850 T6_VF_G(cls_lo) : -1); 1851 } 1852 } else 1853 seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x " 1854 "%012llx%3c %#x%4u%4d", 1855 idx, addr[0], addr[1], addr[2], addr[3], 1856 addr[4], addr[5], (unsigned long long)mask, 1857 (cls_lo & SRAM_VLD_F) ? 'Y' : 'N', 1858 PORTMAP_G(cls_hi), 1859 PF_G(cls_lo), 1860 (cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1); 1861 1862 if (replicate) { 1863 if (adap->params.arch.mps_rplc_size > 128) 1864 seq_printf(seq, " %08x %08x %08x %08x " 1865 "%08x %08x %08x %08x", 1866 rplc[7], rplc[6], rplc[5], rplc[4], 1867 rplc[3], rplc[2], rplc[1], rplc[0]); 1868 else 1869 seq_printf(seq, " %08x %08x %08x %08x", 1870 rplc[3], rplc[2], rplc[1], rplc[0]); 1871 } else { 1872 if (adap->params.arch.mps_rplc_size > 128) 1873 seq_printf(seq, "%72c", ' '); 1874 else 1875 seq_printf(seq, "%36c", ' '); 1876 } 1877 1878 if (chip_ver > CHELSIO_T5) 1879 seq_printf(seq, "%4u%3u%3u%3u %#x\n", 1880 T6_SRAM_PRIO0_G(cls_lo), 1881 T6_SRAM_PRIO1_G(cls_lo), 1882 T6_SRAM_PRIO2_G(cls_lo), 1883 T6_SRAM_PRIO3_G(cls_lo), 1884 (cls_lo >> T6_MULTILISTEN0_S) & 0xf); 1885 else 1886 seq_printf(seq, "%4u%3u%3u%3u %#x\n", 1887 SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo), 1888 SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo), 1889 (cls_lo >> MULTILISTEN0_S) & 0xf); 1890 } 1891 out: return 0; 1892 } 1893 1894 static inline void *mps_tcam_get_idx(struct seq_file *seq, loff_t pos) 1895 { 1896 struct adapter *adap = seq->private; 1897 int max_mac_addr = is_t4(adap->params.chip) ? 1898 NUM_MPS_CLS_SRAM_L_INSTANCES : 1899 NUM_MPS_T5_CLS_SRAM_L_INSTANCES; 1900 return ((pos <= max_mac_addr) ? (void *)(uintptr_t)(pos + 1) : NULL); 1901 } 1902 1903 static void *mps_tcam_start(struct seq_file *seq, loff_t *pos) 1904 { 1905 return *pos ? mps_tcam_get_idx(seq, *pos) : SEQ_START_TOKEN; 1906 } 1907 1908 static void *mps_tcam_next(struct seq_file *seq, void *v, loff_t *pos) 1909 { 1910 ++*pos; 1911 return mps_tcam_get_idx(seq, *pos); 1912 } 1913 1914 static void mps_tcam_stop(struct seq_file *seq, void *v) 1915 { 1916 } 1917 1918 static const struct seq_operations mps_tcam_seq_ops = { 1919 .start = mps_tcam_start, 1920 .next = mps_tcam_next, 1921 .stop = mps_tcam_stop, 1922 .show = mps_tcam_show 1923 }; 1924 1925 static int mps_tcam_open(struct inode *inode, struct file *file) 1926 { 1927 int res = seq_open(file, &mps_tcam_seq_ops); 1928 1929 if (!res) { 1930 struct seq_file *seq = file->private_data; 1931 1932 seq->private = inode->i_private; 1933 } 1934 return res; 1935 } 1936 1937 static const struct file_operations mps_tcam_debugfs_fops = { 1938 .owner = THIS_MODULE, 1939 .open = mps_tcam_open, 1940 .read = seq_read, 1941 .llseek = seq_lseek, 1942 .release = seq_release, 1943 }; 1944 1945 /* Display various sensor information. 1946 */ 1947 static int sensors_show(struct seq_file *seq, void *v) 1948 { 1949 struct adapter *adap = seq->private; 1950 u32 param[7], val[7]; 1951 int ret; 1952 1953 /* Note that if the sensors haven't been initialized and turned on 1954 * we'll get values of 0, so treat those as "<unknown>" ... 1955 */ 1956 param[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 1957 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DIAG) | 1958 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_DIAG_TMP)); 1959 param[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 1960 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DIAG) | 1961 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_DIAG_VDD)); 1962 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 1963 param, val); 1964 1965 if (ret < 0 || val[0] == 0) 1966 seq_puts(seq, "Temperature: <unknown>\n"); 1967 else 1968 seq_printf(seq, "Temperature: %dC\n", val[0]); 1969 1970 if (ret < 0 || val[1] == 0) 1971 seq_puts(seq, "Core VDD: <unknown>\n"); 1972 else 1973 seq_printf(seq, "Core VDD: %dmV\n", val[1]); 1974 1975 return 0; 1976 } 1977 DEFINE_SHOW_ATTRIBUTE(sensors); 1978 1979 #if IS_ENABLED(CONFIG_IPV6) 1980 DEFINE_SHOW_ATTRIBUTE(clip_tbl); 1981 #endif 1982 1983 /*RSS Table. 1984 */ 1985 1986 static int rss_show(struct seq_file *seq, void *v, int idx) 1987 { 1988 u16 *entry = v; 1989 1990 seq_printf(seq, "%4d: %4u %4u %4u %4u %4u %4u %4u %4u\n", 1991 idx * 8, entry[0], entry[1], entry[2], entry[3], entry[4], 1992 entry[5], entry[6], entry[7]); 1993 return 0; 1994 } 1995 1996 static int rss_open(struct inode *inode, struct file *file) 1997 { 1998 struct adapter *adap = inode->i_private; 1999 int ret, nentries; 2000 struct seq_tab *p; 2001 2002 nentries = t4_chip_rss_size(adap); 2003 p = seq_open_tab(file, nentries / 8, 8 * sizeof(u16), 0, rss_show); 2004 if (!p) 2005 return -ENOMEM; 2006 2007 ret = t4_read_rss(adap, (u16 *)p->data); 2008 if (ret) 2009 seq_release_private(inode, file); 2010 2011 return ret; 2012 } 2013 2014 static const struct file_operations rss_debugfs_fops = { 2015 .owner = THIS_MODULE, 2016 .open = rss_open, 2017 .read = seq_read, 2018 .llseek = seq_lseek, 2019 .release = seq_release_private 2020 }; 2021 2022 /* RSS Configuration. 2023 */ 2024 2025 /* Small utility function to return the strings "yes" or "no" if the supplied 2026 * argument is non-zero. 2027 */ 2028 static const char *yesno(int x) 2029 { 2030 static const char *yes = "yes"; 2031 static const char *no = "no"; 2032 2033 return x ? yes : no; 2034 } 2035 2036 static int rss_config_show(struct seq_file *seq, void *v) 2037 { 2038 struct adapter *adapter = seq->private; 2039 static const char * const keymode[] = { 2040 "global", 2041 "global and per-VF scramble", 2042 "per-PF and per-VF scramble", 2043 "per-VF and per-VF scramble", 2044 }; 2045 u32 rssconf; 2046 2047 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_A); 2048 seq_printf(seq, "TP_RSS_CONFIG: %#x\n", rssconf); 2049 seq_printf(seq, " Tnl4TupEnIpv6: %3s\n", yesno(rssconf & 2050 TNL4TUPENIPV6_F)); 2051 seq_printf(seq, " Tnl2TupEnIpv6: %3s\n", yesno(rssconf & 2052 TNL2TUPENIPV6_F)); 2053 seq_printf(seq, " Tnl4TupEnIpv4: %3s\n", yesno(rssconf & 2054 TNL4TUPENIPV4_F)); 2055 seq_printf(seq, " Tnl2TupEnIpv4: %3s\n", yesno(rssconf & 2056 TNL2TUPENIPV4_F)); 2057 seq_printf(seq, " TnlTcpSel: %3s\n", yesno(rssconf & TNLTCPSEL_F)); 2058 seq_printf(seq, " TnlIp6Sel: %3s\n", yesno(rssconf & TNLIP6SEL_F)); 2059 seq_printf(seq, " TnlVrtSel: %3s\n", yesno(rssconf & TNLVRTSEL_F)); 2060 seq_printf(seq, " TnlMapEn: %3s\n", yesno(rssconf & TNLMAPEN_F)); 2061 seq_printf(seq, " OfdHashSave: %3s\n", yesno(rssconf & 2062 OFDHASHSAVE_F)); 2063 seq_printf(seq, " OfdVrtSel: %3s\n", yesno(rssconf & OFDVRTSEL_F)); 2064 seq_printf(seq, " OfdMapEn: %3s\n", yesno(rssconf & OFDMAPEN_F)); 2065 seq_printf(seq, " OfdLkpEn: %3s\n", yesno(rssconf & OFDLKPEN_F)); 2066 seq_printf(seq, " Syn4TupEnIpv6: %3s\n", yesno(rssconf & 2067 SYN4TUPENIPV6_F)); 2068 seq_printf(seq, " Syn2TupEnIpv6: %3s\n", yesno(rssconf & 2069 SYN2TUPENIPV6_F)); 2070 seq_printf(seq, " Syn4TupEnIpv4: %3s\n", yesno(rssconf & 2071 SYN4TUPENIPV4_F)); 2072 seq_printf(seq, " Syn2TupEnIpv4: %3s\n", yesno(rssconf & 2073 SYN2TUPENIPV4_F)); 2074 seq_printf(seq, " Syn4TupEnIpv6: %3s\n", yesno(rssconf & 2075 SYN4TUPENIPV6_F)); 2076 seq_printf(seq, " SynIp6Sel: %3s\n", yesno(rssconf & SYNIP6SEL_F)); 2077 seq_printf(seq, " SynVrt6Sel: %3s\n", yesno(rssconf & SYNVRTSEL_F)); 2078 seq_printf(seq, " SynMapEn: %3s\n", yesno(rssconf & SYNMAPEN_F)); 2079 seq_printf(seq, " SynLkpEn: %3s\n", yesno(rssconf & SYNLKPEN_F)); 2080 seq_printf(seq, " ChnEn: %3s\n", yesno(rssconf & 2081 CHANNELENABLE_F)); 2082 seq_printf(seq, " PrtEn: %3s\n", yesno(rssconf & 2083 PORTENABLE_F)); 2084 seq_printf(seq, " TnlAllLkp: %3s\n", yesno(rssconf & 2085 TNLALLLOOKUP_F)); 2086 seq_printf(seq, " VrtEn: %3s\n", yesno(rssconf & 2087 VIRTENABLE_F)); 2088 seq_printf(seq, " CngEn: %3s\n", yesno(rssconf & 2089 CONGESTIONENABLE_F)); 2090 seq_printf(seq, " HashToeplitz: %3s\n", yesno(rssconf & 2091 HASHTOEPLITZ_F)); 2092 seq_printf(seq, " Udp4En: %3s\n", yesno(rssconf & UDPENABLE_F)); 2093 seq_printf(seq, " Disable: %3s\n", yesno(rssconf & DISABLE_F)); 2094 2095 seq_puts(seq, "\n"); 2096 2097 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_TNL_A); 2098 seq_printf(seq, "TP_RSS_CONFIG_TNL: %#x\n", rssconf); 2099 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf)); 2100 seq_printf(seq, " MaskFilter: %3d\n", MASKFILTER_G(rssconf)); 2101 if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) { 2102 seq_printf(seq, " HashAll: %3s\n", 2103 yesno(rssconf & HASHALL_F)); 2104 seq_printf(seq, " HashEth: %3s\n", 2105 yesno(rssconf & HASHETH_F)); 2106 } 2107 seq_printf(seq, " UseWireCh: %3s\n", yesno(rssconf & USEWIRECH_F)); 2108 2109 seq_puts(seq, "\n"); 2110 2111 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_OFD_A); 2112 seq_printf(seq, "TP_RSS_CONFIG_OFD: %#x\n", rssconf); 2113 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf)); 2114 seq_printf(seq, " RRCplMapEn: %3s\n", yesno(rssconf & 2115 RRCPLMAPEN_F)); 2116 seq_printf(seq, " RRCplQueWidth: %3d\n", RRCPLQUEWIDTH_G(rssconf)); 2117 2118 seq_puts(seq, "\n"); 2119 2120 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_SYN_A); 2121 seq_printf(seq, "TP_RSS_CONFIG_SYN: %#x\n", rssconf); 2122 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf)); 2123 seq_printf(seq, " UseWireCh: %3s\n", yesno(rssconf & USEWIRECH_F)); 2124 2125 seq_puts(seq, "\n"); 2126 2127 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A); 2128 seq_printf(seq, "TP_RSS_CONFIG_VRT: %#x\n", rssconf); 2129 if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) { 2130 seq_printf(seq, " KeyWrAddrX: %3d\n", 2131 KEYWRADDRX_G(rssconf)); 2132 seq_printf(seq, " KeyExtend: %3s\n", 2133 yesno(rssconf & KEYEXTEND_F)); 2134 } 2135 seq_printf(seq, " VfRdRg: %3s\n", yesno(rssconf & VFRDRG_F)); 2136 seq_printf(seq, " VfRdEn: %3s\n", yesno(rssconf & VFRDEN_F)); 2137 seq_printf(seq, " VfPerrEn: %3s\n", yesno(rssconf & VFPERREN_F)); 2138 seq_printf(seq, " KeyPerrEn: %3s\n", yesno(rssconf & KEYPERREN_F)); 2139 seq_printf(seq, " DisVfVlan: %3s\n", yesno(rssconf & 2140 DISABLEVLAN_F)); 2141 seq_printf(seq, " EnUpSwt: %3s\n", yesno(rssconf & ENABLEUP0_F)); 2142 seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf)); 2143 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) 2144 seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf)); 2145 else 2146 seq_printf(seq, " VfWrAddr: %3d\n", 2147 T6_VFWRADDR_G(rssconf)); 2148 seq_printf(seq, " KeyMode: %s\n", keymode[KEYMODE_G(rssconf)]); 2149 seq_printf(seq, " VfWrEn: %3s\n", yesno(rssconf & VFWREN_F)); 2150 seq_printf(seq, " KeyWrEn: %3s\n", yesno(rssconf & KEYWREN_F)); 2151 seq_printf(seq, " KeyWrAddr: %3d\n", KEYWRADDR_G(rssconf)); 2152 2153 seq_puts(seq, "\n"); 2154 2155 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_CNG_A); 2156 seq_printf(seq, "TP_RSS_CONFIG_CNG: %#x\n", rssconf); 2157 seq_printf(seq, " ChnCount3: %3s\n", yesno(rssconf & CHNCOUNT3_F)); 2158 seq_printf(seq, " ChnCount2: %3s\n", yesno(rssconf & CHNCOUNT2_F)); 2159 seq_printf(seq, " ChnCount1: %3s\n", yesno(rssconf & CHNCOUNT1_F)); 2160 seq_printf(seq, " ChnCount0: %3s\n", yesno(rssconf & CHNCOUNT0_F)); 2161 seq_printf(seq, " ChnUndFlow3: %3s\n", yesno(rssconf & 2162 CHNUNDFLOW3_F)); 2163 seq_printf(seq, " ChnUndFlow2: %3s\n", yesno(rssconf & 2164 CHNUNDFLOW2_F)); 2165 seq_printf(seq, " ChnUndFlow1: %3s\n", yesno(rssconf & 2166 CHNUNDFLOW1_F)); 2167 seq_printf(seq, " ChnUndFlow0: %3s\n", yesno(rssconf & 2168 CHNUNDFLOW0_F)); 2169 seq_printf(seq, " RstChn3: %3s\n", yesno(rssconf & RSTCHN3_F)); 2170 seq_printf(seq, " RstChn2: %3s\n", yesno(rssconf & RSTCHN2_F)); 2171 seq_printf(seq, " RstChn1: %3s\n", yesno(rssconf & RSTCHN1_F)); 2172 seq_printf(seq, " RstChn0: %3s\n", yesno(rssconf & RSTCHN0_F)); 2173 seq_printf(seq, " UpdVld: %3s\n", yesno(rssconf & UPDVLD_F)); 2174 seq_printf(seq, " Xoff: %3s\n", yesno(rssconf & XOFF_F)); 2175 seq_printf(seq, " UpdChn3: %3s\n", yesno(rssconf & UPDCHN3_F)); 2176 seq_printf(seq, " UpdChn2: %3s\n", yesno(rssconf & UPDCHN2_F)); 2177 seq_printf(seq, " UpdChn1: %3s\n", yesno(rssconf & UPDCHN1_F)); 2178 seq_printf(seq, " UpdChn0: %3s\n", yesno(rssconf & UPDCHN0_F)); 2179 seq_printf(seq, " Queue: %3d\n", QUEUE_G(rssconf)); 2180 2181 return 0; 2182 } 2183 DEFINE_SHOW_ATTRIBUTE(rss_config); 2184 2185 /* RSS Secret Key. 2186 */ 2187 2188 static int rss_key_show(struct seq_file *seq, void *v) 2189 { 2190 u32 key[10]; 2191 2192 t4_read_rss_key(seq->private, key, true); 2193 seq_printf(seq, "%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x\n", 2194 key[9], key[8], key[7], key[6], key[5], key[4], key[3], 2195 key[2], key[1], key[0]); 2196 return 0; 2197 } 2198 2199 static int rss_key_open(struct inode *inode, struct file *file) 2200 { 2201 return single_open(file, rss_key_show, inode->i_private); 2202 } 2203 2204 static ssize_t rss_key_write(struct file *file, const char __user *buf, 2205 size_t count, loff_t *pos) 2206 { 2207 int i, j; 2208 u32 key[10]; 2209 char s[100], *p; 2210 struct adapter *adap = file_inode(file)->i_private; 2211 2212 if (count > sizeof(s) - 1) 2213 return -EINVAL; 2214 if (copy_from_user(s, buf, count)) 2215 return -EFAULT; 2216 for (i = count; i > 0 && isspace(s[i - 1]); i--) 2217 ; 2218 s[i] = '\0'; 2219 2220 for (p = s, i = 9; i >= 0; i--) { 2221 key[i] = 0; 2222 for (j = 0; j < 8; j++, p++) { 2223 if (!isxdigit(*p)) 2224 return -EINVAL; 2225 key[i] = (key[i] << 4) | hex2val(*p); 2226 } 2227 } 2228 2229 t4_write_rss_key(adap, key, -1, true); 2230 return count; 2231 } 2232 2233 static const struct file_operations rss_key_debugfs_fops = { 2234 .owner = THIS_MODULE, 2235 .open = rss_key_open, 2236 .read = seq_read, 2237 .llseek = seq_lseek, 2238 .release = single_release, 2239 .write = rss_key_write 2240 }; 2241 2242 /* PF RSS Configuration. 2243 */ 2244 2245 struct rss_pf_conf { 2246 u32 rss_pf_map; 2247 u32 rss_pf_mask; 2248 u32 rss_pf_config; 2249 }; 2250 2251 static int rss_pf_config_show(struct seq_file *seq, void *v, int idx) 2252 { 2253 struct rss_pf_conf *pfconf; 2254 2255 if (v == SEQ_START_TOKEN) { 2256 /* use the 0th entry to dump the PF Map Index Size */ 2257 pfconf = seq->private + offsetof(struct seq_tab, data); 2258 seq_printf(seq, "PF Map Index Size = %d\n\n", 2259 LKPIDXSIZE_G(pfconf->rss_pf_map)); 2260 2261 seq_puts(seq, " RSS PF VF Hash Tuple Enable Default\n"); 2262 seq_puts(seq, " Enable IPF Mask Mask IPv6 IPv4 UDP Queue\n"); 2263 seq_puts(seq, " PF Map Chn Prt Map Size Size Four Two Four Two Four Ch1 Ch0\n"); 2264 } else { 2265 #define G_PFnLKPIDX(map, n) \ 2266 (((map) >> PF1LKPIDX_S*(n)) & PF0LKPIDX_M) 2267 #define G_PFnMSKSIZE(mask, n) \ 2268 (((mask) >> PF1MSKSIZE_S*(n)) & PF1MSKSIZE_M) 2269 2270 pfconf = v; 2271 seq_printf(seq, "%3d %3s %3s %3s %3d %3d %3d %3s %3s %3s %3s %3s %3d %3d\n", 2272 idx, 2273 yesno(pfconf->rss_pf_config & MAPENABLE_F), 2274 yesno(pfconf->rss_pf_config & CHNENABLE_F), 2275 yesno(pfconf->rss_pf_config & PRTENABLE_F), 2276 G_PFnLKPIDX(pfconf->rss_pf_map, idx), 2277 G_PFnMSKSIZE(pfconf->rss_pf_mask, idx), 2278 IVFWIDTH_G(pfconf->rss_pf_config), 2279 yesno(pfconf->rss_pf_config & IP6FOURTUPEN_F), 2280 yesno(pfconf->rss_pf_config & IP6TWOTUPEN_F), 2281 yesno(pfconf->rss_pf_config & IP4FOURTUPEN_F), 2282 yesno(pfconf->rss_pf_config & IP4TWOTUPEN_F), 2283 yesno(pfconf->rss_pf_config & UDPFOURTUPEN_F), 2284 CH1DEFAULTQUEUE_G(pfconf->rss_pf_config), 2285 CH0DEFAULTQUEUE_G(pfconf->rss_pf_config)); 2286 2287 #undef G_PFnLKPIDX 2288 #undef G_PFnMSKSIZE 2289 } 2290 return 0; 2291 } 2292 2293 static int rss_pf_config_open(struct inode *inode, struct file *file) 2294 { 2295 struct adapter *adapter = inode->i_private; 2296 struct seq_tab *p; 2297 u32 rss_pf_map, rss_pf_mask; 2298 struct rss_pf_conf *pfconf; 2299 int pf; 2300 2301 p = seq_open_tab(file, 8, sizeof(*pfconf), 1, rss_pf_config_show); 2302 if (!p) 2303 return -ENOMEM; 2304 2305 pfconf = (struct rss_pf_conf *)p->data; 2306 rss_pf_map = t4_read_rss_pf_map(adapter, true); 2307 rss_pf_mask = t4_read_rss_pf_mask(adapter, true); 2308 for (pf = 0; pf < 8; pf++) { 2309 pfconf[pf].rss_pf_map = rss_pf_map; 2310 pfconf[pf].rss_pf_mask = rss_pf_mask; 2311 t4_read_rss_pf_config(adapter, pf, &pfconf[pf].rss_pf_config, 2312 true); 2313 } 2314 return 0; 2315 } 2316 2317 static const struct file_operations rss_pf_config_debugfs_fops = { 2318 .owner = THIS_MODULE, 2319 .open = rss_pf_config_open, 2320 .read = seq_read, 2321 .llseek = seq_lseek, 2322 .release = seq_release_private 2323 }; 2324 2325 /* VF RSS Configuration. 2326 */ 2327 2328 struct rss_vf_conf { 2329 u32 rss_vf_vfl; 2330 u32 rss_vf_vfh; 2331 }; 2332 2333 static int rss_vf_config_show(struct seq_file *seq, void *v, int idx) 2334 { 2335 if (v == SEQ_START_TOKEN) { 2336 seq_puts(seq, " RSS Hash Tuple Enable\n"); 2337 seq_puts(seq, " Enable IVF Dis Enb IPv6 IPv4 UDP Def Secret Key\n"); 2338 seq_puts(seq, " VF Chn Prt Map VLAN uP Four Two Four Two Four Que Idx Hash\n"); 2339 } else { 2340 struct rss_vf_conf *vfconf = v; 2341 2342 seq_printf(seq, "%3d %3s %3s %3d %3s %3s %3s %3s %3s %3s %3s %4d %3d %#10x\n", 2343 idx, 2344 yesno(vfconf->rss_vf_vfh & VFCHNEN_F), 2345 yesno(vfconf->rss_vf_vfh & VFPRTEN_F), 2346 VFLKPIDX_G(vfconf->rss_vf_vfh), 2347 yesno(vfconf->rss_vf_vfh & VFVLNEX_F), 2348 yesno(vfconf->rss_vf_vfh & VFUPEN_F), 2349 yesno(vfconf->rss_vf_vfh & VFIP4FOURTUPEN_F), 2350 yesno(vfconf->rss_vf_vfh & VFIP6TWOTUPEN_F), 2351 yesno(vfconf->rss_vf_vfh & VFIP4FOURTUPEN_F), 2352 yesno(vfconf->rss_vf_vfh & VFIP4TWOTUPEN_F), 2353 yesno(vfconf->rss_vf_vfh & ENABLEUDPHASH_F), 2354 DEFAULTQUEUE_G(vfconf->rss_vf_vfh), 2355 KEYINDEX_G(vfconf->rss_vf_vfh), 2356 vfconf->rss_vf_vfl); 2357 } 2358 return 0; 2359 } 2360 2361 static int rss_vf_config_open(struct inode *inode, struct file *file) 2362 { 2363 struct adapter *adapter = inode->i_private; 2364 struct seq_tab *p; 2365 struct rss_vf_conf *vfconf; 2366 int vf, vfcount = adapter->params.arch.vfcount; 2367 2368 p = seq_open_tab(file, vfcount, sizeof(*vfconf), 1, rss_vf_config_show); 2369 if (!p) 2370 return -ENOMEM; 2371 2372 vfconf = (struct rss_vf_conf *)p->data; 2373 for (vf = 0; vf < vfcount; vf++) { 2374 t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl, 2375 &vfconf[vf].rss_vf_vfh, true); 2376 } 2377 return 0; 2378 } 2379 2380 static const struct file_operations rss_vf_config_debugfs_fops = { 2381 .owner = THIS_MODULE, 2382 .open = rss_vf_config_open, 2383 .read = seq_read, 2384 .llseek = seq_lseek, 2385 .release = seq_release_private 2386 }; 2387 2388 #ifdef CONFIG_CHELSIO_T4_DCB 2389 extern char *dcb_ver_array[]; 2390 2391 /* Data Center Briging information for each port. 2392 */ 2393 static int dcb_info_show(struct seq_file *seq, void *v) 2394 { 2395 struct adapter *adap = seq->private; 2396 2397 if (v == SEQ_START_TOKEN) { 2398 seq_puts(seq, "Data Center Bridging Information\n"); 2399 } else { 2400 int port = (uintptr_t)v - 2; 2401 struct net_device *dev = adap->port[port]; 2402 struct port_info *pi = netdev2pinfo(dev); 2403 struct port_dcb_info *dcb = &pi->dcb; 2404 2405 seq_puts(seq, "\n"); 2406 seq_printf(seq, "Port: %d (DCB negotiated: %s)\n", 2407 port, 2408 cxgb4_dcb_enabled(dev) ? "yes" : "no"); 2409 2410 if (cxgb4_dcb_enabled(dev)) 2411 seq_printf(seq, "[ DCBx Version %s ]\n", 2412 dcb_ver_array[dcb->dcb_version]); 2413 2414 if (dcb->msgs) { 2415 int i; 2416 2417 seq_puts(seq, "\n Index\t\t\t :\t"); 2418 for (i = 0; i < 8; i++) 2419 seq_printf(seq, " %3d", i); 2420 seq_puts(seq, "\n\n"); 2421 } 2422 2423 if (dcb->msgs & CXGB4_DCB_FW_PGID) { 2424 int prio, pgid; 2425 2426 seq_puts(seq, " Priority Group IDs\t :\t"); 2427 for (prio = 0; prio < 8; prio++) { 2428 pgid = (dcb->pgid >> 4 * (7 - prio)) & 0xf; 2429 seq_printf(seq, " %3d", pgid); 2430 } 2431 seq_puts(seq, "\n"); 2432 } 2433 2434 if (dcb->msgs & CXGB4_DCB_FW_PGRATE) { 2435 int pg; 2436 2437 seq_puts(seq, " Priority Group BW(%)\t :\t"); 2438 for (pg = 0; pg < 8; pg++) 2439 seq_printf(seq, " %3d", dcb->pgrate[pg]); 2440 seq_puts(seq, "\n"); 2441 2442 if (dcb->dcb_version == FW_PORT_DCB_VER_IEEE) { 2443 seq_puts(seq, " TSA Algorithm\t\t :\t"); 2444 for (pg = 0; pg < 8; pg++) 2445 seq_printf(seq, " %3d", dcb->tsa[pg]); 2446 seq_puts(seq, "\n"); 2447 } 2448 2449 seq_printf(seq, " Max PG Traffic Classes [%3d ]\n", 2450 dcb->pg_num_tcs_supported); 2451 2452 seq_puts(seq, "\n"); 2453 } 2454 2455 if (dcb->msgs & CXGB4_DCB_FW_PRIORATE) { 2456 int prio; 2457 2458 seq_puts(seq, " Priority Rate\t:\t"); 2459 for (prio = 0; prio < 8; prio++) 2460 seq_printf(seq, " %3d", dcb->priorate[prio]); 2461 seq_puts(seq, "\n"); 2462 } 2463 2464 if (dcb->msgs & CXGB4_DCB_FW_PFC) { 2465 int prio; 2466 2467 seq_puts(seq, " Priority Flow Control :\t"); 2468 for (prio = 0; prio < 8; prio++) { 2469 int pfcen = (dcb->pfcen >> 1 * (7 - prio)) 2470 & 0x1; 2471 seq_printf(seq, " %3d", pfcen); 2472 } 2473 seq_puts(seq, "\n"); 2474 2475 seq_printf(seq, " Max PFC Traffic Classes [%3d ]\n", 2476 dcb->pfc_num_tcs_supported); 2477 2478 seq_puts(seq, "\n"); 2479 } 2480 2481 if (dcb->msgs & CXGB4_DCB_FW_APP_ID) { 2482 int app, napps; 2483 2484 seq_puts(seq, " Application Information:\n"); 2485 seq_puts(seq, " App Priority Selection Protocol\n"); 2486 seq_puts(seq, " Index Map Field ID\n"); 2487 for (app = 0, napps = 0; 2488 app < CXGB4_MAX_DCBX_APP_SUPPORTED; app++) { 2489 struct app_priority *ap; 2490 static const char * const sel_names[] = { 2491 "Ethertype", 2492 "Socket TCP", 2493 "Socket UDP", 2494 "Socket All", 2495 }; 2496 const char *sel_name; 2497 2498 ap = &dcb->app_priority[app]; 2499 /* skip empty slots */ 2500 if (ap->protocolid == 0) 2501 continue; 2502 napps++; 2503 2504 if (ap->sel_field < ARRAY_SIZE(sel_names)) 2505 sel_name = sel_names[ap->sel_field]; 2506 else 2507 sel_name = "UNKNOWN"; 2508 2509 seq_printf(seq, " %3d %#04x %-10s (%d) %#06x (%d)\n", 2510 app, 2511 ap->user_prio_map, 2512 sel_name, ap->sel_field, 2513 ap->protocolid, ap->protocolid); 2514 } 2515 if (napps == 0) 2516 seq_puts(seq, " --- None ---\n"); 2517 } 2518 } 2519 return 0; 2520 } 2521 2522 static inline void *dcb_info_get_idx(struct adapter *adap, loff_t pos) 2523 { 2524 return (pos <= adap->params.nports 2525 ? (void *)((uintptr_t)pos + 1) 2526 : NULL); 2527 } 2528 2529 static void *dcb_info_start(struct seq_file *seq, loff_t *pos) 2530 { 2531 struct adapter *adap = seq->private; 2532 2533 return (*pos 2534 ? dcb_info_get_idx(adap, *pos) 2535 : SEQ_START_TOKEN); 2536 } 2537 2538 static void dcb_info_stop(struct seq_file *seq, void *v) 2539 { 2540 } 2541 2542 static void *dcb_info_next(struct seq_file *seq, void *v, loff_t *pos) 2543 { 2544 struct adapter *adap = seq->private; 2545 2546 (*pos)++; 2547 return dcb_info_get_idx(adap, *pos); 2548 } 2549 2550 static const struct seq_operations dcb_info_seq_ops = { 2551 .start = dcb_info_start, 2552 .next = dcb_info_next, 2553 .stop = dcb_info_stop, 2554 .show = dcb_info_show 2555 }; 2556 2557 static int dcb_info_open(struct inode *inode, struct file *file) 2558 { 2559 int res = seq_open(file, &dcb_info_seq_ops); 2560 2561 if (!res) { 2562 struct seq_file *seq = file->private_data; 2563 2564 seq->private = inode->i_private; 2565 } 2566 return res; 2567 } 2568 2569 static const struct file_operations dcb_info_debugfs_fops = { 2570 .owner = THIS_MODULE, 2571 .open = dcb_info_open, 2572 .read = seq_read, 2573 .llseek = seq_lseek, 2574 .release = seq_release, 2575 }; 2576 #endif /* CONFIG_CHELSIO_T4_DCB */ 2577 2578 static int resources_show(struct seq_file *seq, void *v) 2579 { 2580 struct adapter *adapter = seq->private; 2581 struct pf_resources *pfres = &adapter->params.pfres; 2582 2583 #define S(desc, fmt, var) \ 2584 seq_printf(seq, "%-60s " fmt "\n", \ 2585 desc " (" #var "):", pfres->var) 2586 2587 S("Virtual Interfaces", "%d", nvi); 2588 S("Egress Queues", "%d", neq); 2589 S("Ethernet Control", "%d", nethctrl); 2590 S("Ingress Queues/w Free Lists/Interrupts", "%d", niqflint); 2591 S("Ingress Queues", "%d", niq); 2592 S("Traffic Class", "%d", tc); 2593 S("Port Access Rights Mask", "%#x", pmask); 2594 S("MAC Address Filters", "%d", nexactf); 2595 S("Firmware Command Read Capabilities", "%#x", r_caps); 2596 S("Firmware Command Write/Execute Capabilities", "%#x", wx_caps); 2597 2598 #undef S 2599 2600 return 0; 2601 } 2602 DEFINE_SHOW_ATTRIBUTE(resources); 2603 2604 /** 2605 * ethqset2pinfo - return port_info of an Ethernet Queue Set 2606 * @adap: the adapter 2607 * @qset: Ethernet Queue Set 2608 */ 2609 static inline struct port_info *ethqset2pinfo(struct adapter *adap, int qset) 2610 { 2611 int pidx; 2612 2613 for_each_port(adap, pidx) { 2614 struct port_info *pi = adap2pinfo(adap, pidx); 2615 2616 if (qset >= pi->first_qset && 2617 qset < pi->first_qset + pi->nqsets) 2618 return pi; 2619 } 2620 2621 /* should never happen! */ 2622 BUG(); 2623 return NULL; 2624 } 2625 2626 static int sge_qinfo_uld_txq_entries(const struct adapter *adap, int uld) 2627 { 2628 const struct sge_uld_txq_info *utxq_info = adap->sge.uld_txq_info[uld]; 2629 2630 if (!utxq_info) 2631 return 0; 2632 2633 return DIV_ROUND_UP(utxq_info->ntxq, 4); 2634 } 2635 2636 static int sge_qinfo_uld_rspq_entries(const struct adapter *adap, int uld, 2637 bool ciq) 2638 { 2639 const struct sge_uld_rxq_info *urxq_info = adap->sge.uld_rxq_info[uld]; 2640 2641 if (!urxq_info) 2642 return 0; 2643 2644 return ciq ? DIV_ROUND_UP(urxq_info->nciq, 4) : 2645 DIV_ROUND_UP(urxq_info->nrxq, 4); 2646 } 2647 2648 static int sge_qinfo_uld_rxq_entries(const struct adapter *adap, int uld) 2649 { 2650 return sge_qinfo_uld_rspq_entries(adap, uld, false); 2651 } 2652 2653 static int sge_qinfo_uld_ciq_entries(const struct adapter *adap, int uld) 2654 { 2655 return sge_qinfo_uld_rspq_entries(adap, uld, true); 2656 } 2657 2658 static int sge_qinfo_show(struct seq_file *seq, void *v) 2659 { 2660 int eth_entries, ctrl_entries, eo_entries = 0; 2661 int uld_rxq_entries[CXGB4_ULD_MAX] = { 0 }; 2662 int uld_ciq_entries[CXGB4_ULD_MAX] = { 0 }; 2663 int uld_txq_entries[CXGB4_TX_MAX] = { 0 }; 2664 const struct sge_uld_txq_info *utxq_info; 2665 const struct sge_uld_rxq_info *urxq_info; 2666 struct adapter *adap = seq->private; 2667 int i, n, r = (uintptr_t)v - 1; 2668 struct sge *s = &adap->sge; 2669 2670 eth_entries = DIV_ROUND_UP(adap->sge.ethqsets, 4); 2671 ctrl_entries = DIV_ROUND_UP(MAX_CTRL_QUEUES, 4); 2672 if (adap->sge.eohw_txq) 2673 eo_entries = DIV_ROUND_UP(adap->sge.eoqsets, 4); 2674 2675 mutex_lock(&uld_mutex); 2676 if (s->uld_txq_info) 2677 for (i = 0; i < ARRAY_SIZE(uld_txq_entries); i++) 2678 uld_txq_entries[i] = sge_qinfo_uld_txq_entries(adap, i); 2679 2680 if (s->uld_rxq_info) { 2681 for (i = 0; i < ARRAY_SIZE(uld_rxq_entries); i++) { 2682 uld_rxq_entries[i] = sge_qinfo_uld_rxq_entries(adap, i); 2683 uld_ciq_entries[i] = sge_qinfo_uld_ciq_entries(adap, i); 2684 } 2685 } 2686 2687 if (r) 2688 seq_putc(seq, '\n'); 2689 2690 #define S3(fmt_spec, s, v) \ 2691 do { \ 2692 seq_printf(seq, "%-12s", s); \ 2693 for (i = 0; i < n; ++i) \ 2694 seq_printf(seq, " %16" fmt_spec, v); \ 2695 seq_putc(seq, '\n'); \ 2696 } while (0) 2697 #define S(s, v) S3("s", s, v) 2698 #define T3(fmt_spec, s, v) S3(fmt_spec, s, tx[i].v) 2699 #define T(s, v) S3("u", s, tx[i].v) 2700 #define TL(s, v) T3("lu", s, v) 2701 #define R3(fmt_spec, s, v) S3(fmt_spec, s, rx[i].v) 2702 #define R(s, v) S3("u", s, rx[i].v) 2703 #define RL(s, v) R3("lu", s, v) 2704 2705 if (r < eth_entries) { 2706 int base_qset = r * 4; 2707 const struct sge_eth_rxq *rx = &s->ethrxq[base_qset]; 2708 const struct sge_eth_txq *tx = &s->ethtxq[base_qset]; 2709 2710 n = min(4, s->ethqsets - 4 * r); 2711 2712 S("QType:", "Ethernet"); 2713 S("Interface:", 2714 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A"); 2715 T("TxQ ID:", q.cntxt_id); 2716 T("TxQ size:", q.size); 2717 T("TxQ inuse:", q.in_use); 2718 T("TxQ CIDX:", q.cidx); 2719 T("TxQ PIDX:", q.pidx); 2720 #ifdef CONFIG_CHELSIO_T4_DCB 2721 T("DCB Prio:", dcb_prio); 2722 S3("u", "DCB PGID:", 2723 (ethqset2pinfo(adap, base_qset + i)->dcb.pgid >> 2724 4*(7-tx[i].dcb_prio)) & 0xf); 2725 S3("u", "DCB PFC:", 2726 (ethqset2pinfo(adap, base_qset + i)->dcb.pfcen >> 2727 1*(7-tx[i].dcb_prio)) & 0x1); 2728 #endif 2729 R("RspQ ID:", rspq.abs_id); 2730 R("RspQ size:", rspq.size); 2731 R("RspQE size:", rspq.iqe_len); 2732 R("RspQ CIDX:", rspq.cidx); 2733 R("RspQ Gen:", rspq.gen); 2734 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 2735 S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]); 2736 R("FL ID:", fl.cntxt_id); 2737 R("FL size:", fl.size - 8); 2738 R("FL pend:", fl.pend_cred); 2739 R("FL avail:", fl.avail); 2740 R("FL PIDX:", fl.pidx); 2741 R("FL CIDX:", fl.cidx); 2742 RL("RxPackets:", stats.pkts); 2743 RL("RxCSO:", stats.rx_cso); 2744 RL("VLANxtract:", stats.vlan_ex); 2745 RL("LROmerged:", stats.lro_merged); 2746 RL("LROpackets:", stats.lro_pkts); 2747 RL("RxDrops:", stats.rx_drops); 2748 RL("RxBadPkts:", stats.bad_rx_pkts); 2749 TL("TSO:", tso); 2750 TL("USO:", uso); 2751 TL("TxCSO:", tx_cso); 2752 TL("VLANins:", vlan_ins); 2753 TL("TxQFull:", q.stops); 2754 TL("TxQRestarts:", q.restarts); 2755 TL("TxMapErr:", mapping_err); 2756 RL("FLAllocErr:", fl.alloc_failed); 2757 RL("FLLrgAlcErr:", fl.large_alloc_failed); 2758 RL("FLMapErr:", fl.mapping_err); 2759 RL("FLLow:", fl.low); 2760 RL("FLStarving:", fl.starving); 2761 2762 goto unlock; 2763 } 2764 2765 r -= eth_entries; 2766 if (r < eo_entries) { 2767 int base_qset = r * 4; 2768 const struct sge_ofld_rxq *rx = &s->eohw_rxq[base_qset]; 2769 const struct sge_eohw_txq *tx = &s->eohw_txq[base_qset]; 2770 2771 n = min(4, s->eoqsets - 4 * r); 2772 2773 S("QType:", "ETHOFLD"); 2774 S("Interface:", 2775 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A"); 2776 T("TxQ ID:", q.cntxt_id); 2777 T("TxQ size:", q.size); 2778 T("TxQ inuse:", q.in_use); 2779 T("TxQ CIDX:", q.cidx); 2780 T("TxQ PIDX:", q.pidx); 2781 R("RspQ ID:", rspq.abs_id); 2782 R("RspQ size:", rspq.size); 2783 R("RspQE size:", rspq.iqe_len); 2784 R("RspQ CIDX:", rspq.cidx); 2785 R("RspQ Gen:", rspq.gen); 2786 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 2787 S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]); 2788 R("FL ID:", fl.cntxt_id); 2789 S3("u", "FL size:", rx->fl.size ? rx->fl.size - 8 : 0); 2790 R("FL pend:", fl.pend_cred); 2791 R("FL avail:", fl.avail); 2792 R("FL PIDX:", fl.pidx); 2793 R("FL CIDX:", fl.cidx); 2794 RL("RxPackets:", stats.pkts); 2795 RL("RxImm:", stats.imm); 2796 RL("RxAN", stats.an); 2797 RL("RxNoMem", stats.nomem); 2798 TL("TSO:", tso); 2799 TL("USO:", uso); 2800 TL("TxCSO:", tx_cso); 2801 TL("VLANins:", vlan_ins); 2802 TL("TxQFull:", q.stops); 2803 TL("TxQRestarts:", q.restarts); 2804 TL("TxMapErr:", mapping_err); 2805 RL("FLAllocErr:", fl.alloc_failed); 2806 RL("FLLrgAlcErr:", fl.large_alloc_failed); 2807 RL("FLMapErr:", fl.mapping_err); 2808 RL("FLLow:", fl.low); 2809 RL("FLStarving:", fl.starving); 2810 2811 goto unlock; 2812 } 2813 2814 r -= eo_entries; 2815 if (r < uld_txq_entries[CXGB4_TX_OFLD]) { 2816 const struct sge_uld_txq *tx; 2817 2818 utxq_info = s->uld_txq_info[CXGB4_TX_OFLD]; 2819 tx = &utxq_info->uldtxq[r * 4]; 2820 n = min(4, utxq_info->ntxq - 4 * r); 2821 2822 S("QType:", "OFLD-TXQ"); 2823 T("TxQ ID:", q.cntxt_id); 2824 T("TxQ size:", q.size); 2825 T("TxQ inuse:", q.in_use); 2826 T("TxQ CIDX:", q.cidx); 2827 T("TxQ PIDX:", q.pidx); 2828 2829 goto unlock; 2830 } 2831 2832 r -= uld_txq_entries[CXGB4_TX_OFLD]; 2833 if (r < uld_rxq_entries[CXGB4_ULD_RDMA]) { 2834 const struct sge_ofld_rxq *rx; 2835 2836 urxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; 2837 rx = &urxq_info->uldrxq[r * 4]; 2838 n = min(4, urxq_info->nrxq - 4 * r); 2839 2840 S("QType:", "RDMA-CPL"); 2841 S("Interface:", 2842 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A"); 2843 R("RspQ ID:", rspq.abs_id); 2844 R("RspQ size:", rspq.size); 2845 R("RspQE size:", rspq.iqe_len); 2846 R("RspQ CIDX:", rspq.cidx); 2847 R("RspQ Gen:", rspq.gen); 2848 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 2849 S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]); 2850 R("FL ID:", fl.cntxt_id); 2851 R("FL size:", fl.size - 8); 2852 R("FL pend:", fl.pend_cred); 2853 R("FL avail:", fl.avail); 2854 R("FL PIDX:", fl.pidx); 2855 R("FL CIDX:", fl.cidx); 2856 2857 goto unlock; 2858 } 2859 2860 r -= uld_rxq_entries[CXGB4_ULD_RDMA]; 2861 if (r < uld_ciq_entries[CXGB4_ULD_RDMA]) { 2862 const struct sge_ofld_rxq *rx; 2863 int ciq_idx = 0; 2864 2865 urxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; 2866 ciq_idx = urxq_info->nrxq + (r * 4); 2867 rx = &urxq_info->uldrxq[ciq_idx]; 2868 n = min(4, urxq_info->nciq - 4 * r); 2869 2870 S("QType:", "RDMA-CIQ"); 2871 S("Interface:", 2872 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A"); 2873 R("RspQ ID:", rspq.abs_id); 2874 R("RspQ size:", rspq.size); 2875 R("RspQE size:", rspq.iqe_len); 2876 R("RspQ CIDX:", rspq.cidx); 2877 R("RspQ Gen:", rspq.gen); 2878 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 2879 S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]); 2880 2881 goto unlock; 2882 } 2883 2884 r -= uld_ciq_entries[CXGB4_ULD_RDMA]; 2885 if (r < uld_rxq_entries[CXGB4_ULD_ISCSI]) { 2886 const struct sge_ofld_rxq *rx; 2887 2888 urxq_info = s->uld_rxq_info[CXGB4_ULD_ISCSI]; 2889 rx = &urxq_info->uldrxq[r * 4]; 2890 n = min(4, urxq_info->nrxq - 4 * r); 2891 2892 S("QType:", "iSCSI"); 2893 R("RspQ ID:", rspq.abs_id); 2894 R("RspQ size:", rspq.size); 2895 R("RspQE size:", rspq.iqe_len); 2896 R("RspQ CIDX:", rspq.cidx); 2897 R("RspQ Gen:", rspq.gen); 2898 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 2899 S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]); 2900 R("FL ID:", fl.cntxt_id); 2901 R("FL size:", fl.size - 8); 2902 R("FL pend:", fl.pend_cred); 2903 R("FL avail:", fl.avail); 2904 R("FL PIDX:", fl.pidx); 2905 R("FL CIDX:", fl.cidx); 2906 2907 goto unlock; 2908 } 2909 2910 r -= uld_rxq_entries[CXGB4_ULD_ISCSI]; 2911 if (r < uld_rxq_entries[CXGB4_ULD_ISCSIT]) { 2912 const struct sge_ofld_rxq *rx; 2913 2914 urxq_info = s->uld_rxq_info[CXGB4_ULD_ISCSIT]; 2915 rx = &urxq_info->uldrxq[r * 4]; 2916 n = min(4, urxq_info->nrxq - 4 * r); 2917 2918 S("QType:", "iSCSIT"); 2919 R("RspQ ID:", rspq.abs_id); 2920 R("RspQ size:", rspq.size); 2921 R("RspQE size:", rspq.iqe_len); 2922 R("RspQ CIDX:", rspq.cidx); 2923 R("RspQ Gen:", rspq.gen); 2924 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 2925 S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]); 2926 R("FL ID:", fl.cntxt_id); 2927 R("FL size:", fl.size - 8); 2928 R("FL pend:", fl.pend_cred); 2929 R("FL avail:", fl.avail); 2930 R("FL PIDX:", fl.pidx); 2931 R("FL CIDX:", fl.cidx); 2932 2933 goto unlock; 2934 } 2935 2936 r -= uld_rxq_entries[CXGB4_ULD_ISCSIT]; 2937 if (r < uld_rxq_entries[CXGB4_ULD_TLS]) { 2938 const struct sge_ofld_rxq *rx; 2939 2940 urxq_info = s->uld_rxq_info[CXGB4_ULD_TLS]; 2941 rx = &urxq_info->uldrxq[r * 4]; 2942 n = min(4, urxq_info->nrxq - 4 * r); 2943 2944 S("QType:", "TLS"); 2945 R("RspQ ID:", rspq.abs_id); 2946 R("RspQ size:", rspq.size); 2947 R("RspQE size:", rspq.iqe_len); 2948 R("RspQ CIDX:", rspq.cidx); 2949 R("RspQ Gen:", rspq.gen); 2950 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 2951 S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]); 2952 R("FL ID:", fl.cntxt_id); 2953 R("FL size:", fl.size - 8); 2954 R("FL pend:", fl.pend_cred); 2955 R("FL avail:", fl.avail); 2956 R("FL PIDX:", fl.pidx); 2957 R("FL CIDX:", fl.cidx); 2958 2959 goto unlock; 2960 } 2961 2962 r -= uld_rxq_entries[CXGB4_ULD_TLS]; 2963 if (r < uld_txq_entries[CXGB4_TX_CRYPTO]) { 2964 const struct sge_ofld_rxq *rx; 2965 const struct sge_uld_txq *tx; 2966 2967 utxq_info = s->uld_txq_info[CXGB4_TX_CRYPTO]; 2968 urxq_info = s->uld_rxq_info[CXGB4_ULD_CRYPTO]; 2969 tx = &utxq_info->uldtxq[r * 4]; 2970 rx = &urxq_info->uldrxq[r * 4]; 2971 n = min(4, utxq_info->ntxq - 4 * r); 2972 2973 S("QType:", "Crypto"); 2974 T("TxQ ID:", q.cntxt_id); 2975 T("TxQ size:", q.size); 2976 T("TxQ inuse:", q.in_use); 2977 T("TxQ CIDX:", q.cidx); 2978 T("TxQ PIDX:", q.pidx); 2979 R("RspQ ID:", rspq.abs_id); 2980 R("RspQ size:", rspq.size); 2981 R("RspQE size:", rspq.iqe_len); 2982 R("RspQ CIDX:", rspq.cidx); 2983 R("RspQ Gen:", rspq.gen); 2984 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 2985 S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]); 2986 R("FL ID:", fl.cntxt_id); 2987 R("FL size:", fl.size - 8); 2988 R("FL pend:", fl.pend_cred); 2989 R("FL avail:", fl.avail); 2990 R("FL PIDX:", fl.pidx); 2991 R("FL CIDX:", fl.cidx); 2992 2993 goto unlock; 2994 } 2995 2996 r -= uld_txq_entries[CXGB4_TX_CRYPTO]; 2997 if (r < ctrl_entries) { 2998 const struct sge_ctrl_txq *tx = &s->ctrlq[r * 4]; 2999 3000 n = min(4, adap->params.nports - 4 * r); 3001 3002 S("QType:", "Control"); 3003 T("TxQ ID:", q.cntxt_id); 3004 T("TxQ size:", q.size); 3005 T("TxQ inuse:", q.in_use); 3006 T("TxQ CIDX:", q.cidx); 3007 T("TxQ PIDX:", q.pidx); 3008 TL("TxQFull:", q.stops); 3009 TL("TxQRestarts:", q.restarts); 3010 3011 goto unlock; 3012 } 3013 3014 r -= ctrl_entries; 3015 if (r < 1) { 3016 const struct sge_rspq *evtq = &s->fw_evtq; 3017 3018 seq_printf(seq, "%-12s %16s\n", "QType:", "FW event queue"); 3019 seq_printf(seq, "%-12s %16u\n", "RspQ ID:", evtq->abs_id); 3020 seq_printf(seq, "%-12s %16u\n", "RspQ size:", evtq->size); 3021 seq_printf(seq, "%-12s %16u\n", "RspQE size:", evtq->iqe_len); 3022 seq_printf(seq, "%-12s %16u\n", "RspQ CIDX:", evtq->cidx); 3023 seq_printf(seq, "%-12s %16u\n", "RspQ Gen:", evtq->gen); 3024 seq_printf(seq, "%-12s %16u\n", "Intr delay:", 3025 qtimer_val(adap, evtq)); 3026 seq_printf(seq, "%-12s %16u\n", "Intr pktcnt:", 3027 s->counter_val[evtq->pktcnt_idx]); 3028 3029 goto unlock; 3030 } 3031 3032 unlock: 3033 mutex_unlock(&uld_mutex); 3034 #undef R 3035 #undef RL 3036 #undef T 3037 #undef TL 3038 #undef S 3039 #undef R3 3040 #undef T3 3041 #undef S3 3042 return 0; 3043 } 3044 3045 static int sge_queue_entries(const struct adapter *adap) 3046 { 3047 int tot_uld_entries = 0; 3048 int i; 3049 3050 if (!is_uld(adap)) 3051 goto lld_only; 3052 3053 mutex_lock(&uld_mutex); 3054 for (i = 0; i < CXGB4_TX_MAX; i++) 3055 tot_uld_entries += sge_qinfo_uld_txq_entries(adap, i); 3056 3057 for (i = 0; i < CXGB4_ULD_MAX; i++) { 3058 tot_uld_entries += sge_qinfo_uld_rxq_entries(adap, i); 3059 tot_uld_entries += sge_qinfo_uld_ciq_entries(adap, i); 3060 } 3061 mutex_unlock(&uld_mutex); 3062 3063 lld_only: 3064 return DIV_ROUND_UP(adap->sge.ethqsets, 4) + 3065 (adap->sge.eohw_txq ? DIV_ROUND_UP(adap->sge.eoqsets, 4) : 0) + 3066 tot_uld_entries + 3067 DIV_ROUND_UP(MAX_CTRL_QUEUES, 4) + 1; 3068 } 3069 3070 static void *sge_queue_start(struct seq_file *seq, loff_t *pos) 3071 { 3072 int entries = sge_queue_entries(seq->private); 3073 3074 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL; 3075 } 3076 3077 static void sge_queue_stop(struct seq_file *seq, void *v) 3078 { 3079 } 3080 3081 static void *sge_queue_next(struct seq_file *seq, void *v, loff_t *pos) 3082 { 3083 int entries = sge_queue_entries(seq->private); 3084 3085 ++*pos; 3086 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL; 3087 } 3088 3089 static const struct seq_operations sge_qinfo_seq_ops = { 3090 .start = sge_queue_start, 3091 .next = sge_queue_next, 3092 .stop = sge_queue_stop, 3093 .show = sge_qinfo_show 3094 }; 3095 3096 static int sge_qinfo_open(struct inode *inode, struct file *file) 3097 { 3098 int res = seq_open(file, &sge_qinfo_seq_ops); 3099 3100 if (!res) { 3101 struct seq_file *seq = file->private_data; 3102 3103 seq->private = inode->i_private; 3104 } 3105 return res; 3106 } 3107 3108 static const struct file_operations sge_qinfo_debugfs_fops = { 3109 .owner = THIS_MODULE, 3110 .open = sge_qinfo_open, 3111 .read = seq_read, 3112 .llseek = seq_lseek, 3113 .release = seq_release, 3114 }; 3115 3116 int mem_open(struct inode *inode, struct file *file) 3117 { 3118 unsigned int mem; 3119 struct adapter *adap; 3120 3121 file->private_data = inode->i_private; 3122 3123 mem = (uintptr_t)file->private_data & 0x7; 3124 adap = file->private_data - mem; 3125 3126 (void)t4_fwcache(adap, FW_PARAM_DEV_FWCACHE_FLUSH); 3127 3128 return 0; 3129 } 3130 3131 static ssize_t mem_read(struct file *file, char __user *buf, size_t count, 3132 loff_t *ppos) 3133 { 3134 loff_t pos = *ppos; 3135 loff_t avail = file_inode(file)->i_size; 3136 unsigned int mem = (uintptr_t)file->private_data & 0x7; 3137 struct adapter *adap = file->private_data - mem; 3138 __be32 *data; 3139 int ret; 3140 3141 if (pos < 0) 3142 return -EINVAL; 3143 if (pos >= avail) 3144 return 0; 3145 if (count > avail - pos) 3146 count = avail - pos; 3147 3148 data = kvzalloc(count, GFP_KERNEL); 3149 if (!data) 3150 return -ENOMEM; 3151 3152 spin_lock(&adap->win0_lock); 3153 ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ); 3154 spin_unlock(&adap->win0_lock); 3155 if (ret) { 3156 kvfree(data); 3157 return ret; 3158 } 3159 ret = copy_to_user(buf, data, count); 3160 3161 kvfree(data); 3162 if (ret) 3163 return -EFAULT; 3164 3165 *ppos = pos + count; 3166 return count; 3167 } 3168 static const struct file_operations mem_debugfs_fops = { 3169 .owner = THIS_MODULE, 3170 .open = simple_open, 3171 .read = mem_read, 3172 .llseek = default_llseek, 3173 }; 3174 3175 static int tid_info_show(struct seq_file *seq, void *v) 3176 { 3177 struct adapter *adap = seq->private; 3178 const struct tid_info *t; 3179 enum chip_type chip; 3180 3181 t = &adap->tids; 3182 chip = CHELSIO_CHIP_VERSION(adap->params.chip); 3183 if (t4_read_reg(adap, LE_DB_CONFIG_A) & HASHEN_F) { 3184 unsigned int sb; 3185 seq_printf(seq, "Connections in use: %u\n", 3186 atomic_read(&t->conns_in_use)); 3187 3188 if (chip <= CHELSIO_T5) 3189 sb = t4_read_reg(adap, LE_DB_SERVER_INDEX_A) / 4; 3190 else 3191 sb = t4_read_reg(adap, LE_DB_SRVR_START_INDEX_A); 3192 3193 if (sb) { 3194 seq_printf(seq, "TID range: %u..%u/%u..%u", t->tid_base, 3195 sb - 1, adap->tids.hash_base, 3196 t->tid_base + t->ntids - 1); 3197 seq_printf(seq, ", in use: %u/%u\n", 3198 atomic_read(&t->tids_in_use), 3199 atomic_read(&t->hash_tids_in_use)); 3200 } else if (adap->flags & CXGB4_FW_OFLD_CONN) { 3201 seq_printf(seq, "TID range: %u..%u/%u..%u", 3202 t->aftid_base, 3203 t->aftid_end, 3204 adap->tids.hash_base, 3205 t->tid_base + t->ntids - 1); 3206 seq_printf(seq, ", in use: %u/%u\n", 3207 atomic_read(&t->tids_in_use), 3208 atomic_read(&t->hash_tids_in_use)); 3209 } else { 3210 seq_printf(seq, "TID range: %u..%u", 3211 adap->tids.hash_base, 3212 t->tid_base + t->ntids - 1); 3213 seq_printf(seq, ", in use: %u\n", 3214 atomic_read(&t->hash_tids_in_use)); 3215 } 3216 } else if (t->ntids) { 3217 seq_printf(seq, "Connections in use: %u\n", 3218 atomic_read(&t->conns_in_use)); 3219 3220 seq_printf(seq, "TID range: %u..%u", t->tid_base, 3221 t->tid_base + t->ntids - 1); 3222 seq_printf(seq, ", in use: %u\n", 3223 atomic_read(&t->tids_in_use)); 3224 } 3225 3226 if (t->nstids) 3227 seq_printf(seq, "STID range: %u..%u, in use-IPv4/IPv6: %u/%u\n", 3228 (!t->stid_base && 3229 (chip <= CHELSIO_T5)) ? 3230 t->stid_base + 1 : t->stid_base, 3231 t->stid_base + t->nstids - 1, 3232 t->stids_in_use - t->v6_stids_in_use, 3233 t->v6_stids_in_use); 3234 3235 if (t->natids) 3236 seq_printf(seq, "ATID range: 0..%u, in use: %u\n", 3237 t->natids - 1, t->atids_in_use); 3238 seq_printf(seq, "FTID range: %u..%u\n", t->ftid_base, 3239 t->ftid_base + t->nftids - 1); 3240 if (t->nsftids) 3241 seq_printf(seq, "SFTID range: %u..%u in use: %u\n", 3242 t->sftid_base, t->sftid_base + t->nsftids - 2, 3243 t->sftids_in_use); 3244 if (t->nhpftids) 3245 seq_printf(seq, "HPFTID range: %u..%u\n", t->hpftid_base, 3246 t->hpftid_base + t->nhpftids - 1); 3247 if (t->ntids) 3248 seq_printf(seq, "HW TID usage: %u IP users, %u IPv6 users\n", 3249 t4_read_reg(adap, LE_DB_ACT_CNT_IPV4_A), 3250 t4_read_reg(adap, LE_DB_ACT_CNT_IPV6_A)); 3251 return 0; 3252 } 3253 DEFINE_SHOW_ATTRIBUTE(tid_info); 3254 3255 static void add_debugfs_mem(struct adapter *adap, const char *name, 3256 unsigned int idx, unsigned int size_mb) 3257 { 3258 debugfs_create_file_size(name, 0400, adap->debugfs_root, 3259 (void *)adap + idx, &mem_debugfs_fops, 3260 size_mb << 20); 3261 } 3262 3263 static ssize_t blocked_fl_read(struct file *filp, char __user *ubuf, 3264 size_t count, loff_t *ppos) 3265 { 3266 int len; 3267 const struct adapter *adap = filp->private_data; 3268 char *buf; 3269 ssize_t size = (adap->sge.egr_sz + 3) / 4 + 3270 adap->sge.egr_sz / 32 + 2; /* includes ,/\n/\0 */ 3271 3272 buf = kzalloc(size, GFP_KERNEL); 3273 if (!buf) 3274 return -ENOMEM; 3275 3276 len = snprintf(buf, size - 1, "%*pb\n", 3277 adap->sge.egr_sz, adap->sge.blocked_fl); 3278 len += sprintf(buf + len, "\n"); 3279 size = simple_read_from_buffer(ubuf, count, ppos, buf, len); 3280 kvfree(buf); 3281 return size; 3282 } 3283 3284 static ssize_t blocked_fl_write(struct file *filp, const char __user *ubuf, 3285 size_t count, loff_t *ppos) 3286 { 3287 int err; 3288 unsigned long *t; 3289 struct adapter *adap = filp->private_data; 3290 3291 t = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), sizeof(long), GFP_KERNEL); 3292 if (!t) 3293 return -ENOMEM; 3294 3295 err = bitmap_parse_user(ubuf, count, t, adap->sge.egr_sz); 3296 if (err) { 3297 kvfree(t); 3298 return err; 3299 } 3300 3301 bitmap_copy(adap->sge.blocked_fl, t, adap->sge.egr_sz); 3302 kvfree(t); 3303 return count; 3304 } 3305 3306 static const struct file_operations blocked_fl_fops = { 3307 .owner = THIS_MODULE, 3308 .open = simple_open, 3309 .read = blocked_fl_read, 3310 .write = blocked_fl_write, 3311 .llseek = generic_file_llseek, 3312 }; 3313 3314 static void mem_region_show(struct seq_file *seq, const char *name, 3315 unsigned int from, unsigned int to) 3316 { 3317 char buf[40]; 3318 3319 string_get_size((u64)to - from + 1, 1, STRING_UNITS_2, buf, 3320 sizeof(buf)); 3321 seq_printf(seq, "%-15s %#x-%#x [%s]\n", name, from, to, buf); 3322 } 3323 3324 static int meminfo_show(struct seq_file *seq, void *v) 3325 { 3326 static const char * const memory[] = { "EDC0:", "EDC1:", "MC:", 3327 "MC0:", "MC1:", "HMA:"}; 3328 struct adapter *adap = seq->private; 3329 struct cudbg_meminfo meminfo; 3330 int i, rc; 3331 3332 memset(&meminfo, 0, sizeof(struct cudbg_meminfo)); 3333 rc = cudbg_fill_meminfo(adap, &meminfo); 3334 if (rc) 3335 return -ENXIO; 3336 3337 for (i = 0; i < meminfo.avail_c; i++) 3338 mem_region_show(seq, memory[meminfo.avail[i].idx], 3339 meminfo.avail[i].base, 3340 meminfo.avail[i].limit - 1); 3341 3342 seq_putc(seq, '\n'); 3343 for (i = 0; i < meminfo.mem_c; i++) { 3344 if (meminfo.mem[i].idx >= ARRAY_SIZE(cudbg_region)) 3345 continue; /* skip holes */ 3346 if (!meminfo.mem[i].limit) 3347 meminfo.mem[i].limit = 3348 i < meminfo.mem_c - 1 ? 3349 meminfo.mem[i + 1].base - 1 : ~0; 3350 mem_region_show(seq, cudbg_region[meminfo.mem[i].idx], 3351 meminfo.mem[i].base, meminfo.mem[i].limit); 3352 } 3353 3354 seq_putc(seq, '\n'); 3355 mem_region_show(seq, "uP RAM:", meminfo.up_ram_lo, meminfo.up_ram_hi); 3356 mem_region_show(seq, "uP Extmem2:", meminfo.up_extmem2_lo, 3357 meminfo.up_extmem2_hi); 3358 3359 seq_printf(seq, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n", 3360 meminfo.rx_pages_data[0], meminfo.free_rx_cnt, 3361 meminfo.rx_pages_data[1], meminfo.rx_pages_data[2]); 3362 3363 seq_printf(seq, "%u Tx pages (%u free) of size %u%ciB for %u channels\n", 3364 meminfo.tx_pages_data[0], meminfo.free_tx_cnt, 3365 meminfo.tx_pages_data[1], meminfo.tx_pages_data[2], 3366 meminfo.tx_pages_data[3]); 3367 3368 seq_printf(seq, "%u p-structs (%u free)\n\n", 3369 meminfo.p_structs, meminfo.p_structs_free_cnt); 3370 3371 for (i = 0; i < 4; i++) 3372 /* For T6 these are MAC buffer groups */ 3373 seq_printf(seq, "Port %d using %u pages out of %u allocated\n", 3374 i, meminfo.port_used[i], meminfo.port_alloc[i]); 3375 3376 for (i = 0; i < adap->params.arch.nchan; i++) 3377 /* For T6 these are MAC buffer groups */ 3378 seq_printf(seq, 3379 "Loopback %d using %u pages out of %u allocated\n", 3380 i, meminfo.loopback_used[i], 3381 meminfo.loopback_alloc[i]); 3382 3383 return 0; 3384 } 3385 DEFINE_SHOW_ATTRIBUTE(meminfo); 3386 3387 static int chcr_stats_show(struct seq_file *seq, void *v) 3388 { 3389 struct adapter *adap = seq->private; 3390 3391 seq_puts(seq, "Chelsio Crypto Accelerator Stats \n"); 3392 seq_printf(seq, "Cipher Ops: %10u \n", 3393 atomic_read(&adap->chcr_stats.cipher_rqst)); 3394 seq_printf(seq, "Digest Ops: %10u \n", 3395 atomic_read(&adap->chcr_stats.digest_rqst)); 3396 seq_printf(seq, "Aead Ops: %10u \n", 3397 atomic_read(&adap->chcr_stats.aead_rqst)); 3398 seq_printf(seq, "Completion: %10u \n", 3399 atomic_read(&adap->chcr_stats.complete)); 3400 seq_printf(seq, "Error: %10u \n", 3401 atomic_read(&adap->chcr_stats.error)); 3402 seq_printf(seq, "Fallback: %10u \n", 3403 atomic_read(&adap->chcr_stats.fallback)); 3404 seq_printf(seq, "IPSec PDU: %10u\n", 3405 atomic_read(&adap->chcr_stats.ipsec_cnt)); 3406 seq_printf(seq, "TLS PDU Tx: %10u\n", 3407 atomic_read(&adap->chcr_stats.tls_pdu_tx)); 3408 seq_printf(seq, "TLS PDU Rx: %10u\n", 3409 atomic_read(&adap->chcr_stats.tls_pdu_rx)); 3410 seq_printf(seq, "TLS Keys (DDR) Count: %10u\n", 3411 atomic_read(&adap->chcr_stats.tls_key)); 3412 3413 return 0; 3414 } 3415 DEFINE_SHOW_ATTRIBUTE(chcr_stats); 3416 3417 #define PRINT_ADAP_STATS(string, value) \ 3418 seq_printf(seq, "%-25s %-20llu\n", (string), \ 3419 (unsigned long long)(value)) 3420 3421 #define PRINT_CH_STATS(string, value) \ 3422 do { \ 3423 seq_printf(seq, "%-25s ", (string)); \ 3424 for (i = 0; i < adap->params.arch.nchan; i++) \ 3425 seq_printf(seq, "%-20llu ", \ 3426 (unsigned long long)stats.value[i]); \ 3427 seq_printf(seq, "\n"); \ 3428 } while (0) 3429 3430 #define PRINT_CH_STATS2(string, value) \ 3431 do { \ 3432 seq_printf(seq, "%-25s ", (string)); \ 3433 for (i = 0; i < adap->params.arch.nchan; i++) \ 3434 seq_printf(seq, "%-20llu ", \ 3435 (unsigned long long)stats[i].value); \ 3436 seq_printf(seq, "\n"); \ 3437 } while (0) 3438 3439 static void show_tcp_stats(struct seq_file *seq) 3440 { 3441 struct adapter *adap = seq->private; 3442 struct tp_tcp_stats v4, v6; 3443 3444 spin_lock(&adap->stats_lock); 3445 t4_tp_get_tcp_stats(adap, &v4, &v6, false); 3446 spin_unlock(&adap->stats_lock); 3447 3448 PRINT_ADAP_STATS("tcp_ipv4_out_rsts:", v4.tcp_out_rsts); 3449 PRINT_ADAP_STATS("tcp_ipv4_in_segs:", v4.tcp_in_segs); 3450 PRINT_ADAP_STATS("tcp_ipv4_out_segs:", v4.tcp_out_segs); 3451 PRINT_ADAP_STATS("tcp_ipv4_retrans_segs:", v4.tcp_retrans_segs); 3452 PRINT_ADAP_STATS("tcp_ipv6_out_rsts:", v6.tcp_out_rsts); 3453 PRINT_ADAP_STATS("tcp_ipv6_in_segs:", v6.tcp_in_segs); 3454 PRINT_ADAP_STATS("tcp_ipv6_out_segs:", v6.tcp_out_segs); 3455 PRINT_ADAP_STATS("tcp_ipv6_retrans_segs:", v6.tcp_retrans_segs); 3456 } 3457 3458 static void show_ddp_stats(struct seq_file *seq) 3459 { 3460 struct adapter *adap = seq->private; 3461 struct tp_usm_stats stats; 3462 3463 spin_lock(&adap->stats_lock); 3464 t4_get_usm_stats(adap, &stats, false); 3465 spin_unlock(&adap->stats_lock); 3466 3467 PRINT_ADAP_STATS("usm_ddp_frames:", stats.frames); 3468 PRINT_ADAP_STATS("usm_ddp_octets:", stats.octets); 3469 PRINT_ADAP_STATS("usm_ddp_drops:", stats.drops); 3470 } 3471 3472 static void show_rdma_stats(struct seq_file *seq) 3473 { 3474 struct adapter *adap = seq->private; 3475 struct tp_rdma_stats stats; 3476 3477 spin_lock(&adap->stats_lock); 3478 t4_tp_get_rdma_stats(adap, &stats, false); 3479 spin_unlock(&adap->stats_lock); 3480 3481 PRINT_ADAP_STATS("rdma_no_rqe_mod_defer:", stats.rqe_dfr_mod); 3482 PRINT_ADAP_STATS("rdma_no_rqe_pkt_defer:", stats.rqe_dfr_pkt); 3483 } 3484 3485 static void show_tp_err_adapter_stats(struct seq_file *seq) 3486 { 3487 struct adapter *adap = seq->private; 3488 struct tp_err_stats stats; 3489 3490 spin_lock(&adap->stats_lock); 3491 t4_tp_get_err_stats(adap, &stats, false); 3492 spin_unlock(&adap->stats_lock); 3493 3494 PRINT_ADAP_STATS("tp_err_ofld_no_neigh:", stats.ofld_no_neigh); 3495 PRINT_ADAP_STATS("tp_err_ofld_cong_defer:", stats.ofld_cong_defer); 3496 } 3497 3498 static void show_cpl_stats(struct seq_file *seq) 3499 { 3500 struct adapter *adap = seq->private; 3501 struct tp_cpl_stats stats; 3502 u8 i; 3503 3504 spin_lock(&adap->stats_lock); 3505 t4_tp_get_cpl_stats(adap, &stats, false); 3506 spin_unlock(&adap->stats_lock); 3507 3508 PRINT_CH_STATS("tp_cpl_requests:", req); 3509 PRINT_CH_STATS("tp_cpl_responses:", rsp); 3510 } 3511 3512 static void show_tp_err_channel_stats(struct seq_file *seq) 3513 { 3514 struct adapter *adap = seq->private; 3515 struct tp_err_stats stats; 3516 u8 i; 3517 3518 spin_lock(&adap->stats_lock); 3519 t4_tp_get_err_stats(adap, &stats, false); 3520 spin_unlock(&adap->stats_lock); 3521 3522 PRINT_CH_STATS("tp_mac_in_errs:", mac_in_errs); 3523 PRINT_CH_STATS("tp_hdr_in_errs:", hdr_in_errs); 3524 PRINT_CH_STATS("tp_tcp_in_errs:", tcp_in_errs); 3525 PRINT_CH_STATS("tp_tcp6_in_errs:", tcp6_in_errs); 3526 PRINT_CH_STATS("tp_tnl_cong_drops:", tnl_cong_drops); 3527 PRINT_CH_STATS("tp_tnl_tx_drops:", tnl_tx_drops); 3528 PRINT_CH_STATS("tp_ofld_vlan_drops:", ofld_vlan_drops); 3529 PRINT_CH_STATS("tp_ofld_chan_drops:", ofld_chan_drops); 3530 } 3531 3532 static void show_fcoe_stats(struct seq_file *seq) 3533 { 3534 struct adapter *adap = seq->private; 3535 struct tp_fcoe_stats stats[NCHAN]; 3536 u8 i; 3537 3538 spin_lock(&adap->stats_lock); 3539 for (i = 0; i < adap->params.arch.nchan; i++) 3540 t4_get_fcoe_stats(adap, i, &stats[i], false); 3541 spin_unlock(&adap->stats_lock); 3542 3543 PRINT_CH_STATS2("fcoe_octets_ddp", octets_ddp); 3544 PRINT_CH_STATS2("fcoe_frames_ddp", frames_ddp); 3545 PRINT_CH_STATS2("fcoe_frames_drop", frames_drop); 3546 } 3547 3548 #undef PRINT_CH_STATS2 3549 #undef PRINT_CH_STATS 3550 #undef PRINT_ADAP_STATS 3551 3552 static int tp_stats_show(struct seq_file *seq, void *v) 3553 { 3554 struct adapter *adap = seq->private; 3555 3556 seq_puts(seq, "\n--------Adapter Stats--------\n"); 3557 show_tcp_stats(seq); 3558 show_ddp_stats(seq); 3559 show_rdma_stats(seq); 3560 show_tp_err_adapter_stats(seq); 3561 3562 seq_puts(seq, "\n-------- Channel Stats --------\n"); 3563 if (adap->params.arch.nchan == NCHAN) 3564 seq_printf(seq, "%-25s %-20s %-20s %-20s %-20s\n", 3565 " ", "channel 0", "channel 1", 3566 "channel 2", "channel 3"); 3567 else 3568 seq_printf(seq, "%-25s %-20s %-20s\n", 3569 " ", "channel 0", "channel 1"); 3570 show_cpl_stats(seq); 3571 show_tp_err_channel_stats(seq); 3572 show_fcoe_stats(seq); 3573 3574 return 0; 3575 } 3576 DEFINE_SHOW_ATTRIBUTE(tp_stats); 3577 3578 /* Add an array of Debug FS files. 3579 */ 3580 void add_debugfs_files(struct adapter *adap, 3581 struct t4_debugfs_entry *files, 3582 unsigned int nfiles) 3583 { 3584 int i; 3585 3586 /* debugfs support is best effort */ 3587 for (i = 0; i < nfiles; i++) 3588 debugfs_create_file(files[i].name, files[i].mode, 3589 adap->debugfs_root, 3590 (void *)adap + files[i].data, 3591 files[i].ops); 3592 } 3593 3594 int t4_setup_debugfs(struct adapter *adap) 3595 { 3596 int i; 3597 u32 size = 0; 3598 3599 static struct t4_debugfs_entry t4_debugfs_files[] = { 3600 { "cim_la", &cim_la_fops, 0400, 0 }, 3601 { "cim_pif_la", &cim_pif_la_fops, 0400, 0 }, 3602 { "cim_ma_la", &cim_ma_la_fops, 0400, 0 }, 3603 { "cim_qcfg", &cim_qcfg_fops, 0400, 0 }, 3604 { "clk", &clk_fops, 0400, 0 }, 3605 { "devlog", &devlog_fops, 0400, 0 }, 3606 { "mboxlog", &mboxlog_fops, 0400, 0 }, 3607 { "mbox0", &mbox_debugfs_fops, 0600, 0 }, 3608 { "mbox1", &mbox_debugfs_fops, 0600, 1 }, 3609 { "mbox2", &mbox_debugfs_fops, 0600, 2 }, 3610 { "mbox3", &mbox_debugfs_fops, 0600, 3 }, 3611 { "mbox4", &mbox_debugfs_fops, 0600, 4 }, 3612 { "mbox5", &mbox_debugfs_fops, 0600, 5 }, 3613 { "mbox6", &mbox_debugfs_fops, 0600, 6 }, 3614 { "mbox7", &mbox_debugfs_fops, 0600, 7 }, 3615 { "trace0", &mps_trc_debugfs_fops, 0600, 0 }, 3616 { "trace1", &mps_trc_debugfs_fops, 0600, 1 }, 3617 { "trace2", &mps_trc_debugfs_fops, 0600, 2 }, 3618 { "trace3", &mps_trc_debugfs_fops, 0600, 3 }, 3619 { "l2t", &t4_l2t_fops, 0400, 0}, 3620 { "mps_tcam", &mps_tcam_debugfs_fops, 0400, 0 }, 3621 { "rss", &rss_debugfs_fops, 0400, 0 }, 3622 { "rss_config", &rss_config_fops, 0400, 0 }, 3623 { "rss_key", &rss_key_debugfs_fops, 0400, 0 }, 3624 { "rss_pf_config", &rss_pf_config_debugfs_fops, 0400, 0 }, 3625 { "rss_vf_config", &rss_vf_config_debugfs_fops, 0400, 0 }, 3626 { "resources", &resources_fops, 0400, 0 }, 3627 #ifdef CONFIG_CHELSIO_T4_DCB 3628 { "dcb_info", &dcb_info_debugfs_fops, 0400, 0 }, 3629 #endif 3630 { "sge_qinfo", &sge_qinfo_debugfs_fops, 0400, 0 }, 3631 { "ibq_tp0", &cim_ibq_fops, 0400, 0 }, 3632 { "ibq_tp1", &cim_ibq_fops, 0400, 1 }, 3633 { "ibq_ulp", &cim_ibq_fops, 0400, 2 }, 3634 { "ibq_sge0", &cim_ibq_fops, 0400, 3 }, 3635 { "ibq_sge1", &cim_ibq_fops, 0400, 4 }, 3636 { "ibq_ncsi", &cim_ibq_fops, 0400, 5 }, 3637 { "obq_ulp0", &cim_obq_fops, 0400, 0 }, 3638 { "obq_ulp1", &cim_obq_fops, 0400, 1 }, 3639 { "obq_ulp2", &cim_obq_fops, 0400, 2 }, 3640 { "obq_ulp3", &cim_obq_fops, 0400, 3 }, 3641 { "obq_sge", &cim_obq_fops, 0400, 4 }, 3642 { "obq_ncsi", &cim_obq_fops, 0400, 5 }, 3643 { "tp_la", &tp_la_fops, 0400, 0 }, 3644 { "ulprx_la", &ulprx_la_fops, 0400, 0 }, 3645 { "sensors", &sensors_fops, 0400, 0 }, 3646 { "pm_stats", &pm_stats_debugfs_fops, 0400, 0 }, 3647 { "tx_rate", &tx_rate_fops, 0400, 0 }, 3648 { "cctrl", &cctrl_tbl_fops, 0400, 0 }, 3649 #if IS_ENABLED(CONFIG_IPV6) 3650 { "clip_tbl", &clip_tbl_fops, 0400, 0 }, 3651 #endif 3652 { "tids", &tid_info_fops, 0400, 0}, 3653 { "blocked_fl", &blocked_fl_fops, 0600, 0 }, 3654 { "meminfo", &meminfo_fops, 0400, 0 }, 3655 { "crypto", &chcr_stats_fops, 0400, 0 }, 3656 { "tp_stats", &tp_stats_fops, 0400, 0 }, 3657 }; 3658 3659 /* Debug FS nodes common to all T5 and later adapters. 3660 */ 3661 static struct t4_debugfs_entry t5_debugfs_files[] = { 3662 { "obq_sge_rx_q0", &cim_obq_fops, 0400, 6 }, 3663 { "obq_sge_rx_q1", &cim_obq_fops, 0400, 7 }, 3664 }; 3665 3666 add_debugfs_files(adap, 3667 t4_debugfs_files, 3668 ARRAY_SIZE(t4_debugfs_files)); 3669 if (!is_t4(adap->params.chip)) 3670 add_debugfs_files(adap, 3671 t5_debugfs_files, 3672 ARRAY_SIZE(t5_debugfs_files)); 3673 3674 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 3675 if (i & EDRAM0_ENABLE_F) { 3676 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 3677 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM0_SIZE_G(size)); 3678 } 3679 if (i & EDRAM1_ENABLE_F) { 3680 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 3681 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size)); 3682 } 3683 if (is_t5(adap->params.chip)) { 3684 if (i & EXT_MEM0_ENABLE_F) { 3685 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 3686 add_debugfs_mem(adap, "mc0", MEM_MC0, 3687 EXT_MEM0_SIZE_G(size)); 3688 } 3689 if (i & EXT_MEM1_ENABLE_F) { 3690 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 3691 add_debugfs_mem(adap, "mc1", MEM_MC1, 3692 EXT_MEM1_SIZE_G(size)); 3693 } 3694 } else { 3695 if (i & EXT_MEM_ENABLE_F) { 3696 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A); 3697 add_debugfs_mem(adap, "mc", MEM_MC, 3698 EXT_MEM_SIZE_G(size)); 3699 } 3700 3701 if (i & HMA_MUX_F) { 3702 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 3703 add_debugfs_mem(adap, "hma", MEM_HMA, 3704 EXT_MEM1_SIZE_G(size)); 3705 } 3706 } 3707 3708 debugfs_create_file_size("flash", 0400, adap->debugfs_root, adap, 3709 &flash_debugfs_fops, adap->params.sf_size); 3710 debugfs_create_bool("use_backdoor", 0600, 3711 adap->debugfs_root, &adap->use_bd); 3712 debugfs_create_bool("trace_rss", 0600, 3713 adap->debugfs_root, &adap->trace_rss); 3714 3715 return 0; 3716 } 3717