1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/seq_file.h> 36 #include <linux/debugfs.h> 37 #include <linux/string_helpers.h> 38 #include <linux/sort.h> 39 #include <linux/ctype.h> 40 41 #include "cxgb4.h" 42 #include "t4_regs.h" 43 #include "t4_values.h" 44 #include "t4fw_api.h" 45 #include "cxgb4_debugfs.h" 46 #include "clip_tbl.h" 47 #include "l2t.h" 48 49 /* generic seq_file support for showing a table of size rows x width. */ 50 static void *seq_tab_get_idx(struct seq_tab *tb, loff_t pos) 51 { 52 pos -= tb->skip_first; 53 return pos >= tb->rows ? NULL : &tb->data[pos * tb->width]; 54 } 55 56 static void *seq_tab_start(struct seq_file *seq, loff_t *pos) 57 { 58 struct seq_tab *tb = seq->private; 59 60 if (tb->skip_first && *pos == 0) 61 return SEQ_START_TOKEN; 62 63 return seq_tab_get_idx(tb, *pos); 64 } 65 66 static void *seq_tab_next(struct seq_file *seq, void *v, loff_t *pos) 67 { 68 v = seq_tab_get_idx(seq->private, *pos + 1); 69 if (v) 70 ++*pos; 71 return v; 72 } 73 74 static void seq_tab_stop(struct seq_file *seq, void *v) 75 { 76 } 77 78 static int seq_tab_show(struct seq_file *seq, void *v) 79 { 80 const struct seq_tab *tb = seq->private; 81 82 return tb->show(seq, v, ((char *)v - tb->data) / tb->width); 83 } 84 85 static const struct seq_operations seq_tab_ops = { 86 .start = seq_tab_start, 87 .next = seq_tab_next, 88 .stop = seq_tab_stop, 89 .show = seq_tab_show 90 }; 91 92 struct seq_tab *seq_open_tab(struct file *f, unsigned int rows, 93 unsigned int width, unsigned int have_header, 94 int (*show)(struct seq_file *seq, void *v, int i)) 95 { 96 struct seq_tab *p; 97 98 p = __seq_open_private(f, &seq_tab_ops, sizeof(*p) + rows * width); 99 if (p) { 100 p->show = show; 101 p->rows = rows; 102 p->width = width; 103 p->skip_first = have_header != 0; 104 } 105 return p; 106 } 107 108 /* Trim the size of a seq_tab to the supplied number of rows. The operation is 109 * irreversible. 110 */ 111 static int seq_tab_trim(struct seq_tab *p, unsigned int new_rows) 112 { 113 if (new_rows > p->rows) 114 return -EINVAL; 115 p->rows = new_rows; 116 return 0; 117 } 118 119 static int cim_la_show(struct seq_file *seq, void *v, int idx) 120 { 121 if (v == SEQ_START_TOKEN) 122 seq_puts(seq, "Status Data PC LS0Stat LS0Addr " 123 " LS0Data\n"); 124 else { 125 const u32 *p = v; 126 127 seq_printf(seq, 128 " %02x %x%07x %x%07x %08x %08x %08x%08x%08x%08x\n", 129 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 130 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 131 p[6], p[7]); 132 } 133 return 0; 134 } 135 136 static int cim_la_show_3in1(struct seq_file *seq, void *v, int idx) 137 { 138 if (v == SEQ_START_TOKEN) { 139 seq_puts(seq, "Status Data PC\n"); 140 } else { 141 const u32 *p = v; 142 143 seq_printf(seq, " %02x %08x %08x\n", p[5] & 0xff, p[6], 144 p[7]); 145 seq_printf(seq, " %02x %02x%06x %02x%06x\n", 146 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 147 p[4] & 0xff, p[5] >> 8); 148 seq_printf(seq, " %02x %x%07x %x%07x\n", (p[0] >> 4) & 0xff, 149 p[0] & 0xf, p[1] >> 4, p[1] & 0xf, p[2] >> 4); 150 } 151 return 0; 152 } 153 154 static int cim_la_show_t6(struct seq_file *seq, void *v, int idx) 155 { 156 if (v == SEQ_START_TOKEN) { 157 seq_puts(seq, "Status Inst Data PC LS0Stat " 158 "LS0Addr LS0Data LS1Stat LS1Addr LS1Data\n"); 159 } else { 160 const u32 *p = v; 161 162 seq_printf(seq, " %02x %04x%04x %04x%04x %04x%04x %08x %08x %08x %08x %08x %08x\n", 163 (p[9] >> 16) & 0xff, /* Status */ 164 p[9] & 0xffff, p[8] >> 16, /* Inst */ 165 p[8] & 0xffff, p[7] >> 16, /* Data */ 166 p[7] & 0xffff, p[6] >> 16, /* PC */ 167 p[2], p[1], p[0], /* LS0 Stat, Addr and Data */ 168 p[5], p[4], p[3]); /* LS1 Stat, Addr and Data */ 169 } 170 return 0; 171 } 172 173 static int cim_la_show_pc_t6(struct seq_file *seq, void *v, int idx) 174 { 175 if (v == SEQ_START_TOKEN) { 176 seq_puts(seq, "Status Inst Data PC\n"); 177 } else { 178 const u32 *p = v; 179 180 seq_printf(seq, " %02x %08x %08x %08x\n", 181 p[3] & 0xff, p[2], p[1], p[0]); 182 seq_printf(seq, " %02x %02x%06x %02x%06x %02x%06x\n", 183 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 184 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 185 seq_printf(seq, " %02x %04x%04x %04x%04x %04x%04x\n", 186 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 187 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 188 p[6] >> 16); 189 } 190 return 0; 191 } 192 193 static int cim_la_open(struct inode *inode, struct file *file) 194 { 195 int ret; 196 unsigned int cfg; 197 struct seq_tab *p; 198 struct adapter *adap = inode->i_private; 199 200 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg); 201 if (ret) 202 return ret; 203 204 if (is_t6(adap->params.chip)) { 205 /* +1 to account for integer division of CIMLA_SIZE/10 */ 206 p = seq_open_tab(file, (adap->params.cim_la_size / 10) + 1, 207 10 * sizeof(u32), 1, 208 cfg & UPDBGLACAPTPCONLY_F ? 209 cim_la_show_pc_t6 : cim_la_show_t6); 210 } else { 211 p = seq_open_tab(file, adap->params.cim_la_size / 8, 212 8 * sizeof(u32), 1, 213 cfg & UPDBGLACAPTPCONLY_F ? cim_la_show_3in1 : 214 cim_la_show); 215 } 216 if (!p) 217 return -ENOMEM; 218 219 ret = t4_cim_read_la(adap, (u32 *)p->data, NULL); 220 if (ret) 221 seq_release_private(inode, file); 222 return ret; 223 } 224 225 static const struct file_operations cim_la_fops = { 226 .owner = THIS_MODULE, 227 .open = cim_la_open, 228 .read = seq_read, 229 .llseek = seq_lseek, 230 .release = seq_release_private 231 }; 232 233 static int cim_pif_la_show(struct seq_file *seq, void *v, int idx) 234 { 235 const u32 *p = v; 236 237 if (v == SEQ_START_TOKEN) { 238 seq_puts(seq, "Cntl ID DataBE Addr Data\n"); 239 } else if (idx < CIM_PIFLA_SIZE) { 240 seq_printf(seq, " %02x %02x %04x %08x %08x%08x%08x%08x\n", 241 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, 242 p[5] & 0xffff, p[4], p[3], p[2], p[1], p[0]); 243 } else { 244 if (idx == CIM_PIFLA_SIZE) 245 seq_puts(seq, "\nCntl ID Data\n"); 246 seq_printf(seq, " %02x %02x %08x%08x%08x%08x\n", 247 (p[4] >> 6) & 0xff, p[4] & 0x3f, 248 p[3], p[2], p[1], p[0]); 249 } 250 return 0; 251 } 252 253 static int cim_pif_la_open(struct inode *inode, struct file *file) 254 { 255 struct seq_tab *p; 256 struct adapter *adap = inode->i_private; 257 258 p = seq_open_tab(file, 2 * CIM_PIFLA_SIZE, 6 * sizeof(u32), 1, 259 cim_pif_la_show); 260 if (!p) 261 return -ENOMEM; 262 263 t4_cim_read_pif_la(adap, (u32 *)p->data, 264 (u32 *)p->data + 6 * CIM_PIFLA_SIZE, NULL, NULL); 265 return 0; 266 } 267 268 static const struct file_operations cim_pif_la_fops = { 269 .owner = THIS_MODULE, 270 .open = cim_pif_la_open, 271 .read = seq_read, 272 .llseek = seq_lseek, 273 .release = seq_release_private 274 }; 275 276 static int cim_ma_la_show(struct seq_file *seq, void *v, int idx) 277 { 278 const u32 *p = v; 279 280 if (v == SEQ_START_TOKEN) { 281 seq_puts(seq, "\n"); 282 } else if (idx < CIM_MALA_SIZE) { 283 seq_printf(seq, "%02x%08x%08x%08x%08x\n", 284 p[4], p[3], p[2], p[1], p[0]); 285 } else { 286 if (idx == CIM_MALA_SIZE) 287 seq_puts(seq, 288 "\nCnt ID Tag UE Data RDY VLD\n"); 289 seq_printf(seq, "%3u %2u %x %u %08x%08x %u %u\n", 290 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 291 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 292 (p[1] >> 2) | ((p[2] & 3) << 30), 293 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 294 p[0] & 1); 295 } 296 return 0; 297 } 298 299 static int cim_ma_la_open(struct inode *inode, struct file *file) 300 { 301 struct seq_tab *p; 302 struct adapter *adap = inode->i_private; 303 304 p = seq_open_tab(file, 2 * CIM_MALA_SIZE, 5 * sizeof(u32), 1, 305 cim_ma_la_show); 306 if (!p) 307 return -ENOMEM; 308 309 t4_cim_read_ma_la(adap, (u32 *)p->data, 310 (u32 *)p->data + 5 * CIM_MALA_SIZE); 311 return 0; 312 } 313 314 static const struct file_operations cim_ma_la_fops = { 315 .owner = THIS_MODULE, 316 .open = cim_ma_la_open, 317 .read = seq_read, 318 .llseek = seq_lseek, 319 .release = seq_release_private 320 }; 321 322 static int cim_qcfg_show(struct seq_file *seq, void *v) 323 { 324 static const char * const qname[] = { 325 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", 326 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", 327 "SGE0-RX", "SGE1-RX" 328 }; 329 330 int i; 331 struct adapter *adap = seq->private; 332 u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 333 u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 334 u32 stat[(4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5))]; 335 u16 thres[CIM_NUM_IBQ]; 336 u32 obq_wr_t4[2 * CIM_NUM_OBQ], *wr; 337 u32 obq_wr_t5[2 * CIM_NUM_OBQ_T5]; 338 u32 *p = stat; 339 int cim_num_obq = is_t4(adap->params.chip) ? 340 CIM_NUM_OBQ : CIM_NUM_OBQ_T5; 341 342 i = t4_cim_read(adap, is_t4(adap->params.chip) ? UP_IBQ_0_RDADDR_A : 343 UP_IBQ_0_SHADOW_RDADDR_A, 344 ARRAY_SIZE(stat), stat); 345 if (!i) { 346 if (is_t4(adap->params.chip)) { 347 i = t4_cim_read(adap, UP_OBQ_0_REALADDR_A, 348 ARRAY_SIZE(obq_wr_t4), obq_wr_t4); 349 wr = obq_wr_t4; 350 } else { 351 i = t4_cim_read(adap, UP_OBQ_0_SHADOW_REALADDR_A, 352 ARRAY_SIZE(obq_wr_t5), obq_wr_t5); 353 wr = obq_wr_t5; 354 } 355 } 356 if (i) 357 return i; 358 359 t4_read_cimq_cfg(adap, base, size, thres); 360 361 seq_printf(seq, 362 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail\n"); 363 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 364 seq_printf(seq, "%7s %5x %5u %5u %6x %4x %4u %4u %5u\n", 365 qname[i], base[i], size[i], thres[i], 366 IBQRDADDR_G(p[0]), IBQWRADDR_G(p[1]), 367 QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]), 368 QUEREMFLITS_G(p[2]) * 16); 369 for ( ; i < CIM_NUM_IBQ + cim_num_obq; i++, p += 4, wr += 2) 370 seq_printf(seq, "%7s %5x %5u %12x %4x %4u %4u %5u\n", 371 qname[i], base[i], size[i], 372 QUERDADDR_G(p[0]) & 0x3fff, wr[0] - base[i], 373 QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]), 374 QUEREMFLITS_G(p[2]) * 16); 375 return 0; 376 } 377 378 static int cim_qcfg_open(struct inode *inode, struct file *file) 379 { 380 return single_open(file, cim_qcfg_show, inode->i_private); 381 } 382 383 static const struct file_operations cim_qcfg_fops = { 384 .owner = THIS_MODULE, 385 .open = cim_qcfg_open, 386 .read = seq_read, 387 .llseek = seq_lseek, 388 .release = single_release, 389 }; 390 391 static int cimq_show(struct seq_file *seq, void *v, int idx) 392 { 393 const u32 *p = v; 394 395 seq_printf(seq, "%#06x: %08x %08x %08x %08x\n", idx * 16, p[0], p[1], 396 p[2], p[3]); 397 return 0; 398 } 399 400 static int cim_ibq_open(struct inode *inode, struct file *file) 401 { 402 int ret; 403 struct seq_tab *p; 404 unsigned int qid = (uintptr_t)inode->i_private & 7; 405 struct adapter *adap = inode->i_private - qid; 406 407 p = seq_open_tab(file, CIM_IBQ_SIZE, 4 * sizeof(u32), 0, cimq_show); 408 if (!p) 409 return -ENOMEM; 410 411 ret = t4_read_cim_ibq(adap, qid, (u32 *)p->data, CIM_IBQ_SIZE * 4); 412 if (ret < 0) 413 seq_release_private(inode, file); 414 else 415 ret = 0; 416 return ret; 417 } 418 419 static const struct file_operations cim_ibq_fops = { 420 .owner = THIS_MODULE, 421 .open = cim_ibq_open, 422 .read = seq_read, 423 .llseek = seq_lseek, 424 .release = seq_release_private 425 }; 426 427 static int cim_obq_open(struct inode *inode, struct file *file) 428 { 429 int ret; 430 struct seq_tab *p; 431 unsigned int qid = (uintptr_t)inode->i_private & 7; 432 struct adapter *adap = inode->i_private - qid; 433 434 p = seq_open_tab(file, 6 * CIM_OBQ_SIZE, 4 * sizeof(u32), 0, cimq_show); 435 if (!p) 436 return -ENOMEM; 437 438 ret = t4_read_cim_obq(adap, qid, (u32 *)p->data, 6 * CIM_OBQ_SIZE * 4); 439 if (ret < 0) { 440 seq_release_private(inode, file); 441 } else { 442 seq_tab_trim(p, ret / 4); 443 ret = 0; 444 } 445 return ret; 446 } 447 448 static const struct file_operations cim_obq_fops = { 449 .owner = THIS_MODULE, 450 .open = cim_obq_open, 451 .read = seq_read, 452 .llseek = seq_lseek, 453 .release = seq_release_private 454 }; 455 456 struct field_desc { 457 const char *name; 458 unsigned int start; 459 unsigned int width; 460 }; 461 462 static void field_desc_show(struct seq_file *seq, u64 v, 463 const struct field_desc *p) 464 { 465 char buf[32]; 466 int line_size = 0; 467 468 while (p->name) { 469 u64 mask = (1ULL << p->width) - 1; 470 int len = scnprintf(buf, sizeof(buf), "%s: %llu", p->name, 471 ((unsigned long long)v >> p->start) & mask); 472 473 if (line_size + len >= 79) { 474 line_size = 8; 475 seq_puts(seq, "\n "); 476 } 477 seq_printf(seq, "%s ", buf); 478 line_size += len + 1; 479 p++; 480 } 481 seq_putc(seq, '\n'); 482 } 483 484 static struct field_desc tp_la0[] = { 485 { "RcfOpCodeOut", 60, 4 }, 486 { "State", 56, 4 }, 487 { "WcfState", 52, 4 }, 488 { "RcfOpcSrcOut", 50, 2 }, 489 { "CRxError", 49, 1 }, 490 { "ERxError", 48, 1 }, 491 { "SanityFailed", 47, 1 }, 492 { "SpuriousMsg", 46, 1 }, 493 { "FlushInputMsg", 45, 1 }, 494 { "FlushInputCpl", 44, 1 }, 495 { "RssUpBit", 43, 1 }, 496 { "RssFilterHit", 42, 1 }, 497 { "Tid", 32, 10 }, 498 { "InitTcb", 31, 1 }, 499 { "LineNumber", 24, 7 }, 500 { "Emsg", 23, 1 }, 501 { "EdataOut", 22, 1 }, 502 { "Cmsg", 21, 1 }, 503 { "CdataOut", 20, 1 }, 504 { "EreadPdu", 19, 1 }, 505 { "CreadPdu", 18, 1 }, 506 { "TunnelPkt", 17, 1 }, 507 { "RcfPeerFin", 16, 1 }, 508 { "RcfReasonOut", 12, 4 }, 509 { "TxCchannel", 10, 2 }, 510 { "RcfTxChannel", 8, 2 }, 511 { "RxEchannel", 6, 2 }, 512 { "RcfRxChannel", 5, 1 }, 513 { "RcfDataOutSrdy", 4, 1 }, 514 { "RxDvld", 3, 1 }, 515 { "RxOoDvld", 2, 1 }, 516 { "RxCongestion", 1, 1 }, 517 { "TxCongestion", 0, 1 }, 518 { NULL } 519 }; 520 521 static int tp_la_show(struct seq_file *seq, void *v, int idx) 522 { 523 const u64 *p = v; 524 525 field_desc_show(seq, *p, tp_la0); 526 return 0; 527 } 528 529 static int tp_la_show2(struct seq_file *seq, void *v, int idx) 530 { 531 const u64 *p = v; 532 533 if (idx) 534 seq_putc(seq, '\n'); 535 field_desc_show(seq, p[0], tp_la0); 536 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 537 field_desc_show(seq, p[1], tp_la0); 538 return 0; 539 } 540 541 static int tp_la_show3(struct seq_file *seq, void *v, int idx) 542 { 543 static struct field_desc tp_la1[] = { 544 { "CplCmdIn", 56, 8 }, 545 { "CplCmdOut", 48, 8 }, 546 { "ESynOut", 47, 1 }, 547 { "EAckOut", 46, 1 }, 548 { "EFinOut", 45, 1 }, 549 { "ERstOut", 44, 1 }, 550 { "SynIn", 43, 1 }, 551 { "AckIn", 42, 1 }, 552 { "FinIn", 41, 1 }, 553 { "RstIn", 40, 1 }, 554 { "DataIn", 39, 1 }, 555 { "DataInVld", 38, 1 }, 556 { "PadIn", 37, 1 }, 557 { "RxBufEmpty", 36, 1 }, 558 { "RxDdp", 35, 1 }, 559 { "RxFbCongestion", 34, 1 }, 560 { "TxFbCongestion", 33, 1 }, 561 { "TxPktSumSrdy", 32, 1 }, 562 { "RcfUlpType", 28, 4 }, 563 { "Eread", 27, 1 }, 564 { "Ebypass", 26, 1 }, 565 { "Esave", 25, 1 }, 566 { "Static0", 24, 1 }, 567 { "Cread", 23, 1 }, 568 { "Cbypass", 22, 1 }, 569 { "Csave", 21, 1 }, 570 { "CPktOut", 20, 1 }, 571 { "RxPagePoolFull", 18, 2 }, 572 { "RxLpbkPkt", 17, 1 }, 573 { "TxLpbkPkt", 16, 1 }, 574 { "RxVfValid", 15, 1 }, 575 { "SynLearned", 14, 1 }, 576 { "SetDelEntry", 13, 1 }, 577 { "SetInvEntry", 12, 1 }, 578 { "CpcmdDvld", 11, 1 }, 579 { "CpcmdSave", 10, 1 }, 580 { "RxPstructsFull", 8, 2 }, 581 { "EpcmdDvld", 7, 1 }, 582 { "EpcmdFlush", 6, 1 }, 583 { "EpcmdTrimPrefix", 5, 1 }, 584 { "EpcmdTrimPostfix", 4, 1 }, 585 { "ERssIp4Pkt", 3, 1 }, 586 { "ERssIp6Pkt", 2, 1 }, 587 { "ERssTcpUdpPkt", 1, 1 }, 588 { "ERssFceFipPkt", 0, 1 }, 589 { NULL } 590 }; 591 static struct field_desc tp_la2[] = { 592 { "CplCmdIn", 56, 8 }, 593 { "MpsVfVld", 55, 1 }, 594 { "MpsPf", 52, 3 }, 595 { "MpsVf", 44, 8 }, 596 { "SynIn", 43, 1 }, 597 { "AckIn", 42, 1 }, 598 { "FinIn", 41, 1 }, 599 { "RstIn", 40, 1 }, 600 { "DataIn", 39, 1 }, 601 { "DataInVld", 38, 1 }, 602 { "PadIn", 37, 1 }, 603 { "RxBufEmpty", 36, 1 }, 604 { "RxDdp", 35, 1 }, 605 { "RxFbCongestion", 34, 1 }, 606 { "TxFbCongestion", 33, 1 }, 607 { "TxPktSumSrdy", 32, 1 }, 608 { "RcfUlpType", 28, 4 }, 609 { "Eread", 27, 1 }, 610 { "Ebypass", 26, 1 }, 611 { "Esave", 25, 1 }, 612 { "Static0", 24, 1 }, 613 { "Cread", 23, 1 }, 614 { "Cbypass", 22, 1 }, 615 { "Csave", 21, 1 }, 616 { "CPktOut", 20, 1 }, 617 { "RxPagePoolFull", 18, 2 }, 618 { "RxLpbkPkt", 17, 1 }, 619 { "TxLpbkPkt", 16, 1 }, 620 { "RxVfValid", 15, 1 }, 621 { "SynLearned", 14, 1 }, 622 { "SetDelEntry", 13, 1 }, 623 { "SetInvEntry", 12, 1 }, 624 { "CpcmdDvld", 11, 1 }, 625 { "CpcmdSave", 10, 1 }, 626 { "RxPstructsFull", 8, 2 }, 627 { "EpcmdDvld", 7, 1 }, 628 { "EpcmdFlush", 6, 1 }, 629 { "EpcmdTrimPrefix", 5, 1 }, 630 { "EpcmdTrimPostfix", 4, 1 }, 631 { "ERssIp4Pkt", 3, 1 }, 632 { "ERssIp6Pkt", 2, 1 }, 633 { "ERssTcpUdpPkt", 1, 1 }, 634 { "ERssFceFipPkt", 0, 1 }, 635 { NULL } 636 }; 637 const u64 *p = v; 638 639 if (idx) 640 seq_putc(seq, '\n'); 641 field_desc_show(seq, p[0], tp_la0); 642 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 643 field_desc_show(seq, p[1], (p[0] & BIT(17)) ? tp_la2 : tp_la1); 644 return 0; 645 } 646 647 static int tp_la_open(struct inode *inode, struct file *file) 648 { 649 struct seq_tab *p; 650 struct adapter *adap = inode->i_private; 651 652 switch (DBGLAMODE_G(t4_read_reg(adap, TP_DBG_LA_CONFIG_A))) { 653 case 2: 654 p = seq_open_tab(file, TPLA_SIZE / 2, 2 * sizeof(u64), 0, 655 tp_la_show2); 656 break; 657 case 3: 658 p = seq_open_tab(file, TPLA_SIZE / 2, 2 * sizeof(u64), 0, 659 tp_la_show3); 660 break; 661 default: 662 p = seq_open_tab(file, TPLA_SIZE, sizeof(u64), 0, tp_la_show); 663 } 664 if (!p) 665 return -ENOMEM; 666 667 t4_tp_read_la(adap, (u64 *)p->data, NULL); 668 return 0; 669 } 670 671 static ssize_t tp_la_write(struct file *file, const char __user *buf, 672 size_t count, loff_t *pos) 673 { 674 int err; 675 char s[32]; 676 unsigned long val; 677 size_t size = min(sizeof(s) - 1, count); 678 struct adapter *adap = file_inode(file)->i_private; 679 680 if (copy_from_user(s, buf, size)) 681 return -EFAULT; 682 s[size] = '\0'; 683 err = kstrtoul(s, 0, &val); 684 if (err) 685 return err; 686 if (val > 0xffff) 687 return -EINVAL; 688 adap->params.tp.la_mask = val << 16; 689 t4_set_reg_field(adap, TP_DBG_LA_CONFIG_A, 0xffff0000U, 690 adap->params.tp.la_mask); 691 return count; 692 } 693 694 static const struct file_operations tp_la_fops = { 695 .owner = THIS_MODULE, 696 .open = tp_la_open, 697 .read = seq_read, 698 .llseek = seq_lseek, 699 .release = seq_release_private, 700 .write = tp_la_write 701 }; 702 703 static int ulprx_la_show(struct seq_file *seq, void *v, int idx) 704 { 705 const u32 *p = v; 706 707 if (v == SEQ_START_TOKEN) 708 seq_puts(seq, " Pcmd Type Message" 709 " Data\n"); 710 else 711 seq_printf(seq, "%08x%08x %4x %08x %08x%08x%08x%08x\n", 712 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 713 return 0; 714 } 715 716 static int ulprx_la_open(struct inode *inode, struct file *file) 717 { 718 struct seq_tab *p; 719 struct adapter *adap = inode->i_private; 720 721 p = seq_open_tab(file, ULPRX_LA_SIZE, 8 * sizeof(u32), 1, 722 ulprx_la_show); 723 if (!p) 724 return -ENOMEM; 725 726 t4_ulprx_read_la(adap, (u32 *)p->data); 727 return 0; 728 } 729 730 static const struct file_operations ulprx_la_fops = { 731 .owner = THIS_MODULE, 732 .open = ulprx_la_open, 733 .read = seq_read, 734 .llseek = seq_lseek, 735 .release = seq_release_private 736 }; 737 738 /* Show the PM memory stats. These stats include: 739 * 740 * TX: 741 * Read: memory read operation 742 * Write Bypass: cut-through 743 * Bypass + mem: cut-through and save copy 744 * 745 * RX: 746 * Read: memory read 747 * Write Bypass: cut-through 748 * Flush: payload trim or drop 749 */ 750 static int pm_stats_show(struct seq_file *seq, void *v) 751 { 752 static const char * const tx_pm_stats[] = { 753 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:" 754 }; 755 static const char * const rx_pm_stats[] = { 756 "Read:", "Write bypass:", "Write mem:", "Flush:" 757 }; 758 759 int i; 760 u32 tx_cnt[T6_PM_NSTATS], rx_cnt[T6_PM_NSTATS]; 761 u64 tx_cyc[T6_PM_NSTATS], rx_cyc[T6_PM_NSTATS]; 762 struct adapter *adap = seq->private; 763 764 t4_pmtx_get_stats(adap, tx_cnt, tx_cyc); 765 t4_pmrx_get_stats(adap, rx_cnt, rx_cyc); 766 767 seq_printf(seq, "%13s %10s %20s\n", " ", "Tx pcmds", "Tx bytes"); 768 for (i = 0; i < PM_NSTATS - 1; i++) 769 seq_printf(seq, "%-13s %10u %20llu\n", 770 tx_pm_stats[i], tx_cnt[i], tx_cyc[i]); 771 772 seq_printf(seq, "%13s %10s %20s\n", " ", "Rx pcmds", "Rx bytes"); 773 for (i = 0; i < PM_NSTATS - 1; i++) 774 seq_printf(seq, "%-13s %10u %20llu\n", 775 rx_pm_stats[i], rx_cnt[i], rx_cyc[i]); 776 777 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 778 /* In T5 the granularity of the total wait is too fine. 779 * It is not useful as it reaches the max value too fast. 780 * Hence display this Input FIFO wait for T6 onwards. 781 */ 782 seq_printf(seq, "%13s %10s %20s\n", 783 " ", "Total wait", "Total Occupancy"); 784 seq_printf(seq, "Tx FIFO wait %10u %20llu\n", 785 tx_cnt[i], tx_cyc[i]); 786 seq_printf(seq, "Rx FIFO wait %10u %20llu\n", 787 rx_cnt[i], rx_cyc[i]); 788 789 /* Skip index 6 as there is nothing useful ihere */ 790 i += 2; 791 792 /* At index 7, a new stat for read latency (count, total wait) 793 * is added. 794 */ 795 seq_printf(seq, "%13s %10s %20s\n", 796 " ", "Reads", "Total wait"); 797 seq_printf(seq, "Tx latency %10u %20llu\n", 798 tx_cnt[i], tx_cyc[i]); 799 seq_printf(seq, "Rx latency %10u %20llu\n", 800 rx_cnt[i], rx_cyc[i]); 801 } 802 return 0; 803 } 804 805 static int pm_stats_open(struct inode *inode, struct file *file) 806 { 807 return single_open(file, pm_stats_show, inode->i_private); 808 } 809 810 static ssize_t pm_stats_clear(struct file *file, const char __user *buf, 811 size_t count, loff_t *pos) 812 { 813 struct adapter *adap = file_inode(file)->i_private; 814 815 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, 0); 816 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, 0); 817 return count; 818 } 819 820 static const struct file_operations pm_stats_debugfs_fops = { 821 .owner = THIS_MODULE, 822 .open = pm_stats_open, 823 .read = seq_read, 824 .llseek = seq_lseek, 825 .release = single_release, 826 .write = pm_stats_clear 827 }; 828 829 static int tx_rate_show(struct seq_file *seq, void *v) 830 { 831 u64 nrate[NCHAN], orate[NCHAN]; 832 struct adapter *adap = seq->private; 833 834 t4_get_chan_txrate(adap, nrate, orate); 835 if (adap->params.arch.nchan == NCHAN) { 836 seq_puts(seq, " channel 0 channel 1 " 837 "channel 2 channel 3\n"); 838 seq_printf(seq, "NIC B/s: %10llu %10llu %10llu %10llu\n", 839 (unsigned long long)nrate[0], 840 (unsigned long long)nrate[1], 841 (unsigned long long)nrate[2], 842 (unsigned long long)nrate[3]); 843 seq_printf(seq, "Offload B/s: %10llu %10llu %10llu %10llu\n", 844 (unsigned long long)orate[0], 845 (unsigned long long)orate[1], 846 (unsigned long long)orate[2], 847 (unsigned long long)orate[3]); 848 } else { 849 seq_puts(seq, " channel 0 channel 1\n"); 850 seq_printf(seq, "NIC B/s: %10llu %10llu\n", 851 (unsigned long long)nrate[0], 852 (unsigned long long)nrate[1]); 853 seq_printf(seq, "Offload B/s: %10llu %10llu\n", 854 (unsigned long long)orate[0], 855 (unsigned long long)orate[1]); 856 } 857 return 0; 858 } 859 860 DEFINE_SIMPLE_DEBUGFS_FILE(tx_rate); 861 862 static int cctrl_tbl_show(struct seq_file *seq, void *v) 863 { 864 static const char * const dec_fac[] = { 865 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 866 "0.9375" }; 867 868 int i; 869 u16 (*incr)[NCCTRL_WIN]; 870 struct adapter *adap = seq->private; 871 872 incr = kmalloc(sizeof(*incr) * NMTUS, GFP_KERNEL); 873 if (!incr) 874 return -ENOMEM; 875 876 t4_read_cong_tbl(adap, incr); 877 878 for (i = 0; i < NCCTRL_WIN; ++i) { 879 seq_printf(seq, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 880 incr[0][i], incr[1][i], incr[2][i], incr[3][i], 881 incr[4][i], incr[5][i], incr[6][i], incr[7][i]); 882 seq_printf(seq, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 883 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 884 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 885 adap->params.a_wnd[i], 886 dec_fac[adap->params.b_wnd[i]]); 887 } 888 889 kfree(incr); 890 return 0; 891 } 892 893 DEFINE_SIMPLE_DEBUGFS_FILE(cctrl_tbl); 894 895 /* Format a value in a unit that differs from the value's native unit by the 896 * given factor. 897 */ 898 static char *unit_conv(char *buf, size_t len, unsigned int val, 899 unsigned int factor) 900 { 901 unsigned int rem = val % factor; 902 903 if (rem == 0) { 904 snprintf(buf, len, "%u", val / factor); 905 } else { 906 while (rem % 10 == 0) 907 rem /= 10; 908 snprintf(buf, len, "%u.%u", val / factor, rem); 909 } 910 return buf; 911 } 912 913 static int clk_show(struct seq_file *seq, void *v) 914 { 915 char buf[32]; 916 struct adapter *adap = seq->private; 917 unsigned int cclk_ps = 1000000000 / adap->params.vpd.cclk; /* in ps */ 918 u32 res = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); 919 unsigned int tre = TIMERRESOLUTION_G(res); 920 unsigned int dack_re = DELAYEDACKRESOLUTION_G(res); 921 unsigned long long tp_tick_us = (cclk_ps << tre) / 1000000; /* in us */ 922 923 seq_printf(seq, "Core clock period: %s ns\n", 924 unit_conv(buf, sizeof(buf), cclk_ps, 1000)); 925 seq_printf(seq, "TP timer tick: %s us\n", 926 unit_conv(buf, sizeof(buf), (cclk_ps << tre), 1000000)); 927 seq_printf(seq, "TCP timestamp tick: %s us\n", 928 unit_conv(buf, sizeof(buf), 929 (cclk_ps << TIMESTAMPRESOLUTION_G(res)), 1000000)); 930 seq_printf(seq, "DACK tick: %s us\n", 931 unit_conv(buf, sizeof(buf), (cclk_ps << dack_re), 1000000)); 932 seq_printf(seq, "DACK timer: %u us\n", 933 ((cclk_ps << dack_re) / 1000000) * 934 t4_read_reg(adap, TP_DACK_TIMER_A)); 935 seq_printf(seq, "Retransmit min: %llu us\n", 936 tp_tick_us * t4_read_reg(adap, TP_RXT_MIN_A)); 937 seq_printf(seq, "Retransmit max: %llu us\n", 938 tp_tick_us * t4_read_reg(adap, TP_RXT_MAX_A)); 939 seq_printf(seq, "Persist timer min: %llu us\n", 940 tp_tick_us * t4_read_reg(adap, TP_PERS_MIN_A)); 941 seq_printf(seq, "Persist timer max: %llu us\n", 942 tp_tick_us * t4_read_reg(adap, TP_PERS_MAX_A)); 943 seq_printf(seq, "Keepalive idle timer: %llu us\n", 944 tp_tick_us * t4_read_reg(adap, TP_KEEP_IDLE_A)); 945 seq_printf(seq, "Keepalive interval: %llu us\n", 946 tp_tick_us * t4_read_reg(adap, TP_KEEP_INTVL_A)); 947 seq_printf(seq, "Initial SRTT: %llu us\n", 948 tp_tick_us * INITSRTT_G(t4_read_reg(adap, TP_INIT_SRTT_A))); 949 seq_printf(seq, "FINWAIT2 timer: %llu us\n", 950 tp_tick_us * t4_read_reg(adap, TP_FINWAIT2_TIMER_A)); 951 952 return 0; 953 } 954 955 DEFINE_SIMPLE_DEBUGFS_FILE(clk); 956 957 /* Firmware Device Log dump. */ 958 static const char * const devlog_level_strings[] = { 959 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 960 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 961 [FW_DEVLOG_LEVEL_ERR] = "ERR", 962 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 963 [FW_DEVLOG_LEVEL_INFO] = "INFO", 964 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 965 }; 966 967 static const char * const devlog_facility_strings[] = { 968 [FW_DEVLOG_FACILITY_CORE] = "CORE", 969 [FW_DEVLOG_FACILITY_CF] = "CF", 970 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 971 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 972 [FW_DEVLOG_FACILITY_RES] = "RES", 973 [FW_DEVLOG_FACILITY_HW] = "HW", 974 [FW_DEVLOG_FACILITY_FLR] = "FLR", 975 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 976 [FW_DEVLOG_FACILITY_PHY] = "PHY", 977 [FW_DEVLOG_FACILITY_MAC] = "MAC", 978 [FW_DEVLOG_FACILITY_PORT] = "PORT", 979 [FW_DEVLOG_FACILITY_VI] = "VI", 980 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 981 [FW_DEVLOG_FACILITY_ACL] = "ACL", 982 [FW_DEVLOG_FACILITY_TM] = "TM", 983 [FW_DEVLOG_FACILITY_QFC] = "QFC", 984 [FW_DEVLOG_FACILITY_DCB] = "DCB", 985 [FW_DEVLOG_FACILITY_ETH] = "ETH", 986 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 987 [FW_DEVLOG_FACILITY_RI] = "RI", 988 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 989 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 990 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 991 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE" 992 }; 993 994 /* Information gathered by Device Log Open routine for the display routine. 995 */ 996 struct devlog_info { 997 unsigned int nentries; /* number of entries in log[] */ 998 unsigned int first; /* first [temporal] entry in log[] */ 999 struct fw_devlog_e log[0]; /* Firmware Device Log */ 1000 }; 1001 1002 /* Dump a Firmaware Device Log entry. 1003 */ 1004 static int devlog_show(struct seq_file *seq, void *v) 1005 { 1006 if (v == SEQ_START_TOKEN) 1007 seq_printf(seq, "%10s %15s %8s %8s %s\n", 1008 "Seq#", "Tstamp", "Level", "Facility", "Message"); 1009 else { 1010 struct devlog_info *dinfo = seq->private; 1011 int fidx = (uintptr_t)v - 2; 1012 unsigned long index; 1013 struct fw_devlog_e *e; 1014 1015 /* Get a pointer to the log entry to display. Skip unused log 1016 * entries. 1017 */ 1018 index = dinfo->first + fidx; 1019 if (index >= dinfo->nentries) 1020 index -= dinfo->nentries; 1021 e = &dinfo->log[index]; 1022 if (e->timestamp == 0) 1023 return 0; 1024 1025 /* Print the message. This depends on the firmware using 1026 * exactly the same formating strings as the kernel so we may 1027 * eventually have to put a format interpreter in here ... 1028 */ 1029 seq_printf(seq, "%10d %15llu %8s %8s ", 1030 be32_to_cpu(e->seqno), 1031 be64_to_cpu(e->timestamp), 1032 (e->level < ARRAY_SIZE(devlog_level_strings) 1033 ? devlog_level_strings[e->level] 1034 : "UNKNOWN"), 1035 (e->facility < ARRAY_SIZE(devlog_facility_strings) 1036 ? devlog_facility_strings[e->facility] 1037 : "UNKNOWN")); 1038 seq_printf(seq, e->fmt, 1039 be32_to_cpu(e->params[0]), 1040 be32_to_cpu(e->params[1]), 1041 be32_to_cpu(e->params[2]), 1042 be32_to_cpu(e->params[3]), 1043 be32_to_cpu(e->params[4]), 1044 be32_to_cpu(e->params[5]), 1045 be32_to_cpu(e->params[6]), 1046 be32_to_cpu(e->params[7])); 1047 } 1048 return 0; 1049 } 1050 1051 /* Sequential File Operations for Device Log. 1052 */ 1053 static inline void *devlog_get_idx(struct devlog_info *dinfo, loff_t pos) 1054 { 1055 if (pos > dinfo->nentries) 1056 return NULL; 1057 1058 return (void *)(uintptr_t)(pos + 1); 1059 } 1060 1061 static void *devlog_start(struct seq_file *seq, loff_t *pos) 1062 { 1063 struct devlog_info *dinfo = seq->private; 1064 1065 return (*pos 1066 ? devlog_get_idx(dinfo, *pos) 1067 : SEQ_START_TOKEN); 1068 } 1069 1070 static void *devlog_next(struct seq_file *seq, void *v, loff_t *pos) 1071 { 1072 struct devlog_info *dinfo = seq->private; 1073 1074 (*pos)++; 1075 return devlog_get_idx(dinfo, *pos); 1076 } 1077 1078 static void devlog_stop(struct seq_file *seq, void *v) 1079 { 1080 } 1081 1082 static const struct seq_operations devlog_seq_ops = { 1083 .start = devlog_start, 1084 .next = devlog_next, 1085 .stop = devlog_stop, 1086 .show = devlog_show 1087 }; 1088 1089 /* Set up for reading the firmware's device log. We read the entire log here 1090 * and then display it incrementally in devlog_show(). 1091 */ 1092 static int devlog_open(struct inode *inode, struct file *file) 1093 { 1094 struct adapter *adap = inode->i_private; 1095 struct devlog_params *dparams = &adap->params.devlog; 1096 struct devlog_info *dinfo; 1097 unsigned int index; 1098 u32 fseqno; 1099 int ret; 1100 1101 /* If we don't know where the log is we can't do anything. 1102 */ 1103 if (dparams->start == 0) 1104 return -ENXIO; 1105 1106 /* Allocate the space to read in the firmware's device log and set up 1107 * for the iterated call to our display function. 1108 */ 1109 dinfo = __seq_open_private(file, &devlog_seq_ops, 1110 sizeof(*dinfo) + dparams->size); 1111 if (!dinfo) 1112 return -ENOMEM; 1113 1114 /* Record the basic log buffer information and read in the raw log. 1115 */ 1116 dinfo->nentries = (dparams->size / sizeof(struct fw_devlog_e)); 1117 dinfo->first = 0; 1118 spin_lock(&adap->win0_lock); 1119 ret = t4_memory_rw(adap, adap->params.drv_memwin, dparams->memtype, 1120 dparams->start, dparams->size, (__be32 *)dinfo->log, 1121 T4_MEMORY_READ); 1122 spin_unlock(&adap->win0_lock); 1123 if (ret) { 1124 seq_release_private(inode, file); 1125 return ret; 1126 } 1127 1128 /* Find the earliest (lowest Sequence Number) log entry in the 1129 * circular Device Log. 1130 */ 1131 for (fseqno = ~((u32)0), index = 0; index < dinfo->nentries; index++) { 1132 struct fw_devlog_e *e = &dinfo->log[index]; 1133 __u32 seqno; 1134 1135 if (e->timestamp == 0) 1136 continue; 1137 1138 seqno = be32_to_cpu(e->seqno); 1139 if (seqno < fseqno) { 1140 fseqno = seqno; 1141 dinfo->first = index; 1142 } 1143 } 1144 return 0; 1145 } 1146 1147 static const struct file_operations devlog_fops = { 1148 .owner = THIS_MODULE, 1149 .open = devlog_open, 1150 .read = seq_read, 1151 .llseek = seq_lseek, 1152 .release = seq_release_private 1153 }; 1154 1155 /* Show Firmware Mailbox Command/Reply Log 1156 * 1157 * Note that we don't do any locking when dumping the Firmware Mailbox Log so 1158 * it's possible that we can catch things during a log update and therefore 1159 * see partially corrupted log entries. But it's probably Good Enough(tm). 1160 * If we ever decide that we want to make sure that we're dumping a coherent 1161 * log, we'd need to perform locking in the mailbox logging and in 1162 * mboxlog_open() where we'd need to grab the entire mailbox log in one go 1163 * like we do for the Firmware Device Log. 1164 */ 1165 static int mboxlog_show(struct seq_file *seq, void *v) 1166 { 1167 struct adapter *adapter = seq->private; 1168 struct mbox_cmd_log *log = adapter->mbox_log; 1169 struct mbox_cmd *entry; 1170 int entry_idx, i; 1171 1172 if (v == SEQ_START_TOKEN) { 1173 seq_printf(seq, 1174 "%10s %15s %5s %5s %s\n", 1175 "Seq#", "Tstamp", "Atime", "Etime", 1176 "Command/Reply"); 1177 return 0; 1178 } 1179 1180 entry_idx = log->cursor + ((uintptr_t)v - 2); 1181 if (entry_idx >= log->size) 1182 entry_idx -= log->size; 1183 entry = mbox_cmd_log_entry(log, entry_idx); 1184 1185 /* skip over unused entries */ 1186 if (entry->timestamp == 0) 1187 return 0; 1188 1189 seq_printf(seq, "%10u %15llu %5d %5d", 1190 entry->seqno, entry->timestamp, 1191 entry->access, entry->execute); 1192 for (i = 0; i < MBOX_LEN / 8; i++) { 1193 u64 flit = entry->cmd[i]; 1194 u32 hi = (u32)(flit >> 32); 1195 u32 lo = (u32)flit; 1196 1197 seq_printf(seq, " %08x %08x", hi, lo); 1198 } 1199 seq_puts(seq, "\n"); 1200 return 0; 1201 } 1202 1203 static inline void *mboxlog_get_idx(struct seq_file *seq, loff_t pos) 1204 { 1205 struct adapter *adapter = seq->private; 1206 struct mbox_cmd_log *log = adapter->mbox_log; 1207 1208 return ((pos <= log->size) ? (void *)(uintptr_t)(pos + 1) : NULL); 1209 } 1210 1211 static void *mboxlog_start(struct seq_file *seq, loff_t *pos) 1212 { 1213 return *pos ? mboxlog_get_idx(seq, *pos) : SEQ_START_TOKEN; 1214 } 1215 1216 static void *mboxlog_next(struct seq_file *seq, void *v, loff_t *pos) 1217 { 1218 ++*pos; 1219 return mboxlog_get_idx(seq, *pos); 1220 } 1221 1222 static void mboxlog_stop(struct seq_file *seq, void *v) 1223 { 1224 } 1225 1226 static const struct seq_operations mboxlog_seq_ops = { 1227 .start = mboxlog_start, 1228 .next = mboxlog_next, 1229 .stop = mboxlog_stop, 1230 .show = mboxlog_show 1231 }; 1232 1233 static int mboxlog_open(struct inode *inode, struct file *file) 1234 { 1235 int res = seq_open(file, &mboxlog_seq_ops); 1236 1237 if (!res) { 1238 struct seq_file *seq = file->private_data; 1239 1240 seq->private = inode->i_private; 1241 } 1242 return res; 1243 } 1244 1245 static const struct file_operations mboxlog_fops = { 1246 .owner = THIS_MODULE, 1247 .open = mboxlog_open, 1248 .read = seq_read, 1249 .llseek = seq_lseek, 1250 .release = seq_release, 1251 }; 1252 1253 static int mbox_show(struct seq_file *seq, void *v) 1254 { 1255 static const char * const owner[] = { "none", "FW", "driver", 1256 "unknown", "<unread>" }; 1257 1258 int i; 1259 unsigned int mbox = (uintptr_t)seq->private & 7; 1260 struct adapter *adap = seq->private - mbox; 1261 void __iomem *addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A); 1262 1263 /* For T4 we don't have a shadow copy of the Mailbox Control register. 1264 * And since reading that real register causes a side effect of 1265 * granting ownership, we're best of simply not reading it at all. 1266 */ 1267 if (is_t4(adap->params.chip)) { 1268 i = 4; /* index of "<unread>" */ 1269 } else { 1270 unsigned int ctrl_reg = CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A; 1271 void __iomem *ctrl = adap->regs + PF_REG(mbox, ctrl_reg); 1272 1273 i = MBOWNER_G(readl(ctrl)); 1274 } 1275 1276 seq_printf(seq, "mailbox owned by %s\n\n", owner[i]); 1277 1278 for (i = 0; i < MBOX_LEN; i += 8) 1279 seq_printf(seq, "%016llx\n", 1280 (unsigned long long)readq(addr + i)); 1281 return 0; 1282 } 1283 1284 static int mbox_open(struct inode *inode, struct file *file) 1285 { 1286 return single_open(file, mbox_show, inode->i_private); 1287 } 1288 1289 static ssize_t mbox_write(struct file *file, const char __user *buf, 1290 size_t count, loff_t *pos) 1291 { 1292 int i; 1293 char c = '\n', s[256]; 1294 unsigned long long data[8]; 1295 const struct inode *ino; 1296 unsigned int mbox; 1297 struct adapter *adap; 1298 void __iomem *addr; 1299 void __iomem *ctrl; 1300 1301 if (count > sizeof(s) - 1 || !count) 1302 return -EINVAL; 1303 if (copy_from_user(s, buf, count)) 1304 return -EFAULT; 1305 s[count] = '\0'; 1306 1307 if (sscanf(s, "%llx %llx %llx %llx %llx %llx %llx %llx%c", &data[0], 1308 &data[1], &data[2], &data[3], &data[4], &data[5], &data[6], 1309 &data[7], &c) < 8 || c != '\n') 1310 return -EINVAL; 1311 1312 ino = file_inode(file); 1313 mbox = (uintptr_t)ino->i_private & 7; 1314 adap = ino->i_private - mbox; 1315 addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A); 1316 ctrl = addr + MBOX_LEN; 1317 1318 if (MBOWNER_G(readl(ctrl)) != X_MBOWNER_PL) 1319 return -EBUSY; 1320 1321 for (i = 0; i < 8; i++) 1322 writeq(data[i], addr + 8 * i); 1323 1324 writel(MBMSGVALID_F | MBOWNER_V(X_MBOWNER_FW), ctrl); 1325 return count; 1326 } 1327 1328 static const struct file_operations mbox_debugfs_fops = { 1329 .owner = THIS_MODULE, 1330 .open = mbox_open, 1331 .read = seq_read, 1332 .llseek = seq_lseek, 1333 .release = single_release, 1334 .write = mbox_write 1335 }; 1336 1337 static int mps_trc_show(struct seq_file *seq, void *v) 1338 { 1339 int enabled, i; 1340 struct trace_params tp; 1341 unsigned int trcidx = (uintptr_t)seq->private & 3; 1342 struct adapter *adap = seq->private - trcidx; 1343 1344 t4_get_trace_filter(adap, &tp, trcidx, &enabled); 1345 if (!enabled) { 1346 seq_puts(seq, "tracer is disabled\n"); 1347 return 0; 1348 } 1349 1350 if (tp.skip_ofst * 8 >= TRACE_LEN) { 1351 dev_err(adap->pdev_dev, "illegal trace pattern skip offset\n"); 1352 return -EINVAL; 1353 } 1354 if (tp.port < 8) { 1355 i = adap->chan_map[tp.port & 3]; 1356 if (i >= MAX_NPORTS) { 1357 dev_err(adap->pdev_dev, "tracer %u is assigned " 1358 "to non-existing port\n", trcidx); 1359 return -EINVAL; 1360 } 1361 seq_printf(seq, "tracer is capturing %s %s, ", 1362 adap->port[i]->name, tp.port < 4 ? "Rx" : "Tx"); 1363 } else 1364 seq_printf(seq, "tracer is capturing loopback %d, ", 1365 tp.port - 8); 1366 seq_printf(seq, "snap length: %u, min length: %u\n", tp.snap_len, 1367 tp.min_len); 1368 seq_printf(seq, "packets captured %smatch filter\n", 1369 tp.invert ? "do not " : ""); 1370 1371 if (tp.skip_ofst) { 1372 seq_puts(seq, "filter pattern: "); 1373 for (i = 0; i < tp.skip_ofst * 2; i += 2) 1374 seq_printf(seq, "%08x%08x", tp.data[i], tp.data[i + 1]); 1375 seq_putc(seq, '/'); 1376 for (i = 0; i < tp.skip_ofst * 2; i += 2) 1377 seq_printf(seq, "%08x%08x", tp.mask[i], tp.mask[i + 1]); 1378 seq_puts(seq, "@0\n"); 1379 } 1380 1381 seq_puts(seq, "filter pattern: "); 1382 for (i = tp.skip_ofst * 2; i < TRACE_LEN / 4; i += 2) 1383 seq_printf(seq, "%08x%08x", tp.data[i], tp.data[i + 1]); 1384 seq_putc(seq, '/'); 1385 for (i = tp.skip_ofst * 2; i < TRACE_LEN / 4; i += 2) 1386 seq_printf(seq, "%08x%08x", tp.mask[i], tp.mask[i + 1]); 1387 seq_printf(seq, "@%u\n", (tp.skip_ofst + tp.skip_len) * 8); 1388 return 0; 1389 } 1390 1391 static int mps_trc_open(struct inode *inode, struct file *file) 1392 { 1393 return single_open(file, mps_trc_show, inode->i_private); 1394 } 1395 1396 static unsigned int xdigit2int(unsigned char c) 1397 { 1398 return isdigit(c) ? c - '0' : tolower(c) - 'a' + 10; 1399 } 1400 1401 #define TRC_PORT_NONE 0xff 1402 #define TRC_RSS_ENABLE 0x33 1403 #define TRC_RSS_DISABLE 0x13 1404 1405 /* Set an MPS trace filter. Syntax is: 1406 * 1407 * disable 1408 * 1409 * to disable tracing, or 1410 * 1411 * interface qid=<qid no> [snaplen=<val>] [minlen=<val>] [not] [<pattern>]... 1412 * 1413 * where interface is one of rxN, txN, or loopbackN, N = 0..3, qid can be one 1414 * of the NIC's response qid obtained from sge_qinfo and pattern has the form 1415 * 1416 * <pattern data>[/<pattern mask>][@<anchor>] 1417 * 1418 * Up to 2 filter patterns can be specified. If 2 are supplied the first one 1419 * must be anchored at 0. An omitted mask is taken as a mask of 1s, an omitted 1420 * anchor is taken as 0. 1421 */ 1422 static ssize_t mps_trc_write(struct file *file, const char __user *buf, 1423 size_t count, loff_t *pos) 1424 { 1425 int i, enable, ret; 1426 u32 *data, *mask; 1427 struct trace_params tp; 1428 const struct inode *ino; 1429 unsigned int trcidx; 1430 char *s, *p, *word, *end; 1431 struct adapter *adap; 1432 u32 j; 1433 1434 ino = file_inode(file); 1435 trcidx = (uintptr_t)ino->i_private & 3; 1436 adap = ino->i_private - trcidx; 1437 1438 /* Don't accept input more than 1K, can't be anything valid except lots 1439 * of whitespace. Well, use less. 1440 */ 1441 if (count > 1024) 1442 return -EFBIG; 1443 p = s = kzalloc(count + 1, GFP_USER); 1444 if (!s) 1445 return -ENOMEM; 1446 if (copy_from_user(s, buf, count)) { 1447 count = -EFAULT; 1448 goto out; 1449 } 1450 1451 if (s[count - 1] == '\n') 1452 s[count - 1] = '\0'; 1453 1454 enable = strcmp("disable", s) != 0; 1455 if (!enable) 1456 goto apply; 1457 1458 /* enable or disable trace multi rss filter */ 1459 if (adap->trace_rss) 1460 t4_write_reg(adap, MPS_TRC_CFG_A, TRC_RSS_ENABLE); 1461 else 1462 t4_write_reg(adap, MPS_TRC_CFG_A, TRC_RSS_DISABLE); 1463 1464 memset(&tp, 0, sizeof(tp)); 1465 tp.port = TRC_PORT_NONE; 1466 i = 0; /* counts pattern nibbles */ 1467 1468 while (p) { 1469 while (isspace(*p)) 1470 p++; 1471 word = strsep(&p, " "); 1472 if (!*word) 1473 break; 1474 1475 if (!strncmp(word, "qid=", 4)) { 1476 end = (char *)word + 4; 1477 ret = kstrtouint(end, 10, &j); 1478 if (ret) 1479 goto out; 1480 if (!adap->trace_rss) { 1481 t4_write_reg(adap, MPS_T5_TRC_RSS_CONTROL_A, j); 1482 continue; 1483 } 1484 1485 switch (trcidx) { 1486 case 0: 1487 t4_write_reg(adap, MPS_TRC_RSS_CONTROL_A, j); 1488 break; 1489 case 1: 1490 t4_write_reg(adap, 1491 MPS_TRC_FILTER1_RSS_CONTROL_A, j); 1492 break; 1493 case 2: 1494 t4_write_reg(adap, 1495 MPS_TRC_FILTER2_RSS_CONTROL_A, j); 1496 break; 1497 case 3: 1498 t4_write_reg(adap, 1499 MPS_TRC_FILTER3_RSS_CONTROL_A, j); 1500 break; 1501 } 1502 continue; 1503 } 1504 if (!strncmp(word, "snaplen=", 8)) { 1505 end = (char *)word + 8; 1506 ret = kstrtouint(end, 10, &j); 1507 if (ret || j > 9600) { 1508 inval: count = -EINVAL; 1509 goto out; 1510 } 1511 tp.snap_len = j; 1512 continue; 1513 } 1514 if (!strncmp(word, "minlen=", 7)) { 1515 end = (char *)word + 7; 1516 ret = kstrtouint(end, 10, &j); 1517 if (ret || j > TFMINPKTSIZE_M) 1518 goto inval; 1519 tp.min_len = j; 1520 continue; 1521 } 1522 if (!strcmp(word, "not")) { 1523 tp.invert = !tp.invert; 1524 continue; 1525 } 1526 if (!strncmp(word, "loopback", 8) && tp.port == TRC_PORT_NONE) { 1527 if (word[8] < '0' || word[8] > '3' || word[9]) 1528 goto inval; 1529 tp.port = word[8] - '0' + 8; 1530 continue; 1531 } 1532 if (!strncmp(word, "tx", 2) && tp.port == TRC_PORT_NONE) { 1533 if (word[2] < '0' || word[2] > '3' || word[3]) 1534 goto inval; 1535 tp.port = word[2] - '0' + 4; 1536 if (adap->chan_map[tp.port & 3] >= MAX_NPORTS) 1537 goto inval; 1538 continue; 1539 } 1540 if (!strncmp(word, "rx", 2) && tp.port == TRC_PORT_NONE) { 1541 if (word[2] < '0' || word[2] > '3' || word[3]) 1542 goto inval; 1543 tp.port = word[2] - '0'; 1544 if (adap->chan_map[tp.port] >= MAX_NPORTS) 1545 goto inval; 1546 continue; 1547 } 1548 if (!isxdigit(*word)) 1549 goto inval; 1550 1551 /* we have found a trace pattern */ 1552 if (i) { /* split pattern */ 1553 if (tp.skip_len) /* too many splits */ 1554 goto inval; 1555 tp.skip_ofst = i / 16; 1556 } 1557 1558 data = &tp.data[i / 8]; 1559 mask = &tp.mask[i / 8]; 1560 j = i; 1561 1562 while (isxdigit(*word)) { 1563 if (i >= TRACE_LEN * 2) { 1564 count = -EFBIG; 1565 goto out; 1566 } 1567 *data = (*data << 4) + xdigit2int(*word++); 1568 if (++i % 8 == 0) 1569 data++; 1570 } 1571 if (*word == '/') { 1572 word++; 1573 while (isxdigit(*word)) { 1574 if (j >= i) /* mask longer than data */ 1575 goto inval; 1576 *mask = (*mask << 4) + xdigit2int(*word++); 1577 if (++j % 8 == 0) 1578 mask++; 1579 } 1580 if (i != j) /* mask shorter than data */ 1581 goto inval; 1582 } else { /* no mask, use all 1s */ 1583 for ( ; i - j >= 8; j += 8) 1584 *mask++ = 0xffffffff; 1585 if (i % 8) 1586 *mask = (1 << (i % 8) * 4) - 1; 1587 } 1588 if (*word == '@') { 1589 end = (char *)word + 1; 1590 ret = kstrtouint(end, 10, &j); 1591 if (*end && *end != '\n') 1592 goto inval; 1593 if (j & 7) /* doesn't start at multiple of 8 */ 1594 goto inval; 1595 j /= 8; 1596 if (j < tp.skip_ofst) /* overlaps earlier pattern */ 1597 goto inval; 1598 if (j - tp.skip_ofst > 31) /* skip too big */ 1599 goto inval; 1600 tp.skip_len = j - tp.skip_ofst; 1601 } 1602 if (i % 8) { 1603 *data <<= (8 - i % 8) * 4; 1604 *mask <<= (8 - i % 8) * 4; 1605 i = (i + 15) & ~15; /* 8-byte align */ 1606 } 1607 } 1608 1609 if (tp.port == TRC_PORT_NONE) 1610 goto inval; 1611 1612 apply: 1613 i = t4_set_trace_filter(adap, &tp, trcidx, enable); 1614 if (i) 1615 count = i; 1616 out: 1617 kfree(s); 1618 return count; 1619 } 1620 1621 static const struct file_operations mps_trc_debugfs_fops = { 1622 .owner = THIS_MODULE, 1623 .open = mps_trc_open, 1624 .read = seq_read, 1625 .llseek = seq_lseek, 1626 .release = single_release, 1627 .write = mps_trc_write 1628 }; 1629 1630 static ssize_t flash_read(struct file *file, char __user *buf, size_t count, 1631 loff_t *ppos) 1632 { 1633 loff_t pos = *ppos; 1634 loff_t avail = file_inode(file)->i_size; 1635 struct adapter *adap = file->private_data; 1636 1637 if (pos < 0) 1638 return -EINVAL; 1639 if (pos >= avail) 1640 return 0; 1641 if (count > avail - pos) 1642 count = avail - pos; 1643 1644 while (count) { 1645 size_t len; 1646 int ret, ofst; 1647 u8 data[256]; 1648 1649 ofst = pos & 3; 1650 len = min(count + ofst, sizeof(data)); 1651 ret = t4_read_flash(adap, pos - ofst, (len + 3) / 4, 1652 (u32 *)data, 1); 1653 if (ret) 1654 return ret; 1655 1656 len -= ofst; 1657 if (copy_to_user(buf, data + ofst, len)) 1658 return -EFAULT; 1659 1660 buf += len; 1661 pos += len; 1662 count -= len; 1663 } 1664 count = pos - *ppos; 1665 *ppos = pos; 1666 return count; 1667 } 1668 1669 static const struct file_operations flash_debugfs_fops = { 1670 .owner = THIS_MODULE, 1671 .open = mem_open, 1672 .read = flash_read, 1673 .llseek = default_llseek, 1674 }; 1675 1676 static inline void tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask) 1677 { 1678 *mask = x | y; 1679 y = (__force u64)cpu_to_be64(y); 1680 memcpy(addr, (char *)&y + 2, ETH_ALEN); 1681 } 1682 1683 static int mps_tcam_show(struct seq_file *seq, void *v) 1684 { 1685 struct adapter *adap = seq->private; 1686 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip); 1687 if (v == SEQ_START_TOKEN) { 1688 if (chip_ver > CHELSIO_T5) { 1689 seq_puts(seq, "Idx Ethernet address Mask " 1690 " VNI Mask IVLAN Vld " 1691 "DIP_Hit Lookup Port " 1692 "Vld Ports PF VF " 1693 "Replication " 1694 " P0 P1 P2 P3 ML\n"); 1695 } else { 1696 if (adap->params.arch.mps_rplc_size > 128) 1697 seq_puts(seq, "Idx Ethernet address Mask " 1698 "Vld Ports PF VF " 1699 "Replication " 1700 " P0 P1 P2 P3 ML\n"); 1701 else 1702 seq_puts(seq, "Idx Ethernet address Mask " 1703 "Vld Ports PF VF Replication" 1704 " P0 P1 P2 P3 ML\n"); 1705 } 1706 } else { 1707 u64 mask; 1708 u8 addr[ETH_ALEN]; 1709 bool replicate, dip_hit = false, vlan_vld = false; 1710 unsigned int idx = (uintptr_t)v - 2; 1711 u64 tcamy, tcamx, val; 1712 u32 cls_lo, cls_hi, ctl, data2, vnix = 0, vniy = 0; 1713 u32 rplc[8] = {0}; 1714 u8 lookup_type = 0, port_num = 0; 1715 u16 ivlan = 0; 1716 1717 if (chip_ver > CHELSIO_T5) { 1718 /* CtlCmdType - 0: Read, 1: Write 1719 * CtlTcamSel - 0: TCAM0, 1: TCAM1 1720 * CtlXYBitSel- 0: Y bit, 1: X bit 1721 */ 1722 1723 /* Read tcamy */ 1724 ctl = CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0); 1725 if (idx < 256) 1726 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0); 1727 else 1728 ctl |= CTLTCAMINDEX_V(idx - 256) | 1729 CTLTCAMSEL_V(1); 1730 t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1731 val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A); 1732 tcamy = DMACH_G(val) << 32; 1733 tcamy |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A); 1734 data2 = t4_read_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A); 1735 lookup_type = DATALKPTYPE_G(data2); 1736 /* 0 - Outer header, 1 - Inner header 1737 * [71:48] bit locations are overloaded for 1738 * outer vs. inner lookup types. 1739 */ 1740 if (lookup_type && (lookup_type != DATALKPTYPE_M)) { 1741 /* Inner header VNI */ 1742 vniy = ((data2 & DATAVIDH2_F) << 23) | 1743 (DATAVIDH1_G(data2) << 16) | VIDL_G(val); 1744 dip_hit = data2 & DATADIPHIT_F; 1745 } else { 1746 vlan_vld = data2 & DATAVIDH2_F; 1747 ivlan = VIDL_G(val); 1748 } 1749 port_num = DATAPORTNUM_G(data2); 1750 1751 /* Read tcamx. Change the control param */ 1752 ctl |= CTLXYBITSEL_V(1); 1753 t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl); 1754 val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A); 1755 tcamx = DMACH_G(val) << 32; 1756 tcamx |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A); 1757 data2 = t4_read_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A); 1758 if (lookup_type && (lookup_type != DATALKPTYPE_M)) { 1759 /* Inner header VNI mask */ 1760 vnix = ((data2 & DATAVIDH2_F) << 23) | 1761 (DATAVIDH1_G(data2) << 16) | VIDL_G(val); 1762 } 1763 } else { 1764 tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx)); 1765 tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx)); 1766 } 1767 1768 cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx)); 1769 cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx)); 1770 1771 if (tcamx & tcamy) { 1772 seq_printf(seq, "%3u -\n", idx); 1773 goto out; 1774 } 1775 1776 rplc[0] = rplc[1] = rplc[2] = rplc[3] = 0; 1777 if (chip_ver > CHELSIO_T5) 1778 replicate = (cls_lo & T6_REPLICATE_F); 1779 else 1780 replicate = (cls_lo & REPLICATE_F); 1781 1782 if (replicate) { 1783 struct fw_ldst_cmd ldst_cmd; 1784 int ret; 1785 struct fw_ldst_mps_rplc mps_rplc; 1786 u32 ldst_addrspc; 1787 1788 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 1789 ldst_addrspc = 1790 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS); 1791 ldst_cmd.op_to_addrspace = 1792 htonl(FW_CMD_OP_V(FW_LDST_CMD) | 1793 FW_CMD_REQUEST_F | 1794 FW_CMD_READ_F | 1795 ldst_addrspc); 1796 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd)); 1797 ldst_cmd.u.mps.rplc.fid_idx = 1798 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) | 1799 FW_LDST_CMD_IDX_V(idx)); 1800 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, 1801 sizeof(ldst_cmd), &ldst_cmd); 1802 if (ret) 1803 dev_warn(adap->pdev_dev, "Can't read MPS " 1804 "replication map for idx %d: %d\n", 1805 idx, -ret); 1806 else { 1807 mps_rplc = ldst_cmd.u.mps.rplc; 1808 rplc[0] = ntohl(mps_rplc.rplc31_0); 1809 rplc[1] = ntohl(mps_rplc.rplc63_32); 1810 rplc[2] = ntohl(mps_rplc.rplc95_64); 1811 rplc[3] = ntohl(mps_rplc.rplc127_96); 1812 if (adap->params.arch.mps_rplc_size > 128) { 1813 rplc[4] = ntohl(mps_rplc.rplc159_128); 1814 rplc[5] = ntohl(mps_rplc.rplc191_160); 1815 rplc[6] = ntohl(mps_rplc.rplc223_192); 1816 rplc[7] = ntohl(mps_rplc.rplc255_224); 1817 } 1818 } 1819 } 1820 1821 tcamxy2valmask(tcamx, tcamy, addr, &mask); 1822 if (chip_ver > CHELSIO_T5) { 1823 /* Inner header lookup */ 1824 if (lookup_type && (lookup_type != DATALKPTYPE_M)) { 1825 seq_printf(seq, 1826 "%3u %02x:%02x:%02x:%02x:%02x:%02x " 1827 "%012llx %06x %06x - - %3c" 1828 " 'I' %4x " 1829 "%3c %#x%4u%4d", idx, addr[0], 1830 addr[1], addr[2], addr[3], 1831 addr[4], addr[5], 1832 (unsigned long long)mask, 1833 vniy, vnix, dip_hit ? 'Y' : 'N', 1834 port_num, 1835 (cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N', 1836 PORTMAP_G(cls_hi), 1837 T6_PF_G(cls_lo), 1838 (cls_lo & T6_VF_VALID_F) ? 1839 T6_VF_G(cls_lo) : -1); 1840 } else { 1841 seq_printf(seq, 1842 "%3u %02x:%02x:%02x:%02x:%02x:%02x " 1843 "%012llx - - ", 1844 idx, addr[0], addr[1], addr[2], 1845 addr[3], addr[4], addr[5], 1846 (unsigned long long)mask); 1847 1848 if (vlan_vld) 1849 seq_printf(seq, "%4u Y ", ivlan); 1850 else 1851 seq_puts(seq, " - N "); 1852 1853 seq_printf(seq, 1854 "- %3c %4x %3c %#x%4u%4d", 1855 lookup_type ? 'I' : 'O', port_num, 1856 (cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N', 1857 PORTMAP_G(cls_hi), 1858 T6_PF_G(cls_lo), 1859 (cls_lo & T6_VF_VALID_F) ? 1860 T6_VF_G(cls_lo) : -1); 1861 } 1862 } else 1863 seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x " 1864 "%012llx%3c %#x%4u%4d", 1865 idx, addr[0], addr[1], addr[2], addr[3], 1866 addr[4], addr[5], (unsigned long long)mask, 1867 (cls_lo & SRAM_VLD_F) ? 'Y' : 'N', 1868 PORTMAP_G(cls_hi), 1869 PF_G(cls_lo), 1870 (cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1); 1871 1872 if (replicate) { 1873 if (adap->params.arch.mps_rplc_size > 128) 1874 seq_printf(seq, " %08x %08x %08x %08x " 1875 "%08x %08x %08x %08x", 1876 rplc[7], rplc[6], rplc[5], rplc[4], 1877 rplc[3], rplc[2], rplc[1], rplc[0]); 1878 else 1879 seq_printf(seq, " %08x %08x %08x %08x", 1880 rplc[3], rplc[2], rplc[1], rplc[0]); 1881 } else { 1882 if (adap->params.arch.mps_rplc_size > 128) 1883 seq_printf(seq, "%72c", ' '); 1884 else 1885 seq_printf(seq, "%36c", ' '); 1886 } 1887 1888 if (chip_ver > CHELSIO_T5) 1889 seq_printf(seq, "%4u%3u%3u%3u %#x\n", 1890 T6_SRAM_PRIO0_G(cls_lo), 1891 T6_SRAM_PRIO1_G(cls_lo), 1892 T6_SRAM_PRIO2_G(cls_lo), 1893 T6_SRAM_PRIO3_G(cls_lo), 1894 (cls_lo >> T6_MULTILISTEN0_S) & 0xf); 1895 else 1896 seq_printf(seq, "%4u%3u%3u%3u %#x\n", 1897 SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo), 1898 SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo), 1899 (cls_lo >> MULTILISTEN0_S) & 0xf); 1900 } 1901 out: return 0; 1902 } 1903 1904 static inline void *mps_tcam_get_idx(struct seq_file *seq, loff_t pos) 1905 { 1906 struct adapter *adap = seq->private; 1907 int max_mac_addr = is_t4(adap->params.chip) ? 1908 NUM_MPS_CLS_SRAM_L_INSTANCES : 1909 NUM_MPS_T5_CLS_SRAM_L_INSTANCES; 1910 return ((pos <= max_mac_addr) ? (void *)(uintptr_t)(pos + 1) : NULL); 1911 } 1912 1913 static void *mps_tcam_start(struct seq_file *seq, loff_t *pos) 1914 { 1915 return *pos ? mps_tcam_get_idx(seq, *pos) : SEQ_START_TOKEN; 1916 } 1917 1918 static void *mps_tcam_next(struct seq_file *seq, void *v, loff_t *pos) 1919 { 1920 ++*pos; 1921 return mps_tcam_get_idx(seq, *pos); 1922 } 1923 1924 static void mps_tcam_stop(struct seq_file *seq, void *v) 1925 { 1926 } 1927 1928 static const struct seq_operations mps_tcam_seq_ops = { 1929 .start = mps_tcam_start, 1930 .next = mps_tcam_next, 1931 .stop = mps_tcam_stop, 1932 .show = mps_tcam_show 1933 }; 1934 1935 static int mps_tcam_open(struct inode *inode, struct file *file) 1936 { 1937 int res = seq_open(file, &mps_tcam_seq_ops); 1938 1939 if (!res) { 1940 struct seq_file *seq = file->private_data; 1941 1942 seq->private = inode->i_private; 1943 } 1944 return res; 1945 } 1946 1947 static const struct file_operations mps_tcam_debugfs_fops = { 1948 .owner = THIS_MODULE, 1949 .open = mps_tcam_open, 1950 .read = seq_read, 1951 .llseek = seq_lseek, 1952 .release = seq_release, 1953 }; 1954 1955 /* Display various sensor information. 1956 */ 1957 static int sensors_show(struct seq_file *seq, void *v) 1958 { 1959 struct adapter *adap = seq->private; 1960 u32 param[7], val[7]; 1961 int ret; 1962 1963 /* Note that if the sensors haven't been initialized and turned on 1964 * we'll get values of 0, so treat those as "<unknown>" ... 1965 */ 1966 param[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 1967 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DIAG) | 1968 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_DIAG_TMP)); 1969 param[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 1970 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DIAG) | 1971 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_DIAG_VDD)); 1972 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 1973 param, val); 1974 1975 if (ret < 0 || val[0] == 0) 1976 seq_puts(seq, "Temperature: <unknown>\n"); 1977 else 1978 seq_printf(seq, "Temperature: %dC\n", val[0]); 1979 1980 if (ret < 0 || val[1] == 0) 1981 seq_puts(seq, "Core VDD: <unknown>\n"); 1982 else 1983 seq_printf(seq, "Core VDD: %dmV\n", val[1]); 1984 1985 return 0; 1986 } 1987 1988 DEFINE_SIMPLE_DEBUGFS_FILE(sensors); 1989 1990 #if IS_ENABLED(CONFIG_IPV6) 1991 static int clip_tbl_open(struct inode *inode, struct file *file) 1992 { 1993 return single_open(file, clip_tbl_show, inode->i_private); 1994 } 1995 1996 static const struct file_operations clip_tbl_debugfs_fops = { 1997 .owner = THIS_MODULE, 1998 .open = clip_tbl_open, 1999 .read = seq_read, 2000 .llseek = seq_lseek, 2001 .release = single_release 2002 }; 2003 #endif 2004 2005 /*RSS Table. 2006 */ 2007 2008 static int rss_show(struct seq_file *seq, void *v, int idx) 2009 { 2010 u16 *entry = v; 2011 2012 seq_printf(seq, "%4d: %4u %4u %4u %4u %4u %4u %4u %4u\n", 2013 idx * 8, entry[0], entry[1], entry[2], entry[3], entry[4], 2014 entry[5], entry[6], entry[7]); 2015 return 0; 2016 } 2017 2018 static int rss_open(struct inode *inode, struct file *file) 2019 { 2020 int ret; 2021 struct seq_tab *p; 2022 struct adapter *adap = inode->i_private; 2023 2024 p = seq_open_tab(file, RSS_NENTRIES / 8, 8 * sizeof(u16), 0, rss_show); 2025 if (!p) 2026 return -ENOMEM; 2027 2028 ret = t4_read_rss(adap, (u16 *)p->data); 2029 if (ret) 2030 seq_release_private(inode, file); 2031 2032 return ret; 2033 } 2034 2035 static const struct file_operations rss_debugfs_fops = { 2036 .owner = THIS_MODULE, 2037 .open = rss_open, 2038 .read = seq_read, 2039 .llseek = seq_lseek, 2040 .release = seq_release_private 2041 }; 2042 2043 /* RSS Configuration. 2044 */ 2045 2046 /* Small utility function to return the strings "yes" or "no" if the supplied 2047 * argument is non-zero. 2048 */ 2049 static const char *yesno(int x) 2050 { 2051 static const char *yes = "yes"; 2052 static const char *no = "no"; 2053 2054 return x ? yes : no; 2055 } 2056 2057 static int rss_config_show(struct seq_file *seq, void *v) 2058 { 2059 struct adapter *adapter = seq->private; 2060 static const char * const keymode[] = { 2061 "global", 2062 "global and per-VF scramble", 2063 "per-PF and per-VF scramble", 2064 "per-VF and per-VF scramble", 2065 }; 2066 u32 rssconf; 2067 2068 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_A); 2069 seq_printf(seq, "TP_RSS_CONFIG: %#x\n", rssconf); 2070 seq_printf(seq, " Tnl4TupEnIpv6: %3s\n", yesno(rssconf & 2071 TNL4TUPENIPV6_F)); 2072 seq_printf(seq, " Tnl2TupEnIpv6: %3s\n", yesno(rssconf & 2073 TNL2TUPENIPV6_F)); 2074 seq_printf(seq, " Tnl4TupEnIpv4: %3s\n", yesno(rssconf & 2075 TNL4TUPENIPV4_F)); 2076 seq_printf(seq, " Tnl2TupEnIpv4: %3s\n", yesno(rssconf & 2077 TNL2TUPENIPV4_F)); 2078 seq_printf(seq, " TnlTcpSel: %3s\n", yesno(rssconf & TNLTCPSEL_F)); 2079 seq_printf(seq, " TnlIp6Sel: %3s\n", yesno(rssconf & TNLIP6SEL_F)); 2080 seq_printf(seq, " TnlVrtSel: %3s\n", yesno(rssconf & TNLVRTSEL_F)); 2081 seq_printf(seq, " TnlMapEn: %3s\n", yesno(rssconf & TNLMAPEN_F)); 2082 seq_printf(seq, " OfdHashSave: %3s\n", yesno(rssconf & 2083 OFDHASHSAVE_F)); 2084 seq_printf(seq, " OfdVrtSel: %3s\n", yesno(rssconf & OFDVRTSEL_F)); 2085 seq_printf(seq, " OfdMapEn: %3s\n", yesno(rssconf & OFDMAPEN_F)); 2086 seq_printf(seq, " OfdLkpEn: %3s\n", yesno(rssconf & OFDLKPEN_F)); 2087 seq_printf(seq, " Syn4TupEnIpv6: %3s\n", yesno(rssconf & 2088 SYN4TUPENIPV6_F)); 2089 seq_printf(seq, " Syn2TupEnIpv6: %3s\n", yesno(rssconf & 2090 SYN2TUPENIPV6_F)); 2091 seq_printf(seq, " Syn4TupEnIpv4: %3s\n", yesno(rssconf & 2092 SYN4TUPENIPV4_F)); 2093 seq_printf(seq, " Syn2TupEnIpv4: %3s\n", yesno(rssconf & 2094 SYN2TUPENIPV4_F)); 2095 seq_printf(seq, " Syn4TupEnIpv6: %3s\n", yesno(rssconf & 2096 SYN4TUPENIPV6_F)); 2097 seq_printf(seq, " SynIp6Sel: %3s\n", yesno(rssconf & SYNIP6SEL_F)); 2098 seq_printf(seq, " SynVrt6Sel: %3s\n", yesno(rssconf & SYNVRTSEL_F)); 2099 seq_printf(seq, " SynMapEn: %3s\n", yesno(rssconf & SYNMAPEN_F)); 2100 seq_printf(seq, " SynLkpEn: %3s\n", yesno(rssconf & SYNLKPEN_F)); 2101 seq_printf(seq, " ChnEn: %3s\n", yesno(rssconf & 2102 CHANNELENABLE_F)); 2103 seq_printf(seq, " PrtEn: %3s\n", yesno(rssconf & 2104 PORTENABLE_F)); 2105 seq_printf(seq, " TnlAllLkp: %3s\n", yesno(rssconf & 2106 TNLALLLOOKUP_F)); 2107 seq_printf(seq, " VrtEn: %3s\n", yesno(rssconf & 2108 VIRTENABLE_F)); 2109 seq_printf(seq, " CngEn: %3s\n", yesno(rssconf & 2110 CONGESTIONENABLE_F)); 2111 seq_printf(seq, " HashToeplitz: %3s\n", yesno(rssconf & 2112 HASHTOEPLITZ_F)); 2113 seq_printf(seq, " Udp4En: %3s\n", yesno(rssconf & UDPENABLE_F)); 2114 seq_printf(seq, " Disable: %3s\n", yesno(rssconf & DISABLE_F)); 2115 2116 seq_puts(seq, "\n"); 2117 2118 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_TNL_A); 2119 seq_printf(seq, "TP_RSS_CONFIG_TNL: %#x\n", rssconf); 2120 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf)); 2121 seq_printf(seq, " MaskFilter: %3d\n", MASKFILTER_G(rssconf)); 2122 if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) { 2123 seq_printf(seq, " HashAll: %3s\n", 2124 yesno(rssconf & HASHALL_F)); 2125 seq_printf(seq, " HashEth: %3s\n", 2126 yesno(rssconf & HASHETH_F)); 2127 } 2128 seq_printf(seq, " UseWireCh: %3s\n", yesno(rssconf & USEWIRECH_F)); 2129 2130 seq_puts(seq, "\n"); 2131 2132 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_OFD_A); 2133 seq_printf(seq, "TP_RSS_CONFIG_OFD: %#x\n", rssconf); 2134 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf)); 2135 seq_printf(seq, " RRCplMapEn: %3s\n", yesno(rssconf & 2136 RRCPLMAPEN_F)); 2137 seq_printf(seq, " RRCplQueWidth: %3d\n", RRCPLQUEWIDTH_G(rssconf)); 2138 2139 seq_puts(seq, "\n"); 2140 2141 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_SYN_A); 2142 seq_printf(seq, "TP_RSS_CONFIG_SYN: %#x\n", rssconf); 2143 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf)); 2144 seq_printf(seq, " UseWireCh: %3s\n", yesno(rssconf & USEWIRECH_F)); 2145 2146 seq_puts(seq, "\n"); 2147 2148 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A); 2149 seq_printf(seq, "TP_RSS_CONFIG_VRT: %#x\n", rssconf); 2150 if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) { 2151 seq_printf(seq, " KeyWrAddrX: %3d\n", 2152 KEYWRADDRX_G(rssconf)); 2153 seq_printf(seq, " KeyExtend: %3s\n", 2154 yesno(rssconf & KEYEXTEND_F)); 2155 } 2156 seq_printf(seq, " VfRdRg: %3s\n", yesno(rssconf & VFRDRG_F)); 2157 seq_printf(seq, " VfRdEn: %3s\n", yesno(rssconf & VFRDEN_F)); 2158 seq_printf(seq, " VfPerrEn: %3s\n", yesno(rssconf & VFPERREN_F)); 2159 seq_printf(seq, " KeyPerrEn: %3s\n", yesno(rssconf & KEYPERREN_F)); 2160 seq_printf(seq, " DisVfVlan: %3s\n", yesno(rssconf & 2161 DISABLEVLAN_F)); 2162 seq_printf(seq, " EnUpSwt: %3s\n", yesno(rssconf & ENABLEUP0_F)); 2163 seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf)); 2164 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) 2165 seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf)); 2166 else 2167 seq_printf(seq, " VfWrAddr: %3d\n", 2168 T6_VFWRADDR_G(rssconf)); 2169 seq_printf(seq, " KeyMode: %s\n", keymode[KEYMODE_G(rssconf)]); 2170 seq_printf(seq, " VfWrEn: %3s\n", yesno(rssconf & VFWREN_F)); 2171 seq_printf(seq, " KeyWrEn: %3s\n", yesno(rssconf & KEYWREN_F)); 2172 seq_printf(seq, " KeyWrAddr: %3d\n", KEYWRADDR_G(rssconf)); 2173 2174 seq_puts(seq, "\n"); 2175 2176 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_CNG_A); 2177 seq_printf(seq, "TP_RSS_CONFIG_CNG: %#x\n", rssconf); 2178 seq_printf(seq, " ChnCount3: %3s\n", yesno(rssconf & CHNCOUNT3_F)); 2179 seq_printf(seq, " ChnCount2: %3s\n", yesno(rssconf & CHNCOUNT2_F)); 2180 seq_printf(seq, " ChnCount1: %3s\n", yesno(rssconf & CHNCOUNT1_F)); 2181 seq_printf(seq, " ChnCount0: %3s\n", yesno(rssconf & CHNCOUNT0_F)); 2182 seq_printf(seq, " ChnUndFlow3: %3s\n", yesno(rssconf & 2183 CHNUNDFLOW3_F)); 2184 seq_printf(seq, " ChnUndFlow2: %3s\n", yesno(rssconf & 2185 CHNUNDFLOW2_F)); 2186 seq_printf(seq, " ChnUndFlow1: %3s\n", yesno(rssconf & 2187 CHNUNDFLOW1_F)); 2188 seq_printf(seq, " ChnUndFlow0: %3s\n", yesno(rssconf & 2189 CHNUNDFLOW0_F)); 2190 seq_printf(seq, " RstChn3: %3s\n", yesno(rssconf & RSTCHN3_F)); 2191 seq_printf(seq, " RstChn2: %3s\n", yesno(rssconf & RSTCHN2_F)); 2192 seq_printf(seq, " RstChn1: %3s\n", yesno(rssconf & RSTCHN1_F)); 2193 seq_printf(seq, " RstChn0: %3s\n", yesno(rssconf & RSTCHN0_F)); 2194 seq_printf(seq, " UpdVld: %3s\n", yesno(rssconf & UPDVLD_F)); 2195 seq_printf(seq, " Xoff: %3s\n", yesno(rssconf & XOFF_F)); 2196 seq_printf(seq, " UpdChn3: %3s\n", yesno(rssconf & UPDCHN3_F)); 2197 seq_printf(seq, " UpdChn2: %3s\n", yesno(rssconf & UPDCHN2_F)); 2198 seq_printf(seq, " UpdChn1: %3s\n", yesno(rssconf & UPDCHN1_F)); 2199 seq_printf(seq, " UpdChn0: %3s\n", yesno(rssconf & UPDCHN0_F)); 2200 seq_printf(seq, " Queue: %3d\n", QUEUE_G(rssconf)); 2201 2202 return 0; 2203 } 2204 2205 DEFINE_SIMPLE_DEBUGFS_FILE(rss_config); 2206 2207 /* RSS Secret Key. 2208 */ 2209 2210 static int rss_key_show(struct seq_file *seq, void *v) 2211 { 2212 u32 key[10]; 2213 2214 t4_read_rss_key(seq->private, key, true); 2215 seq_printf(seq, "%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x\n", 2216 key[9], key[8], key[7], key[6], key[5], key[4], key[3], 2217 key[2], key[1], key[0]); 2218 return 0; 2219 } 2220 2221 static int rss_key_open(struct inode *inode, struct file *file) 2222 { 2223 return single_open(file, rss_key_show, inode->i_private); 2224 } 2225 2226 static ssize_t rss_key_write(struct file *file, const char __user *buf, 2227 size_t count, loff_t *pos) 2228 { 2229 int i, j; 2230 u32 key[10]; 2231 char s[100], *p; 2232 struct adapter *adap = file_inode(file)->i_private; 2233 2234 if (count > sizeof(s) - 1) 2235 return -EINVAL; 2236 if (copy_from_user(s, buf, count)) 2237 return -EFAULT; 2238 for (i = count; i > 0 && isspace(s[i - 1]); i--) 2239 ; 2240 s[i] = '\0'; 2241 2242 for (p = s, i = 9; i >= 0; i--) { 2243 key[i] = 0; 2244 for (j = 0; j < 8; j++, p++) { 2245 if (!isxdigit(*p)) 2246 return -EINVAL; 2247 key[i] = (key[i] << 4) | hex2val(*p); 2248 } 2249 } 2250 2251 t4_write_rss_key(adap, key, -1, true); 2252 return count; 2253 } 2254 2255 static const struct file_operations rss_key_debugfs_fops = { 2256 .owner = THIS_MODULE, 2257 .open = rss_key_open, 2258 .read = seq_read, 2259 .llseek = seq_lseek, 2260 .release = single_release, 2261 .write = rss_key_write 2262 }; 2263 2264 /* PF RSS Configuration. 2265 */ 2266 2267 struct rss_pf_conf { 2268 u32 rss_pf_map; 2269 u32 rss_pf_mask; 2270 u32 rss_pf_config; 2271 }; 2272 2273 static int rss_pf_config_show(struct seq_file *seq, void *v, int idx) 2274 { 2275 struct rss_pf_conf *pfconf; 2276 2277 if (v == SEQ_START_TOKEN) { 2278 /* use the 0th entry to dump the PF Map Index Size */ 2279 pfconf = seq->private + offsetof(struct seq_tab, data); 2280 seq_printf(seq, "PF Map Index Size = %d\n\n", 2281 LKPIDXSIZE_G(pfconf->rss_pf_map)); 2282 2283 seq_puts(seq, " RSS PF VF Hash Tuple Enable Default\n"); 2284 seq_puts(seq, " Enable IPF Mask Mask IPv6 IPv4 UDP Queue\n"); 2285 seq_puts(seq, " PF Map Chn Prt Map Size Size Four Two Four Two Four Ch1 Ch0\n"); 2286 } else { 2287 #define G_PFnLKPIDX(map, n) \ 2288 (((map) >> PF1LKPIDX_S*(n)) & PF0LKPIDX_M) 2289 #define G_PFnMSKSIZE(mask, n) \ 2290 (((mask) >> PF1MSKSIZE_S*(n)) & PF1MSKSIZE_M) 2291 2292 pfconf = v; 2293 seq_printf(seq, "%3d %3s %3s %3s %3d %3d %3d %3s %3s %3s %3s %3s %3d %3d\n", 2294 idx, 2295 yesno(pfconf->rss_pf_config & MAPENABLE_F), 2296 yesno(pfconf->rss_pf_config & CHNENABLE_F), 2297 yesno(pfconf->rss_pf_config & PRTENABLE_F), 2298 G_PFnLKPIDX(pfconf->rss_pf_map, idx), 2299 G_PFnMSKSIZE(pfconf->rss_pf_mask, idx), 2300 IVFWIDTH_G(pfconf->rss_pf_config), 2301 yesno(pfconf->rss_pf_config & IP6FOURTUPEN_F), 2302 yesno(pfconf->rss_pf_config & IP6TWOTUPEN_F), 2303 yesno(pfconf->rss_pf_config & IP4FOURTUPEN_F), 2304 yesno(pfconf->rss_pf_config & IP4TWOTUPEN_F), 2305 yesno(pfconf->rss_pf_config & UDPFOURTUPEN_F), 2306 CH1DEFAULTQUEUE_G(pfconf->rss_pf_config), 2307 CH0DEFAULTQUEUE_G(pfconf->rss_pf_config)); 2308 2309 #undef G_PFnLKPIDX 2310 #undef G_PFnMSKSIZE 2311 } 2312 return 0; 2313 } 2314 2315 static int rss_pf_config_open(struct inode *inode, struct file *file) 2316 { 2317 struct adapter *adapter = inode->i_private; 2318 struct seq_tab *p; 2319 u32 rss_pf_map, rss_pf_mask; 2320 struct rss_pf_conf *pfconf; 2321 int pf; 2322 2323 p = seq_open_tab(file, 8, sizeof(*pfconf), 1, rss_pf_config_show); 2324 if (!p) 2325 return -ENOMEM; 2326 2327 pfconf = (struct rss_pf_conf *)p->data; 2328 rss_pf_map = t4_read_rss_pf_map(adapter, true); 2329 rss_pf_mask = t4_read_rss_pf_mask(adapter, true); 2330 for (pf = 0; pf < 8; pf++) { 2331 pfconf[pf].rss_pf_map = rss_pf_map; 2332 pfconf[pf].rss_pf_mask = rss_pf_mask; 2333 t4_read_rss_pf_config(adapter, pf, &pfconf[pf].rss_pf_config, 2334 true); 2335 } 2336 return 0; 2337 } 2338 2339 static const struct file_operations rss_pf_config_debugfs_fops = { 2340 .owner = THIS_MODULE, 2341 .open = rss_pf_config_open, 2342 .read = seq_read, 2343 .llseek = seq_lseek, 2344 .release = seq_release_private 2345 }; 2346 2347 /* VF RSS Configuration. 2348 */ 2349 2350 struct rss_vf_conf { 2351 u32 rss_vf_vfl; 2352 u32 rss_vf_vfh; 2353 }; 2354 2355 static int rss_vf_config_show(struct seq_file *seq, void *v, int idx) 2356 { 2357 if (v == SEQ_START_TOKEN) { 2358 seq_puts(seq, " RSS Hash Tuple Enable\n"); 2359 seq_puts(seq, " Enable IVF Dis Enb IPv6 IPv4 UDP Def Secret Key\n"); 2360 seq_puts(seq, " VF Chn Prt Map VLAN uP Four Two Four Two Four Que Idx Hash\n"); 2361 } else { 2362 struct rss_vf_conf *vfconf = v; 2363 2364 seq_printf(seq, "%3d %3s %3s %3d %3s %3s %3s %3s %3s %3s %3s %4d %3d %#10x\n", 2365 idx, 2366 yesno(vfconf->rss_vf_vfh & VFCHNEN_F), 2367 yesno(vfconf->rss_vf_vfh & VFPRTEN_F), 2368 VFLKPIDX_G(vfconf->rss_vf_vfh), 2369 yesno(vfconf->rss_vf_vfh & VFVLNEX_F), 2370 yesno(vfconf->rss_vf_vfh & VFUPEN_F), 2371 yesno(vfconf->rss_vf_vfh & VFIP4FOURTUPEN_F), 2372 yesno(vfconf->rss_vf_vfh & VFIP6TWOTUPEN_F), 2373 yesno(vfconf->rss_vf_vfh & VFIP4FOURTUPEN_F), 2374 yesno(vfconf->rss_vf_vfh & VFIP4TWOTUPEN_F), 2375 yesno(vfconf->rss_vf_vfh & ENABLEUDPHASH_F), 2376 DEFAULTQUEUE_G(vfconf->rss_vf_vfh), 2377 KEYINDEX_G(vfconf->rss_vf_vfh), 2378 vfconf->rss_vf_vfl); 2379 } 2380 return 0; 2381 } 2382 2383 static int rss_vf_config_open(struct inode *inode, struct file *file) 2384 { 2385 struct adapter *adapter = inode->i_private; 2386 struct seq_tab *p; 2387 struct rss_vf_conf *vfconf; 2388 int vf, vfcount = adapter->params.arch.vfcount; 2389 2390 p = seq_open_tab(file, vfcount, sizeof(*vfconf), 1, rss_vf_config_show); 2391 if (!p) 2392 return -ENOMEM; 2393 2394 vfconf = (struct rss_vf_conf *)p->data; 2395 for (vf = 0; vf < vfcount; vf++) { 2396 t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl, 2397 &vfconf[vf].rss_vf_vfh, true); 2398 } 2399 return 0; 2400 } 2401 2402 static const struct file_operations rss_vf_config_debugfs_fops = { 2403 .owner = THIS_MODULE, 2404 .open = rss_vf_config_open, 2405 .read = seq_read, 2406 .llseek = seq_lseek, 2407 .release = seq_release_private 2408 }; 2409 2410 /** 2411 * ethqset2pinfo - return port_info of an Ethernet Queue Set 2412 * @adap: the adapter 2413 * @qset: Ethernet Queue Set 2414 */ 2415 static inline struct port_info *ethqset2pinfo(struct adapter *adap, int qset) 2416 { 2417 int pidx; 2418 2419 for_each_port(adap, pidx) { 2420 struct port_info *pi = adap2pinfo(adap, pidx); 2421 2422 if (qset >= pi->first_qset && 2423 qset < pi->first_qset + pi->nqsets) 2424 return pi; 2425 } 2426 2427 /* should never happen! */ 2428 BUG_ON(1); 2429 return NULL; 2430 } 2431 2432 static int sge_qinfo_show(struct seq_file *seq, void *v) 2433 { 2434 struct adapter *adap = seq->private; 2435 int eth_entries = DIV_ROUND_UP(adap->sge.ethqsets, 4); 2436 int ofld_entries = DIV_ROUND_UP(adap->sge.ofldqsets, 4); 2437 int ctrl_entries = DIV_ROUND_UP(MAX_CTRL_QUEUES, 4); 2438 int i, r = (uintptr_t)v - 1; 2439 int ofld_idx = r - eth_entries; 2440 int ctrl_idx = ofld_idx - ofld_entries; 2441 int fq_idx = ctrl_idx - ctrl_entries; 2442 2443 if (r) 2444 seq_putc(seq, '\n'); 2445 2446 #define S3(fmt_spec, s, v) \ 2447 do { \ 2448 seq_printf(seq, "%-12s", s); \ 2449 for (i = 0; i < n; ++i) \ 2450 seq_printf(seq, " %16" fmt_spec, v); \ 2451 seq_putc(seq, '\n'); \ 2452 } while (0) 2453 #define S(s, v) S3("s", s, v) 2454 #define T3(fmt_spec, s, v) S3(fmt_spec, s, tx[i].v) 2455 #define T(s, v) S3("u", s, tx[i].v) 2456 #define TL(s, v) T3("lu", s, v) 2457 #define R3(fmt_spec, s, v) S3(fmt_spec, s, rx[i].v) 2458 #define R(s, v) S3("u", s, rx[i].v) 2459 #define RL(s, v) R3("lu", s, v) 2460 2461 if (r < eth_entries) { 2462 int base_qset = r * 4; 2463 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[base_qset]; 2464 const struct sge_eth_txq *tx = &adap->sge.ethtxq[base_qset]; 2465 int n = min(4, adap->sge.ethqsets - 4 * r); 2466 2467 S("QType:", "Ethernet"); 2468 S("Interface:", 2469 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A"); 2470 T("TxQ ID:", q.cntxt_id); 2471 T("TxQ size:", q.size); 2472 T("TxQ inuse:", q.in_use); 2473 T("TxQ CIDX:", q.cidx); 2474 T("TxQ PIDX:", q.pidx); 2475 #ifdef CONFIG_CHELSIO_T4_DCB 2476 T("DCB Prio:", dcb_prio); 2477 S3("u", "DCB PGID:", 2478 (ethqset2pinfo(adap, base_qset + i)->dcb.pgid >> 2479 4*(7-tx[i].dcb_prio)) & 0xf); 2480 S3("u", "DCB PFC:", 2481 (ethqset2pinfo(adap, base_qset + i)->dcb.pfcen >> 2482 1*(7-tx[i].dcb_prio)) & 0x1); 2483 #endif 2484 R("RspQ ID:", rspq.abs_id); 2485 R("RspQ size:", rspq.size); 2486 R("RspQE size:", rspq.iqe_len); 2487 R("RspQ CIDX:", rspq.cidx); 2488 R("RspQ Gen:", rspq.gen); 2489 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq)); 2490 S3("u", "Intr pktcnt:", 2491 adap->sge.counter_val[rx[i].rspq.pktcnt_idx]); 2492 R("FL ID:", fl.cntxt_id); 2493 R("FL size:", fl.size - 8); 2494 R("FL pend:", fl.pend_cred); 2495 R("FL avail:", fl.avail); 2496 R("FL PIDX:", fl.pidx); 2497 R("FL CIDX:", fl.cidx); 2498 RL("RxPackets:", stats.pkts); 2499 RL("RxCSO:", stats.rx_cso); 2500 RL("VLANxtract:", stats.vlan_ex); 2501 RL("LROmerged:", stats.lro_merged); 2502 RL("LROpackets:", stats.lro_pkts); 2503 RL("RxDrops:", stats.rx_drops); 2504 TL("TSO:", tso); 2505 TL("TxCSO:", tx_cso); 2506 TL("VLANins:", vlan_ins); 2507 TL("TxQFull:", q.stops); 2508 TL("TxQRestarts:", q.restarts); 2509 TL("TxMapErr:", mapping_err); 2510 RL("FLAllocErr:", fl.alloc_failed); 2511 RL("FLLrgAlcErr:", fl.large_alloc_failed); 2512 RL("FLMapErr:", fl.mapping_err); 2513 RL("FLLow:", fl.low); 2514 RL("FLStarving:", fl.starving); 2515 2516 } else if (ctrl_idx < ctrl_entries) { 2517 const struct sge_ctrl_txq *tx = &adap->sge.ctrlq[ctrl_idx * 4]; 2518 int n = min(4, adap->params.nports - 4 * ctrl_idx); 2519 2520 S("QType:", "Control"); 2521 T("TxQ ID:", q.cntxt_id); 2522 T("TxQ size:", q.size); 2523 T("TxQ inuse:", q.in_use); 2524 T("TxQ CIDX:", q.cidx); 2525 T("TxQ PIDX:", q.pidx); 2526 TL("TxQFull:", q.stops); 2527 TL("TxQRestarts:", q.restarts); 2528 } else if (fq_idx == 0) { 2529 const struct sge_rspq *evtq = &adap->sge.fw_evtq; 2530 2531 seq_printf(seq, "%-12s %16s\n", "QType:", "FW event queue"); 2532 seq_printf(seq, "%-12s %16u\n", "RspQ ID:", evtq->abs_id); 2533 seq_printf(seq, "%-12s %16u\n", "RspQ size:", evtq->size); 2534 seq_printf(seq, "%-12s %16u\n", "RspQE size:", evtq->iqe_len); 2535 seq_printf(seq, "%-12s %16u\n", "RspQ CIDX:", evtq->cidx); 2536 seq_printf(seq, "%-12s %16u\n", "RspQ Gen:", evtq->gen); 2537 seq_printf(seq, "%-12s %16u\n", "Intr delay:", 2538 qtimer_val(adap, evtq)); 2539 seq_printf(seq, "%-12s %16u\n", "Intr pktcnt:", 2540 adap->sge.counter_val[evtq->pktcnt_idx]); 2541 } 2542 #undef R 2543 #undef RL 2544 #undef T 2545 #undef TL 2546 #undef S 2547 #undef R3 2548 #undef T3 2549 #undef S3 2550 return 0; 2551 } 2552 2553 static int sge_queue_entries(const struct adapter *adap) 2554 { 2555 return DIV_ROUND_UP(adap->sge.ethqsets, 4) + 2556 DIV_ROUND_UP(adap->sge.ofldqsets, 4) + 2557 DIV_ROUND_UP(MAX_CTRL_QUEUES, 4) + 1; 2558 } 2559 2560 static void *sge_queue_start(struct seq_file *seq, loff_t *pos) 2561 { 2562 int entries = sge_queue_entries(seq->private); 2563 2564 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL; 2565 } 2566 2567 static void sge_queue_stop(struct seq_file *seq, void *v) 2568 { 2569 } 2570 2571 static void *sge_queue_next(struct seq_file *seq, void *v, loff_t *pos) 2572 { 2573 int entries = sge_queue_entries(seq->private); 2574 2575 ++*pos; 2576 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL; 2577 } 2578 2579 static const struct seq_operations sge_qinfo_seq_ops = { 2580 .start = sge_queue_start, 2581 .next = sge_queue_next, 2582 .stop = sge_queue_stop, 2583 .show = sge_qinfo_show 2584 }; 2585 2586 static int sge_qinfo_open(struct inode *inode, struct file *file) 2587 { 2588 int res = seq_open(file, &sge_qinfo_seq_ops); 2589 2590 if (!res) { 2591 struct seq_file *seq = file->private_data; 2592 2593 seq->private = inode->i_private; 2594 } 2595 return res; 2596 } 2597 2598 static const struct file_operations sge_qinfo_debugfs_fops = { 2599 .owner = THIS_MODULE, 2600 .open = sge_qinfo_open, 2601 .read = seq_read, 2602 .llseek = seq_lseek, 2603 .release = seq_release, 2604 }; 2605 2606 int mem_open(struct inode *inode, struct file *file) 2607 { 2608 unsigned int mem; 2609 struct adapter *adap; 2610 2611 file->private_data = inode->i_private; 2612 2613 mem = (uintptr_t)file->private_data & 0x3; 2614 adap = file->private_data - mem; 2615 2616 (void)t4_fwcache(adap, FW_PARAM_DEV_FWCACHE_FLUSH); 2617 2618 return 0; 2619 } 2620 2621 static ssize_t mem_read(struct file *file, char __user *buf, size_t count, 2622 loff_t *ppos) 2623 { 2624 loff_t pos = *ppos; 2625 loff_t avail = file_inode(file)->i_size; 2626 unsigned int mem = (uintptr_t)file->private_data & 3; 2627 struct adapter *adap = file->private_data - mem; 2628 __be32 *data; 2629 int ret; 2630 2631 if (pos < 0) 2632 return -EINVAL; 2633 if (pos >= avail) 2634 return 0; 2635 if (count > avail - pos) 2636 count = avail - pos; 2637 2638 data = kvzalloc(count, GFP_KERNEL); 2639 if (!data) 2640 return -ENOMEM; 2641 2642 spin_lock(&adap->win0_lock); 2643 ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ); 2644 spin_unlock(&adap->win0_lock); 2645 if (ret) { 2646 kvfree(data); 2647 return ret; 2648 } 2649 ret = copy_to_user(buf, data, count); 2650 2651 kvfree(data); 2652 if (ret) 2653 return -EFAULT; 2654 2655 *ppos = pos + count; 2656 return count; 2657 } 2658 static const struct file_operations mem_debugfs_fops = { 2659 .owner = THIS_MODULE, 2660 .open = simple_open, 2661 .read = mem_read, 2662 .llseek = default_llseek, 2663 }; 2664 2665 static int tid_info_show(struct seq_file *seq, void *v) 2666 { 2667 struct adapter *adap = seq->private; 2668 const struct tid_info *t = &adap->tids; 2669 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip); 2670 2671 if (t4_read_reg(adap, LE_DB_CONFIG_A) & HASHEN_F) { 2672 unsigned int sb; 2673 seq_printf(seq, "Connections in use: %u\n", 2674 atomic_read(&t->conns_in_use)); 2675 2676 if (chip <= CHELSIO_T5) 2677 sb = t4_read_reg(adap, LE_DB_SERVER_INDEX_A) / 4; 2678 else 2679 sb = t4_read_reg(adap, LE_DB_SRVR_START_INDEX_A); 2680 2681 if (sb) { 2682 seq_printf(seq, "TID range: 0..%u/%u..%u", sb - 1, 2683 adap->tids.hash_base, 2684 t->ntids - 1); 2685 seq_printf(seq, ", in use: %u/%u\n", 2686 atomic_read(&t->tids_in_use), 2687 atomic_read(&t->hash_tids_in_use)); 2688 } else if (adap->flags & FW_OFLD_CONN) { 2689 seq_printf(seq, "TID range: %u..%u/%u..%u", 2690 t->aftid_base, 2691 t->aftid_end, 2692 adap->tids.hash_base, 2693 t->ntids - 1); 2694 seq_printf(seq, ", in use: %u/%u\n", 2695 atomic_read(&t->tids_in_use), 2696 atomic_read(&t->hash_tids_in_use)); 2697 } else { 2698 seq_printf(seq, "TID range: %u..%u", 2699 adap->tids.hash_base, 2700 t->ntids - 1); 2701 seq_printf(seq, ", in use: %u\n", 2702 atomic_read(&t->hash_tids_in_use)); 2703 } 2704 } else if (t->ntids) { 2705 seq_printf(seq, "Connections in use: %u\n", 2706 atomic_read(&t->conns_in_use)); 2707 2708 seq_printf(seq, "TID range: 0..%u", t->ntids - 1); 2709 seq_printf(seq, ", in use: %u\n", 2710 atomic_read(&t->tids_in_use)); 2711 } 2712 2713 if (t->nstids) 2714 seq_printf(seq, "STID range: %u..%u, in use-IPv4/IPv6: %u/%u\n", 2715 (!t->stid_base && 2716 (chip <= CHELSIO_T5)) ? 2717 t->stid_base + 1 : t->stid_base, 2718 t->stid_base + t->nstids - 1, 2719 t->stids_in_use - t->v6_stids_in_use, 2720 t->v6_stids_in_use); 2721 2722 if (t->natids) 2723 seq_printf(seq, "ATID range: 0..%u, in use: %u\n", 2724 t->natids - 1, t->atids_in_use); 2725 seq_printf(seq, "FTID range: %u..%u\n", t->ftid_base, 2726 t->ftid_base + t->nftids - 1); 2727 if (t->nsftids) 2728 seq_printf(seq, "SFTID range: %u..%u in use: %u\n", 2729 t->sftid_base, t->sftid_base + t->nsftids - 2, 2730 t->sftids_in_use); 2731 if (t->ntids) 2732 seq_printf(seq, "HW TID usage: %u IP users, %u IPv6 users\n", 2733 t4_read_reg(adap, LE_DB_ACT_CNT_IPV4_A), 2734 t4_read_reg(adap, LE_DB_ACT_CNT_IPV6_A)); 2735 return 0; 2736 } 2737 2738 DEFINE_SIMPLE_DEBUGFS_FILE(tid_info); 2739 2740 static void add_debugfs_mem(struct adapter *adap, const char *name, 2741 unsigned int idx, unsigned int size_mb) 2742 { 2743 debugfs_create_file_size(name, S_IRUSR, adap->debugfs_root, 2744 (void *)adap + idx, &mem_debugfs_fops, 2745 size_mb << 20); 2746 } 2747 2748 static ssize_t blocked_fl_read(struct file *filp, char __user *ubuf, 2749 size_t count, loff_t *ppos) 2750 { 2751 int len; 2752 const struct adapter *adap = filp->private_data; 2753 char *buf; 2754 ssize_t size = (adap->sge.egr_sz + 3) / 4 + 2755 adap->sge.egr_sz / 32 + 2; /* includes ,/\n/\0 */ 2756 2757 buf = kzalloc(size, GFP_KERNEL); 2758 if (!buf) 2759 return -ENOMEM; 2760 2761 len = snprintf(buf, size - 1, "%*pb\n", 2762 adap->sge.egr_sz, adap->sge.blocked_fl); 2763 len += sprintf(buf + len, "\n"); 2764 size = simple_read_from_buffer(ubuf, count, ppos, buf, len); 2765 kvfree(buf); 2766 return size; 2767 } 2768 2769 static ssize_t blocked_fl_write(struct file *filp, const char __user *ubuf, 2770 size_t count, loff_t *ppos) 2771 { 2772 int err; 2773 unsigned long *t; 2774 struct adapter *adap = filp->private_data; 2775 2776 t = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), sizeof(long), GFP_KERNEL); 2777 if (!t) 2778 return -ENOMEM; 2779 2780 err = bitmap_parse_user(ubuf, count, t, adap->sge.egr_sz); 2781 if (err) 2782 return err; 2783 2784 bitmap_copy(adap->sge.blocked_fl, t, adap->sge.egr_sz); 2785 kvfree(t); 2786 return count; 2787 } 2788 2789 static const struct file_operations blocked_fl_fops = { 2790 .owner = THIS_MODULE, 2791 .open = simple_open, 2792 .read = blocked_fl_read, 2793 .write = blocked_fl_write, 2794 .llseek = generic_file_llseek, 2795 }; 2796 2797 struct mem_desc { 2798 unsigned int base; 2799 unsigned int limit; 2800 unsigned int idx; 2801 }; 2802 2803 static int mem_desc_cmp(const void *a, const void *b) 2804 { 2805 return ((const struct mem_desc *)a)->base - 2806 ((const struct mem_desc *)b)->base; 2807 } 2808 2809 static void mem_region_show(struct seq_file *seq, const char *name, 2810 unsigned int from, unsigned int to) 2811 { 2812 char buf[40]; 2813 2814 string_get_size((u64)to - from + 1, 1, STRING_UNITS_2, buf, 2815 sizeof(buf)); 2816 seq_printf(seq, "%-15s %#x-%#x [%s]\n", name, from, to, buf); 2817 } 2818 2819 static int meminfo_show(struct seq_file *seq, void *v) 2820 { 2821 static const char * const memory[] = { "EDC0:", "EDC1:", "MC:", 2822 "MC0:", "MC1:"}; 2823 static const char * const region[] = { 2824 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 2825 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 2826 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 2827 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 2828 "RQUDP region:", "PBL region:", "TXPBL region:", 2829 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 2830 "On-chip queues:" 2831 }; 2832 2833 int i, n; 2834 u32 lo, hi, used, alloc; 2835 struct mem_desc avail[4]; 2836 struct mem_desc mem[ARRAY_SIZE(region) + 3]; /* up to 3 holes */ 2837 struct mem_desc *md = mem; 2838 struct adapter *adap = seq->private; 2839 2840 for (i = 0; i < ARRAY_SIZE(mem); i++) { 2841 mem[i].limit = 0; 2842 mem[i].idx = i; 2843 } 2844 2845 /* Find and sort the populated memory ranges */ 2846 i = 0; 2847 lo = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 2848 if (lo & EDRAM0_ENABLE_F) { 2849 hi = t4_read_reg(adap, MA_EDRAM0_BAR_A); 2850 avail[i].base = EDRAM0_BASE_G(hi) << 20; 2851 avail[i].limit = avail[i].base + (EDRAM0_SIZE_G(hi) << 20); 2852 avail[i].idx = 0; 2853 i++; 2854 } 2855 if (lo & EDRAM1_ENABLE_F) { 2856 hi = t4_read_reg(adap, MA_EDRAM1_BAR_A); 2857 avail[i].base = EDRAM1_BASE_G(hi) << 20; 2858 avail[i].limit = avail[i].base + (EDRAM1_SIZE_G(hi) << 20); 2859 avail[i].idx = 1; 2860 i++; 2861 } 2862 2863 if (is_t5(adap->params.chip)) { 2864 if (lo & EXT_MEM0_ENABLE_F) { 2865 hi = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 2866 avail[i].base = EXT_MEM0_BASE_G(hi) << 20; 2867 avail[i].limit = 2868 avail[i].base + (EXT_MEM0_SIZE_G(hi) << 20); 2869 avail[i].idx = 3; 2870 i++; 2871 } 2872 if (lo & EXT_MEM1_ENABLE_F) { 2873 hi = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 2874 avail[i].base = EXT_MEM1_BASE_G(hi) << 20; 2875 avail[i].limit = 2876 avail[i].base + (EXT_MEM1_SIZE_G(hi) << 20); 2877 avail[i].idx = 4; 2878 i++; 2879 } 2880 } else { 2881 if (lo & EXT_MEM_ENABLE_F) { 2882 hi = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A); 2883 avail[i].base = EXT_MEM_BASE_G(hi) << 20; 2884 avail[i].limit = 2885 avail[i].base + (EXT_MEM_SIZE_G(hi) << 20); 2886 avail[i].idx = 2; 2887 i++; 2888 } 2889 } 2890 if (!i) /* no memory available */ 2891 return 0; 2892 sort(avail, i, sizeof(struct mem_desc), mem_desc_cmp, NULL); 2893 2894 (md++)->base = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A); 2895 (md++)->base = t4_read_reg(adap, SGE_IMSG_CTXT_BADDR_A); 2896 (md++)->base = t4_read_reg(adap, SGE_FLM_CACHE_BADDR_A); 2897 (md++)->base = t4_read_reg(adap, TP_CMM_TCB_BASE_A); 2898 (md++)->base = t4_read_reg(adap, TP_CMM_MM_BASE_A); 2899 (md++)->base = t4_read_reg(adap, TP_CMM_TIMER_BASE_A); 2900 (md++)->base = t4_read_reg(adap, TP_CMM_MM_RX_FLST_BASE_A); 2901 (md++)->base = t4_read_reg(adap, TP_CMM_MM_TX_FLST_BASE_A); 2902 (md++)->base = t4_read_reg(adap, TP_CMM_MM_PS_FLST_BASE_A); 2903 2904 /* the next few have explicit upper bounds */ 2905 md->base = t4_read_reg(adap, TP_PMM_TX_BASE_A); 2906 md->limit = md->base - 1 + 2907 t4_read_reg(adap, TP_PMM_TX_PAGE_SIZE_A) * 2908 PMTXMAXPAGE_G(t4_read_reg(adap, TP_PMM_TX_MAX_PAGE_A)); 2909 md++; 2910 2911 md->base = t4_read_reg(adap, TP_PMM_RX_BASE_A); 2912 md->limit = md->base - 1 + 2913 t4_read_reg(adap, TP_PMM_RX_PAGE_SIZE_A) * 2914 PMRXMAXPAGE_G(t4_read_reg(adap, TP_PMM_RX_MAX_PAGE_A)); 2915 md++; 2916 2917 if (t4_read_reg(adap, LE_DB_CONFIG_A) & HASHEN_F) { 2918 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) { 2919 hi = t4_read_reg(adap, LE_DB_TID_HASHBASE_A) / 4; 2920 md->base = t4_read_reg(adap, LE_DB_HASH_TID_BASE_A); 2921 } else { 2922 hi = t4_read_reg(adap, LE_DB_HASH_TID_BASE_A); 2923 md->base = t4_read_reg(adap, 2924 LE_DB_HASH_TBL_BASE_ADDR_A); 2925 } 2926 md->limit = 0; 2927 } else { 2928 md->base = 0; 2929 md->idx = ARRAY_SIZE(region); /* hide it */ 2930 } 2931 md++; 2932 2933 #define ulp_region(reg) do { \ 2934 md->base = t4_read_reg(adap, ULP_ ## reg ## _LLIMIT_A);\ 2935 (md++)->limit = t4_read_reg(adap, ULP_ ## reg ## _ULIMIT_A); \ 2936 } while (0) 2937 2938 ulp_region(RX_ISCSI); 2939 ulp_region(RX_TDDP); 2940 ulp_region(TX_TPT); 2941 ulp_region(RX_STAG); 2942 ulp_region(RX_RQ); 2943 ulp_region(RX_RQUDP); 2944 ulp_region(RX_PBL); 2945 ulp_region(TX_PBL); 2946 #undef ulp_region 2947 md->base = 0; 2948 md->idx = ARRAY_SIZE(region); 2949 if (!is_t4(adap->params.chip)) { 2950 u32 size = 0; 2951 u32 sge_ctrl = t4_read_reg(adap, SGE_CONTROL2_A); 2952 u32 fifo_size = t4_read_reg(adap, SGE_DBVFIFO_SIZE_A); 2953 2954 if (is_t5(adap->params.chip)) { 2955 if (sge_ctrl & VFIFO_ENABLE_F) 2956 size = DBVFIFO_SIZE_G(fifo_size); 2957 } else { 2958 size = T6_DBVFIFO_SIZE_G(fifo_size); 2959 } 2960 2961 if (size) { 2962 md->base = BASEADDR_G(t4_read_reg(adap, 2963 SGE_DBVFIFO_BADDR_A)); 2964 md->limit = md->base + (size << 2) - 1; 2965 } 2966 } 2967 2968 md++; 2969 2970 md->base = t4_read_reg(adap, ULP_RX_CTX_BASE_A); 2971 md->limit = 0; 2972 md++; 2973 md->base = t4_read_reg(adap, ULP_TX_ERR_TABLE_BASE_A); 2974 md->limit = 0; 2975 md++; 2976 2977 md->base = adap->vres.ocq.start; 2978 if (adap->vres.ocq.size) 2979 md->limit = md->base + adap->vres.ocq.size - 1; 2980 else 2981 md->idx = ARRAY_SIZE(region); /* hide it */ 2982 md++; 2983 2984 /* add any address-space holes, there can be up to 3 */ 2985 for (n = 0; n < i - 1; n++) 2986 if (avail[n].limit < avail[n + 1].base) 2987 (md++)->base = avail[n].limit; 2988 if (avail[n].limit) 2989 (md++)->base = avail[n].limit; 2990 2991 n = md - mem; 2992 sort(mem, n, sizeof(struct mem_desc), mem_desc_cmp, NULL); 2993 2994 for (lo = 0; lo < i; lo++) 2995 mem_region_show(seq, memory[avail[lo].idx], avail[lo].base, 2996 avail[lo].limit - 1); 2997 2998 seq_putc(seq, '\n'); 2999 for (i = 0; i < n; i++) { 3000 if (mem[i].idx >= ARRAY_SIZE(region)) 3001 continue; /* skip holes */ 3002 if (!mem[i].limit) 3003 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 3004 mem_region_show(seq, region[mem[i].idx], mem[i].base, 3005 mem[i].limit); 3006 } 3007 3008 seq_putc(seq, '\n'); 3009 lo = t4_read_reg(adap, CIM_SDRAM_BASE_ADDR_A); 3010 hi = t4_read_reg(adap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1; 3011 mem_region_show(seq, "uP RAM:", lo, hi); 3012 3013 lo = t4_read_reg(adap, CIM_EXTMEM2_BASE_ADDR_A); 3014 hi = t4_read_reg(adap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1; 3015 mem_region_show(seq, "uP Extmem2:", lo, hi); 3016 3017 lo = t4_read_reg(adap, TP_PMM_RX_MAX_PAGE_A); 3018 seq_printf(seq, "\n%u Rx pages of size %uKiB for %u channels\n", 3019 PMRXMAXPAGE_G(lo), 3020 t4_read_reg(adap, TP_PMM_RX_PAGE_SIZE_A) >> 10, 3021 (lo & PMRXNUMCHN_F) ? 2 : 1); 3022 3023 lo = t4_read_reg(adap, TP_PMM_TX_MAX_PAGE_A); 3024 hi = t4_read_reg(adap, TP_PMM_TX_PAGE_SIZE_A); 3025 seq_printf(seq, "%u Tx pages of size %u%ciB for %u channels\n", 3026 PMTXMAXPAGE_G(lo), 3027 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 3028 hi >= (1 << 20) ? 'M' : 'K', 1 << PMTXNUMCHN_G(lo)); 3029 seq_printf(seq, "%u p-structs\n\n", 3030 t4_read_reg(adap, TP_CMM_MM_MAX_PSTRUCT_A)); 3031 3032 for (i = 0; i < 4; i++) { 3033 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) 3034 lo = t4_read_reg(adap, MPS_RX_MAC_BG_PG_CNT0_A + i * 4); 3035 else 3036 lo = t4_read_reg(adap, MPS_RX_PG_RSV0_A + i * 4); 3037 if (is_t5(adap->params.chip)) { 3038 used = T5_USED_G(lo); 3039 alloc = T5_ALLOC_G(lo); 3040 } else { 3041 used = USED_G(lo); 3042 alloc = ALLOC_G(lo); 3043 } 3044 /* For T6 these are MAC buffer groups */ 3045 seq_printf(seq, "Port %d using %u pages out of %u allocated\n", 3046 i, used, alloc); 3047 } 3048 for (i = 0; i < adap->params.arch.nchan; i++) { 3049 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) 3050 lo = t4_read_reg(adap, 3051 MPS_RX_LPBK_BG_PG_CNT0_A + i * 4); 3052 else 3053 lo = t4_read_reg(adap, MPS_RX_PG_RSV4_A + i * 4); 3054 if (is_t5(adap->params.chip)) { 3055 used = T5_USED_G(lo); 3056 alloc = T5_ALLOC_G(lo); 3057 } else { 3058 used = USED_G(lo); 3059 alloc = ALLOC_G(lo); 3060 } 3061 /* For T6 these are MAC buffer groups */ 3062 seq_printf(seq, 3063 "Loopback %d using %u pages out of %u allocated\n", 3064 i, used, alloc); 3065 } 3066 return 0; 3067 } 3068 3069 static int meminfo_open(struct inode *inode, struct file *file) 3070 { 3071 return single_open(file, meminfo_show, inode->i_private); 3072 } 3073 3074 static const struct file_operations meminfo_fops = { 3075 .owner = THIS_MODULE, 3076 .open = meminfo_open, 3077 .read = seq_read, 3078 .llseek = seq_lseek, 3079 .release = single_release, 3080 }; 3081 3082 static int chcr_show(struct seq_file *seq, void *v) 3083 { 3084 struct adapter *adap = seq->private; 3085 3086 seq_puts(seq, "Chelsio Crypto Accelerator Stats \n"); 3087 seq_printf(seq, "Cipher Ops: %10u \n", 3088 atomic_read(&adap->chcr_stats.cipher_rqst)); 3089 seq_printf(seq, "Digest Ops: %10u \n", 3090 atomic_read(&adap->chcr_stats.digest_rqst)); 3091 seq_printf(seq, "Aead Ops: %10u \n", 3092 atomic_read(&adap->chcr_stats.aead_rqst)); 3093 seq_printf(seq, "Completion: %10u \n", 3094 atomic_read(&adap->chcr_stats.complete)); 3095 seq_printf(seq, "Error: %10u \n", 3096 atomic_read(&adap->chcr_stats.error)); 3097 seq_printf(seq, "Fallback: %10u \n", 3098 atomic_read(&adap->chcr_stats.fallback)); 3099 return 0; 3100 } 3101 3102 3103 static int chcr_stats_open(struct inode *inode, struct file *file) 3104 { 3105 return single_open(file, chcr_show, inode->i_private); 3106 } 3107 3108 static const struct file_operations chcr_stats_debugfs_fops = { 3109 .owner = THIS_MODULE, 3110 .open = chcr_stats_open, 3111 .read = seq_read, 3112 .llseek = seq_lseek, 3113 .release = single_release, 3114 }; 3115 /* Add an array of Debug FS files. 3116 */ 3117 void add_debugfs_files(struct adapter *adap, 3118 struct t4_debugfs_entry *files, 3119 unsigned int nfiles) 3120 { 3121 int i; 3122 3123 /* debugfs support is best effort */ 3124 for (i = 0; i < nfiles; i++) 3125 debugfs_create_file(files[i].name, files[i].mode, 3126 adap->debugfs_root, 3127 (void *)adap + files[i].data, 3128 files[i].ops); 3129 } 3130 3131 int t4_setup_debugfs(struct adapter *adap) 3132 { 3133 int i; 3134 u32 size = 0; 3135 struct dentry *de; 3136 3137 static struct t4_debugfs_entry t4_debugfs_files[] = { 3138 { "cim_la", &cim_la_fops, S_IRUSR, 0 }, 3139 { "cim_pif_la", &cim_pif_la_fops, S_IRUSR, 0 }, 3140 { "cim_ma_la", &cim_ma_la_fops, S_IRUSR, 0 }, 3141 { "cim_qcfg", &cim_qcfg_fops, S_IRUSR, 0 }, 3142 { "clk", &clk_debugfs_fops, S_IRUSR, 0 }, 3143 { "devlog", &devlog_fops, S_IRUSR, 0 }, 3144 { "mboxlog", &mboxlog_fops, S_IRUSR, 0 }, 3145 { "mbox0", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 0 }, 3146 { "mbox1", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 1 }, 3147 { "mbox2", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 2 }, 3148 { "mbox3", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 3 }, 3149 { "mbox4", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 4 }, 3150 { "mbox5", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 5 }, 3151 { "mbox6", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 6 }, 3152 { "mbox7", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 7 }, 3153 { "trace0", &mps_trc_debugfs_fops, S_IRUSR | S_IWUSR, 0 }, 3154 { "trace1", &mps_trc_debugfs_fops, S_IRUSR | S_IWUSR, 1 }, 3155 { "trace2", &mps_trc_debugfs_fops, S_IRUSR | S_IWUSR, 2 }, 3156 { "trace3", &mps_trc_debugfs_fops, S_IRUSR | S_IWUSR, 3 }, 3157 { "l2t", &t4_l2t_fops, S_IRUSR, 0}, 3158 { "mps_tcam", &mps_tcam_debugfs_fops, S_IRUSR, 0 }, 3159 { "rss", &rss_debugfs_fops, S_IRUSR, 0 }, 3160 { "rss_config", &rss_config_debugfs_fops, S_IRUSR, 0 }, 3161 { "rss_key", &rss_key_debugfs_fops, S_IRUSR, 0 }, 3162 { "rss_pf_config", &rss_pf_config_debugfs_fops, S_IRUSR, 0 }, 3163 { "rss_vf_config", &rss_vf_config_debugfs_fops, S_IRUSR, 0 }, 3164 { "sge_qinfo", &sge_qinfo_debugfs_fops, S_IRUSR, 0 }, 3165 { "ibq_tp0", &cim_ibq_fops, S_IRUSR, 0 }, 3166 { "ibq_tp1", &cim_ibq_fops, S_IRUSR, 1 }, 3167 { "ibq_ulp", &cim_ibq_fops, S_IRUSR, 2 }, 3168 { "ibq_sge0", &cim_ibq_fops, S_IRUSR, 3 }, 3169 { "ibq_sge1", &cim_ibq_fops, S_IRUSR, 4 }, 3170 { "ibq_ncsi", &cim_ibq_fops, S_IRUSR, 5 }, 3171 { "obq_ulp0", &cim_obq_fops, S_IRUSR, 0 }, 3172 { "obq_ulp1", &cim_obq_fops, S_IRUSR, 1 }, 3173 { "obq_ulp2", &cim_obq_fops, S_IRUSR, 2 }, 3174 { "obq_ulp3", &cim_obq_fops, S_IRUSR, 3 }, 3175 { "obq_sge", &cim_obq_fops, S_IRUSR, 4 }, 3176 { "obq_ncsi", &cim_obq_fops, S_IRUSR, 5 }, 3177 { "tp_la", &tp_la_fops, S_IRUSR, 0 }, 3178 { "ulprx_la", &ulprx_la_fops, S_IRUSR, 0 }, 3179 { "sensors", &sensors_debugfs_fops, S_IRUSR, 0 }, 3180 { "pm_stats", &pm_stats_debugfs_fops, S_IRUSR, 0 }, 3181 { "tx_rate", &tx_rate_debugfs_fops, S_IRUSR, 0 }, 3182 { "cctrl", &cctrl_tbl_debugfs_fops, S_IRUSR, 0 }, 3183 #if IS_ENABLED(CONFIG_IPV6) 3184 { "clip_tbl", &clip_tbl_debugfs_fops, S_IRUSR, 0 }, 3185 #endif 3186 { "tids", &tid_info_debugfs_fops, S_IRUSR, 0}, 3187 { "blocked_fl", &blocked_fl_fops, S_IRUSR | S_IWUSR, 0 }, 3188 { "meminfo", &meminfo_fops, S_IRUSR, 0 }, 3189 { "crypto", &chcr_stats_debugfs_fops, S_IRUSR, 0 }, 3190 }; 3191 3192 /* Debug FS nodes common to all T5 and later adapters. 3193 */ 3194 static struct t4_debugfs_entry t5_debugfs_files[] = { 3195 { "obq_sge_rx_q0", &cim_obq_fops, S_IRUSR, 6 }, 3196 { "obq_sge_rx_q1", &cim_obq_fops, S_IRUSR, 7 }, 3197 }; 3198 3199 add_debugfs_files(adap, 3200 t4_debugfs_files, 3201 ARRAY_SIZE(t4_debugfs_files)); 3202 if (!is_t4(adap->params.chip)) 3203 add_debugfs_files(adap, 3204 t5_debugfs_files, 3205 ARRAY_SIZE(t5_debugfs_files)); 3206 3207 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 3208 if (i & EDRAM0_ENABLE_F) { 3209 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 3210 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM0_SIZE_G(size)); 3211 } 3212 if (i & EDRAM1_ENABLE_F) { 3213 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 3214 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size)); 3215 } 3216 if (is_t5(adap->params.chip)) { 3217 if (i & EXT_MEM0_ENABLE_F) { 3218 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 3219 add_debugfs_mem(adap, "mc0", MEM_MC0, 3220 EXT_MEM0_SIZE_G(size)); 3221 } 3222 if (i & EXT_MEM1_ENABLE_F) { 3223 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 3224 add_debugfs_mem(adap, "mc1", MEM_MC1, 3225 EXT_MEM1_SIZE_G(size)); 3226 } 3227 } else { 3228 if (i & EXT_MEM_ENABLE_F) { 3229 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A); 3230 add_debugfs_mem(adap, "mc", MEM_MC, 3231 EXT_MEM_SIZE_G(size)); 3232 } 3233 } 3234 3235 de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap, 3236 &flash_debugfs_fops, adap->params.sf_size); 3237 debugfs_create_bool("use_backdoor", S_IWUSR | S_IRUSR, 3238 adap->debugfs_root, &adap->use_bd); 3239 debugfs_create_bool("trace_rss", S_IWUSR | S_IRUSR, 3240 adap->debugfs_root, &adap->trace_rss); 3241 3242 return 0; 3243 } 3244