1 /* 2 * Copyright (C) 2017 Chelsio Communications. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 */ 17 18 #include "t4_regs.h" 19 #include "cxgb4.h" 20 #include "cxgb4_cudbg.h" 21 #include "cudbg_zlib.h" 22 23 static const struct cxgb4_collect_entity cxgb4_collect_mem_dump[] = { 24 { CUDBG_EDC0, cudbg_collect_edc0_meminfo }, 25 { CUDBG_EDC1, cudbg_collect_edc1_meminfo }, 26 { CUDBG_MC0, cudbg_collect_mc0_meminfo }, 27 { CUDBG_MC1, cudbg_collect_mc1_meminfo }, 28 { CUDBG_HMA, cudbg_collect_hma_meminfo }, 29 }; 30 31 static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = { 32 { CUDBG_MBOX_LOG, cudbg_collect_mbox_log }, 33 { CUDBG_DEV_LOG, cudbg_collect_fw_devlog }, 34 { CUDBG_REG_DUMP, cudbg_collect_reg_dump }, 35 { CUDBG_CIM_LA, cudbg_collect_cim_la }, 36 { CUDBG_CIM_MA_LA, cudbg_collect_cim_ma_la }, 37 { CUDBG_CIM_QCFG, cudbg_collect_cim_qcfg }, 38 { CUDBG_CIM_IBQ_TP0, cudbg_collect_cim_ibq_tp0 }, 39 { CUDBG_CIM_IBQ_TP1, cudbg_collect_cim_ibq_tp1 }, 40 { CUDBG_CIM_IBQ_ULP, cudbg_collect_cim_ibq_ulp }, 41 { CUDBG_CIM_IBQ_SGE0, cudbg_collect_cim_ibq_sge0 }, 42 { CUDBG_CIM_IBQ_SGE1, cudbg_collect_cim_ibq_sge1 }, 43 { CUDBG_CIM_IBQ_NCSI, cudbg_collect_cim_ibq_ncsi }, 44 { CUDBG_CIM_OBQ_ULP0, cudbg_collect_cim_obq_ulp0 }, 45 { CUDBG_CIM_OBQ_ULP1, cudbg_collect_cim_obq_ulp1 }, 46 { CUDBG_CIM_OBQ_ULP2, cudbg_collect_cim_obq_ulp2 }, 47 { CUDBG_CIM_OBQ_ULP3, cudbg_collect_cim_obq_ulp3 }, 48 { CUDBG_CIM_OBQ_SGE, cudbg_collect_cim_obq_sge }, 49 { CUDBG_CIM_OBQ_NCSI, cudbg_collect_cim_obq_ncsi }, 50 { CUDBG_RSS, cudbg_collect_rss }, 51 { CUDBG_RSS_VF_CONF, cudbg_collect_rss_vf_config }, 52 { CUDBG_PATH_MTU, cudbg_collect_path_mtu }, 53 { CUDBG_PM_STATS, cudbg_collect_pm_stats }, 54 { CUDBG_HW_SCHED, cudbg_collect_hw_sched }, 55 { CUDBG_TP_INDIRECT, cudbg_collect_tp_indirect }, 56 { CUDBG_SGE_INDIRECT, cudbg_collect_sge_indirect }, 57 { CUDBG_ULPRX_LA, cudbg_collect_ulprx_la }, 58 { CUDBG_TP_LA, cudbg_collect_tp_la }, 59 { CUDBG_MEMINFO, cudbg_collect_meminfo }, 60 { CUDBG_CIM_PIF_LA, cudbg_collect_cim_pif_la }, 61 { CUDBG_CLK, cudbg_collect_clk_info }, 62 { CUDBG_CIM_OBQ_RXQ0, cudbg_collect_obq_sge_rx_q0 }, 63 { CUDBG_CIM_OBQ_RXQ1, cudbg_collect_obq_sge_rx_q1 }, 64 { CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect }, 65 { CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect }, 66 { CUDBG_TID_INFO, cudbg_collect_tid }, 67 { CUDBG_PCIE_CONFIG, cudbg_collect_pcie_config }, 68 { CUDBG_DUMP_CONTEXT, cudbg_collect_dump_context }, 69 { CUDBG_MPS_TCAM, cudbg_collect_mps_tcam }, 70 { CUDBG_VPD_DATA, cudbg_collect_vpd_data }, 71 { CUDBG_LE_TCAM, cudbg_collect_le_tcam }, 72 { CUDBG_CCTRL, cudbg_collect_cctrl }, 73 { CUDBG_MA_INDIRECT, cudbg_collect_ma_indirect }, 74 { CUDBG_ULPTX_LA, cudbg_collect_ulptx_la }, 75 { CUDBG_UP_CIM_INDIRECT, cudbg_collect_up_cim_indirect }, 76 { CUDBG_PBT_TABLE, cudbg_collect_pbt_tables }, 77 { CUDBG_HMA_INDIRECT, cudbg_collect_hma_indirect }, 78 }; 79 80 static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity) 81 { 82 struct cudbg_tcam tcam_region = { 0 }; 83 u32 value, n = 0, len = 0; 84 85 switch (entity) { 86 case CUDBG_REG_DUMP: 87 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { 88 case CHELSIO_T4: 89 len = T4_REGMAP_SIZE; 90 break; 91 case CHELSIO_T5: 92 case CHELSIO_T6: 93 len = T5_REGMAP_SIZE; 94 break; 95 default: 96 break; 97 } 98 break; 99 case CUDBG_DEV_LOG: 100 len = adap->params.devlog.size; 101 break; 102 case CUDBG_CIM_LA: 103 if (is_t6(adap->params.chip)) { 104 len = adap->params.cim_la_size / 10 + 1; 105 len *= 10 * sizeof(u32); 106 } else { 107 len = adap->params.cim_la_size / 8; 108 len *= 8 * sizeof(u32); 109 } 110 len += sizeof(u32); /* for reading CIM LA configuration */ 111 break; 112 case CUDBG_CIM_MA_LA: 113 len = 2 * CIM_MALA_SIZE * 5 * sizeof(u32); 114 break; 115 case CUDBG_CIM_QCFG: 116 len = sizeof(struct cudbg_cim_qcfg); 117 break; 118 case CUDBG_CIM_IBQ_TP0: 119 case CUDBG_CIM_IBQ_TP1: 120 case CUDBG_CIM_IBQ_ULP: 121 case CUDBG_CIM_IBQ_SGE0: 122 case CUDBG_CIM_IBQ_SGE1: 123 case CUDBG_CIM_IBQ_NCSI: 124 len = CIM_IBQ_SIZE * 4 * sizeof(u32); 125 break; 126 case CUDBG_CIM_OBQ_ULP0: 127 len = cudbg_cim_obq_size(adap, 0); 128 break; 129 case CUDBG_CIM_OBQ_ULP1: 130 len = cudbg_cim_obq_size(adap, 1); 131 break; 132 case CUDBG_CIM_OBQ_ULP2: 133 len = cudbg_cim_obq_size(adap, 2); 134 break; 135 case CUDBG_CIM_OBQ_ULP3: 136 len = cudbg_cim_obq_size(adap, 3); 137 break; 138 case CUDBG_CIM_OBQ_SGE: 139 len = cudbg_cim_obq_size(adap, 4); 140 break; 141 case CUDBG_CIM_OBQ_NCSI: 142 len = cudbg_cim_obq_size(adap, 5); 143 break; 144 case CUDBG_CIM_OBQ_RXQ0: 145 len = cudbg_cim_obq_size(adap, 6); 146 break; 147 case CUDBG_CIM_OBQ_RXQ1: 148 len = cudbg_cim_obq_size(adap, 7); 149 break; 150 case CUDBG_EDC0: 151 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 152 if (value & EDRAM0_ENABLE_F) { 153 value = t4_read_reg(adap, MA_EDRAM0_BAR_A); 154 len = EDRAM0_SIZE_G(value); 155 } 156 len = cudbg_mbytes_to_bytes(len); 157 break; 158 case CUDBG_EDC1: 159 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 160 if (value & EDRAM1_ENABLE_F) { 161 value = t4_read_reg(adap, MA_EDRAM1_BAR_A); 162 len = EDRAM1_SIZE_G(value); 163 } 164 len = cudbg_mbytes_to_bytes(len); 165 break; 166 case CUDBG_MC0: 167 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 168 if (value & EXT_MEM0_ENABLE_F) { 169 value = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 170 len = EXT_MEM0_SIZE_G(value); 171 } 172 len = cudbg_mbytes_to_bytes(len); 173 break; 174 case CUDBG_MC1: 175 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 176 if (value & EXT_MEM1_ENABLE_F) { 177 value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 178 len = EXT_MEM1_SIZE_G(value); 179 } 180 len = cudbg_mbytes_to_bytes(len); 181 break; 182 case CUDBG_RSS: 183 len = t4_chip_rss_size(adap) * sizeof(u16); 184 break; 185 case CUDBG_RSS_VF_CONF: 186 len = adap->params.arch.vfcount * 187 sizeof(struct cudbg_rss_vf_conf); 188 break; 189 case CUDBG_PATH_MTU: 190 len = NMTUS * sizeof(u16); 191 break; 192 case CUDBG_PM_STATS: 193 len = sizeof(struct cudbg_pm_stats); 194 break; 195 case CUDBG_HW_SCHED: 196 len = sizeof(struct cudbg_hw_sched); 197 break; 198 case CUDBG_TP_INDIRECT: 199 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { 200 case CHELSIO_T5: 201 n = sizeof(t5_tp_pio_array) + 202 sizeof(t5_tp_tm_pio_array) + 203 sizeof(t5_tp_mib_index_array); 204 break; 205 case CHELSIO_T6: 206 n = sizeof(t6_tp_pio_array) + 207 sizeof(t6_tp_tm_pio_array) + 208 sizeof(t6_tp_mib_index_array); 209 break; 210 default: 211 break; 212 } 213 n = n / (IREG_NUM_ELEM * sizeof(u32)); 214 len = sizeof(struct ireg_buf) * n; 215 break; 216 case CUDBG_SGE_INDIRECT: 217 len = sizeof(struct ireg_buf) * 2 + 218 sizeof(struct sge_qbase_reg_field); 219 break; 220 case CUDBG_ULPRX_LA: 221 len = sizeof(struct cudbg_ulprx_la); 222 break; 223 case CUDBG_TP_LA: 224 len = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64); 225 break; 226 case CUDBG_MEMINFO: 227 len = sizeof(struct cudbg_meminfo); 228 break; 229 case CUDBG_CIM_PIF_LA: 230 len = sizeof(struct cudbg_cim_pif_la); 231 len += 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32); 232 break; 233 case CUDBG_CLK: 234 len = sizeof(struct cudbg_clk_info); 235 break; 236 case CUDBG_PCIE_INDIRECT: 237 n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); 238 len = sizeof(struct ireg_buf) * n * 2; 239 break; 240 case CUDBG_PM_INDIRECT: 241 n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32)); 242 len = sizeof(struct ireg_buf) * n * 2; 243 break; 244 case CUDBG_TID_INFO: 245 len = sizeof(struct cudbg_tid_info_region_rev1); 246 break; 247 case CUDBG_PCIE_CONFIG: 248 len = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS; 249 break; 250 case CUDBG_DUMP_CONTEXT: 251 len = cudbg_dump_context_size(adap); 252 break; 253 case CUDBG_MPS_TCAM: 254 len = sizeof(struct cudbg_mps_tcam) * 255 adap->params.arch.mps_tcam_size; 256 break; 257 case CUDBG_VPD_DATA: 258 len = sizeof(struct cudbg_vpd_data); 259 break; 260 case CUDBG_LE_TCAM: 261 cudbg_fill_le_tcam_info(adap, &tcam_region); 262 len = sizeof(struct cudbg_tcam) + 263 sizeof(struct cudbg_tid_data) * tcam_region.max_tid; 264 break; 265 case CUDBG_CCTRL: 266 len = sizeof(u16) * NMTUS * NCCTRL_WIN; 267 break; 268 case CUDBG_MA_INDIRECT: 269 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 270 n = sizeof(t6_ma_ireg_array) / 271 (IREG_NUM_ELEM * sizeof(u32)); 272 len = sizeof(struct ireg_buf) * n * 2; 273 } 274 break; 275 case CUDBG_ULPTX_LA: 276 len = sizeof(struct cudbg_ulptx_la); 277 break; 278 case CUDBG_UP_CIM_INDIRECT: 279 n = 0; 280 if (is_t5(adap->params.chip)) 281 n = sizeof(t5_up_cim_reg_array) / 282 ((IREG_NUM_ELEM + 1) * sizeof(u32)); 283 else if (is_t6(adap->params.chip)) 284 n = sizeof(t6_up_cim_reg_array) / 285 ((IREG_NUM_ELEM + 1) * sizeof(u32)); 286 len = sizeof(struct ireg_buf) * n; 287 break; 288 case CUDBG_PBT_TABLE: 289 len = sizeof(struct cudbg_pbt_tables); 290 break; 291 case CUDBG_MBOX_LOG: 292 len = sizeof(struct cudbg_mbox_log) * adap->mbox_log->size; 293 break; 294 case CUDBG_HMA_INDIRECT: 295 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 296 n = sizeof(t6_hma_ireg_array) / 297 (IREG_NUM_ELEM * sizeof(u32)); 298 len = sizeof(struct ireg_buf) * n; 299 } 300 break; 301 case CUDBG_HMA: 302 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 303 if (value & HMA_MUX_F) { 304 /* In T6, there's no MC1. So, HMA shares MC1 305 * address space. 306 */ 307 value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 308 len = EXT_MEM1_SIZE_G(value); 309 } 310 len = cudbg_mbytes_to_bytes(len); 311 break; 312 default: 313 break; 314 } 315 316 return len; 317 } 318 319 u32 cxgb4_get_dump_length(struct adapter *adap, u32 flag) 320 { 321 u32 i, entity; 322 u32 len = 0; 323 u32 wsize; 324 325 if (flag & CXGB4_ETH_DUMP_HW) { 326 for (i = 0; i < ARRAY_SIZE(cxgb4_collect_hw_dump); i++) { 327 entity = cxgb4_collect_hw_dump[i].entity; 328 len += cxgb4_get_entity_length(adap, entity); 329 } 330 } 331 332 if (flag & CXGB4_ETH_DUMP_MEM) { 333 for (i = 0; i < ARRAY_SIZE(cxgb4_collect_mem_dump); i++) { 334 entity = cxgb4_collect_mem_dump[i].entity; 335 len += cxgb4_get_entity_length(adap, entity); 336 } 337 } 338 339 /* If compression is enabled, a smaller destination buffer is enough */ 340 wsize = cudbg_get_workspace_size(); 341 if (wsize && len > CUDBG_DUMP_BUFF_SIZE) 342 len = CUDBG_DUMP_BUFF_SIZE; 343 344 return len; 345 } 346 347 static void cxgb4_cudbg_collect_entity(struct cudbg_init *pdbg_init, 348 struct cudbg_buffer *dbg_buff, 349 const struct cxgb4_collect_entity *e_arr, 350 u32 arr_size, void *buf, u32 *tot_size) 351 { 352 struct cudbg_error cudbg_err = { 0 }; 353 struct cudbg_entity_hdr *entity_hdr; 354 u32 i, total_size = 0; 355 int ret; 356 357 for (i = 0; i < arr_size; i++) { 358 const struct cxgb4_collect_entity *e = &e_arr[i]; 359 360 entity_hdr = cudbg_get_entity_hdr(buf, e->entity); 361 entity_hdr->entity_type = e->entity; 362 entity_hdr->start_offset = dbg_buff->offset; 363 memset(&cudbg_err, 0, sizeof(struct cudbg_error)); 364 ret = e->collect_cb(pdbg_init, dbg_buff, &cudbg_err); 365 if (ret) { 366 entity_hdr->size = 0; 367 dbg_buff->offset = entity_hdr->start_offset; 368 } else { 369 cudbg_align_debug_buffer(dbg_buff, entity_hdr); 370 } 371 372 /* Log error and continue with next entity */ 373 if (cudbg_err.sys_err) 374 ret = CUDBG_SYSTEM_ERROR; 375 376 entity_hdr->hdr_flags = ret; 377 entity_hdr->sys_err = cudbg_err.sys_err; 378 entity_hdr->sys_warn = cudbg_err.sys_warn; 379 total_size += entity_hdr->size; 380 } 381 382 *tot_size += total_size; 383 } 384 385 static int cudbg_alloc_compress_buff(struct cudbg_init *pdbg_init) 386 { 387 u32 workspace_size; 388 389 workspace_size = cudbg_get_workspace_size(); 390 pdbg_init->compress_buff = vzalloc(CUDBG_COMPRESS_BUFF_SIZE + 391 workspace_size); 392 if (!pdbg_init->compress_buff) 393 return -ENOMEM; 394 395 pdbg_init->compress_buff_size = CUDBG_COMPRESS_BUFF_SIZE; 396 pdbg_init->workspace = (u8 *)pdbg_init->compress_buff + 397 CUDBG_COMPRESS_BUFF_SIZE - workspace_size; 398 return 0; 399 } 400 401 static void cudbg_free_compress_buff(struct cudbg_init *pdbg_init) 402 { 403 if (pdbg_init->compress_buff) 404 vfree(pdbg_init->compress_buff); 405 } 406 407 int cxgb4_cudbg_collect(struct adapter *adap, void *buf, u32 *buf_size, 408 u32 flag) 409 { 410 struct cudbg_buffer dbg_buff = { 0 }; 411 u32 size, min_size, total_size = 0; 412 struct cudbg_init cudbg_init; 413 struct cudbg_hdr *cudbg_hdr; 414 int rc; 415 416 size = *buf_size; 417 418 memset(&cudbg_init, 0, sizeof(struct cudbg_init)); 419 cudbg_init.adap = adap; 420 cudbg_init.outbuf = buf; 421 cudbg_init.outbuf_size = size; 422 423 dbg_buff.data = buf; 424 dbg_buff.size = size; 425 dbg_buff.offset = 0; 426 427 cudbg_hdr = (struct cudbg_hdr *)buf; 428 cudbg_hdr->signature = CUDBG_SIGNATURE; 429 cudbg_hdr->hdr_len = sizeof(struct cudbg_hdr); 430 cudbg_hdr->major_ver = CUDBG_MAJOR_VERSION; 431 cudbg_hdr->minor_ver = CUDBG_MINOR_VERSION; 432 cudbg_hdr->max_entities = CUDBG_MAX_ENTITY; 433 cudbg_hdr->chip_ver = adap->params.chip; 434 cudbg_hdr->dump_type = CUDBG_DUMP_TYPE_MINI; 435 436 min_size = sizeof(struct cudbg_hdr) + 437 sizeof(struct cudbg_entity_hdr) * 438 cudbg_hdr->max_entities; 439 if (size < min_size) 440 return -ENOMEM; 441 442 rc = cudbg_get_workspace_size(); 443 if (rc) { 444 /* Zlib available. So, use zlib deflate */ 445 cudbg_init.compress_type = CUDBG_COMPRESSION_ZLIB; 446 rc = cudbg_alloc_compress_buff(&cudbg_init); 447 if (rc) { 448 /* Ignore error and continue without compression. */ 449 dev_warn(adap->pdev_dev, 450 "Fail allocating compression buffer ret: %d. Continuing without compression.\n", 451 rc); 452 cudbg_init.compress_type = CUDBG_COMPRESSION_NONE; 453 rc = 0; 454 } 455 } else { 456 cudbg_init.compress_type = CUDBG_COMPRESSION_NONE; 457 } 458 459 cudbg_hdr->compress_type = cudbg_init.compress_type; 460 dbg_buff.offset += min_size; 461 total_size = dbg_buff.offset; 462 463 if (flag & CXGB4_ETH_DUMP_HW) 464 cxgb4_cudbg_collect_entity(&cudbg_init, &dbg_buff, 465 cxgb4_collect_hw_dump, 466 ARRAY_SIZE(cxgb4_collect_hw_dump), 467 buf, 468 &total_size); 469 470 if (flag & CXGB4_ETH_DUMP_MEM) 471 cxgb4_cudbg_collect_entity(&cudbg_init, &dbg_buff, 472 cxgb4_collect_mem_dump, 473 ARRAY_SIZE(cxgb4_collect_mem_dump), 474 buf, 475 &total_size); 476 477 cudbg_free_compress_buff(&cudbg_init); 478 cudbg_hdr->data_len = total_size; 479 if (cudbg_init.compress_type != CUDBG_COMPRESSION_NONE) 480 *buf_size = size; 481 else 482 *buf_size = total_size; 483 return 0; 484 } 485 486 void cxgb4_init_ethtool_dump(struct adapter *adapter) 487 { 488 adapter->eth_dump.flag = CXGB4_ETH_DUMP_NONE; 489 adapter->eth_dump.version = adapter->params.fw_vers; 490 adapter->eth_dump.len = 0; 491 } 492 493 static int cxgb4_cudbg_vmcoredd_collect(struct vmcoredd_data *data, void *buf) 494 { 495 struct adapter *adap = container_of(data, struct adapter, vmcoredd); 496 u32 len = data->size; 497 498 return cxgb4_cudbg_collect(adap, buf, &len, CXGB4_ETH_DUMP_ALL); 499 } 500 501 int cxgb4_cudbg_vmcore_add_dump(struct adapter *adap) 502 { 503 struct vmcoredd_data *data = &adap->vmcoredd; 504 u32 len; 505 506 len = sizeof(struct cudbg_hdr) + 507 sizeof(struct cudbg_entity_hdr) * CUDBG_MAX_ENTITY; 508 len += CUDBG_DUMP_BUFF_SIZE; 509 510 data->size = len; 511 snprintf(data->dump_name, sizeof(data->dump_name), "%s_%s", 512 cxgb4_driver_name, adap->name); 513 data->vmcoredd_callback = cxgb4_cudbg_vmcoredd_collect; 514 515 return vmcore_add_device_dump(data); 516 } 517