1 /* 2 * Copyright (C) 2017 Chelsio Communications. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 */ 17 18 #include "t4_regs.h" 19 #include "cxgb4.h" 20 #include "cxgb4_cudbg.h" 21 #include "cudbg_entity.h" 22 23 static const struct cxgb4_collect_entity cxgb4_collect_mem_dump[] = { 24 { CUDBG_EDC0, cudbg_collect_edc0_meminfo }, 25 { CUDBG_EDC1, cudbg_collect_edc1_meminfo }, 26 }; 27 28 static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = { 29 { CUDBG_MBOX_LOG, cudbg_collect_mbox_log }, 30 { CUDBG_DEV_LOG, cudbg_collect_fw_devlog }, 31 { CUDBG_REG_DUMP, cudbg_collect_reg_dump }, 32 { CUDBG_CIM_LA, cudbg_collect_cim_la }, 33 { CUDBG_CIM_MA_LA, cudbg_collect_cim_ma_la }, 34 { CUDBG_CIM_QCFG, cudbg_collect_cim_qcfg }, 35 { CUDBG_CIM_IBQ_TP0, cudbg_collect_cim_ibq_tp0 }, 36 { CUDBG_CIM_IBQ_TP1, cudbg_collect_cim_ibq_tp1 }, 37 { CUDBG_CIM_IBQ_ULP, cudbg_collect_cim_ibq_ulp }, 38 { CUDBG_CIM_IBQ_SGE0, cudbg_collect_cim_ibq_sge0 }, 39 { CUDBG_CIM_IBQ_SGE1, cudbg_collect_cim_ibq_sge1 }, 40 { CUDBG_CIM_IBQ_NCSI, cudbg_collect_cim_ibq_ncsi }, 41 { CUDBG_CIM_OBQ_ULP0, cudbg_collect_cim_obq_ulp0 }, 42 { CUDBG_CIM_OBQ_ULP1, cudbg_collect_cim_obq_ulp1 }, 43 { CUDBG_CIM_OBQ_ULP2, cudbg_collect_cim_obq_ulp2 }, 44 { CUDBG_CIM_OBQ_ULP3, cudbg_collect_cim_obq_ulp3 }, 45 { CUDBG_CIM_OBQ_SGE, cudbg_collect_cim_obq_sge }, 46 { CUDBG_CIM_OBQ_NCSI, cudbg_collect_cim_obq_ncsi }, 47 { CUDBG_RSS, cudbg_collect_rss }, 48 { CUDBG_RSS_VF_CONF, cudbg_collect_rss_vf_config }, 49 { CUDBG_PATH_MTU, cudbg_collect_path_mtu }, 50 { CUDBG_PM_STATS, cudbg_collect_pm_stats }, 51 { CUDBG_HW_SCHED, cudbg_collect_hw_sched }, 52 { CUDBG_TP_INDIRECT, cudbg_collect_tp_indirect }, 53 { CUDBG_SGE_INDIRECT, cudbg_collect_sge_indirect }, 54 { CUDBG_ULPRX_LA, cudbg_collect_ulprx_la }, 55 { CUDBG_TP_LA, cudbg_collect_tp_la }, 56 { CUDBG_CIM_PIF_LA, cudbg_collect_cim_pif_la }, 57 { CUDBG_CLK, cudbg_collect_clk_info }, 58 { CUDBG_CIM_OBQ_RXQ0, cudbg_collect_obq_sge_rx_q0 }, 59 { CUDBG_CIM_OBQ_RXQ1, cudbg_collect_obq_sge_rx_q1 }, 60 { CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect }, 61 { CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect }, 62 { CUDBG_TID_INFO, cudbg_collect_tid }, 63 { CUDBG_MPS_TCAM, cudbg_collect_mps_tcam }, 64 { CUDBG_VPD_DATA, cudbg_collect_vpd_data }, 65 { CUDBG_CCTRL, cudbg_collect_cctrl }, 66 { CUDBG_MA_INDIRECT, cudbg_collect_ma_indirect }, 67 { CUDBG_ULPTX_LA, cudbg_collect_ulptx_la }, 68 { CUDBG_UP_CIM_INDIRECT, cudbg_collect_up_cim_indirect }, 69 { CUDBG_PBT_TABLE, cudbg_collect_pbt_tables }, 70 { CUDBG_HMA_INDIRECT, cudbg_collect_hma_indirect }, 71 }; 72 73 static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity) 74 { 75 u32 value, n = 0, len = 0; 76 77 switch (entity) { 78 case CUDBG_REG_DUMP: 79 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { 80 case CHELSIO_T4: 81 len = T4_REGMAP_SIZE; 82 break; 83 case CHELSIO_T5: 84 case CHELSIO_T6: 85 len = T5_REGMAP_SIZE; 86 break; 87 default: 88 break; 89 } 90 break; 91 case CUDBG_DEV_LOG: 92 len = adap->params.devlog.size; 93 break; 94 case CUDBG_CIM_LA: 95 if (is_t6(adap->params.chip)) { 96 len = adap->params.cim_la_size / 10 + 1; 97 len *= 11 * sizeof(u32); 98 } else { 99 len = adap->params.cim_la_size / 8; 100 len *= 8 * sizeof(u32); 101 } 102 len += sizeof(u32); /* for reading CIM LA configuration */ 103 break; 104 case CUDBG_CIM_MA_LA: 105 len = 2 * CIM_MALA_SIZE * 5 * sizeof(u32); 106 break; 107 case CUDBG_CIM_QCFG: 108 len = sizeof(struct cudbg_cim_qcfg); 109 break; 110 case CUDBG_CIM_IBQ_TP0: 111 case CUDBG_CIM_IBQ_TP1: 112 case CUDBG_CIM_IBQ_ULP: 113 case CUDBG_CIM_IBQ_SGE0: 114 case CUDBG_CIM_IBQ_SGE1: 115 case CUDBG_CIM_IBQ_NCSI: 116 len = CIM_IBQ_SIZE * 4 * sizeof(u32); 117 break; 118 case CUDBG_CIM_OBQ_ULP0: 119 len = cudbg_cim_obq_size(adap, 0); 120 break; 121 case CUDBG_CIM_OBQ_ULP1: 122 len = cudbg_cim_obq_size(adap, 1); 123 break; 124 case CUDBG_CIM_OBQ_ULP2: 125 len = cudbg_cim_obq_size(adap, 2); 126 break; 127 case CUDBG_CIM_OBQ_ULP3: 128 len = cudbg_cim_obq_size(adap, 3); 129 break; 130 case CUDBG_CIM_OBQ_SGE: 131 len = cudbg_cim_obq_size(adap, 4); 132 break; 133 case CUDBG_CIM_OBQ_NCSI: 134 len = cudbg_cim_obq_size(adap, 5); 135 break; 136 case CUDBG_CIM_OBQ_RXQ0: 137 len = cudbg_cim_obq_size(adap, 6); 138 break; 139 case CUDBG_CIM_OBQ_RXQ1: 140 len = cudbg_cim_obq_size(adap, 7); 141 break; 142 case CUDBG_EDC0: 143 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 144 if (value & EDRAM0_ENABLE_F) { 145 value = t4_read_reg(adap, MA_EDRAM0_BAR_A); 146 len = EDRAM0_SIZE_G(value); 147 } 148 len = cudbg_mbytes_to_bytes(len); 149 break; 150 case CUDBG_EDC1: 151 value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); 152 if (value & EDRAM1_ENABLE_F) { 153 value = t4_read_reg(adap, MA_EDRAM1_BAR_A); 154 len = EDRAM1_SIZE_G(value); 155 } 156 len = cudbg_mbytes_to_bytes(len); 157 break; 158 case CUDBG_RSS: 159 len = RSS_NENTRIES * sizeof(u16); 160 break; 161 case CUDBG_RSS_VF_CONF: 162 len = adap->params.arch.vfcount * 163 sizeof(struct cudbg_rss_vf_conf); 164 break; 165 case CUDBG_PATH_MTU: 166 len = NMTUS * sizeof(u16); 167 break; 168 case CUDBG_PM_STATS: 169 len = sizeof(struct cudbg_pm_stats); 170 break; 171 case CUDBG_HW_SCHED: 172 len = sizeof(struct cudbg_hw_sched); 173 break; 174 case CUDBG_TP_INDIRECT: 175 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { 176 case CHELSIO_T5: 177 n = sizeof(t5_tp_pio_array) + 178 sizeof(t5_tp_tm_pio_array) + 179 sizeof(t5_tp_mib_index_array); 180 break; 181 case CHELSIO_T6: 182 n = sizeof(t6_tp_pio_array) + 183 sizeof(t6_tp_tm_pio_array) + 184 sizeof(t6_tp_mib_index_array); 185 break; 186 default: 187 break; 188 } 189 n = n / (IREG_NUM_ELEM * sizeof(u32)); 190 len = sizeof(struct ireg_buf) * n; 191 break; 192 case CUDBG_SGE_INDIRECT: 193 len = sizeof(struct ireg_buf) * 2; 194 break; 195 case CUDBG_ULPRX_LA: 196 len = sizeof(struct cudbg_ulprx_la); 197 break; 198 case CUDBG_TP_LA: 199 len = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64); 200 break; 201 case CUDBG_CIM_PIF_LA: 202 len = sizeof(struct cudbg_cim_pif_la); 203 len += 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32); 204 break; 205 case CUDBG_CLK: 206 len = sizeof(struct cudbg_clk_info); 207 break; 208 case CUDBG_PCIE_INDIRECT: 209 n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); 210 len = sizeof(struct ireg_buf) * n * 2; 211 break; 212 case CUDBG_PM_INDIRECT: 213 n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32)); 214 len = sizeof(struct ireg_buf) * n * 2; 215 break; 216 case CUDBG_TID_INFO: 217 len = sizeof(struct cudbg_tid_info_region_rev1); 218 break; 219 case CUDBG_MPS_TCAM: 220 len = sizeof(struct cudbg_mps_tcam) * 221 adap->params.arch.mps_tcam_size; 222 break; 223 case CUDBG_VPD_DATA: 224 len = sizeof(struct cudbg_vpd_data); 225 break; 226 case CUDBG_CCTRL: 227 len = sizeof(u16) * NMTUS * NCCTRL_WIN; 228 break; 229 case CUDBG_MA_INDIRECT: 230 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 231 n = sizeof(t6_ma_ireg_array) / 232 (IREG_NUM_ELEM * sizeof(u32)); 233 len = sizeof(struct ireg_buf) * n * 2; 234 } 235 break; 236 case CUDBG_ULPTX_LA: 237 len = sizeof(struct cudbg_ulptx_la); 238 break; 239 case CUDBG_UP_CIM_INDIRECT: 240 n = sizeof(t5_up_cim_reg_array) / (IREG_NUM_ELEM * sizeof(u32)); 241 len = sizeof(struct ireg_buf) * n; 242 break; 243 case CUDBG_PBT_TABLE: 244 len = sizeof(struct cudbg_pbt_tables); 245 break; 246 case CUDBG_MBOX_LOG: 247 len = sizeof(struct cudbg_mbox_log) * adap->mbox_log->size; 248 break; 249 case CUDBG_HMA_INDIRECT: 250 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 251 n = sizeof(t6_hma_ireg_array) / 252 (IREG_NUM_ELEM * sizeof(u32)); 253 len = sizeof(struct ireg_buf) * n; 254 } 255 break; 256 default: 257 break; 258 } 259 260 return len; 261 } 262 263 u32 cxgb4_get_dump_length(struct adapter *adap, u32 flag) 264 { 265 u32 i, entity; 266 u32 len = 0; 267 268 if (flag & CXGB4_ETH_DUMP_HW) { 269 for (i = 0; i < ARRAY_SIZE(cxgb4_collect_hw_dump); i++) { 270 entity = cxgb4_collect_hw_dump[i].entity; 271 len += cxgb4_get_entity_length(adap, entity); 272 } 273 } 274 275 if (flag & CXGB4_ETH_DUMP_MEM) { 276 for (i = 0; i < ARRAY_SIZE(cxgb4_collect_mem_dump); i++) { 277 entity = cxgb4_collect_mem_dump[i].entity; 278 len += cxgb4_get_entity_length(adap, entity); 279 } 280 } 281 282 return len; 283 } 284 285 static void cxgb4_cudbg_collect_entity(struct cudbg_init *pdbg_init, 286 struct cudbg_buffer *dbg_buff, 287 const struct cxgb4_collect_entity *e_arr, 288 u32 arr_size, void *buf, u32 *tot_size) 289 { 290 struct adapter *adap = pdbg_init->adap; 291 struct cudbg_error cudbg_err = { 0 }; 292 struct cudbg_entity_hdr *entity_hdr; 293 u32 entity_size, i; 294 u32 total_size = 0; 295 int ret; 296 297 for (i = 0; i < arr_size; i++) { 298 const struct cxgb4_collect_entity *e = &e_arr[i]; 299 300 /* Skip entities that won't fit in output buffer */ 301 entity_size = cxgb4_get_entity_length(adap, e->entity); 302 if (entity_size > 303 pdbg_init->outbuf_size - *tot_size - total_size) 304 continue; 305 306 entity_hdr = cudbg_get_entity_hdr(buf, e->entity); 307 entity_hdr->entity_type = e->entity; 308 entity_hdr->start_offset = dbg_buff->offset; 309 memset(&cudbg_err, 0, sizeof(struct cudbg_error)); 310 ret = e->collect_cb(pdbg_init, dbg_buff, &cudbg_err); 311 if (ret) { 312 entity_hdr->size = 0; 313 dbg_buff->offset = entity_hdr->start_offset; 314 } else { 315 cudbg_align_debug_buffer(dbg_buff, entity_hdr); 316 } 317 318 /* Log error and continue with next entity */ 319 if (cudbg_err.sys_err) 320 ret = CUDBG_SYSTEM_ERROR; 321 322 entity_hdr->hdr_flags = ret; 323 entity_hdr->sys_err = cudbg_err.sys_err; 324 entity_hdr->sys_warn = cudbg_err.sys_warn; 325 total_size += entity_hdr->size; 326 } 327 328 *tot_size += total_size; 329 } 330 331 int cxgb4_cudbg_collect(struct adapter *adap, void *buf, u32 *buf_size, 332 u32 flag) 333 { 334 struct cudbg_init cudbg_init = { 0 }; 335 struct cudbg_buffer dbg_buff = { 0 }; 336 u32 size, min_size, total_size = 0; 337 struct cudbg_hdr *cudbg_hdr; 338 339 size = *buf_size; 340 341 cudbg_init.adap = adap; 342 cudbg_init.outbuf = buf; 343 cudbg_init.outbuf_size = size; 344 345 dbg_buff.data = buf; 346 dbg_buff.size = size; 347 dbg_buff.offset = 0; 348 349 cudbg_hdr = (struct cudbg_hdr *)buf; 350 cudbg_hdr->signature = CUDBG_SIGNATURE; 351 cudbg_hdr->hdr_len = sizeof(struct cudbg_hdr); 352 cudbg_hdr->major_ver = CUDBG_MAJOR_VERSION; 353 cudbg_hdr->minor_ver = CUDBG_MINOR_VERSION; 354 cudbg_hdr->max_entities = CUDBG_MAX_ENTITY; 355 cudbg_hdr->chip_ver = adap->params.chip; 356 cudbg_hdr->dump_type = CUDBG_DUMP_TYPE_MINI; 357 cudbg_hdr->compress_type = CUDBG_COMPRESSION_NONE; 358 359 min_size = sizeof(struct cudbg_hdr) + 360 sizeof(struct cudbg_entity_hdr) * 361 cudbg_hdr->max_entities; 362 if (size < min_size) 363 return -ENOMEM; 364 365 dbg_buff.offset += min_size; 366 total_size = dbg_buff.offset; 367 368 if (flag & CXGB4_ETH_DUMP_HW) 369 cxgb4_cudbg_collect_entity(&cudbg_init, &dbg_buff, 370 cxgb4_collect_hw_dump, 371 ARRAY_SIZE(cxgb4_collect_hw_dump), 372 buf, 373 &total_size); 374 375 if (flag & CXGB4_ETH_DUMP_MEM) 376 cxgb4_cudbg_collect_entity(&cudbg_init, &dbg_buff, 377 cxgb4_collect_mem_dump, 378 ARRAY_SIZE(cxgb4_collect_mem_dump), 379 buf, 380 &total_size); 381 382 cudbg_hdr->data_len = total_size; 383 *buf_size = total_size; 384 return 0; 385 } 386 387 void cxgb4_init_ethtool_dump(struct adapter *adapter) 388 { 389 adapter->eth_dump.flag = CXGB4_ETH_DUMP_NONE; 390 adapter->eth_dump.version = adapter->params.fw_vers; 391 adapter->eth_dump.len = 0; 392 } 393