1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/rhashtable.h> 50 #include <linux/etherdevice.h> 51 #include <linux/net_tstamp.h> 52 #include <linux/ptp_clock_kernel.h> 53 #include <linux/ptp_classify.h> 54 #include <linux/crash_dump.h> 55 #include <linux/thermal.h> 56 #include <asm/io.h> 57 #include "t4_chip_type.h" 58 #include "cxgb4_uld.h" 59 60 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 61 extern struct list_head adapter_list; 62 extern struct mutex uld_mutex; 63 64 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 65 * This is the same as calc_tx_descs() for a TSO packet with 66 * nr_frags == MAX_SKB_FRAGS. 67 */ 68 #define ETHTXQ_STOP_THRES \ 69 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 70 71 enum { 72 MAX_NPORTS = 4, /* max # of ports */ 73 SERNUM_LEN = 24, /* Serial # length */ 74 EC_LEN = 16, /* E/C length */ 75 ID_LEN = 16, /* ID length */ 76 PN_LEN = 16, /* Part Number length */ 77 MACADDR_LEN = 12, /* MAC Address length */ 78 }; 79 80 enum { 81 T4_REGMAP_SIZE = (160 * 1024), 82 T5_REGMAP_SIZE = (332 * 1024), 83 }; 84 85 enum { 86 MEM_EDC0, 87 MEM_EDC1, 88 MEM_MC, 89 MEM_MC0 = MEM_MC, 90 MEM_MC1, 91 MEM_HMA, 92 }; 93 94 enum { 95 MEMWIN0_APERTURE = 2048, 96 MEMWIN0_BASE = 0x1b800, 97 MEMWIN1_APERTURE = 32768, 98 MEMWIN1_BASE = 0x28000, 99 MEMWIN1_BASE_T5 = 0x52000, 100 MEMWIN2_APERTURE = 65536, 101 MEMWIN2_BASE = 0x30000, 102 MEMWIN2_APERTURE_T5 = 131072, 103 MEMWIN2_BASE_T5 = 0x60000, 104 }; 105 106 enum dev_master { 107 MASTER_CANT, 108 MASTER_MAY, 109 MASTER_MUST 110 }; 111 112 enum dev_state { 113 DEV_STATE_UNINIT, 114 DEV_STATE_INIT, 115 DEV_STATE_ERR 116 }; 117 118 enum cc_pause { 119 PAUSE_RX = 1 << 0, 120 PAUSE_TX = 1 << 1, 121 PAUSE_AUTONEG = 1 << 2 122 }; 123 124 enum cc_fec { 125 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 126 FEC_RS = 1 << 1, /* Reed-Solomon */ 127 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 128 }; 129 130 struct port_stats { 131 u64 tx_octets; /* total # of octets in good frames */ 132 u64 tx_frames; /* all good frames */ 133 u64 tx_bcast_frames; /* all broadcast frames */ 134 u64 tx_mcast_frames; /* all multicast frames */ 135 u64 tx_ucast_frames; /* all unicast frames */ 136 u64 tx_error_frames; /* all error frames */ 137 138 u64 tx_frames_64; /* # of Tx frames in a particular range */ 139 u64 tx_frames_65_127; 140 u64 tx_frames_128_255; 141 u64 tx_frames_256_511; 142 u64 tx_frames_512_1023; 143 u64 tx_frames_1024_1518; 144 u64 tx_frames_1519_max; 145 146 u64 tx_drop; /* # of dropped Tx frames */ 147 u64 tx_pause; /* # of transmitted pause frames */ 148 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 149 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 150 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 151 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 152 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 153 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 154 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 155 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 156 157 u64 rx_octets; /* total # of octets in good frames */ 158 u64 rx_frames; /* all good frames */ 159 u64 rx_bcast_frames; /* all broadcast frames */ 160 u64 rx_mcast_frames; /* all multicast frames */ 161 u64 rx_ucast_frames; /* all unicast frames */ 162 u64 rx_too_long; /* # of frames exceeding MTU */ 163 u64 rx_jabber; /* # of jabber frames */ 164 u64 rx_fcs_err; /* # of received frames with bad FCS */ 165 u64 rx_len_err; /* # of received frames with length error */ 166 u64 rx_symbol_err; /* symbol errors */ 167 u64 rx_runt; /* # of short frames */ 168 169 u64 rx_frames_64; /* # of Rx frames in a particular range */ 170 u64 rx_frames_65_127; 171 u64 rx_frames_128_255; 172 u64 rx_frames_256_511; 173 u64 rx_frames_512_1023; 174 u64 rx_frames_1024_1518; 175 u64 rx_frames_1519_max; 176 177 u64 rx_pause; /* # of received pause frames */ 178 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 179 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 180 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 181 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 182 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 183 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 184 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 185 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 186 187 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 188 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 189 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 190 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 191 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 192 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 193 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 194 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 195 }; 196 197 struct lb_port_stats { 198 u64 octets; 199 u64 frames; 200 u64 bcast_frames; 201 u64 mcast_frames; 202 u64 ucast_frames; 203 u64 error_frames; 204 205 u64 frames_64; 206 u64 frames_65_127; 207 u64 frames_128_255; 208 u64 frames_256_511; 209 u64 frames_512_1023; 210 u64 frames_1024_1518; 211 u64 frames_1519_max; 212 213 u64 drop; 214 215 u64 ovflow0; 216 u64 ovflow1; 217 u64 ovflow2; 218 u64 ovflow3; 219 u64 trunc0; 220 u64 trunc1; 221 u64 trunc2; 222 u64 trunc3; 223 }; 224 225 struct tp_tcp_stats { 226 u32 tcp_out_rsts; 227 u64 tcp_in_segs; 228 u64 tcp_out_segs; 229 u64 tcp_retrans_segs; 230 }; 231 232 struct tp_usm_stats { 233 u32 frames; 234 u32 drops; 235 u64 octets; 236 }; 237 238 struct tp_fcoe_stats { 239 u32 frames_ddp; 240 u32 frames_drop; 241 u64 octets_ddp; 242 }; 243 244 struct tp_err_stats { 245 u32 mac_in_errs[4]; 246 u32 hdr_in_errs[4]; 247 u32 tcp_in_errs[4]; 248 u32 tnl_cong_drops[4]; 249 u32 ofld_chan_drops[4]; 250 u32 tnl_tx_drops[4]; 251 u32 ofld_vlan_drops[4]; 252 u32 tcp6_in_errs[4]; 253 u32 ofld_no_neigh; 254 u32 ofld_cong_defer; 255 }; 256 257 struct tp_cpl_stats { 258 u32 req[4]; 259 u32 rsp[4]; 260 }; 261 262 struct tp_rdma_stats { 263 u32 rqe_dfr_pkt; 264 u32 rqe_dfr_mod; 265 }; 266 267 struct sge_params { 268 u32 hps; /* host page size for our PF/VF */ 269 u32 eq_qpp; /* egress queues/page for our PF/VF */ 270 u32 iq_qpp; /* egress queues/page for our PF/VF */ 271 }; 272 273 struct tp_params { 274 unsigned int tre; /* log2 of core clocks per TP tick */ 275 unsigned int la_mask; /* what events are recorded by TP LA */ 276 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 277 /* channel map */ 278 279 uint32_t dack_re; /* DACK timer resolution */ 280 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 281 282 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 283 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 284 285 /* cached TP_OUT_CONFIG compressed error vector 286 * and passing outer header info for encapsulated packets. 287 */ 288 int rx_pkt_encap; 289 290 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 291 * subset of the set of fields which may be present in the Compressed 292 * Filter Tuple portion of filters and TCP TCB connections. The 293 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 294 * Since a variable number of fields may or may not be present, their 295 * shifted field positions within the Compressed Filter Tuple may 296 * vary, or not even be present if the field isn't selected in 297 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 298 * places we store their offsets here, or a -1 if the field isn't 299 * present. 300 */ 301 int fcoe_shift; 302 int port_shift; 303 int vnic_shift; 304 int vlan_shift; 305 int tos_shift; 306 int protocol_shift; 307 int ethertype_shift; 308 int macmatch_shift; 309 int matchtype_shift; 310 int frag_shift; 311 312 u64 hash_filter_mask; 313 }; 314 315 struct vpd_params { 316 unsigned int cclk; 317 u8 ec[EC_LEN + 1]; 318 u8 sn[SERNUM_LEN + 1]; 319 u8 id[ID_LEN + 1]; 320 u8 pn[PN_LEN + 1]; 321 u8 na[MACADDR_LEN + 1]; 322 }; 323 324 /* Maximum resources provisioned for a PCI PF. 325 */ 326 struct pf_resources { 327 unsigned int nvi; /* N virtual interfaces */ 328 unsigned int neq; /* N egress Qs */ 329 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 330 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 331 unsigned int niq; /* N ingress Qs */ 332 unsigned int tc; /* PCI-E traffic class */ 333 unsigned int pmask; /* port access rights mask */ 334 unsigned int nexactf; /* N exact MPS filters */ 335 unsigned int r_caps; /* read capabilities */ 336 unsigned int wx_caps; /* write/execute capabilities */ 337 }; 338 339 struct pci_params { 340 unsigned int vpd_cap_addr; 341 unsigned char speed; 342 unsigned char width; 343 }; 344 345 struct devlog_params { 346 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 347 u32 start; /* start of log in firmware memory */ 348 u32 size; /* size of log */ 349 }; 350 351 /* Stores chip specific parameters */ 352 struct arch_specific_params { 353 u8 nchan; 354 u8 pm_stats_cnt; 355 u8 cng_ch_bits_log; /* congestion channel map bits width */ 356 u16 mps_rplc_size; 357 u16 vfcount; 358 u32 sge_fl_db; 359 u16 mps_tcam_size; 360 }; 361 362 struct adapter_params { 363 struct sge_params sge; 364 struct tp_params tp; 365 struct vpd_params vpd; 366 struct pf_resources pfres; 367 struct pci_params pci; 368 struct devlog_params devlog; 369 enum pcie_memwin drv_memwin; 370 371 unsigned int cim_la_size; 372 373 unsigned int sf_size; /* serial flash size in bytes */ 374 unsigned int sf_nsec; /* # of flash sectors */ 375 376 unsigned int fw_vers; /* firmware version */ 377 unsigned int bs_vers; /* bootstrap version */ 378 unsigned int tp_vers; /* TP microcode version */ 379 unsigned int er_vers; /* expansion ROM version */ 380 unsigned int scfg_vers; /* Serial Configuration version */ 381 unsigned int vpd_vers; /* VPD Version */ 382 u8 api_vers[7]; 383 384 unsigned short mtus[NMTUS]; 385 unsigned short a_wnd[NCCTRL_WIN]; 386 unsigned short b_wnd[NCCTRL_WIN]; 387 388 unsigned char nports; /* # of ethernet ports */ 389 unsigned char portvec; 390 enum chip_type chip; /* chip code */ 391 struct arch_specific_params arch; /* chip specific params */ 392 unsigned char offload; 393 unsigned char crypto; /* HW capability for crypto */ 394 395 unsigned char bypass; 396 unsigned char hash_filter; 397 398 unsigned int ofldq_wr_cred; 399 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 400 401 unsigned int nsched_cls; /* number of traffic classes */ 402 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 403 unsigned int max_ird_adapter; /* Max read depth per adapter */ 404 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 405 u8 fw_caps_support; /* 32-bit Port Capabilities */ 406 bool filter2_wr_support; /* FW support for FILTER2_WR */ 407 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 408 409 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 410 * used by the Port 411 */ 412 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 413 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 414 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 415 }; 416 417 /* State needed to monitor the forward progress of SGE Ingress DMA activities 418 * and possible hangs. 419 */ 420 struct sge_idma_monitor_state { 421 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 422 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 423 unsigned int idma_state[2]; /* IDMA Hang detect state */ 424 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 425 unsigned int idma_warn[2]; /* time to warning in HZ */ 426 }; 427 428 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 429 * The access and execute times are signed in order to accommodate negative 430 * error returns. 431 */ 432 struct mbox_cmd { 433 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 434 u64 timestamp; /* OS-dependent timestamp */ 435 u32 seqno; /* sequence number */ 436 s16 access; /* time (ms) to access mailbox */ 437 s16 execute; /* time (ms) to execute */ 438 }; 439 440 struct mbox_cmd_log { 441 unsigned int size; /* number of entries in the log */ 442 unsigned int cursor; /* next position in the log to write */ 443 u32 seqno; /* next sequence number */ 444 /* variable length mailbox command log starts here */ 445 }; 446 447 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 448 * return a pointer to the specified entry. 449 */ 450 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 451 unsigned int entry_idx) 452 { 453 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 454 } 455 456 #include "t4fw_api.h" 457 458 #define FW_VERSION(chip) ( \ 459 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 460 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 461 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 462 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 463 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 464 465 struct fw_info { 466 u8 chip; 467 char *fs_name; 468 char *fw_mod_name; 469 struct fw_hdr fw_hdr; 470 }; 471 472 struct trace_params { 473 u32 data[TRACE_LEN / 4]; 474 u32 mask[TRACE_LEN / 4]; 475 unsigned short snap_len; 476 unsigned short min_len; 477 unsigned char skip_ofst; 478 unsigned char skip_len; 479 unsigned char invert; 480 unsigned char port; 481 }; 482 483 /* Firmware Port Capabilities types. */ 484 485 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 486 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 487 488 enum fw_caps { 489 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 490 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 491 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 492 }; 493 494 struct link_config { 495 fw_port_cap32_t pcaps; /* link capabilities */ 496 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 497 fw_port_cap32_t acaps; /* advertised capabilities */ 498 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 499 500 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 501 unsigned int speed; /* actual link speed (Mb/s) */ 502 503 enum cc_pause requested_fc; /* flow control user has requested */ 504 enum cc_pause fc; /* actual link flow control */ 505 506 enum cc_fec requested_fec; /* Forward Error Correction: */ 507 enum cc_fec fec; /* requested and actual in use */ 508 509 unsigned char autoneg; /* autonegotiating? */ 510 511 unsigned char link_ok; /* link up? */ 512 unsigned char link_down_rc; /* link down reason */ 513 514 bool new_module; /* ->OS Transceiver Module inserted */ 515 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 516 }; 517 518 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 519 520 enum { 521 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 522 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 523 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 524 }; 525 526 enum { 527 MAX_TXQ_ENTRIES = 16384, 528 MAX_CTRL_TXQ_ENTRIES = 1024, 529 MAX_RSPQ_ENTRIES = 16384, 530 MAX_RX_BUFFERS = 16384, 531 MIN_TXQ_ENTRIES = 32, 532 MIN_CTRL_TXQ_ENTRIES = 32, 533 MIN_RSPQ_ENTRIES = 128, 534 MIN_FL_ENTRIES = 16 535 }; 536 537 enum { 538 MAX_TXQ_DESC_SIZE = 64, 539 MAX_RXQ_DESC_SIZE = 128, 540 MAX_FL_DESC_SIZE = 8, 541 MAX_CTRL_TXQ_DESC_SIZE = 64, 542 }; 543 544 enum { 545 INGQ_EXTRAS = 2, /* firmware event queue and */ 546 /* forwarded interrupts */ 547 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 548 }; 549 550 enum { 551 PRIV_FLAG_PORT_TX_VM_BIT, 552 }; 553 554 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 555 556 #define PRIV_FLAGS_ADAP 0 557 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 558 559 struct adapter; 560 struct sge_rspq; 561 562 #include "cxgb4_dcb.h" 563 564 #ifdef CONFIG_CHELSIO_T4_FCOE 565 #include "cxgb4_fcoe.h" 566 #endif /* CONFIG_CHELSIO_T4_FCOE */ 567 568 struct port_info { 569 struct adapter *adapter; 570 u16 viid; 571 s16 xact_addr_filt; /* index of exact MAC address filter */ 572 u16 rss_size; /* size of VI's RSS table slice */ 573 s8 mdio_addr; 574 enum fw_port_type port_type; 575 u8 mod_type; 576 u8 port_id; 577 u8 tx_chan; 578 u8 lport; /* associated offload logical port */ 579 u8 nqsets; /* # of qsets */ 580 u8 first_qset; /* index of first qset */ 581 u8 rss_mode; 582 struct link_config link_cfg; 583 u16 *rss; 584 struct port_stats stats_base; 585 #ifdef CONFIG_CHELSIO_T4_DCB 586 struct port_dcb_info dcb; /* Data Center Bridging support */ 587 #endif 588 #ifdef CONFIG_CHELSIO_T4_FCOE 589 struct cxgb_fcoe fcoe; 590 #endif /* CONFIG_CHELSIO_T4_FCOE */ 591 bool rxtstamp; /* Enable TS */ 592 struct hwtstamp_config tstamp_config; 593 bool ptp_enable; 594 struct sched_table *sched_tbl; 595 u32 eth_flags; 596 597 /* viid and smt fields either returned by fw 598 * or decoded by parsing viid by driver. 599 */ 600 u8 vin; 601 u8 vivld; 602 u8 smt_idx; 603 }; 604 605 struct dentry; 606 struct work_struct; 607 608 enum { /* adapter flags */ 609 FULL_INIT_DONE = (1 << 0), 610 DEV_ENABLED = (1 << 1), 611 USING_MSI = (1 << 2), 612 USING_MSIX = (1 << 3), 613 FW_OK = (1 << 4), 614 RSS_TNLALLLOOKUP = (1 << 5), 615 USING_SOFT_PARAMS = (1 << 6), 616 MASTER_PF = (1 << 7), 617 FW_OFLD_CONN = (1 << 9), 618 ROOT_NO_RELAXED_ORDERING = (1 << 10), 619 SHUTTING_DOWN = (1 << 11), 620 }; 621 622 enum { 623 ULP_CRYPTO_LOOKASIDE = 1 << 0, 624 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 625 }; 626 627 struct rx_sw_desc; 628 629 struct sge_fl { /* SGE free-buffer queue state */ 630 unsigned int avail; /* # of available Rx buffers */ 631 unsigned int pend_cred; /* new buffers since last FL DB ring */ 632 unsigned int cidx; /* consumer index */ 633 unsigned int pidx; /* producer index */ 634 unsigned long alloc_failed; /* # of times buffer allocation failed */ 635 unsigned long large_alloc_failed; 636 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 637 unsigned long low; /* # of times momentarily starving */ 638 unsigned long starving; 639 /* RO fields */ 640 unsigned int cntxt_id; /* SGE context id for the free list */ 641 unsigned int size; /* capacity of free list */ 642 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 643 __be64 *desc; /* address of HW Rx descriptor ring */ 644 dma_addr_t addr; /* bus address of HW ring start */ 645 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 646 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 647 }; 648 649 /* A packet gather list */ 650 struct pkt_gl { 651 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 652 struct page_frag frags[MAX_SKB_FRAGS]; 653 void *va; /* virtual address of first byte */ 654 unsigned int nfrags; /* # of fragments */ 655 unsigned int tot_len; /* total length of fragments */ 656 }; 657 658 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 659 const struct pkt_gl *gl); 660 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 661 /* LRO related declarations for ULD */ 662 struct t4_lro_mgr { 663 #define MAX_LRO_SESSIONS 64 664 u8 lro_session_cnt; /* # of sessions to aggregate */ 665 unsigned long lro_pkts; /* # of LRO super packets */ 666 unsigned long lro_merged; /* # of wire packets merged by LRO */ 667 struct sk_buff_head lroq; /* list of aggregated sessions */ 668 }; 669 670 struct sge_rspq { /* state for an SGE response queue */ 671 struct napi_struct napi; 672 const __be64 *cur_desc; /* current descriptor in queue */ 673 unsigned int cidx; /* consumer index */ 674 u8 gen; /* current generation bit */ 675 u8 intr_params; /* interrupt holdoff parameters */ 676 u8 next_intr_params; /* holdoff params for next interrupt */ 677 u8 adaptive_rx; 678 u8 pktcnt_idx; /* interrupt packet threshold */ 679 u8 uld; /* ULD handling this queue */ 680 u8 idx; /* queue index within its group */ 681 int offset; /* offset into current Rx buffer */ 682 u16 cntxt_id; /* SGE context id for the response q */ 683 u16 abs_id; /* absolute SGE id for the response q */ 684 __be64 *desc; /* address of HW response ring */ 685 dma_addr_t phys_addr; /* physical address of the ring */ 686 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 687 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 688 unsigned int iqe_len; /* entry size */ 689 unsigned int size; /* capacity of response queue */ 690 struct adapter *adap; 691 struct net_device *netdev; /* associated net device */ 692 rspq_handler_t handler; 693 rspq_flush_handler_t flush_handler; 694 struct t4_lro_mgr lro_mgr; 695 }; 696 697 struct sge_eth_stats { /* Ethernet queue statistics */ 698 unsigned long pkts; /* # of ethernet packets */ 699 unsigned long lro_pkts; /* # of LRO super packets */ 700 unsigned long lro_merged; /* # of wire packets merged by LRO */ 701 unsigned long rx_cso; /* # of Rx checksum offloads */ 702 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 703 unsigned long rx_drops; /* # of packets dropped due to no mem */ 704 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 705 }; 706 707 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 708 struct sge_rspq rspq; 709 struct sge_fl fl; 710 struct sge_eth_stats stats; 711 } ____cacheline_aligned_in_smp; 712 713 struct sge_ofld_stats { /* offload queue statistics */ 714 unsigned long pkts; /* # of packets */ 715 unsigned long imm; /* # of immediate-data packets */ 716 unsigned long an; /* # of asynchronous notifications */ 717 unsigned long nomem; /* # of responses deferred due to no mem */ 718 }; 719 720 struct sge_ofld_rxq { /* SW offload Rx queue */ 721 struct sge_rspq rspq; 722 struct sge_fl fl; 723 struct sge_ofld_stats stats; 724 } ____cacheline_aligned_in_smp; 725 726 struct tx_desc { 727 __be64 flit[8]; 728 }; 729 730 struct tx_sw_desc; 731 732 struct sge_txq { 733 unsigned int in_use; /* # of in-use Tx descriptors */ 734 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 735 unsigned int size; /* # of descriptors */ 736 unsigned int cidx; /* SW consumer index */ 737 unsigned int pidx; /* producer index */ 738 unsigned long stops; /* # of times q has been stopped */ 739 unsigned long restarts; /* # of queue restarts */ 740 unsigned int cntxt_id; /* SGE context id for the Tx q */ 741 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 742 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 743 struct sge_qstat *stat; /* queue status entry */ 744 dma_addr_t phys_addr; /* physical address of the ring */ 745 spinlock_t db_lock; 746 int db_disabled; 747 unsigned short db_pidx; 748 unsigned short db_pidx_inc; 749 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 750 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 751 }; 752 753 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 754 struct sge_txq q; 755 struct netdev_queue *txq; /* associated netdev TX queue */ 756 #ifdef CONFIG_CHELSIO_T4_DCB 757 u8 dcb_prio; /* DCB Priority bound to queue */ 758 #endif 759 unsigned long tso; /* # of TSO requests */ 760 unsigned long tx_cso; /* # of Tx checksum offloads */ 761 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 762 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 763 } ____cacheline_aligned_in_smp; 764 765 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 766 struct sge_txq q; 767 struct adapter *adap; 768 struct sk_buff_head sendq; /* list of backpressured packets */ 769 struct tasklet_struct qresume_tsk; /* restarts the queue */ 770 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 771 u8 full; /* the Tx ring is full */ 772 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 773 } ____cacheline_aligned_in_smp; 774 775 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 776 struct sge_txq q; 777 struct adapter *adap; 778 struct sk_buff_head sendq; /* list of backpressured packets */ 779 struct tasklet_struct qresume_tsk; /* restarts the queue */ 780 u8 full; /* the Tx ring is full */ 781 } ____cacheline_aligned_in_smp; 782 783 struct sge_uld_rxq_info { 784 char name[IFNAMSIZ]; /* name of ULD driver */ 785 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 786 u16 *msix_tbl; /* msix_tbl for uld */ 787 u16 *rspq_id; /* response queue id's of rxq */ 788 u16 nrxq; /* # of ingress uld queues */ 789 u16 nciq; /* # of completion queues */ 790 u8 uld; /* uld type */ 791 }; 792 793 struct sge_uld_txq_info { 794 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 795 atomic_t users; /* num users */ 796 u16 ntxq; /* # of egress uld queues */ 797 }; 798 799 struct sge { 800 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 801 struct sge_eth_txq ptptxq; 802 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 803 804 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 805 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 806 struct sge_uld_rxq_info **uld_rxq_info; 807 struct sge_uld_txq_info **uld_txq_info; 808 809 struct sge_rspq intrq ____cacheline_aligned_in_smp; 810 spinlock_t intrq_lock; 811 812 u16 max_ethqsets; /* # of available Ethernet queue sets */ 813 u16 ethqsets; /* # of active Ethernet queue sets */ 814 u16 ethtxq_rover; /* Tx queue to clean up next */ 815 u16 ofldqsets; /* # of active ofld queue sets */ 816 u16 nqs_per_uld; /* # of Rx queues per ULD */ 817 u16 timer_val[SGE_NTIMERS]; 818 u8 counter_val[SGE_NCOUNTERS]; 819 u32 fl_pg_order; /* large page allocation size */ 820 u32 stat_len; /* length of status page at ring end */ 821 u32 pktshift; /* padding between CPL & packet data */ 822 u32 fl_align; /* response queue message alignment */ 823 u32 fl_starve_thres; /* Free List starvation threshold */ 824 825 struct sge_idma_monitor_state idma_monitor; 826 unsigned int egr_start; 827 unsigned int egr_sz; 828 unsigned int ingr_start; 829 unsigned int ingr_sz; 830 void **egr_map; /* qid->queue egress queue map */ 831 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 832 unsigned long *starving_fl; 833 unsigned long *txq_maperr; 834 unsigned long *blocked_fl; 835 struct timer_list rx_timer; /* refills starving FLs */ 836 struct timer_list tx_timer; /* checks Tx queues */ 837 }; 838 839 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 840 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 841 842 struct l2t_data; 843 844 #ifdef CONFIG_PCI_IOV 845 846 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 847 * Configuration initialization for T5 only has SR-IOV functionality enabled 848 * on PF0-3 in order to simplify everything. 849 */ 850 #define NUM_OF_PF_WITH_SRIOV 4 851 852 #endif 853 854 struct doorbell_stats { 855 u32 db_drop; 856 u32 db_empty; 857 u32 db_full; 858 }; 859 860 struct hash_mac_addr { 861 struct list_head list; 862 u8 addr[ETH_ALEN]; 863 }; 864 865 struct uld_msix_bmap { 866 unsigned long *msix_bmap; 867 unsigned int mapsize; 868 spinlock_t lock; /* lock for acquiring bitmap */ 869 }; 870 871 struct uld_msix_info { 872 unsigned short vec; 873 char desc[IFNAMSIZ + 10]; 874 unsigned int idx; 875 }; 876 877 struct vf_info { 878 unsigned char vf_mac_addr[ETH_ALEN]; 879 unsigned int tx_rate; 880 bool pf_set_mac; 881 u16 vlan; 882 }; 883 884 enum { 885 HMA_DMA_MAPPED_FLAG = 1 886 }; 887 888 struct hma_data { 889 unsigned char flags; 890 struct sg_table *sgt; 891 dma_addr_t *phy_addr; /* physical address of the page */ 892 }; 893 894 struct mbox_list { 895 struct list_head list; 896 }; 897 898 struct mps_encap_entry { 899 atomic_t refcnt; 900 }; 901 902 #if IS_ENABLED(CONFIG_THERMAL) 903 struct ch_thermal { 904 struct thermal_zone_device *tzdev; 905 int trip_temp; 906 int trip_type; 907 }; 908 #endif 909 910 struct adapter { 911 void __iomem *regs; 912 void __iomem *bar2; 913 u32 t4_bar0; 914 struct pci_dev *pdev; 915 struct device *pdev_dev; 916 const char *name; 917 unsigned int mbox; 918 unsigned int pf; 919 unsigned int flags; 920 unsigned int adap_idx; 921 enum chip_type chip; 922 u32 eth_flags; 923 924 int msg_enable; 925 __be16 vxlan_port; 926 u8 vxlan_port_cnt; 927 __be16 geneve_port; 928 u8 geneve_port_cnt; 929 930 struct adapter_params params; 931 struct cxgb4_virt_res vres; 932 unsigned int swintr; 933 934 struct { 935 unsigned short vec; 936 char desc[IFNAMSIZ + 10]; 937 } msix_info[MAX_INGQ + 1]; 938 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 939 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 940 int msi_idx; 941 942 struct doorbell_stats db_stats; 943 struct sge sge; 944 945 struct net_device *port[MAX_NPORTS]; 946 u8 chan_map[NCHAN]; /* channel -> port map */ 947 948 struct vf_info *vfinfo; 949 u8 num_vfs; 950 951 u32 filter_mode; 952 unsigned int l2t_start; 953 unsigned int l2t_end; 954 struct l2t_data *l2t; 955 unsigned int clipt_start; 956 unsigned int clipt_end; 957 struct clip_tbl *clipt; 958 unsigned int rawf_start; 959 unsigned int rawf_cnt; 960 struct smt_data *smt; 961 struct mps_encap_entry *mps_encap; 962 struct cxgb4_uld_info *uld; 963 void *uld_handle[CXGB4_ULD_MAX]; 964 unsigned int num_uld; 965 unsigned int num_ofld_uld; 966 struct list_head list_node; 967 struct list_head rcu_node; 968 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 969 970 void *iscsi_ppm; 971 972 struct tid_info tids; 973 void **tid_release_head; 974 spinlock_t tid_release_lock; 975 struct workqueue_struct *workq; 976 struct work_struct tid_release_task; 977 struct work_struct db_full_task; 978 struct work_struct db_drop_task; 979 struct work_struct fatal_err_notify_task; 980 bool tid_release_task_busy; 981 982 /* lock for mailbox cmd list */ 983 spinlock_t mbox_lock; 984 struct mbox_list mlist; 985 986 /* support for mailbox command/reply logging */ 987 #define T4_OS_LOG_MBOX_CMDS 256 988 struct mbox_cmd_log *mbox_log; 989 990 struct mutex uld_mutex; 991 992 struct dentry *debugfs_root; 993 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 994 bool trace_rss; /* 1 implies that different RSS flit per filter is 995 * used per filter else if 0 default RSS flit is 996 * used for all 4 filters. 997 */ 998 999 struct ptp_clock *ptp_clock; 1000 struct ptp_clock_info ptp_clock_info; 1001 struct sk_buff *ptp_tx_skb; 1002 /* ptp lock */ 1003 spinlock_t ptp_lock; 1004 spinlock_t stats_lock; 1005 spinlock_t win0_lock ____cacheline_aligned_in_smp; 1006 1007 /* TC u32 offload */ 1008 struct cxgb4_tc_u32_table *tc_u32; 1009 struct chcr_stats_debug chcr_stats; 1010 1011 /* TC flower offload */ 1012 bool tc_flower_initialized; 1013 struct rhashtable flower_tbl; 1014 struct rhashtable_params flower_ht_params; 1015 struct timer_list flower_stats_timer; 1016 struct work_struct flower_stats_work; 1017 1018 /* Ethtool Dump */ 1019 struct ethtool_dump eth_dump; 1020 1021 /* HMA */ 1022 struct hma_data hma; 1023 1024 struct srq_data *srq; 1025 1026 /* Dump buffer for collecting logs in kdump kernel */ 1027 struct vmcoredd_data vmcoredd; 1028 #if IS_ENABLED(CONFIG_THERMAL) 1029 struct ch_thermal ch_thermal; 1030 #endif 1031 }; 1032 1033 /* Support for "sched-class" command to allow a TX Scheduling Class to be 1034 * programmed with various parameters. 1035 */ 1036 struct ch_sched_params { 1037 s8 type; /* packet or flow */ 1038 union { 1039 struct { 1040 s8 level; /* scheduler hierarchy level */ 1041 s8 mode; /* per-class or per-flow */ 1042 s8 rateunit; /* bit or packet rate */ 1043 s8 ratemode; /* %port relative or kbps absolute */ 1044 s8 channel; /* scheduler channel [0..N] */ 1045 s8 class; /* scheduler class [0..N] */ 1046 s32 minrate; /* minimum rate */ 1047 s32 maxrate; /* maximum rate */ 1048 s16 weight; /* percent weight */ 1049 s16 pktsize; /* average packet size */ 1050 } params; 1051 } u; 1052 }; 1053 1054 enum { 1055 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 1056 }; 1057 1058 enum { 1059 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 1060 }; 1061 1062 enum { 1063 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1064 }; 1065 1066 enum { 1067 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1068 }; 1069 1070 enum { 1071 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1072 }; 1073 1074 struct tx_sw_desc { /* SW state per Tx descriptor */ 1075 struct sk_buff *skb; 1076 struct ulptx_sgl *sgl; 1077 }; 1078 1079 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1080 * to be bound to a TX Scheduling Class. 1081 */ 1082 struct ch_sched_queue { 1083 s8 queue; /* queue index */ 1084 s8 class; /* class index */ 1085 }; 1086 1087 /* Defined bit width of user definable filter tuples 1088 */ 1089 #define ETHTYPE_BITWIDTH 16 1090 #define FRAG_BITWIDTH 1 1091 #define MACIDX_BITWIDTH 9 1092 #define FCOE_BITWIDTH 1 1093 #define IPORT_BITWIDTH 3 1094 #define MATCHTYPE_BITWIDTH 3 1095 #define PROTO_BITWIDTH 8 1096 #define TOS_BITWIDTH 8 1097 #define PF_BITWIDTH 8 1098 #define VF_BITWIDTH 8 1099 #define IVLAN_BITWIDTH 16 1100 #define OVLAN_BITWIDTH 16 1101 #define ENCAP_VNI_BITWIDTH 24 1102 1103 /* Filter matching rules. These consist of a set of ingress packet field 1104 * (value, mask) tuples. The associated ingress packet field matches the 1105 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1106 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1107 * matches an ingress packet when all of the individual individual field 1108 * matching rules are true. 1109 * 1110 * Partial field masks are always valid, however, while it may be easy to 1111 * understand their meanings for some fields (e.g. IP address to match a 1112 * subnet), for others making sensible partial masks is less intuitive (e.g. 1113 * MPS match type) ... 1114 * 1115 * Most of the following data structures are modeled on T4 capabilities. 1116 * Drivers for earlier chips use the subsets which make sense for those chips. 1117 * We really need to come up with a hardware-independent mechanism to 1118 * represent hardware filter capabilities ... 1119 */ 1120 struct ch_filter_tuple { 1121 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1122 * register selects which of these fields will participate in the 1123 * filter match rules -- up to a maximum of 36 bits. Because 1124 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1125 * set of fields. 1126 */ 1127 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1128 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1129 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1130 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1131 uint32_t pfvf_vld:1; /* PF/VF valid */ 1132 uint32_t encap_vld:1; /* Encapsulation valid */ 1133 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1134 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1135 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1136 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1137 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1138 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1139 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1140 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1141 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1142 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1143 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1144 1145 /* Uncompressed header matching field rules. These are always 1146 * available for field rules. 1147 */ 1148 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1149 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1150 uint16_t lport; /* local port */ 1151 uint16_t fport; /* foreign port */ 1152 }; 1153 1154 /* A filter ioctl command. 1155 */ 1156 struct ch_filter_specification { 1157 /* Administrative fields for filter. 1158 */ 1159 uint32_t hitcnts:1; /* count filter hits in TCB */ 1160 uint32_t prio:1; /* filter has priority over active/server */ 1161 1162 /* Fundamental filter typing. This is the one element of filter 1163 * matching that doesn't exist as a (value, mask) tuple. 1164 */ 1165 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1166 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1167 1168 /* Packet dispatch information. Ingress packets which match the 1169 * filter rules will be dropped, passed to the host or switched back 1170 * out as egress packets. 1171 */ 1172 uint32_t action:2; /* drop, pass, switch */ 1173 1174 uint32_t rpttid:1; /* report TID in RSS hash field */ 1175 1176 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1177 uint32_t iq:10; /* ingress queue */ 1178 1179 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1180 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1181 /* 1 => TCB contains IQ ID */ 1182 1183 /* Switch proxy/rewrite fields. An ingress packet which matches a 1184 * filter with "switch" set will be looped back out as an egress 1185 * packet -- potentially with some Ethernet header rewriting. 1186 */ 1187 uint32_t eport:2; /* egress port to switch packet out */ 1188 uint32_t newdmac:1; /* rewrite destination MAC address */ 1189 uint32_t newsmac:1; /* rewrite source MAC address */ 1190 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1191 uint32_t nat_mode:3; /* specify NAT operation mode */ 1192 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1193 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1194 uint16_t vlan; /* VLAN Tag to insert */ 1195 1196 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1197 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1198 u16 nat_lport; /* local port to use after NAT'ing */ 1199 u16 nat_fport; /* foreign port to use after NAT'ing */ 1200 1201 /* reservation for future additions */ 1202 u8 rsvd[24]; 1203 1204 /* Filter rule value/mask pairs. 1205 */ 1206 struct ch_filter_tuple val; 1207 struct ch_filter_tuple mask; 1208 }; 1209 1210 enum { 1211 FILTER_PASS = 0, /* default */ 1212 FILTER_DROP, 1213 FILTER_SWITCH 1214 }; 1215 1216 enum { 1217 VLAN_NOCHANGE = 0, /* default */ 1218 VLAN_REMOVE, 1219 VLAN_INSERT, 1220 VLAN_REWRITE 1221 }; 1222 1223 enum { 1224 NAT_MODE_NONE = 0, /* No NAT performed */ 1225 NAT_MODE_DIP, /* NAT on Dst IP */ 1226 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1227 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1228 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1229 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1230 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1231 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1232 }; 1233 1234 /* Host shadow copy of ingress filter entry. This is in host native format 1235 * and doesn't match the ordering or bit order, etc. of the hardware of the 1236 * firmware command. The use of bit-field structure elements is purely to 1237 * remind ourselves of the field size limitations and save memory in the case 1238 * where the filter table is large. 1239 */ 1240 struct filter_entry { 1241 /* Administrative fields for filter. */ 1242 u32 valid:1; /* filter allocated and valid */ 1243 u32 locked:1; /* filter is administratively locked */ 1244 1245 u32 pending:1; /* filter action is pending firmware reply */ 1246 struct filter_ctx *ctx; /* Caller's completion hook */ 1247 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1248 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1249 struct net_device *dev; /* Associated net device */ 1250 u32 tid; /* This will store the actual tid */ 1251 1252 /* The filter itself. Most of this is a straight copy of information 1253 * provided by the extended ioctl(). Some fields are translated to 1254 * internal forms -- for instance the Ingress Queue ID passed in from 1255 * the ioctl() is translated into the Absolute Ingress Queue ID. 1256 */ 1257 struct ch_filter_specification fs; 1258 }; 1259 1260 static inline int is_offload(const struct adapter *adap) 1261 { 1262 return adap->params.offload; 1263 } 1264 1265 static inline int is_hashfilter(const struct adapter *adap) 1266 { 1267 return adap->params.hash_filter; 1268 } 1269 1270 static inline int is_pci_uld(const struct adapter *adap) 1271 { 1272 return adap->params.crypto; 1273 } 1274 1275 static inline int is_uld(const struct adapter *adap) 1276 { 1277 return (adap->params.offload || adap->params.crypto); 1278 } 1279 1280 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1281 { 1282 return readl(adap->regs + reg_addr); 1283 } 1284 1285 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1286 { 1287 writel(val, adap->regs + reg_addr); 1288 } 1289 1290 #ifndef readq 1291 static inline u64 readq(const volatile void __iomem *addr) 1292 { 1293 return readl(addr) + ((u64)readl(addr + 4) << 32); 1294 } 1295 1296 static inline void writeq(u64 val, volatile void __iomem *addr) 1297 { 1298 writel(val, addr); 1299 writel(val >> 32, addr + 4); 1300 } 1301 #endif 1302 1303 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1304 { 1305 return readq(adap->regs + reg_addr); 1306 } 1307 1308 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1309 { 1310 writeq(val, adap->regs + reg_addr); 1311 } 1312 1313 /** 1314 * t4_set_hw_addr - store a port's MAC address in SW 1315 * @adapter: the adapter 1316 * @port_idx: the port index 1317 * @hw_addr: the Ethernet address 1318 * 1319 * Store the Ethernet address of the given port in SW. Called by the common 1320 * code when it retrieves a port's Ethernet address from EEPROM. 1321 */ 1322 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1323 u8 hw_addr[]) 1324 { 1325 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1326 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1327 } 1328 1329 /** 1330 * netdev2pinfo - return the port_info structure associated with a net_device 1331 * @dev: the netdev 1332 * 1333 * Return the struct port_info associated with a net_device 1334 */ 1335 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1336 { 1337 return netdev_priv(dev); 1338 } 1339 1340 /** 1341 * adap2pinfo - return the port_info of a port 1342 * @adap: the adapter 1343 * @idx: the port index 1344 * 1345 * Return the port_info structure for the port of the given index. 1346 */ 1347 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1348 { 1349 return netdev_priv(adap->port[idx]); 1350 } 1351 1352 /** 1353 * netdev2adap - return the adapter structure associated with a net_device 1354 * @dev: the netdev 1355 * 1356 * Return the struct adapter associated with a net_device 1357 */ 1358 static inline struct adapter *netdev2adap(const struct net_device *dev) 1359 { 1360 return netdev2pinfo(dev)->adapter; 1361 } 1362 1363 /* Return a version number to identify the type of adapter. The scheme is: 1364 * - bits 0..9: chip version 1365 * - bits 10..15: chip revision 1366 * - bits 16..23: register dump version 1367 */ 1368 static inline unsigned int mk_adap_vers(struct adapter *ap) 1369 { 1370 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1371 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1372 } 1373 1374 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1375 static inline unsigned int qtimer_val(const struct adapter *adap, 1376 const struct sge_rspq *q) 1377 { 1378 unsigned int idx = q->intr_params >> 1; 1379 1380 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1381 } 1382 1383 /* driver version & name used for ethtool_drvinfo */ 1384 extern char cxgb4_driver_name[]; 1385 extern const char cxgb4_driver_version[]; 1386 1387 void t4_os_portmod_changed(struct adapter *adap, int port_id); 1388 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1389 1390 void t4_free_sge_resources(struct adapter *adap); 1391 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1392 irq_handler_t t4_intr_handler(struct adapter *adap); 1393 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1394 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1395 const struct pkt_gl *gl); 1396 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1397 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1398 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1399 struct net_device *dev, int intr_idx, 1400 struct sge_fl *fl, rspq_handler_t hnd, 1401 rspq_flush_handler_t flush_handler, int cong); 1402 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1403 struct net_device *dev, struct netdev_queue *netdevq, 1404 unsigned int iqid); 1405 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1406 struct net_device *dev, unsigned int iqid, 1407 unsigned int cmplqid); 1408 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1409 unsigned int cmplqid); 1410 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1411 struct net_device *dev, unsigned int iqid, 1412 unsigned int uld_type); 1413 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1414 int t4_sge_init(struct adapter *adap); 1415 void t4_sge_start(struct adapter *adap); 1416 void t4_sge_stop(struct adapter *adap); 1417 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1418 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1419 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1420 extern int dbfifo_int_thresh; 1421 1422 #define for_each_port(adapter, iter) \ 1423 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1424 1425 static inline int is_bypass(struct adapter *adap) 1426 { 1427 return adap->params.bypass; 1428 } 1429 1430 static inline int is_bypass_device(int device) 1431 { 1432 /* this should be set based upon device capabilities */ 1433 switch (device) { 1434 case 0x440b: 1435 case 0x440c: 1436 return 1; 1437 default: 1438 return 0; 1439 } 1440 } 1441 1442 static inline int is_10gbt_device(int device) 1443 { 1444 /* this should be set based upon device capabilities */ 1445 switch (device) { 1446 case 0x4409: 1447 case 0x4486: 1448 return 1; 1449 1450 default: 1451 return 0; 1452 } 1453 } 1454 1455 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1456 { 1457 return adap->params.vpd.cclk / 1000; 1458 } 1459 1460 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1461 unsigned int us) 1462 { 1463 return (us * adap->params.vpd.cclk) / 1000; 1464 } 1465 1466 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1467 unsigned int ticks) 1468 { 1469 /* add Core Clock / 2 to round ticks to nearest uS */ 1470 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1471 adapter->params.vpd.cclk); 1472 } 1473 1474 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1475 unsigned int ticks) 1476 { 1477 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1478 } 1479 1480 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1481 u32 val); 1482 1483 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1484 int size, void *rpl, bool sleep_ok, int timeout); 1485 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1486 void *rpl, bool sleep_ok); 1487 1488 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1489 const void *cmd, int size, void *rpl, 1490 int timeout) 1491 { 1492 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1493 timeout); 1494 } 1495 1496 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1497 int size, void *rpl) 1498 { 1499 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1500 } 1501 1502 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1503 int size, void *rpl) 1504 { 1505 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1506 } 1507 1508 /** 1509 * hash_mac_addr - return the hash value of a MAC address 1510 * @addr: the 48-bit Ethernet MAC address 1511 * 1512 * Hashes a MAC address according to the hash function used by HW inexact 1513 * (hash) address matching. 1514 */ 1515 static inline int hash_mac_addr(const u8 *addr) 1516 { 1517 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1518 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1519 1520 a ^= b; 1521 a ^= (a >> 12); 1522 a ^= (a >> 6); 1523 return a & 0x3f; 1524 } 1525 1526 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1527 unsigned int cnt); 1528 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1529 unsigned int us, unsigned int cnt, 1530 unsigned int size, unsigned int iqe_size) 1531 { 1532 q->adap = adap; 1533 cxgb4_set_rspq_intr_params(q, us, cnt); 1534 q->iqe_len = iqe_size; 1535 q->size = size; 1536 } 1537 1538 /** 1539 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1540 * @fw_mod_type: the Firmware Mofule Type 1541 * 1542 * Return whether the Firmware Module Type represents a real Transceiver 1543 * Module/Cable Module Type which has been inserted. 1544 */ 1545 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1546 { 1547 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1548 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1549 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1550 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1551 } 1552 1553 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1554 unsigned int data_reg, const u32 *vals, 1555 unsigned int nregs, unsigned int start_idx); 1556 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1557 unsigned int data_reg, u32 *vals, unsigned int nregs, 1558 unsigned int start_idx); 1559 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1560 1561 struct fw_filter_wr; 1562 1563 void t4_intr_enable(struct adapter *adapter); 1564 void t4_intr_disable(struct adapter *adapter); 1565 int t4_slow_intr_handler(struct adapter *adapter); 1566 1567 int t4_wait_dev_ready(void __iomem *regs); 1568 1569 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 1570 unsigned int port, struct link_config *lc, 1571 bool sleep_ok, int timeout); 1572 1573 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 1574 unsigned int port, struct link_config *lc) 1575 { 1576 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1577 true, FW_CMD_MAX_TIMEOUT); 1578 } 1579 1580 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 1581 unsigned int port, struct link_config *lc) 1582 { 1583 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1584 false, FW_CMD_MAX_TIMEOUT); 1585 } 1586 1587 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1588 1589 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1590 u32 t4_get_util_window(struct adapter *adap); 1591 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1592 1593 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1594 u32 *mem_base, u32 *mem_aperture); 1595 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1596 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1597 int dir); 1598 #define T4_MEMORY_WRITE 0 1599 #define T4_MEMORY_READ 1 1600 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1601 void *buf, int dir); 1602 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1603 u32 len, __be32 *buf) 1604 { 1605 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1606 } 1607 1608 unsigned int t4_get_regs_len(struct adapter *adapter); 1609 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1610 1611 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1612 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1613 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1614 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1615 int t4_get_pfres(struct adapter *adapter); 1616 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1617 unsigned int nwords, u32 *data, int byte_oriented); 1618 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1619 int t4_load_phy_fw(struct adapter *adap, 1620 int win, spinlock_t *lock, 1621 int (*phy_fw_version)(const u8 *, size_t), 1622 const u8 *phy_fw_data, size_t phy_fw_size); 1623 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1624 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1625 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1626 const u8 *fw_data, unsigned int size, int force); 1627 int t4_fl_pkt_align(struct adapter *adap); 1628 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1629 int t4_check_fw_version(struct adapter *adap); 1630 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1631 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1632 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1633 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1634 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1635 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1636 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1637 int t4_get_version_info(struct adapter *adapter); 1638 void t4_dump_version_info(struct adapter *adapter); 1639 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1640 const u8 *fw_data, unsigned int fw_size, 1641 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1642 int t4_prep_adapter(struct adapter *adapter); 1643 int t4_shutdown_adapter(struct adapter *adapter); 1644 1645 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1646 int t4_bar2_sge_qregs(struct adapter *adapter, 1647 unsigned int qid, 1648 enum t4_bar2_qtype qtype, 1649 int user, 1650 u64 *pbar2_qoffset, 1651 unsigned int *pbar2_qid); 1652 1653 unsigned int qtimer_val(const struct adapter *adap, 1654 const struct sge_rspq *q); 1655 1656 int t4_init_devlog_params(struct adapter *adapter); 1657 int t4_init_sge_params(struct adapter *adapter); 1658 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1659 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1660 int t4_init_rss_mode(struct adapter *adap, int mbox); 1661 int t4_init_portinfo(struct port_info *pi, int mbox, 1662 int port, int pf, int vf, u8 mac[]); 1663 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1664 void t4_fatal_err(struct adapter *adapter); 1665 unsigned int t4_chip_rss_size(struct adapter *adapter); 1666 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1667 int start, int n, const u16 *rspq, unsigned int nrspq); 1668 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1669 unsigned int flags); 1670 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1671 unsigned int flags, unsigned int defq); 1672 int t4_read_rss(struct adapter *adapter, u16 *entries); 1673 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1674 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1675 bool sleep_ok); 1676 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1677 u32 *valp, bool sleep_ok); 1678 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1679 u32 *vfl, u32 *vfh, bool sleep_ok); 1680 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1681 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1682 1683 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1684 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1685 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1686 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1687 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1688 size_t n); 1689 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1690 size_t n); 1691 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1692 unsigned int *valp); 1693 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1694 const unsigned int *valp); 1695 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1696 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1697 unsigned int *pif_req_wrptr, 1698 unsigned int *pif_rsp_wrptr); 1699 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1700 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1701 const char *t4_get_port_type_description(enum fw_port_type port_type); 1702 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1703 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1704 struct port_stats *stats, 1705 struct port_stats *offset); 1706 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1707 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1708 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1709 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1710 unsigned int mask, unsigned int val); 1711 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1712 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1713 bool sleep_ok); 1714 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1715 bool sleep_ok); 1716 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1717 bool sleep_ok); 1718 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1719 bool sleep_ok); 1720 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1721 struct tp_tcp_stats *v6, bool sleep_ok); 1722 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1723 struct tp_fcoe_stats *st, bool sleep_ok); 1724 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1725 const unsigned short *alpha, const unsigned short *beta); 1726 1727 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1728 1729 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1730 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1731 1732 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1733 const u8 *addr); 1734 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1735 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1736 1737 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1738 enum dev_master master, enum dev_state *state); 1739 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1740 int t4_early_init(struct adapter *adap, unsigned int mbox); 1741 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1742 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1743 unsigned int cache_line_size); 1744 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1745 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1746 unsigned int vf, unsigned int nparams, const u32 *params, 1747 u32 *val); 1748 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1749 unsigned int vf, unsigned int nparams, const u32 *params, 1750 u32 *val); 1751 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1752 unsigned int vf, unsigned int nparams, const u32 *params, 1753 u32 *val, int rw, bool sleep_ok); 1754 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1755 unsigned int pf, unsigned int vf, 1756 unsigned int nparams, const u32 *params, 1757 const u32 *val, int timeout); 1758 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1759 unsigned int vf, unsigned int nparams, const u32 *params, 1760 const u32 *val); 1761 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1762 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1763 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1764 unsigned int vi, unsigned int cmask, unsigned int pmask, 1765 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1766 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1767 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1768 unsigned int *rss_size, u8 *vivld, u8 *vin); 1769 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1770 unsigned int pf, unsigned int vf, 1771 unsigned int viid); 1772 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1773 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1774 bool sleep_ok); 1775 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1776 const u8 *addr, const u8 *mask, unsigned int idx, 1777 u8 lookup_type, u8 port_id, bool sleep_ok); 1778 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 1779 bool sleep_ok); 1780 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 1781 const u8 *addr, const u8 *mask, unsigned int vni, 1782 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 1783 bool sleep_ok); 1784 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1785 const u8 *addr, const u8 *mask, unsigned int idx, 1786 u8 lookup_type, u8 port_id, bool sleep_ok); 1787 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1788 unsigned int viid, bool free, unsigned int naddr, 1789 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1790 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1791 unsigned int viid, unsigned int naddr, 1792 const u8 **addr, bool sleep_ok); 1793 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1794 int idx, const u8 *addr, bool persist, u8 *smt_idx); 1795 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1796 bool ucast, u64 vec, bool sleep_ok); 1797 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1798 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1799 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1800 struct port_info *pi, 1801 bool rx_en, bool tx_en, bool dcb_en); 1802 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1803 bool rx_en, bool tx_en); 1804 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1805 unsigned int nblinks); 1806 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1807 unsigned int mmd, unsigned int reg, u16 *valp); 1808 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1809 unsigned int mmd, unsigned int reg, u16 val); 1810 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1811 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1812 unsigned int fl0id, unsigned int fl1id); 1813 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1814 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1815 unsigned int fl0id, unsigned int fl1id); 1816 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1817 unsigned int vf, unsigned int eqid); 1818 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1819 unsigned int vf, unsigned int eqid); 1820 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1821 unsigned int vf, unsigned int eqid); 1822 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1823 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1824 int t4_update_port_info(struct port_info *pi); 1825 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1826 unsigned int *speedp, unsigned int *mtup); 1827 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1828 void t4_db_full(struct adapter *adapter); 1829 void t4_db_dropped(struct adapter *adapter); 1830 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1831 int filter_index, int enable); 1832 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1833 int filter_index, int *enabled); 1834 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1835 u32 addr, u32 val); 1836 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1837 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1838 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1839 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1840 enum ctxt_type ctype, u32 *data); 1841 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1842 enum ctxt_type ctype, u32 *data); 1843 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1844 int rateunit, int ratemode, int channel, int class, 1845 int minrate, int maxrate, int weight, int pktsize); 1846 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1847 void t4_idma_monitor_init(struct adapter *adapter, 1848 struct sge_idma_monitor_state *idma); 1849 void t4_idma_monitor(struct adapter *adapter, 1850 struct sge_idma_monitor_state *idma, 1851 int hz, int ticks); 1852 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1853 unsigned int naddr, u8 *addr); 1854 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1855 u32 start_index, bool sleep_ok); 1856 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1857 u32 start_index, bool sleep_ok); 1858 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1859 u32 start_index, bool sleep_ok); 1860 1861 void t4_uld_mem_free(struct adapter *adap); 1862 int t4_uld_mem_alloc(struct adapter *adap); 1863 void t4_uld_clean_up(struct adapter *adap); 1864 void t4_register_netevent_notifier(void); 1865 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1866 unsigned int devid, unsigned int offset, 1867 unsigned int len, u8 *buf); 1868 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1869 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1870 unsigned int n, bool unmap); 1871 void free_txq(struct adapter *adap, struct sge_txq *q); 1872 void cxgb4_reclaim_completed_tx(struct adapter *adap, 1873 struct sge_txq *q, bool unmap); 1874 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1875 dma_addr_t *addr); 1876 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1877 void *pos); 1878 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1879 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1880 const dma_addr_t *addr); 1881 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 1882 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 1883 u16 vlan); 1884 int cxgb4_dcb_enabled(const struct net_device *dev); 1885 1886 int cxgb4_thermal_init(struct adapter *adap); 1887 int cxgb4_thermal_remove(struct adapter *adap); 1888 1889 #endif /* __CXGB4_H__ */ 1890