1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <linux/ptp_clock_kernel.h> 52 #include <linux/ptp_classify.h> 53 #include <asm/io.h> 54 #include "t4_chip_type.h" 55 #include "cxgb4_uld.h" 56 57 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 58 extern struct list_head adapter_list; 59 extern struct mutex uld_mutex; 60 61 enum { 62 MAX_NPORTS = 4, /* max # of ports */ 63 SERNUM_LEN = 24, /* Serial # length */ 64 EC_LEN = 16, /* E/C length */ 65 ID_LEN = 16, /* ID length */ 66 PN_LEN = 16, /* Part Number length */ 67 MACADDR_LEN = 12, /* MAC Address length */ 68 }; 69 70 enum { 71 T4_REGMAP_SIZE = (160 * 1024), 72 T5_REGMAP_SIZE = (332 * 1024), 73 }; 74 75 enum { 76 MEM_EDC0, 77 MEM_EDC1, 78 MEM_MC, 79 MEM_MC0 = MEM_MC, 80 MEM_MC1 81 }; 82 83 enum { 84 MEMWIN0_APERTURE = 2048, 85 MEMWIN0_BASE = 0x1b800, 86 MEMWIN1_APERTURE = 32768, 87 MEMWIN1_BASE = 0x28000, 88 MEMWIN1_BASE_T5 = 0x52000, 89 MEMWIN2_APERTURE = 65536, 90 MEMWIN2_BASE = 0x30000, 91 MEMWIN2_APERTURE_T5 = 131072, 92 MEMWIN2_BASE_T5 = 0x60000, 93 }; 94 95 enum dev_master { 96 MASTER_CANT, 97 MASTER_MAY, 98 MASTER_MUST 99 }; 100 101 enum dev_state { 102 DEV_STATE_UNINIT, 103 DEV_STATE_INIT, 104 DEV_STATE_ERR 105 }; 106 107 enum { 108 PAUSE_RX = 1 << 0, 109 PAUSE_TX = 1 << 1, 110 PAUSE_AUTONEG = 1 << 2 111 }; 112 113 enum { 114 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 115 FEC_RS = 1 << 1, /* Reed-Solomon */ 116 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 117 }; 118 119 struct port_stats { 120 u64 tx_octets; /* total # of octets in good frames */ 121 u64 tx_frames; /* all good frames */ 122 u64 tx_bcast_frames; /* all broadcast frames */ 123 u64 tx_mcast_frames; /* all multicast frames */ 124 u64 tx_ucast_frames; /* all unicast frames */ 125 u64 tx_error_frames; /* all error frames */ 126 127 u64 tx_frames_64; /* # of Tx frames in a particular range */ 128 u64 tx_frames_65_127; 129 u64 tx_frames_128_255; 130 u64 tx_frames_256_511; 131 u64 tx_frames_512_1023; 132 u64 tx_frames_1024_1518; 133 u64 tx_frames_1519_max; 134 135 u64 tx_drop; /* # of dropped Tx frames */ 136 u64 tx_pause; /* # of transmitted pause frames */ 137 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 138 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 139 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 140 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 141 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 142 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 143 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 144 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 145 146 u64 rx_octets; /* total # of octets in good frames */ 147 u64 rx_frames; /* all good frames */ 148 u64 rx_bcast_frames; /* all broadcast frames */ 149 u64 rx_mcast_frames; /* all multicast frames */ 150 u64 rx_ucast_frames; /* all unicast frames */ 151 u64 rx_too_long; /* # of frames exceeding MTU */ 152 u64 rx_jabber; /* # of jabber frames */ 153 u64 rx_fcs_err; /* # of received frames with bad FCS */ 154 u64 rx_len_err; /* # of received frames with length error */ 155 u64 rx_symbol_err; /* symbol errors */ 156 u64 rx_runt; /* # of short frames */ 157 158 u64 rx_frames_64; /* # of Rx frames in a particular range */ 159 u64 rx_frames_65_127; 160 u64 rx_frames_128_255; 161 u64 rx_frames_256_511; 162 u64 rx_frames_512_1023; 163 u64 rx_frames_1024_1518; 164 u64 rx_frames_1519_max; 165 166 u64 rx_pause; /* # of received pause frames */ 167 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 168 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 169 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 170 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 171 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 172 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 173 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 174 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 175 176 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 177 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 178 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 179 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 180 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 181 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 182 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 183 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 184 }; 185 186 struct lb_port_stats { 187 u64 octets; 188 u64 frames; 189 u64 bcast_frames; 190 u64 mcast_frames; 191 u64 ucast_frames; 192 u64 error_frames; 193 194 u64 frames_64; 195 u64 frames_65_127; 196 u64 frames_128_255; 197 u64 frames_256_511; 198 u64 frames_512_1023; 199 u64 frames_1024_1518; 200 u64 frames_1519_max; 201 202 u64 drop; 203 204 u64 ovflow0; 205 u64 ovflow1; 206 u64 ovflow2; 207 u64 ovflow3; 208 u64 trunc0; 209 u64 trunc1; 210 u64 trunc2; 211 u64 trunc3; 212 }; 213 214 struct tp_tcp_stats { 215 u32 tcp_out_rsts; 216 u64 tcp_in_segs; 217 u64 tcp_out_segs; 218 u64 tcp_retrans_segs; 219 }; 220 221 struct tp_usm_stats { 222 u32 frames; 223 u32 drops; 224 u64 octets; 225 }; 226 227 struct tp_fcoe_stats { 228 u32 frames_ddp; 229 u32 frames_drop; 230 u64 octets_ddp; 231 }; 232 233 struct tp_err_stats { 234 u32 mac_in_errs[4]; 235 u32 hdr_in_errs[4]; 236 u32 tcp_in_errs[4]; 237 u32 tnl_cong_drops[4]; 238 u32 ofld_chan_drops[4]; 239 u32 tnl_tx_drops[4]; 240 u32 ofld_vlan_drops[4]; 241 u32 tcp6_in_errs[4]; 242 u32 ofld_no_neigh; 243 u32 ofld_cong_defer; 244 }; 245 246 struct tp_cpl_stats { 247 u32 req[4]; 248 u32 rsp[4]; 249 }; 250 251 struct tp_rdma_stats { 252 u32 rqe_dfr_pkt; 253 u32 rqe_dfr_mod; 254 }; 255 256 struct sge_params { 257 u32 hps; /* host page size for our PF/VF */ 258 u32 eq_qpp; /* egress queues/page for our PF/VF */ 259 u32 iq_qpp; /* egress queues/page for our PF/VF */ 260 }; 261 262 struct tp_params { 263 unsigned int tre; /* log2 of core clocks per TP tick */ 264 unsigned int la_mask; /* what events are recorded by TP LA */ 265 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 266 /* channel map */ 267 268 uint32_t dack_re; /* DACK timer resolution */ 269 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 270 271 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 272 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 273 274 /* cached TP_OUT_CONFIG compressed error vector 275 * and passing outer header info for encapsulated packets. 276 */ 277 int rx_pkt_encap; 278 279 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 280 * subset of the set of fields which may be present in the Compressed 281 * Filter Tuple portion of filters and TCP TCB connections. The 282 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 283 * Since a variable number of fields may or may not be present, their 284 * shifted field positions within the Compressed Filter Tuple may 285 * vary, or not even be present if the field isn't selected in 286 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 287 * places we store their offsets here, or a -1 if the field isn't 288 * present. 289 */ 290 int vlan_shift; 291 int vnic_shift; 292 int port_shift; 293 int protocol_shift; 294 }; 295 296 struct vpd_params { 297 unsigned int cclk; 298 u8 ec[EC_LEN + 1]; 299 u8 sn[SERNUM_LEN + 1]; 300 u8 id[ID_LEN + 1]; 301 u8 pn[PN_LEN + 1]; 302 u8 na[MACADDR_LEN + 1]; 303 }; 304 305 struct pci_params { 306 unsigned char speed; 307 unsigned char width; 308 }; 309 310 struct devlog_params { 311 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 312 u32 start; /* start of log in firmware memory */ 313 u32 size; /* size of log */ 314 }; 315 316 /* Stores chip specific parameters */ 317 struct arch_specific_params { 318 u8 nchan; 319 u8 pm_stats_cnt; 320 u8 cng_ch_bits_log; /* congestion channel map bits width */ 321 u16 mps_rplc_size; 322 u16 vfcount; 323 u32 sge_fl_db; 324 u16 mps_tcam_size; 325 }; 326 327 struct adapter_params { 328 struct sge_params sge; 329 struct tp_params tp; 330 struct vpd_params vpd; 331 struct pci_params pci; 332 struct devlog_params devlog; 333 enum pcie_memwin drv_memwin; 334 335 unsigned int cim_la_size; 336 337 unsigned int sf_size; /* serial flash size in bytes */ 338 unsigned int sf_nsec; /* # of flash sectors */ 339 unsigned int sf_fw_start; /* start of FW image in flash */ 340 341 unsigned int fw_vers; 342 unsigned int bs_vers; /* bootstrap version */ 343 unsigned int tp_vers; 344 unsigned int er_vers; /* expansion ROM version */ 345 u8 api_vers[7]; 346 347 unsigned short mtus[NMTUS]; 348 unsigned short a_wnd[NCCTRL_WIN]; 349 unsigned short b_wnd[NCCTRL_WIN]; 350 351 unsigned char nports; /* # of ethernet ports */ 352 unsigned char portvec; 353 enum chip_type chip; /* chip code */ 354 struct arch_specific_params arch; /* chip specific params */ 355 unsigned char offload; 356 unsigned char crypto; /* HW capability for crypto */ 357 358 unsigned char bypass; 359 360 unsigned int ofldq_wr_cred; 361 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 362 363 unsigned int nsched_cls; /* number of traffic classes */ 364 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 365 unsigned int max_ird_adapter; /* Max read depth per adapter */ 366 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 367 368 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 369 * used by the Port 370 */ 371 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 372 }; 373 374 /* State needed to monitor the forward progress of SGE Ingress DMA activities 375 * and possible hangs. 376 */ 377 struct sge_idma_monitor_state { 378 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 379 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 380 unsigned int idma_state[2]; /* IDMA Hang detect state */ 381 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 382 unsigned int idma_warn[2]; /* time to warning in HZ */ 383 }; 384 385 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 386 * The access and execute times are signed in order to accommodate negative 387 * error returns. 388 */ 389 struct mbox_cmd { 390 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 391 u64 timestamp; /* OS-dependent timestamp */ 392 u32 seqno; /* sequence number */ 393 s16 access; /* time (ms) to access mailbox */ 394 s16 execute; /* time (ms) to execute */ 395 }; 396 397 struct mbox_cmd_log { 398 unsigned int size; /* number of entries in the log */ 399 unsigned int cursor; /* next position in the log to write */ 400 u32 seqno; /* next sequence number */ 401 /* variable length mailbox command log starts here */ 402 }; 403 404 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 405 * return a pointer to the specified entry. 406 */ 407 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 408 unsigned int entry_idx) 409 { 410 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 411 } 412 413 #include "t4fw_api.h" 414 415 #define FW_VERSION(chip) ( \ 416 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 417 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 418 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 419 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 420 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 421 422 struct fw_info { 423 u8 chip; 424 char *fs_name; 425 char *fw_mod_name; 426 struct fw_hdr fw_hdr; 427 }; 428 429 struct trace_params { 430 u32 data[TRACE_LEN / 4]; 431 u32 mask[TRACE_LEN / 4]; 432 unsigned short snap_len; 433 unsigned short min_len; 434 unsigned char skip_ofst; 435 unsigned char skip_len; 436 unsigned char invert; 437 unsigned char port; 438 }; 439 440 struct link_config { 441 unsigned short supported; /* link capabilities */ 442 unsigned short advertising; /* advertised capabilities */ 443 unsigned short lp_advertising; /* peer advertised capabilities */ 444 unsigned int requested_speed; /* speed user has requested */ 445 unsigned int speed; /* actual link speed */ 446 unsigned char requested_fc; /* flow control user has requested */ 447 unsigned char fc; /* actual link flow control */ 448 unsigned char auto_fec; /* Forward Error Correction: */ 449 unsigned char requested_fec; /* "automatic" (IEEE 802.3), */ 450 unsigned char fec; /* requested, and actual in use */ 451 unsigned char autoneg; /* autonegotiating? */ 452 unsigned char link_ok; /* link up? */ 453 unsigned char link_down_rc; /* link down reason */ 454 }; 455 456 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 457 458 enum { 459 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 460 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 461 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 462 }; 463 464 enum { 465 MAX_TXQ_ENTRIES = 16384, 466 MAX_CTRL_TXQ_ENTRIES = 1024, 467 MAX_RSPQ_ENTRIES = 16384, 468 MAX_RX_BUFFERS = 16384, 469 MIN_TXQ_ENTRIES = 32, 470 MIN_CTRL_TXQ_ENTRIES = 32, 471 MIN_RSPQ_ENTRIES = 128, 472 MIN_FL_ENTRIES = 16 473 }; 474 475 enum { 476 INGQ_EXTRAS = 2, /* firmware event queue and */ 477 /* forwarded interrupts */ 478 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 479 }; 480 481 struct adapter; 482 struct sge_rspq; 483 484 #include "cxgb4_dcb.h" 485 486 #ifdef CONFIG_CHELSIO_T4_FCOE 487 #include "cxgb4_fcoe.h" 488 #endif /* CONFIG_CHELSIO_T4_FCOE */ 489 490 struct port_info { 491 struct adapter *adapter; 492 u16 viid; 493 s16 xact_addr_filt; /* index of exact MAC address filter */ 494 u16 rss_size; /* size of VI's RSS table slice */ 495 s8 mdio_addr; 496 enum fw_port_type port_type; 497 u8 mod_type; 498 u8 port_id; 499 u8 tx_chan; 500 u8 lport; /* associated offload logical port */ 501 u8 nqsets; /* # of qsets */ 502 u8 first_qset; /* index of first qset */ 503 u8 rss_mode; 504 struct link_config link_cfg; 505 u16 *rss; 506 struct port_stats stats_base; 507 #ifdef CONFIG_CHELSIO_T4_DCB 508 struct port_dcb_info dcb; /* Data Center Bridging support */ 509 #endif 510 #ifdef CONFIG_CHELSIO_T4_FCOE 511 struct cxgb_fcoe fcoe; 512 #endif /* CONFIG_CHELSIO_T4_FCOE */ 513 bool rxtstamp; /* Enable TS */ 514 struct hwtstamp_config tstamp_config; 515 bool ptp_enable; 516 struct sched_table *sched_tbl; 517 }; 518 519 struct dentry; 520 struct work_struct; 521 522 enum { /* adapter flags */ 523 FULL_INIT_DONE = (1 << 0), 524 DEV_ENABLED = (1 << 1), 525 USING_MSI = (1 << 2), 526 USING_MSIX = (1 << 3), 527 FW_OK = (1 << 4), 528 RSS_TNLALLLOOKUP = (1 << 5), 529 USING_SOFT_PARAMS = (1 << 6), 530 MASTER_PF = (1 << 7), 531 FW_OFLD_CONN = (1 << 9), 532 ROOT_NO_RELAXED_ORDERING = (1 << 10), 533 }; 534 535 enum { 536 ULP_CRYPTO_LOOKASIDE = 1 << 0, 537 }; 538 539 struct rx_sw_desc; 540 541 struct sge_fl { /* SGE free-buffer queue state */ 542 unsigned int avail; /* # of available Rx buffers */ 543 unsigned int pend_cred; /* new buffers since last FL DB ring */ 544 unsigned int cidx; /* consumer index */ 545 unsigned int pidx; /* producer index */ 546 unsigned long alloc_failed; /* # of times buffer allocation failed */ 547 unsigned long large_alloc_failed; 548 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 549 unsigned long low; /* # of times momentarily starving */ 550 unsigned long starving; 551 /* RO fields */ 552 unsigned int cntxt_id; /* SGE context id for the free list */ 553 unsigned int size; /* capacity of free list */ 554 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 555 __be64 *desc; /* address of HW Rx descriptor ring */ 556 dma_addr_t addr; /* bus address of HW ring start */ 557 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 558 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 559 }; 560 561 /* A packet gather list */ 562 struct pkt_gl { 563 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 564 struct page_frag frags[MAX_SKB_FRAGS]; 565 void *va; /* virtual address of first byte */ 566 unsigned int nfrags; /* # of fragments */ 567 unsigned int tot_len; /* total length of fragments */ 568 }; 569 570 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 571 const struct pkt_gl *gl); 572 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 573 /* LRO related declarations for ULD */ 574 struct t4_lro_mgr { 575 #define MAX_LRO_SESSIONS 64 576 u8 lro_session_cnt; /* # of sessions to aggregate */ 577 unsigned long lro_pkts; /* # of LRO super packets */ 578 unsigned long lro_merged; /* # of wire packets merged by LRO */ 579 struct sk_buff_head lroq; /* list of aggregated sessions */ 580 }; 581 582 struct sge_rspq { /* state for an SGE response queue */ 583 struct napi_struct napi; 584 const __be64 *cur_desc; /* current descriptor in queue */ 585 unsigned int cidx; /* consumer index */ 586 u8 gen; /* current generation bit */ 587 u8 intr_params; /* interrupt holdoff parameters */ 588 u8 next_intr_params; /* holdoff params for next interrupt */ 589 u8 adaptive_rx; 590 u8 pktcnt_idx; /* interrupt packet threshold */ 591 u8 uld; /* ULD handling this queue */ 592 u8 idx; /* queue index within its group */ 593 int offset; /* offset into current Rx buffer */ 594 u16 cntxt_id; /* SGE context id for the response q */ 595 u16 abs_id; /* absolute SGE id for the response q */ 596 __be64 *desc; /* address of HW response ring */ 597 dma_addr_t phys_addr; /* physical address of the ring */ 598 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 599 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 600 unsigned int iqe_len; /* entry size */ 601 unsigned int size; /* capacity of response queue */ 602 struct adapter *adap; 603 struct net_device *netdev; /* associated net device */ 604 rspq_handler_t handler; 605 rspq_flush_handler_t flush_handler; 606 struct t4_lro_mgr lro_mgr; 607 }; 608 609 struct sge_eth_stats { /* Ethernet queue statistics */ 610 unsigned long pkts; /* # of ethernet packets */ 611 unsigned long lro_pkts; /* # of LRO super packets */ 612 unsigned long lro_merged; /* # of wire packets merged by LRO */ 613 unsigned long rx_cso; /* # of Rx checksum offloads */ 614 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 615 unsigned long rx_drops; /* # of packets dropped due to no mem */ 616 }; 617 618 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 619 struct sge_rspq rspq; 620 struct sge_fl fl; 621 struct sge_eth_stats stats; 622 } ____cacheline_aligned_in_smp; 623 624 struct sge_ofld_stats { /* offload queue statistics */ 625 unsigned long pkts; /* # of packets */ 626 unsigned long imm; /* # of immediate-data packets */ 627 unsigned long an; /* # of asynchronous notifications */ 628 unsigned long nomem; /* # of responses deferred due to no mem */ 629 }; 630 631 struct sge_ofld_rxq { /* SW offload Rx queue */ 632 struct sge_rspq rspq; 633 struct sge_fl fl; 634 struct sge_ofld_stats stats; 635 } ____cacheline_aligned_in_smp; 636 637 struct tx_desc { 638 __be64 flit[8]; 639 }; 640 641 struct tx_sw_desc; 642 643 struct sge_txq { 644 unsigned int in_use; /* # of in-use Tx descriptors */ 645 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 646 unsigned int size; /* # of descriptors */ 647 unsigned int cidx; /* SW consumer index */ 648 unsigned int pidx; /* producer index */ 649 unsigned long stops; /* # of times q has been stopped */ 650 unsigned long restarts; /* # of queue restarts */ 651 unsigned int cntxt_id; /* SGE context id for the Tx q */ 652 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 653 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 654 struct sge_qstat *stat; /* queue status entry */ 655 dma_addr_t phys_addr; /* physical address of the ring */ 656 spinlock_t db_lock; 657 int db_disabled; 658 unsigned short db_pidx; 659 unsigned short db_pidx_inc; 660 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 661 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 662 }; 663 664 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 665 struct sge_txq q; 666 struct netdev_queue *txq; /* associated netdev TX queue */ 667 #ifdef CONFIG_CHELSIO_T4_DCB 668 u8 dcb_prio; /* DCB Priority bound to queue */ 669 #endif 670 unsigned long tso; /* # of TSO requests */ 671 unsigned long tx_cso; /* # of Tx checksum offloads */ 672 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 673 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 674 } ____cacheline_aligned_in_smp; 675 676 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 677 struct sge_txq q; 678 struct adapter *adap; 679 struct sk_buff_head sendq; /* list of backpressured packets */ 680 struct tasklet_struct qresume_tsk; /* restarts the queue */ 681 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 682 u8 full; /* the Tx ring is full */ 683 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 684 } ____cacheline_aligned_in_smp; 685 686 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 687 struct sge_txq q; 688 struct adapter *adap; 689 struct sk_buff_head sendq; /* list of backpressured packets */ 690 struct tasklet_struct qresume_tsk; /* restarts the queue */ 691 u8 full; /* the Tx ring is full */ 692 } ____cacheline_aligned_in_smp; 693 694 struct sge_uld_rxq_info { 695 char name[IFNAMSIZ]; /* name of ULD driver */ 696 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 697 u16 *msix_tbl; /* msix_tbl for uld */ 698 u16 *rspq_id; /* response queue id's of rxq */ 699 u16 nrxq; /* # of ingress uld queues */ 700 u16 nciq; /* # of completion queues */ 701 u8 uld; /* uld type */ 702 }; 703 704 struct sge_uld_txq_info { 705 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 706 atomic_t users; /* num users */ 707 u16 ntxq; /* # of egress uld queues */ 708 }; 709 710 struct sge { 711 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 712 struct sge_eth_txq ptptxq; 713 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 714 715 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 716 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 717 struct sge_uld_rxq_info **uld_rxq_info; 718 struct sge_uld_txq_info **uld_txq_info; 719 720 struct sge_rspq intrq ____cacheline_aligned_in_smp; 721 spinlock_t intrq_lock; 722 723 u16 max_ethqsets; /* # of available Ethernet queue sets */ 724 u16 ethqsets; /* # of active Ethernet queue sets */ 725 u16 ethtxq_rover; /* Tx queue to clean up next */ 726 u16 ofldqsets; /* # of active ofld queue sets */ 727 u16 nqs_per_uld; /* # of Rx queues per ULD */ 728 u16 timer_val[SGE_NTIMERS]; 729 u8 counter_val[SGE_NCOUNTERS]; 730 u32 fl_pg_order; /* large page allocation size */ 731 u32 stat_len; /* length of status page at ring end */ 732 u32 pktshift; /* padding between CPL & packet data */ 733 u32 fl_align; /* response queue message alignment */ 734 u32 fl_starve_thres; /* Free List starvation threshold */ 735 736 struct sge_idma_monitor_state idma_monitor; 737 unsigned int egr_start; 738 unsigned int egr_sz; 739 unsigned int ingr_start; 740 unsigned int ingr_sz; 741 void **egr_map; /* qid->queue egress queue map */ 742 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 743 unsigned long *starving_fl; 744 unsigned long *txq_maperr; 745 unsigned long *blocked_fl; 746 struct timer_list rx_timer; /* refills starving FLs */ 747 struct timer_list tx_timer; /* checks Tx queues */ 748 }; 749 750 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 751 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 752 753 struct l2t_data; 754 755 #ifdef CONFIG_PCI_IOV 756 757 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 758 * Configuration initialization for T5 only has SR-IOV functionality enabled 759 * on PF0-3 in order to simplify everything. 760 */ 761 #define NUM_OF_PF_WITH_SRIOV 4 762 763 #endif 764 765 struct doorbell_stats { 766 u32 db_drop; 767 u32 db_empty; 768 u32 db_full; 769 }; 770 771 struct hash_mac_addr { 772 struct list_head list; 773 u8 addr[ETH_ALEN]; 774 }; 775 776 struct uld_msix_bmap { 777 unsigned long *msix_bmap; 778 unsigned int mapsize; 779 spinlock_t lock; /* lock for acquiring bitmap */ 780 }; 781 782 struct uld_msix_info { 783 unsigned short vec; 784 char desc[IFNAMSIZ + 10]; 785 unsigned int idx; 786 }; 787 788 struct vf_info { 789 unsigned char vf_mac_addr[ETH_ALEN]; 790 unsigned int tx_rate; 791 bool pf_set_mac; 792 }; 793 794 struct mbox_list { 795 struct list_head list; 796 }; 797 798 struct adapter { 799 void __iomem *regs; 800 void __iomem *bar2; 801 u32 t4_bar0; 802 struct pci_dev *pdev; 803 struct device *pdev_dev; 804 const char *name; 805 unsigned int mbox; 806 unsigned int pf; 807 unsigned int flags; 808 unsigned int adap_idx; 809 enum chip_type chip; 810 811 int msg_enable; 812 813 struct adapter_params params; 814 struct cxgb4_virt_res vres; 815 unsigned int swintr; 816 817 struct { 818 unsigned short vec; 819 char desc[IFNAMSIZ + 10]; 820 } msix_info[MAX_INGQ + 1]; 821 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 822 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 823 int msi_idx; 824 825 struct doorbell_stats db_stats; 826 struct sge sge; 827 828 struct net_device *port[MAX_NPORTS]; 829 u8 chan_map[NCHAN]; /* channel -> port map */ 830 831 struct vf_info *vfinfo; 832 u8 num_vfs; 833 834 u32 filter_mode; 835 unsigned int l2t_start; 836 unsigned int l2t_end; 837 struct l2t_data *l2t; 838 unsigned int clipt_start; 839 unsigned int clipt_end; 840 struct clip_tbl *clipt; 841 struct cxgb4_uld_info *uld; 842 void *uld_handle[CXGB4_ULD_MAX]; 843 unsigned int num_uld; 844 unsigned int num_ofld_uld; 845 struct list_head list_node; 846 struct list_head rcu_node; 847 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 848 849 void *iscsi_ppm; 850 851 struct tid_info tids; 852 void **tid_release_head; 853 spinlock_t tid_release_lock; 854 struct workqueue_struct *workq; 855 struct work_struct tid_release_task; 856 struct work_struct db_full_task; 857 struct work_struct db_drop_task; 858 bool tid_release_task_busy; 859 860 /* lock for mailbox cmd list */ 861 spinlock_t mbox_lock; 862 struct mbox_list mlist; 863 864 /* support for mailbox command/reply logging */ 865 #define T4_OS_LOG_MBOX_CMDS 256 866 struct mbox_cmd_log *mbox_log; 867 868 struct mutex uld_mutex; 869 870 struct dentry *debugfs_root; 871 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 872 bool trace_rss; /* 1 implies that different RSS flit per filter is 873 * used per filter else if 0 default RSS flit is 874 * used for all 4 filters. 875 */ 876 877 struct ptp_clock *ptp_clock; 878 struct ptp_clock_info ptp_clock_info; 879 struct sk_buff *ptp_tx_skb; 880 /* ptp lock */ 881 spinlock_t ptp_lock; 882 spinlock_t stats_lock; 883 spinlock_t win0_lock ____cacheline_aligned_in_smp; 884 885 /* TC u32 offload */ 886 struct cxgb4_tc_u32_table *tc_u32; 887 struct chcr_stats_debug chcr_stats; 888 }; 889 890 /* Support for "sched-class" command to allow a TX Scheduling Class to be 891 * programmed with various parameters. 892 */ 893 struct ch_sched_params { 894 s8 type; /* packet or flow */ 895 union { 896 struct { 897 s8 level; /* scheduler hierarchy level */ 898 s8 mode; /* per-class or per-flow */ 899 s8 rateunit; /* bit or packet rate */ 900 s8 ratemode; /* %port relative or kbps absolute */ 901 s8 channel; /* scheduler channel [0..N] */ 902 s8 class; /* scheduler class [0..N] */ 903 s32 minrate; /* minimum rate */ 904 s32 maxrate; /* maximum rate */ 905 s16 weight; /* percent weight */ 906 s16 pktsize; /* average packet size */ 907 } params; 908 } u; 909 }; 910 911 enum { 912 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 913 }; 914 915 enum { 916 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 917 }; 918 919 enum { 920 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 921 }; 922 923 enum { 924 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 925 }; 926 927 enum { 928 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 929 }; 930 931 /* Support for "sched_queue" command to allow one or more NIC TX Queues 932 * to be bound to a TX Scheduling Class. 933 */ 934 struct ch_sched_queue { 935 s8 queue; /* queue index */ 936 s8 class; /* class index */ 937 }; 938 939 /* Defined bit width of user definable filter tuples 940 */ 941 #define ETHTYPE_BITWIDTH 16 942 #define FRAG_BITWIDTH 1 943 #define MACIDX_BITWIDTH 9 944 #define FCOE_BITWIDTH 1 945 #define IPORT_BITWIDTH 3 946 #define MATCHTYPE_BITWIDTH 3 947 #define PROTO_BITWIDTH 8 948 #define TOS_BITWIDTH 8 949 #define PF_BITWIDTH 8 950 #define VF_BITWIDTH 8 951 #define IVLAN_BITWIDTH 16 952 #define OVLAN_BITWIDTH 16 953 954 /* Filter matching rules. These consist of a set of ingress packet field 955 * (value, mask) tuples. The associated ingress packet field matches the 956 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 957 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 958 * matches an ingress packet when all of the individual individual field 959 * matching rules are true. 960 * 961 * Partial field masks are always valid, however, while it may be easy to 962 * understand their meanings for some fields (e.g. IP address to match a 963 * subnet), for others making sensible partial masks is less intuitive (e.g. 964 * MPS match type) ... 965 * 966 * Most of the following data structures are modeled on T4 capabilities. 967 * Drivers for earlier chips use the subsets which make sense for those chips. 968 * We really need to come up with a hardware-independent mechanism to 969 * represent hardware filter capabilities ... 970 */ 971 struct ch_filter_tuple { 972 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 973 * register selects which of these fields will participate in the 974 * filter match rules -- up to a maximum of 36 bits. Because 975 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 976 * set of fields. 977 */ 978 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 979 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 980 uint32_t ivlan_vld:1; /* inner VLAN valid */ 981 uint32_t ovlan_vld:1; /* outer VLAN valid */ 982 uint32_t pfvf_vld:1; /* PF/VF valid */ 983 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 984 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 985 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 986 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 987 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 988 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 989 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 990 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 991 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 992 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 993 994 /* Uncompressed header matching field rules. These are always 995 * available for field rules. 996 */ 997 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 998 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 999 uint16_t lport; /* local port */ 1000 uint16_t fport; /* foreign port */ 1001 }; 1002 1003 /* A filter ioctl command. 1004 */ 1005 struct ch_filter_specification { 1006 /* Administrative fields for filter. 1007 */ 1008 uint32_t hitcnts:1; /* count filter hits in TCB */ 1009 uint32_t prio:1; /* filter has priority over active/server */ 1010 1011 /* Fundamental filter typing. This is the one element of filter 1012 * matching that doesn't exist as a (value, mask) tuple. 1013 */ 1014 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1015 1016 /* Packet dispatch information. Ingress packets which match the 1017 * filter rules will be dropped, passed to the host or switched back 1018 * out as egress packets. 1019 */ 1020 uint32_t action:2; /* drop, pass, switch */ 1021 1022 uint32_t rpttid:1; /* report TID in RSS hash field */ 1023 1024 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1025 uint32_t iq:10; /* ingress queue */ 1026 1027 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1028 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1029 /* 1 => TCB contains IQ ID */ 1030 1031 /* Switch proxy/rewrite fields. An ingress packet which matches a 1032 * filter with "switch" set will be looped back out as an egress 1033 * packet -- potentially with some Ethernet header rewriting. 1034 */ 1035 uint32_t eport:2; /* egress port to switch packet out */ 1036 uint32_t newdmac:1; /* rewrite destination MAC address */ 1037 uint32_t newsmac:1; /* rewrite source MAC address */ 1038 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1039 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1040 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1041 uint16_t vlan; /* VLAN Tag to insert */ 1042 1043 /* Filter rule value/mask pairs. 1044 */ 1045 struct ch_filter_tuple val; 1046 struct ch_filter_tuple mask; 1047 }; 1048 1049 enum { 1050 FILTER_PASS = 0, /* default */ 1051 FILTER_DROP, 1052 FILTER_SWITCH 1053 }; 1054 1055 enum { 1056 VLAN_NOCHANGE = 0, /* default */ 1057 VLAN_REMOVE, 1058 VLAN_INSERT, 1059 VLAN_REWRITE 1060 }; 1061 1062 /* Host shadow copy of ingress filter entry. This is in host native format 1063 * and doesn't match the ordering or bit order, etc. of the hardware of the 1064 * firmware command. The use of bit-field structure elements is purely to 1065 * remind ourselves of the field size limitations and save memory in the case 1066 * where the filter table is large. 1067 */ 1068 struct filter_entry { 1069 /* Administrative fields for filter. */ 1070 u32 valid:1; /* filter allocated and valid */ 1071 u32 locked:1; /* filter is administratively locked */ 1072 1073 u32 pending:1; /* filter action is pending firmware reply */ 1074 u32 smtidx:8; /* Source MAC Table index for smac */ 1075 struct filter_ctx *ctx; /* Caller's completion hook */ 1076 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1077 struct net_device *dev; /* Associated net device */ 1078 u32 tid; /* This will store the actual tid */ 1079 1080 /* The filter itself. Most of this is a straight copy of information 1081 * provided by the extended ioctl(). Some fields are translated to 1082 * internal forms -- for instance the Ingress Queue ID passed in from 1083 * the ioctl() is translated into the Absolute Ingress Queue ID. 1084 */ 1085 struct ch_filter_specification fs; 1086 }; 1087 1088 static inline int is_offload(const struct adapter *adap) 1089 { 1090 return adap->params.offload; 1091 } 1092 1093 static inline int is_pci_uld(const struct adapter *adap) 1094 { 1095 return adap->params.crypto; 1096 } 1097 1098 static inline int is_uld(const struct adapter *adap) 1099 { 1100 return (adap->params.offload || adap->params.crypto); 1101 } 1102 1103 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1104 { 1105 return readl(adap->regs + reg_addr); 1106 } 1107 1108 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1109 { 1110 writel(val, adap->regs + reg_addr); 1111 } 1112 1113 #ifndef readq 1114 static inline u64 readq(const volatile void __iomem *addr) 1115 { 1116 return readl(addr) + ((u64)readl(addr + 4) << 32); 1117 } 1118 1119 static inline void writeq(u64 val, volatile void __iomem *addr) 1120 { 1121 writel(val, addr); 1122 writel(val >> 32, addr + 4); 1123 } 1124 #endif 1125 1126 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1127 { 1128 return readq(adap->regs + reg_addr); 1129 } 1130 1131 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1132 { 1133 writeq(val, adap->regs + reg_addr); 1134 } 1135 1136 /** 1137 * t4_set_hw_addr - store a port's MAC address in SW 1138 * @adapter: the adapter 1139 * @port_idx: the port index 1140 * @hw_addr: the Ethernet address 1141 * 1142 * Store the Ethernet address of the given port in SW. Called by the common 1143 * code when it retrieves a port's Ethernet address from EEPROM. 1144 */ 1145 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1146 u8 hw_addr[]) 1147 { 1148 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1149 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1150 } 1151 1152 /** 1153 * netdev2pinfo - return the port_info structure associated with a net_device 1154 * @dev: the netdev 1155 * 1156 * Return the struct port_info associated with a net_device 1157 */ 1158 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1159 { 1160 return netdev_priv(dev); 1161 } 1162 1163 /** 1164 * adap2pinfo - return the port_info of a port 1165 * @adap: the adapter 1166 * @idx: the port index 1167 * 1168 * Return the port_info structure for the port of the given index. 1169 */ 1170 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1171 { 1172 return netdev_priv(adap->port[idx]); 1173 } 1174 1175 /** 1176 * netdev2adap - return the adapter structure associated with a net_device 1177 * @dev: the netdev 1178 * 1179 * Return the struct adapter associated with a net_device 1180 */ 1181 static inline struct adapter *netdev2adap(const struct net_device *dev) 1182 { 1183 return netdev2pinfo(dev)->adapter; 1184 } 1185 1186 /* Return a version number to identify the type of adapter. The scheme is: 1187 * - bits 0..9: chip version 1188 * - bits 10..15: chip revision 1189 * - bits 16..23: register dump version 1190 */ 1191 static inline unsigned int mk_adap_vers(struct adapter *ap) 1192 { 1193 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1194 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1195 } 1196 1197 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1198 static inline unsigned int qtimer_val(const struct adapter *adap, 1199 const struct sge_rspq *q) 1200 { 1201 unsigned int idx = q->intr_params >> 1; 1202 1203 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1204 } 1205 1206 /* driver version & name used for ethtool_drvinfo */ 1207 extern char cxgb4_driver_name[]; 1208 extern const char cxgb4_driver_version[]; 1209 1210 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1211 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1212 1213 void t4_free_sge_resources(struct adapter *adap); 1214 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1215 irq_handler_t t4_intr_handler(struct adapter *adap); 1216 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1217 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1218 const struct pkt_gl *gl); 1219 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1220 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1221 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1222 struct net_device *dev, int intr_idx, 1223 struct sge_fl *fl, rspq_handler_t hnd, 1224 rspq_flush_handler_t flush_handler, int cong); 1225 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1226 struct net_device *dev, struct netdev_queue *netdevq, 1227 unsigned int iqid); 1228 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1229 struct net_device *dev, unsigned int iqid, 1230 unsigned int cmplqid); 1231 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1232 unsigned int cmplqid); 1233 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1234 struct net_device *dev, unsigned int iqid, 1235 unsigned int uld_type); 1236 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1237 int t4_sge_init(struct adapter *adap); 1238 void t4_sge_start(struct adapter *adap); 1239 void t4_sge_stop(struct adapter *adap); 1240 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1241 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1242 extern int dbfifo_int_thresh; 1243 1244 #define for_each_port(adapter, iter) \ 1245 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1246 1247 static inline int is_bypass(struct adapter *adap) 1248 { 1249 return adap->params.bypass; 1250 } 1251 1252 static inline int is_bypass_device(int device) 1253 { 1254 /* this should be set based upon device capabilities */ 1255 switch (device) { 1256 case 0x440b: 1257 case 0x440c: 1258 return 1; 1259 default: 1260 return 0; 1261 } 1262 } 1263 1264 static inline int is_10gbt_device(int device) 1265 { 1266 /* this should be set based upon device capabilities */ 1267 switch (device) { 1268 case 0x4409: 1269 case 0x4486: 1270 return 1; 1271 1272 default: 1273 return 0; 1274 } 1275 } 1276 1277 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1278 { 1279 return adap->params.vpd.cclk / 1000; 1280 } 1281 1282 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1283 unsigned int us) 1284 { 1285 return (us * adap->params.vpd.cclk) / 1000; 1286 } 1287 1288 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1289 unsigned int ticks) 1290 { 1291 /* add Core Clock / 2 to round ticks to nearest uS */ 1292 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1293 adapter->params.vpd.cclk); 1294 } 1295 1296 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1297 u32 val); 1298 1299 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1300 int size, void *rpl, bool sleep_ok, int timeout); 1301 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1302 void *rpl, bool sleep_ok); 1303 1304 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1305 const void *cmd, int size, void *rpl, 1306 int timeout) 1307 { 1308 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1309 timeout); 1310 } 1311 1312 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1313 int size, void *rpl) 1314 { 1315 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1316 } 1317 1318 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1319 int size, void *rpl) 1320 { 1321 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1322 } 1323 1324 /** 1325 * hash_mac_addr - return the hash value of a MAC address 1326 * @addr: the 48-bit Ethernet MAC address 1327 * 1328 * Hashes a MAC address according to the hash function used by HW inexact 1329 * (hash) address matching. 1330 */ 1331 static inline int hash_mac_addr(const u8 *addr) 1332 { 1333 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1334 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1335 1336 a ^= b; 1337 a ^= (a >> 12); 1338 a ^= (a >> 6); 1339 return a & 0x3f; 1340 } 1341 1342 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1343 unsigned int cnt); 1344 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1345 unsigned int us, unsigned int cnt, 1346 unsigned int size, unsigned int iqe_size) 1347 { 1348 q->adap = adap; 1349 cxgb4_set_rspq_intr_params(q, us, cnt); 1350 q->iqe_len = iqe_size; 1351 q->size = size; 1352 } 1353 1354 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1355 unsigned int data_reg, const u32 *vals, 1356 unsigned int nregs, unsigned int start_idx); 1357 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1358 unsigned int data_reg, u32 *vals, unsigned int nregs, 1359 unsigned int start_idx); 1360 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1361 1362 struct fw_filter_wr; 1363 1364 void t4_intr_enable(struct adapter *adapter); 1365 void t4_intr_disable(struct adapter *adapter); 1366 int t4_slow_intr_handler(struct adapter *adapter); 1367 1368 int t4_wait_dev_ready(void __iomem *regs); 1369 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1370 struct link_config *lc); 1371 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1372 1373 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1374 u32 t4_get_util_window(struct adapter *adap); 1375 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1376 1377 #define T4_MEMORY_WRITE 0 1378 #define T4_MEMORY_READ 1 1379 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1380 void *buf, int dir); 1381 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1382 u32 len, __be32 *buf) 1383 { 1384 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1385 } 1386 1387 unsigned int t4_get_regs_len(struct adapter *adapter); 1388 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1389 1390 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1391 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1392 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1393 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1394 unsigned int nwords, u32 *data, int byte_oriented); 1395 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1396 int t4_load_phy_fw(struct adapter *adap, 1397 int win, spinlock_t *lock, 1398 int (*phy_fw_version)(const u8 *, size_t), 1399 const u8 *phy_fw_data, size_t phy_fw_size); 1400 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1401 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1402 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1403 const u8 *fw_data, unsigned int size, int force); 1404 int t4_fl_pkt_align(struct adapter *adap); 1405 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1406 int t4_check_fw_version(struct adapter *adap); 1407 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1408 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1409 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1410 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1411 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1412 const u8 *fw_data, unsigned int fw_size, 1413 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1414 int t4_prep_adapter(struct adapter *adapter); 1415 int t4_shutdown_adapter(struct adapter *adapter); 1416 1417 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1418 int t4_bar2_sge_qregs(struct adapter *adapter, 1419 unsigned int qid, 1420 enum t4_bar2_qtype qtype, 1421 int user, 1422 u64 *pbar2_qoffset, 1423 unsigned int *pbar2_qid); 1424 1425 unsigned int qtimer_val(const struct adapter *adap, 1426 const struct sge_rspq *q); 1427 1428 int t4_init_devlog_params(struct adapter *adapter); 1429 int t4_init_sge_params(struct adapter *adapter); 1430 int t4_init_tp_params(struct adapter *adap); 1431 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1432 int t4_init_rss_mode(struct adapter *adap, int mbox); 1433 int t4_init_portinfo(struct port_info *pi, int mbox, 1434 int port, int pf, int vf, u8 mac[]); 1435 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1436 void t4_fatal_err(struct adapter *adapter); 1437 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1438 int start, int n, const u16 *rspq, unsigned int nrspq); 1439 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1440 unsigned int flags); 1441 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1442 unsigned int flags, unsigned int defq); 1443 int t4_read_rss(struct adapter *adapter, u16 *entries); 1444 void t4_read_rss_key(struct adapter *adapter, u32 *key); 1445 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1446 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1447 u32 *valp); 1448 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1449 u32 *vfl, u32 *vfh); 1450 u32 t4_read_rss_pf_map(struct adapter *adapter); 1451 u32 t4_read_rss_pf_mask(struct adapter *adapter); 1452 1453 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1454 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1455 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1456 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1457 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1458 size_t n); 1459 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1460 size_t n); 1461 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1462 unsigned int *valp); 1463 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1464 const unsigned int *valp); 1465 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1466 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1467 unsigned int *pif_req_wrptr, 1468 unsigned int *pif_rsp_wrptr); 1469 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1470 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1471 const char *t4_get_port_type_description(enum fw_port_type port_type); 1472 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1473 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1474 struct port_stats *stats, 1475 struct port_stats *offset); 1476 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1477 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1478 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1479 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1480 unsigned int mask, unsigned int val); 1481 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1482 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1483 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1484 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1485 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1486 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1487 struct tp_tcp_stats *v6); 1488 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1489 struct tp_fcoe_stats *st); 1490 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1491 const unsigned short *alpha, const unsigned short *beta); 1492 1493 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1494 1495 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1496 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1497 1498 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1499 const u8 *addr); 1500 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1501 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1502 1503 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1504 enum dev_master master, enum dev_state *state); 1505 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1506 int t4_early_init(struct adapter *adap, unsigned int mbox); 1507 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1508 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1509 unsigned int cache_line_size); 1510 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1511 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1512 unsigned int vf, unsigned int nparams, const u32 *params, 1513 u32 *val); 1514 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1515 unsigned int vf, unsigned int nparams, const u32 *params, 1516 u32 *val); 1517 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1518 unsigned int vf, unsigned int nparams, const u32 *params, 1519 u32 *val, int rw, bool sleep_ok); 1520 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1521 unsigned int pf, unsigned int vf, 1522 unsigned int nparams, const u32 *params, 1523 const u32 *val, int timeout); 1524 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1525 unsigned int vf, unsigned int nparams, const u32 *params, 1526 const u32 *val); 1527 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1528 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1529 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1530 unsigned int vi, unsigned int cmask, unsigned int pmask, 1531 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1532 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1533 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1534 unsigned int *rss_size); 1535 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1536 unsigned int pf, unsigned int vf, 1537 unsigned int viid); 1538 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1539 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1540 bool sleep_ok); 1541 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1542 unsigned int viid, bool free, unsigned int naddr, 1543 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1544 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1545 unsigned int viid, unsigned int naddr, 1546 const u8 **addr, bool sleep_ok); 1547 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1548 int idx, const u8 *addr, bool persist, bool add_smt); 1549 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1550 bool ucast, u64 vec, bool sleep_ok); 1551 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1552 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1553 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1554 bool rx_en, bool tx_en); 1555 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1556 unsigned int nblinks); 1557 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1558 unsigned int mmd, unsigned int reg, u16 *valp); 1559 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1560 unsigned int mmd, unsigned int reg, u16 val); 1561 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1562 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1563 unsigned int fl0id, unsigned int fl1id); 1564 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1565 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1566 unsigned int fl0id, unsigned int fl1id); 1567 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1568 unsigned int vf, unsigned int eqid); 1569 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1570 unsigned int vf, unsigned int eqid); 1571 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1572 unsigned int vf, unsigned int eqid); 1573 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1574 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1575 int t4_update_port_info(struct port_info *pi); 1576 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1577 void t4_db_full(struct adapter *adapter); 1578 void t4_db_dropped(struct adapter *adapter); 1579 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1580 int filter_index, int enable); 1581 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1582 int filter_index, int *enabled); 1583 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1584 u32 addr, u32 val); 1585 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1586 int rateunit, int ratemode, int channel, int class, 1587 int minrate, int maxrate, int weight, int pktsize); 1588 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1589 void t4_idma_monitor_init(struct adapter *adapter, 1590 struct sge_idma_monitor_state *idma); 1591 void t4_idma_monitor(struct adapter *adapter, 1592 struct sge_idma_monitor_state *idma, 1593 int hz, int ticks); 1594 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1595 unsigned int naddr, u8 *addr); 1596 void t4_uld_mem_free(struct adapter *adap); 1597 int t4_uld_mem_alloc(struct adapter *adap); 1598 void t4_uld_clean_up(struct adapter *adap); 1599 void t4_register_netevent_notifier(void); 1600 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1601 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1602 unsigned int n, bool unmap); 1603 void free_txq(struct adapter *adap, struct sge_txq *q); 1604 #endif /* __CXGB4_H__ */ 1605