1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <linux/ptp_clock_kernel.h> 52 #include <linux/ptp_classify.h> 53 #include <linux/crash_dump.h> 54 #include <asm/io.h> 55 #include "t4_chip_type.h" 56 #include "cxgb4_uld.h" 57 58 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 59 extern struct list_head adapter_list; 60 extern struct mutex uld_mutex; 61 62 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 63 * This is the same as calc_tx_descs() for a TSO packet with 64 * nr_frags == MAX_SKB_FRAGS. 65 */ 66 #define ETHTXQ_STOP_THRES \ 67 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 68 69 enum { 70 MAX_NPORTS = 4, /* max # of ports */ 71 SERNUM_LEN = 24, /* Serial # length */ 72 EC_LEN = 16, /* E/C length */ 73 ID_LEN = 16, /* ID length */ 74 PN_LEN = 16, /* Part Number length */ 75 MACADDR_LEN = 12, /* MAC Address length */ 76 }; 77 78 enum { 79 T4_REGMAP_SIZE = (160 * 1024), 80 T5_REGMAP_SIZE = (332 * 1024), 81 }; 82 83 enum { 84 MEM_EDC0, 85 MEM_EDC1, 86 MEM_MC, 87 MEM_MC0 = MEM_MC, 88 MEM_MC1, 89 MEM_HMA, 90 }; 91 92 enum { 93 MEMWIN0_APERTURE = 2048, 94 MEMWIN0_BASE = 0x1b800, 95 MEMWIN1_APERTURE = 32768, 96 MEMWIN1_BASE = 0x28000, 97 MEMWIN1_BASE_T5 = 0x52000, 98 MEMWIN2_APERTURE = 65536, 99 MEMWIN2_BASE = 0x30000, 100 MEMWIN2_APERTURE_T5 = 131072, 101 MEMWIN2_BASE_T5 = 0x60000, 102 }; 103 104 enum dev_master { 105 MASTER_CANT, 106 MASTER_MAY, 107 MASTER_MUST 108 }; 109 110 enum dev_state { 111 DEV_STATE_UNINIT, 112 DEV_STATE_INIT, 113 DEV_STATE_ERR 114 }; 115 116 enum cc_pause { 117 PAUSE_RX = 1 << 0, 118 PAUSE_TX = 1 << 1, 119 PAUSE_AUTONEG = 1 << 2 120 }; 121 122 enum cc_fec { 123 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 124 FEC_RS = 1 << 1, /* Reed-Solomon */ 125 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 126 }; 127 128 struct port_stats { 129 u64 tx_octets; /* total # of octets in good frames */ 130 u64 tx_frames; /* all good frames */ 131 u64 tx_bcast_frames; /* all broadcast frames */ 132 u64 tx_mcast_frames; /* all multicast frames */ 133 u64 tx_ucast_frames; /* all unicast frames */ 134 u64 tx_error_frames; /* all error frames */ 135 136 u64 tx_frames_64; /* # of Tx frames in a particular range */ 137 u64 tx_frames_65_127; 138 u64 tx_frames_128_255; 139 u64 tx_frames_256_511; 140 u64 tx_frames_512_1023; 141 u64 tx_frames_1024_1518; 142 u64 tx_frames_1519_max; 143 144 u64 tx_drop; /* # of dropped Tx frames */ 145 u64 tx_pause; /* # of transmitted pause frames */ 146 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 147 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 148 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 149 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 150 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 151 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 152 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 153 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 154 155 u64 rx_octets; /* total # of octets in good frames */ 156 u64 rx_frames; /* all good frames */ 157 u64 rx_bcast_frames; /* all broadcast frames */ 158 u64 rx_mcast_frames; /* all multicast frames */ 159 u64 rx_ucast_frames; /* all unicast frames */ 160 u64 rx_too_long; /* # of frames exceeding MTU */ 161 u64 rx_jabber; /* # of jabber frames */ 162 u64 rx_fcs_err; /* # of received frames with bad FCS */ 163 u64 rx_len_err; /* # of received frames with length error */ 164 u64 rx_symbol_err; /* symbol errors */ 165 u64 rx_runt; /* # of short frames */ 166 167 u64 rx_frames_64; /* # of Rx frames in a particular range */ 168 u64 rx_frames_65_127; 169 u64 rx_frames_128_255; 170 u64 rx_frames_256_511; 171 u64 rx_frames_512_1023; 172 u64 rx_frames_1024_1518; 173 u64 rx_frames_1519_max; 174 175 u64 rx_pause; /* # of received pause frames */ 176 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 177 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 178 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 179 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 180 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 181 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 182 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 183 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 184 185 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 186 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 187 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 188 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 189 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 190 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 191 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 192 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 193 }; 194 195 struct lb_port_stats { 196 u64 octets; 197 u64 frames; 198 u64 bcast_frames; 199 u64 mcast_frames; 200 u64 ucast_frames; 201 u64 error_frames; 202 203 u64 frames_64; 204 u64 frames_65_127; 205 u64 frames_128_255; 206 u64 frames_256_511; 207 u64 frames_512_1023; 208 u64 frames_1024_1518; 209 u64 frames_1519_max; 210 211 u64 drop; 212 213 u64 ovflow0; 214 u64 ovflow1; 215 u64 ovflow2; 216 u64 ovflow3; 217 u64 trunc0; 218 u64 trunc1; 219 u64 trunc2; 220 u64 trunc3; 221 }; 222 223 struct tp_tcp_stats { 224 u32 tcp_out_rsts; 225 u64 tcp_in_segs; 226 u64 tcp_out_segs; 227 u64 tcp_retrans_segs; 228 }; 229 230 struct tp_usm_stats { 231 u32 frames; 232 u32 drops; 233 u64 octets; 234 }; 235 236 struct tp_fcoe_stats { 237 u32 frames_ddp; 238 u32 frames_drop; 239 u64 octets_ddp; 240 }; 241 242 struct tp_err_stats { 243 u32 mac_in_errs[4]; 244 u32 hdr_in_errs[4]; 245 u32 tcp_in_errs[4]; 246 u32 tnl_cong_drops[4]; 247 u32 ofld_chan_drops[4]; 248 u32 tnl_tx_drops[4]; 249 u32 ofld_vlan_drops[4]; 250 u32 tcp6_in_errs[4]; 251 u32 ofld_no_neigh; 252 u32 ofld_cong_defer; 253 }; 254 255 struct tp_cpl_stats { 256 u32 req[4]; 257 u32 rsp[4]; 258 }; 259 260 struct tp_rdma_stats { 261 u32 rqe_dfr_pkt; 262 u32 rqe_dfr_mod; 263 }; 264 265 struct sge_params { 266 u32 hps; /* host page size for our PF/VF */ 267 u32 eq_qpp; /* egress queues/page for our PF/VF */ 268 u32 iq_qpp; /* egress queues/page for our PF/VF */ 269 }; 270 271 struct tp_params { 272 unsigned int tre; /* log2 of core clocks per TP tick */ 273 unsigned int la_mask; /* what events are recorded by TP LA */ 274 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 275 /* channel map */ 276 277 uint32_t dack_re; /* DACK timer resolution */ 278 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 279 280 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 281 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 282 283 /* cached TP_OUT_CONFIG compressed error vector 284 * and passing outer header info for encapsulated packets. 285 */ 286 int rx_pkt_encap; 287 288 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 289 * subset of the set of fields which may be present in the Compressed 290 * Filter Tuple portion of filters and TCP TCB connections. The 291 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 292 * Since a variable number of fields may or may not be present, their 293 * shifted field positions within the Compressed Filter Tuple may 294 * vary, or not even be present if the field isn't selected in 295 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 296 * places we store their offsets here, or a -1 if the field isn't 297 * present. 298 */ 299 int fcoe_shift; 300 int port_shift; 301 int vnic_shift; 302 int vlan_shift; 303 int tos_shift; 304 int protocol_shift; 305 int ethertype_shift; 306 int macmatch_shift; 307 int matchtype_shift; 308 int frag_shift; 309 310 u64 hash_filter_mask; 311 }; 312 313 struct vpd_params { 314 unsigned int cclk; 315 u8 ec[EC_LEN + 1]; 316 u8 sn[SERNUM_LEN + 1]; 317 u8 id[ID_LEN + 1]; 318 u8 pn[PN_LEN + 1]; 319 u8 na[MACADDR_LEN + 1]; 320 }; 321 322 struct pci_params { 323 unsigned int vpd_cap_addr; 324 unsigned char speed; 325 unsigned char width; 326 }; 327 328 struct devlog_params { 329 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 330 u32 start; /* start of log in firmware memory */ 331 u32 size; /* size of log */ 332 }; 333 334 /* Stores chip specific parameters */ 335 struct arch_specific_params { 336 u8 nchan; 337 u8 pm_stats_cnt; 338 u8 cng_ch_bits_log; /* congestion channel map bits width */ 339 u16 mps_rplc_size; 340 u16 vfcount; 341 u32 sge_fl_db; 342 u16 mps_tcam_size; 343 }; 344 345 struct adapter_params { 346 struct sge_params sge; 347 struct tp_params tp; 348 struct vpd_params vpd; 349 struct pci_params pci; 350 struct devlog_params devlog; 351 enum pcie_memwin drv_memwin; 352 353 unsigned int cim_la_size; 354 355 unsigned int sf_size; /* serial flash size in bytes */ 356 unsigned int sf_nsec; /* # of flash sectors */ 357 358 unsigned int fw_vers; /* firmware version */ 359 unsigned int bs_vers; /* bootstrap version */ 360 unsigned int tp_vers; /* TP microcode version */ 361 unsigned int er_vers; /* expansion ROM version */ 362 unsigned int scfg_vers; /* Serial Configuration version */ 363 unsigned int vpd_vers; /* VPD Version */ 364 u8 api_vers[7]; 365 366 unsigned short mtus[NMTUS]; 367 unsigned short a_wnd[NCCTRL_WIN]; 368 unsigned short b_wnd[NCCTRL_WIN]; 369 370 unsigned char nports; /* # of ethernet ports */ 371 unsigned char portvec; 372 enum chip_type chip; /* chip code */ 373 struct arch_specific_params arch; /* chip specific params */ 374 unsigned char offload; 375 unsigned char crypto; /* HW capability for crypto */ 376 377 unsigned char bypass; 378 unsigned char hash_filter; 379 380 unsigned int ofldq_wr_cred; 381 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 382 383 unsigned int nsched_cls; /* number of traffic classes */ 384 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 385 unsigned int max_ird_adapter; /* Max read depth per adapter */ 386 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 387 u8 fw_caps_support; /* 32-bit Port Capabilities */ 388 bool filter2_wr_support; /* FW support for FILTER2_WR */ 389 390 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 391 * used by the Port 392 */ 393 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 394 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 395 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 396 }; 397 398 /* State needed to monitor the forward progress of SGE Ingress DMA activities 399 * and possible hangs. 400 */ 401 struct sge_idma_monitor_state { 402 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 403 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 404 unsigned int idma_state[2]; /* IDMA Hang detect state */ 405 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 406 unsigned int idma_warn[2]; /* time to warning in HZ */ 407 }; 408 409 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 410 * The access and execute times are signed in order to accommodate negative 411 * error returns. 412 */ 413 struct mbox_cmd { 414 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 415 u64 timestamp; /* OS-dependent timestamp */ 416 u32 seqno; /* sequence number */ 417 s16 access; /* time (ms) to access mailbox */ 418 s16 execute; /* time (ms) to execute */ 419 }; 420 421 struct mbox_cmd_log { 422 unsigned int size; /* number of entries in the log */ 423 unsigned int cursor; /* next position in the log to write */ 424 u32 seqno; /* next sequence number */ 425 /* variable length mailbox command log starts here */ 426 }; 427 428 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 429 * return a pointer to the specified entry. 430 */ 431 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 432 unsigned int entry_idx) 433 { 434 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 435 } 436 437 #include "t4fw_api.h" 438 439 #define FW_VERSION(chip) ( \ 440 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 441 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 442 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 443 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 444 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 445 446 struct fw_info { 447 u8 chip; 448 char *fs_name; 449 char *fw_mod_name; 450 struct fw_hdr fw_hdr; 451 }; 452 453 struct trace_params { 454 u32 data[TRACE_LEN / 4]; 455 u32 mask[TRACE_LEN / 4]; 456 unsigned short snap_len; 457 unsigned short min_len; 458 unsigned char skip_ofst; 459 unsigned char skip_len; 460 unsigned char invert; 461 unsigned char port; 462 }; 463 464 /* Firmware Port Capabilities types. */ 465 466 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 467 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 468 469 enum fw_caps { 470 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 471 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 472 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 473 }; 474 475 struct link_config { 476 fw_port_cap32_t pcaps; /* link capabilities */ 477 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 478 fw_port_cap32_t acaps; /* advertised capabilities */ 479 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 480 481 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 482 unsigned int speed; /* actual link speed (Mb/s) */ 483 484 enum cc_pause requested_fc; /* flow control user has requested */ 485 enum cc_pause fc; /* actual link flow control */ 486 487 enum cc_fec requested_fec; /* Forward Error Correction: */ 488 enum cc_fec fec; /* requested and actual in use */ 489 490 unsigned char autoneg; /* autonegotiating? */ 491 492 unsigned char link_ok; /* link up? */ 493 unsigned char link_down_rc; /* link down reason */ 494 }; 495 496 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 497 498 enum { 499 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 500 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 501 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 502 }; 503 504 enum { 505 MAX_TXQ_ENTRIES = 16384, 506 MAX_CTRL_TXQ_ENTRIES = 1024, 507 MAX_RSPQ_ENTRIES = 16384, 508 MAX_RX_BUFFERS = 16384, 509 MIN_TXQ_ENTRIES = 32, 510 MIN_CTRL_TXQ_ENTRIES = 32, 511 MIN_RSPQ_ENTRIES = 128, 512 MIN_FL_ENTRIES = 16 513 }; 514 515 enum { 516 INGQ_EXTRAS = 2, /* firmware event queue and */ 517 /* forwarded interrupts */ 518 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 519 }; 520 521 struct adapter; 522 struct sge_rspq; 523 524 #include "cxgb4_dcb.h" 525 526 #ifdef CONFIG_CHELSIO_T4_FCOE 527 #include "cxgb4_fcoe.h" 528 #endif /* CONFIG_CHELSIO_T4_FCOE */ 529 530 struct port_info { 531 struct adapter *adapter; 532 u16 viid; 533 s16 xact_addr_filt; /* index of exact MAC address filter */ 534 u16 rss_size; /* size of VI's RSS table slice */ 535 s8 mdio_addr; 536 enum fw_port_type port_type; 537 u8 mod_type; 538 u8 port_id; 539 u8 tx_chan; 540 u8 lport; /* associated offload logical port */ 541 u8 nqsets; /* # of qsets */ 542 u8 first_qset; /* index of first qset */ 543 u8 rss_mode; 544 struct link_config link_cfg; 545 u16 *rss; 546 struct port_stats stats_base; 547 #ifdef CONFIG_CHELSIO_T4_DCB 548 struct port_dcb_info dcb; /* Data Center Bridging support */ 549 #endif 550 #ifdef CONFIG_CHELSIO_T4_FCOE 551 struct cxgb_fcoe fcoe; 552 #endif /* CONFIG_CHELSIO_T4_FCOE */ 553 bool rxtstamp; /* Enable TS */ 554 struct hwtstamp_config tstamp_config; 555 bool ptp_enable; 556 struct sched_table *sched_tbl; 557 }; 558 559 struct dentry; 560 struct work_struct; 561 562 enum { /* adapter flags */ 563 FULL_INIT_DONE = (1 << 0), 564 DEV_ENABLED = (1 << 1), 565 USING_MSI = (1 << 2), 566 USING_MSIX = (1 << 3), 567 FW_OK = (1 << 4), 568 RSS_TNLALLLOOKUP = (1 << 5), 569 USING_SOFT_PARAMS = (1 << 6), 570 MASTER_PF = (1 << 7), 571 FW_OFLD_CONN = (1 << 9), 572 ROOT_NO_RELAXED_ORDERING = (1 << 10), 573 SHUTTING_DOWN = (1 << 11), 574 }; 575 576 enum { 577 ULP_CRYPTO_LOOKASIDE = 1 << 0, 578 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 579 }; 580 581 struct rx_sw_desc; 582 583 struct sge_fl { /* SGE free-buffer queue state */ 584 unsigned int avail; /* # of available Rx buffers */ 585 unsigned int pend_cred; /* new buffers since last FL DB ring */ 586 unsigned int cidx; /* consumer index */ 587 unsigned int pidx; /* producer index */ 588 unsigned long alloc_failed; /* # of times buffer allocation failed */ 589 unsigned long large_alloc_failed; 590 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 591 unsigned long low; /* # of times momentarily starving */ 592 unsigned long starving; 593 /* RO fields */ 594 unsigned int cntxt_id; /* SGE context id for the free list */ 595 unsigned int size; /* capacity of free list */ 596 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 597 __be64 *desc; /* address of HW Rx descriptor ring */ 598 dma_addr_t addr; /* bus address of HW ring start */ 599 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 600 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 601 }; 602 603 /* A packet gather list */ 604 struct pkt_gl { 605 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 606 struct page_frag frags[MAX_SKB_FRAGS]; 607 void *va; /* virtual address of first byte */ 608 unsigned int nfrags; /* # of fragments */ 609 unsigned int tot_len; /* total length of fragments */ 610 }; 611 612 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 613 const struct pkt_gl *gl); 614 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 615 /* LRO related declarations for ULD */ 616 struct t4_lro_mgr { 617 #define MAX_LRO_SESSIONS 64 618 u8 lro_session_cnt; /* # of sessions to aggregate */ 619 unsigned long lro_pkts; /* # of LRO super packets */ 620 unsigned long lro_merged; /* # of wire packets merged by LRO */ 621 struct sk_buff_head lroq; /* list of aggregated sessions */ 622 }; 623 624 struct sge_rspq { /* state for an SGE response queue */ 625 struct napi_struct napi; 626 const __be64 *cur_desc; /* current descriptor in queue */ 627 unsigned int cidx; /* consumer index */ 628 u8 gen; /* current generation bit */ 629 u8 intr_params; /* interrupt holdoff parameters */ 630 u8 next_intr_params; /* holdoff params for next interrupt */ 631 u8 adaptive_rx; 632 u8 pktcnt_idx; /* interrupt packet threshold */ 633 u8 uld; /* ULD handling this queue */ 634 u8 idx; /* queue index within its group */ 635 int offset; /* offset into current Rx buffer */ 636 u16 cntxt_id; /* SGE context id for the response q */ 637 u16 abs_id; /* absolute SGE id for the response q */ 638 __be64 *desc; /* address of HW response ring */ 639 dma_addr_t phys_addr; /* physical address of the ring */ 640 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 641 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 642 unsigned int iqe_len; /* entry size */ 643 unsigned int size; /* capacity of response queue */ 644 struct adapter *adap; 645 struct net_device *netdev; /* associated net device */ 646 rspq_handler_t handler; 647 rspq_flush_handler_t flush_handler; 648 struct t4_lro_mgr lro_mgr; 649 }; 650 651 struct sge_eth_stats { /* Ethernet queue statistics */ 652 unsigned long pkts; /* # of ethernet packets */ 653 unsigned long lro_pkts; /* # of LRO super packets */ 654 unsigned long lro_merged; /* # of wire packets merged by LRO */ 655 unsigned long rx_cso; /* # of Rx checksum offloads */ 656 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 657 unsigned long rx_drops; /* # of packets dropped due to no mem */ 658 }; 659 660 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 661 struct sge_rspq rspq; 662 struct sge_fl fl; 663 struct sge_eth_stats stats; 664 } ____cacheline_aligned_in_smp; 665 666 struct sge_ofld_stats { /* offload queue statistics */ 667 unsigned long pkts; /* # of packets */ 668 unsigned long imm; /* # of immediate-data packets */ 669 unsigned long an; /* # of asynchronous notifications */ 670 unsigned long nomem; /* # of responses deferred due to no mem */ 671 }; 672 673 struct sge_ofld_rxq { /* SW offload Rx queue */ 674 struct sge_rspq rspq; 675 struct sge_fl fl; 676 struct sge_ofld_stats stats; 677 } ____cacheline_aligned_in_smp; 678 679 struct tx_desc { 680 __be64 flit[8]; 681 }; 682 683 struct tx_sw_desc; 684 685 struct sge_txq { 686 unsigned int in_use; /* # of in-use Tx descriptors */ 687 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 688 unsigned int size; /* # of descriptors */ 689 unsigned int cidx; /* SW consumer index */ 690 unsigned int pidx; /* producer index */ 691 unsigned long stops; /* # of times q has been stopped */ 692 unsigned long restarts; /* # of queue restarts */ 693 unsigned int cntxt_id; /* SGE context id for the Tx q */ 694 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 695 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 696 struct sge_qstat *stat; /* queue status entry */ 697 dma_addr_t phys_addr; /* physical address of the ring */ 698 spinlock_t db_lock; 699 int db_disabled; 700 unsigned short db_pidx; 701 unsigned short db_pidx_inc; 702 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 703 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 704 }; 705 706 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 707 struct sge_txq q; 708 struct netdev_queue *txq; /* associated netdev TX queue */ 709 #ifdef CONFIG_CHELSIO_T4_DCB 710 u8 dcb_prio; /* DCB Priority bound to queue */ 711 #endif 712 unsigned long tso; /* # of TSO requests */ 713 unsigned long tx_cso; /* # of Tx checksum offloads */ 714 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 715 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 716 } ____cacheline_aligned_in_smp; 717 718 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 719 struct sge_txq q; 720 struct adapter *adap; 721 struct sk_buff_head sendq; /* list of backpressured packets */ 722 struct tasklet_struct qresume_tsk; /* restarts the queue */ 723 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 724 u8 full; /* the Tx ring is full */ 725 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 726 } ____cacheline_aligned_in_smp; 727 728 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 729 struct sge_txq q; 730 struct adapter *adap; 731 struct sk_buff_head sendq; /* list of backpressured packets */ 732 struct tasklet_struct qresume_tsk; /* restarts the queue */ 733 u8 full; /* the Tx ring is full */ 734 } ____cacheline_aligned_in_smp; 735 736 struct sge_uld_rxq_info { 737 char name[IFNAMSIZ]; /* name of ULD driver */ 738 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 739 u16 *msix_tbl; /* msix_tbl for uld */ 740 u16 *rspq_id; /* response queue id's of rxq */ 741 u16 nrxq; /* # of ingress uld queues */ 742 u16 nciq; /* # of completion queues */ 743 u8 uld; /* uld type */ 744 }; 745 746 struct sge_uld_txq_info { 747 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 748 atomic_t users; /* num users */ 749 u16 ntxq; /* # of egress uld queues */ 750 }; 751 752 struct sge { 753 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 754 struct sge_eth_txq ptptxq; 755 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 756 757 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 758 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 759 struct sge_uld_rxq_info **uld_rxq_info; 760 struct sge_uld_txq_info **uld_txq_info; 761 762 struct sge_rspq intrq ____cacheline_aligned_in_smp; 763 spinlock_t intrq_lock; 764 765 u16 max_ethqsets; /* # of available Ethernet queue sets */ 766 u16 ethqsets; /* # of active Ethernet queue sets */ 767 u16 ethtxq_rover; /* Tx queue to clean up next */ 768 u16 ofldqsets; /* # of active ofld queue sets */ 769 u16 nqs_per_uld; /* # of Rx queues per ULD */ 770 u16 timer_val[SGE_NTIMERS]; 771 u8 counter_val[SGE_NCOUNTERS]; 772 u32 fl_pg_order; /* large page allocation size */ 773 u32 stat_len; /* length of status page at ring end */ 774 u32 pktshift; /* padding between CPL & packet data */ 775 u32 fl_align; /* response queue message alignment */ 776 u32 fl_starve_thres; /* Free List starvation threshold */ 777 778 struct sge_idma_monitor_state idma_monitor; 779 unsigned int egr_start; 780 unsigned int egr_sz; 781 unsigned int ingr_start; 782 unsigned int ingr_sz; 783 void **egr_map; /* qid->queue egress queue map */ 784 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 785 unsigned long *starving_fl; 786 unsigned long *txq_maperr; 787 unsigned long *blocked_fl; 788 struct timer_list rx_timer; /* refills starving FLs */ 789 struct timer_list tx_timer; /* checks Tx queues */ 790 }; 791 792 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 793 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 794 795 struct l2t_data; 796 797 #ifdef CONFIG_PCI_IOV 798 799 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 800 * Configuration initialization for T5 only has SR-IOV functionality enabled 801 * on PF0-3 in order to simplify everything. 802 */ 803 #define NUM_OF_PF_WITH_SRIOV 4 804 805 #endif 806 807 struct doorbell_stats { 808 u32 db_drop; 809 u32 db_empty; 810 u32 db_full; 811 }; 812 813 struct hash_mac_addr { 814 struct list_head list; 815 u8 addr[ETH_ALEN]; 816 }; 817 818 struct uld_msix_bmap { 819 unsigned long *msix_bmap; 820 unsigned int mapsize; 821 spinlock_t lock; /* lock for acquiring bitmap */ 822 }; 823 824 struct uld_msix_info { 825 unsigned short vec; 826 char desc[IFNAMSIZ + 10]; 827 unsigned int idx; 828 }; 829 830 struct vf_info { 831 unsigned char vf_mac_addr[ETH_ALEN]; 832 unsigned int tx_rate; 833 bool pf_set_mac; 834 u16 vlan; 835 }; 836 837 enum { 838 HMA_DMA_MAPPED_FLAG = 1 839 }; 840 841 struct hma_data { 842 unsigned char flags; 843 struct sg_table *sgt; 844 dma_addr_t *phy_addr; /* physical address of the page */ 845 }; 846 847 struct mbox_list { 848 struct list_head list; 849 }; 850 851 struct mps_encap_entry { 852 atomic_t refcnt; 853 }; 854 855 struct adapter { 856 void __iomem *regs; 857 void __iomem *bar2; 858 u32 t4_bar0; 859 struct pci_dev *pdev; 860 struct device *pdev_dev; 861 const char *name; 862 unsigned int mbox; 863 unsigned int pf; 864 unsigned int flags; 865 unsigned int adap_idx; 866 enum chip_type chip; 867 868 int msg_enable; 869 __be16 vxlan_port; 870 u8 vxlan_port_cnt; 871 __be16 geneve_port; 872 u8 geneve_port_cnt; 873 874 struct adapter_params params; 875 struct cxgb4_virt_res vres; 876 unsigned int swintr; 877 878 struct { 879 unsigned short vec; 880 char desc[IFNAMSIZ + 10]; 881 } msix_info[MAX_INGQ + 1]; 882 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 883 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 884 int msi_idx; 885 886 struct doorbell_stats db_stats; 887 struct sge sge; 888 889 struct net_device *port[MAX_NPORTS]; 890 u8 chan_map[NCHAN]; /* channel -> port map */ 891 892 struct vf_info *vfinfo; 893 u8 num_vfs; 894 895 u32 filter_mode; 896 unsigned int l2t_start; 897 unsigned int l2t_end; 898 struct l2t_data *l2t; 899 unsigned int clipt_start; 900 unsigned int clipt_end; 901 struct clip_tbl *clipt; 902 unsigned int rawf_start; 903 unsigned int rawf_cnt; 904 struct smt_data *smt; 905 struct mps_encap_entry *mps_encap; 906 struct cxgb4_uld_info *uld; 907 void *uld_handle[CXGB4_ULD_MAX]; 908 unsigned int num_uld; 909 unsigned int num_ofld_uld; 910 struct list_head list_node; 911 struct list_head rcu_node; 912 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 913 914 void *iscsi_ppm; 915 916 struct tid_info tids; 917 void **tid_release_head; 918 spinlock_t tid_release_lock; 919 struct workqueue_struct *workq; 920 struct work_struct tid_release_task; 921 struct work_struct db_full_task; 922 struct work_struct db_drop_task; 923 struct work_struct fatal_err_notify_task; 924 bool tid_release_task_busy; 925 926 /* lock for mailbox cmd list */ 927 spinlock_t mbox_lock; 928 struct mbox_list mlist; 929 930 /* support for mailbox command/reply logging */ 931 #define T4_OS_LOG_MBOX_CMDS 256 932 struct mbox_cmd_log *mbox_log; 933 934 struct mutex uld_mutex; 935 936 struct dentry *debugfs_root; 937 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 938 bool trace_rss; /* 1 implies that different RSS flit per filter is 939 * used per filter else if 0 default RSS flit is 940 * used for all 4 filters. 941 */ 942 943 struct ptp_clock *ptp_clock; 944 struct ptp_clock_info ptp_clock_info; 945 struct sk_buff *ptp_tx_skb; 946 /* ptp lock */ 947 spinlock_t ptp_lock; 948 spinlock_t stats_lock; 949 spinlock_t win0_lock ____cacheline_aligned_in_smp; 950 951 /* TC u32 offload */ 952 struct cxgb4_tc_u32_table *tc_u32; 953 struct chcr_stats_debug chcr_stats; 954 955 /* TC flower offload */ 956 struct rhashtable flower_tbl; 957 struct rhashtable_params flower_ht_params; 958 struct timer_list flower_stats_timer; 959 struct work_struct flower_stats_work; 960 961 /* Ethtool Dump */ 962 struct ethtool_dump eth_dump; 963 964 /* HMA */ 965 struct hma_data hma; 966 967 struct srq_data *srq; 968 969 /* Dump buffer for collecting logs in kdump kernel */ 970 struct vmcoredd_data vmcoredd; 971 }; 972 973 /* Support for "sched-class" command to allow a TX Scheduling Class to be 974 * programmed with various parameters. 975 */ 976 struct ch_sched_params { 977 s8 type; /* packet or flow */ 978 union { 979 struct { 980 s8 level; /* scheduler hierarchy level */ 981 s8 mode; /* per-class or per-flow */ 982 s8 rateunit; /* bit or packet rate */ 983 s8 ratemode; /* %port relative or kbps absolute */ 984 s8 channel; /* scheduler channel [0..N] */ 985 s8 class; /* scheduler class [0..N] */ 986 s32 minrate; /* minimum rate */ 987 s32 maxrate; /* maximum rate */ 988 s16 weight; /* percent weight */ 989 s16 pktsize; /* average packet size */ 990 } params; 991 } u; 992 }; 993 994 enum { 995 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 996 }; 997 998 enum { 999 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 1000 }; 1001 1002 enum { 1003 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1004 }; 1005 1006 enum { 1007 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1008 }; 1009 1010 enum { 1011 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1012 }; 1013 1014 struct tx_sw_desc { /* SW state per Tx descriptor */ 1015 struct sk_buff *skb; 1016 struct ulptx_sgl *sgl; 1017 }; 1018 1019 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1020 * to be bound to a TX Scheduling Class. 1021 */ 1022 struct ch_sched_queue { 1023 s8 queue; /* queue index */ 1024 s8 class; /* class index */ 1025 }; 1026 1027 /* Defined bit width of user definable filter tuples 1028 */ 1029 #define ETHTYPE_BITWIDTH 16 1030 #define FRAG_BITWIDTH 1 1031 #define MACIDX_BITWIDTH 9 1032 #define FCOE_BITWIDTH 1 1033 #define IPORT_BITWIDTH 3 1034 #define MATCHTYPE_BITWIDTH 3 1035 #define PROTO_BITWIDTH 8 1036 #define TOS_BITWIDTH 8 1037 #define PF_BITWIDTH 8 1038 #define VF_BITWIDTH 8 1039 #define IVLAN_BITWIDTH 16 1040 #define OVLAN_BITWIDTH 16 1041 #define ENCAP_VNI_BITWIDTH 24 1042 1043 /* Filter matching rules. These consist of a set of ingress packet field 1044 * (value, mask) tuples. The associated ingress packet field matches the 1045 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1046 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1047 * matches an ingress packet when all of the individual individual field 1048 * matching rules are true. 1049 * 1050 * Partial field masks are always valid, however, while it may be easy to 1051 * understand their meanings for some fields (e.g. IP address to match a 1052 * subnet), for others making sensible partial masks is less intuitive (e.g. 1053 * MPS match type) ... 1054 * 1055 * Most of the following data structures are modeled on T4 capabilities. 1056 * Drivers for earlier chips use the subsets which make sense for those chips. 1057 * We really need to come up with a hardware-independent mechanism to 1058 * represent hardware filter capabilities ... 1059 */ 1060 struct ch_filter_tuple { 1061 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1062 * register selects which of these fields will participate in the 1063 * filter match rules -- up to a maximum of 36 bits. Because 1064 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1065 * set of fields. 1066 */ 1067 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1068 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1069 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1070 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1071 uint32_t pfvf_vld:1; /* PF/VF valid */ 1072 uint32_t encap_vld:1; /* Encapsulation valid */ 1073 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1074 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1075 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1076 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1077 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1078 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1079 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1080 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1081 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1082 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1083 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1084 1085 /* Uncompressed header matching field rules. These are always 1086 * available for field rules. 1087 */ 1088 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1089 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1090 uint16_t lport; /* local port */ 1091 uint16_t fport; /* foreign port */ 1092 }; 1093 1094 /* A filter ioctl command. 1095 */ 1096 struct ch_filter_specification { 1097 /* Administrative fields for filter. 1098 */ 1099 uint32_t hitcnts:1; /* count filter hits in TCB */ 1100 uint32_t prio:1; /* filter has priority over active/server */ 1101 1102 /* Fundamental filter typing. This is the one element of filter 1103 * matching that doesn't exist as a (value, mask) tuple. 1104 */ 1105 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1106 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1107 1108 /* Packet dispatch information. Ingress packets which match the 1109 * filter rules will be dropped, passed to the host or switched back 1110 * out as egress packets. 1111 */ 1112 uint32_t action:2; /* drop, pass, switch */ 1113 1114 uint32_t rpttid:1; /* report TID in RSS hash field */ 1115 1116 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1117 uint32_t iq:10; /* ingress queue */ 1118 1119 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1120 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1121 /* 1 => TCB contains IQ ID */ 1122 1123 /* Switch proxy/rewrite fields. An ingress packet which matches a 1124 * filter with "switch" set will be looped back out as an egress 1125 * packet -- potentially with some Ethernet header rewriting. 1126 */ 1127 uint32_t eport:2; /* egress port to switch packet out */ 1128 uint32_t newdmac:1; /* rewrite destination MAC address */ 1129 uint32_t newsmac:1; /* rewrite source MAC address */ 1130 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1131 uint32_t nat_mode:3; /* specify NAT operation mode */ 1132 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1133 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1134 uint16_t vlan; /* VLAN Tag to insert */ 1135 1136 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1137 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1138 u16 nat_lport; /* local port to use after NAT'ing */ 1139 u16 nat_fport; /* foreign port to use after NAT'ing */ 1140 1141 /* reservation for future additions */ 1142 u8 rsvd[24]; 1143 1144 /* Filter rule value/mask pairs. 1145 */ 1146 struct ch_filter_tuple val; 1147 struct ch_filter_tuple mask; 1148 }; 1149 1150 enum { 1151 FILTER_PASS = 0, /* default */ 1152 FILTER_DROP, 1153 FILTER_SWITCH 1154 }; 1155 1156 enum { 1157 VLAN_NOCHANGE = 0, /* default */ 1158 VLAN_REMOVE, 1159 VLAN_INSERT, 1160 VLAN_REWRITE 1161 }; 1162 1163 enum { 1164 NAT_MODE_NONE = 0, /* No NAT performed */ 1165 NAT_MODE_DIP, /* NAT on Dst IP */ 1166 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1167 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1168 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1169 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1170 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1171 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1172 }; 1173 1174 /* Host shadow copy of ingress filter entry. This is in host native format 1175 * and doesn't match the ordering or bit order, etc. of the hardware of the 1176 * firmware command. The use of bit-field structure elements is purely to 1177 * remind ourselves of the field size limitations and save memory in the case 1178 * where the filter table is large. 1179 */ 1180 struct filter_entry { 1181 /* Administrative fields for filter. */ 1182 u32 valid:1; /* filter allocated and valid */ 1183 u32 locked:1; /* filter is administratively locked */ 1184 1185 u32 pending:1; /* filter action is pending firmware reply */ 1186 struct filter_ctx *ctx; /* Caller's completion hook */ 1187 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1188 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1189 struct net_device *dev; /* Associated net device */ 1190 u32 tid; /* This will store the actual tid */ 1191 1192 /* The filter itself. Most of this is a straight copy of information 1193 * provided by the extended ioctl(). Some fields are translated to 1194 * internal forms -- for instance the Ingress Queue ID passed in from 1195 * the ioctl() is translated into the Absolute Ingress Queue ID. 1196 */ 1197 struct ch_filter_specification fs; 1198 }; 1199 1200 static inline int is_offload(const struct adapter *adap) 1201 { 1202 return adap->params.offload; 1203 } 1204 1205 static inline int is_hashfilter(const struct adapter *adap) 1206 { 1207 return adap->params.hash_filter; 1208 } 1209 1210 static inline int is_pci_uld(const struct adapter *adap) 1211 { 1212 return adap->params.crypto; 1213 } 1214 1215 static inline int is_uld(const struct adapter *adap) 1216 { 1217 return (adap->params.offload || adap->params.crypto); 1218 } 1219 1220 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1221 { 1222 return readl(adap->regs + reg_addr); 1223 } 1224 1225 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1226 { 1227 writel(val, adap->regs + reg_addr); 1228 } 1229 1230 #ifndef readq 1231 static inline u64 readq(const volatile void __iomem *addr) 1232 { 1233 return readl(addr) + ((u64)readl(addr + 4) << 32); 1234 } 1235 1236 static inline void writeq(u64 val, volatile void __iomem *addr) 1237 { 1238 writel(val, addr); 1239 writel(val >> 32, addr + 4); 1240 } 1241 #endif 1242 1243 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1244 { 1245 return readq(adap->regs + reg_addr); 1246 } 1247 1248 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1249 { 1250 writeq(val, adap->regs + reg_addr); 1251 } 1252 1253 /** 1254 * t4_set_hw_addr - store a port's MAC address in SW 1255 * @adapter: the adapter 1256 * @port_idx: the port index 1257 * @hw_addr: the Ethernet address 1258 * 1259 * Store the Ethernet address of the given port in SW. Called by the common 1260 * code when it retrieves a port's Ethernet address from EEPROM. 1261 */ 1262 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1263 u8 hw_addr[]) 1264 { 1265 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1266 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1267 } 1268 1269 /** 1270 * netdev2pinfo - return the port_info structure associated with a net_device 1271 * @dev: the netdev 1272 * 1273 * Return the struct port_info associated with a net_device 1274 */ 1275 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1276 { 1277 return netdev_priv(dev); 1278 } 1279 1280 /** 1281 * adap2pinfo - return the port_info of a port 1282 * @adap: the adapter 1283 * @idx: the port index 1284 * 1285 * Return the port_info structure for the port of the given index. 1286 */ 1287 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1288 { 1289 return netdev_priv(adap->port[idx]); 1290 } 1291 1292 /** 1293 * netdev2adap - return the adapter structure associated with a net_device 1294 * @dev: the netdev 1295 * 1296 * Return the struct adapter associated with a net_device 1297 */ 1298 static inline struct adapter *netdev2adap(const struct net_device *dev) 1299 { 1300 return netdev2pinfo(dev)->adapter; 1301 } 1302 1303 /* Return a version number to identify the type of adapter. The scheme is: 1304 * - bits 0..9: chip version 1305 * - bits 10..15: chip revision 1306 * - bits 16..23: register dump version 1307 */ 1308 static inline unsigned int mk_adap_vers(struct adapter *ap) 1309 { 1310 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1311 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1312 } 1313 1314 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1315 static inline unsigned int qtimer_val(const struct adapter *adap, 1316 const struct sge_rspq *q) 1317 { 1318 unsigned int idx = q->intr_params >> 1; 1319 1320 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1321 } 1322 1323 /* driver version & name used for ethtool_drvinfo */ 1324 extern char cxgb4_driver_name[]; 1325 extern const char cxgb4_driver_version[]; 1326 1327 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1328 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1329 1330 void t4_free_sge_resources(struct adapter *adap); 1331 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1332 irq_handler_t t4_intr_handler(struct adapter *adap); 1333 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1334 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1335 const struct pkt_gl *gl); 1336 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1337 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1338 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1339 struct net_device *dev, int intr_idx, 1340 struct sge_fl *fl, rspq_handler_t hnd, 1341 rspq_flush_handler_t flush_handler, int cong); 1342 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1343 struct net_device *dev, struct netdev_queue *netdevq, 1344 unsigned int iqid); 1345 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1346 struct net_device *dev, unsigned int iqid, 1347 unsigned int cmplqid); 1348 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1349 unsigned int cmplqid); 1350 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1351 struct net_device *dev, unsigned int iqid, 1352 unsigned int uld_type); 1353 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1354 int t4_sge_init(struct adapter *adap); 1355 void t4_sge_start(struct adapter *adap); 1356 void t4_sge_stop(struct adapter *adap); 1357 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1358 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1359 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1360 extern int dbfifo_int_thresh; 1361 1362 #define for_each_port(adapter, iter) \ 1363 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1364 1365 static inline int is_bypass(struct adapter *adap) 1366 { 1367 return adap->params.bypass; 1368 } 1369 1370 static inline int is_bypass_device(int device) 1371 { 1372 /* this should be set based upon device capabilities */ 1373 switch (device) { 1374 case 0x440b: 1375 case 0x440c: 1376 return 1; 1377 default: 1378 return 0; 1379 } 1380 } 1381 1382 static inline int is_10gbt_device(int device) 1383 { 1384 /* this should be set based upon device capabilities */ 1385 switch (device) { 1386 case 0x4409: 1387 case 0x4486: 1388 return 1; 1389 1390 default: 1391 return 0; 1392 } 1393 } 1394 1395 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1396 { 1397 return adap->params.vpd.cclk / 1000; 1398 } 1399 1400 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1401 unsigned int us) 1402 { 1403 return (us * adap->params.vpd.cclk) / 1000; 1404 } 1405 1406 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1407 unsigned int ticks) 1408 { 1409 /* add Core Clock / 2 to round ticks to nearest uS */ 1410 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1411 adapter->params.vpd.cclk); 1412 } 1413 1414 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1415 unsigned int ticks) 1416 { 1417 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1418 } 1419 1420 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1421 u32 val); 1422 1423 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1424 int size, void *rpl, bool sleep_ok, int timeout); 1425 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1426 void *rpl, bool sleep_ok); 1427 1428 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1429 const void *cmd, int size, void *rpl, 1430 int timeout) 1431 { 1432 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1433 timeout); 1434 } 1435 1436 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1437 int size, void *rpl) 1438 { 1439 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1440 } 1441 1442 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1443 int size, void *rpl) 1444 { 1445 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1446 } 1447 1448 /** 1449 * hash_mac_addr - return the hash value of a MAC address 1450 * @addr: the 48-bit Ethernet MAC address 1451 * 1452 * Hashes a MAC address according to the hash function used by HW inexact 1453 * (hash) address matching. 1454 */ 1455 static inline int hash_mac_addr(const u8 *addr) 1456 { 1457 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1458 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1459 1460 a ^= b; 1461 a ^= (a >> 12); 1462 a ^= (a >> 6); 1463 return a & 0x3f; 1464 } 1465 1466 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1467 unsigned int cnt); 1468 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1469 unsigned int us, unsigned int cnt, 1470 unsigned int size, unsigned int iqe_size) 1471 { 1472 q->adap = adap; 1473 cxgb4_set_rspq_intr_params(q, us, cnt); 1474 q->iqe_len = iqe_size; 1475 q->size = size; 1476 } 1477 1478 /** 1479 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1480 * @fw_mod_type: the Firmware Mofule Type 1481 * 1482 * Return whether the Firmware Module Type represents a real Transceiver 1483 * Module/Cable Module Type which has been inserted. 1484 */ 1485 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1486 { 1487 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1488 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1489 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1490 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1491 } 1492 1493 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1494 unsigned int data_reg, const u32 *vals, 1495 unsigned int nregs, unsigned int start_idx); 1496 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1497 unsigned int data_reg, u32 *vals, unsigned int nregs, 1498 unsigned int start_idx); 1499 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1500 1501 struct fw_filter_wr; 1502 1503 void t4_intr_enable(struct adapter *adapter); 1504 void t4_intr_disable(struct adapter *adapter); 1505 int t4_slow_intr_handler(struct adapter *adapter); 1506 1507 int t4_wait_dev_ready(void __iomem *regs); 1508 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1509 struct link_config *lc); 1510 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1511 1512 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1513 u32 t4_get_util_window(struct adapter *adap); 1514 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1515 1516 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1517 u32 *mem_base, u32 *mem_aperture); 1518 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1519 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1520 int dir); 1521 #define T4_MEMORY_WRITE 0 1522 #define T4_MEMORY_READ 1 1523 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1524 void *buf, int dir); 1525 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1526 u32 len, __be32 *buf) 1527 { 1528 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1529 } 1530 1531 unsigned int t4_get_regs_len(struct adapter *adapter); 1532 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1533 1534 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1535 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1536 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1537 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1538 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1539 unsigned int nwords, u32 *data, int byte_oriented); 1540 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1541 int t4_load_phy_fw(struct adapter *adap, 1542 int win, spinlock_t *lock, 1543 int (*phy_fw_version)(const u8 *, size_t), 1544 const u8 *phy_fw_data, size_t phy_fw_size); 1545 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1546 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1547 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1548 const u8 *fw_data, unsigned int size, int force); 1549 int t4_fl_pkt_align(struct adapter *adap); 1550 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1551 int t4_check_fw_version(struct adapter *adap); 1552 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1553 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1554 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1555 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1556 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1557 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1558 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1559 int t4_get_version_info(struct adapter *adapter); 1560 void t4_dump_version_info(struct adapter *adapter); 1561 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1562 const u8 *fw_data, unsigned int fw_size, 1563 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1564 int t4_prep_adapter(struct adapter *adapter); 1565 int t4_shutdown_adapter(struct adapter *adapter); 1566 1567 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1568 int t4_bar2_sge_qregs(struct adapter *adapter, 1569 unsigned int qid, 1570 enum t4_bar2_qtype qtype, 1571 int user, 1572 u64 *pbar2_qoffset, 1573 unsigned int *pbar2_qid); 1574 1575 unsigned int qtimer_val(const struct adapter *adap, 1576 const struct sge_rspq *q); 1577 1578 int t4_init_devlog_params(struct adapter *adapter); 1579 int t4_init_sge_params(struct adapter *adapter); 1580 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1581 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1582 int t4_init_rss_mode(struct adapter *adap, int mbox); 1583 int t4_init_portinfo(struct port_info *pi, int mbox, 1584 int port, int pf, int vf, u8 mac[]); 1585 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1586 void t4_fatal_err(struct adapter *adapter); 1587 unsigned int t4_chip_rss_size(struct adapter *adapter); 1588 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1589 int start, int n, const u16 *rspq, unsigned int nrspq); 1590 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1591 unsigned int flags); 1592 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1593 unsigned int flags, unsigned int defq); 1594 int t4_read_rss(struct adapter *adapter, u16 *entries); 1595 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1596 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1597 bool sleep_ok); 1598 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1599 u32 *valp, bool sleep_ok); 1600 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1601 u32 *vfl, u32 *vfh, bool sleep_ok); 1602 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1603 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1604 1605 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1606 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1607 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1608 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1609 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1610 size_t n); 1611 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1612 size_t n); 1613 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1614 unsigned int *valp); 1615 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1616 const unsigned int *valp); 1617 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1618 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1619 unsigned int *pif_req_wrptr, 1620 unsigned int *pif_rsp_wrptr); 1621 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1622 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1623 const char *t4_get_port_type_description(enum fw_port_type port_type); 1624 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1625 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1626 struct port_stats *stats, 1627 struct port_stats *offset); 1628 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1629 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1630 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1631 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1632 unsigned int mask, unsigned int val); 1633 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1634 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1635 bool sleep_ok); 1636 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1637 bool sleep_ok); 1638 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1639 bool sleep_ok); 1640 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1641 bool sleep_ok); 1642 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1643 struct tp_tcp_stats *v6, bool sleep_ok); 1644 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1645 struct tp_fcoe_stats *st, bool sleep_ok); 1646 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1647 const unsigned short *alpha, const unsigned short *beta); 1648 1649 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1650 1651 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1652 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1653 1654 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1655 const u8 *addr); 1656 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1657 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1658 1659 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1660 enum dev_master master, enum dev_state *state); 1661 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1662 int t4_early_init(struct adapter *adap, unsigned int mbox); 1663 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1664 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1665 unsigned int cache_line_size); 1666 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1667 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1668 unsigned int vf, unsigned int nparams, const u32 *params, 1669 u32 *val); 1670 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1671 unsigned int vf, unsigned int nparams, const u32 *params, 1672 u32 *val); 1673 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1674 unsigned int vf, unsigned int nparams, const u32 *params, 1675 u32 *val, int rw, bool sleep_ok); 1676 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1677 unsigned int pf, unsigned int vf, 1678 unsigned int nparams, const u32 *params, 1679 const u32 *val, int timeout); 1680 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1681 unsigned int vf, unsigned int nparams, const u32 *params, 1682 const u32 *val); 1683 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1684 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1685 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1686 unsigned int vi, unsigned int cmask, unsigned int pmask, 1687 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1688 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1689 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1690 unsigned int *rss_size); 1691 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1692 unsigned int pf, unsigned int vf, 1693 unsigned int viid); 1694 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1695 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1696 bool sleep_ok); 1697 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1698 const u8 *addr, const u8 *mask, unsigned int idx, 1699 u8 lookup_type, u8 port_id, bool sleep_ok); 1700 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 1701 bool sleep_ok); 1702 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 1703 const u8 *addr, const u8 *mask, unsigned int vni, 1704 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 1705 bool sleep_ok); 1706 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1707 const u8 *addr, const u8 *mask, unsigned int idx, 1708 u8 lookup_type, u8 port_id, bool sleep_ok); 1709 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1710 unsigned int viid, bool free, unsigned int naddr, 1711 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1712 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1713 unsigned int viid, unsigned int naddr, 1714 const u8 **addr, bool sleep_ok); 1715 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1716 int idx, const u8 *addr, bool persist, bool add_smt); 1717 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1718 bool ucast, u64 vec, bool sleep_ok); 1719 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1720 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1721 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1722 bool rx_en, bool tx_en); 1723 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1724 unsigned int nblinks); 1725 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1726 unsigned int mmd, unsigned int reg, u16 *valp); 1727 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1728 unsigned int mmd, unsigned int reg, u16 val); 1729 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1730 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1731 unsigned int fl0id, unsigned int fl1id); 1732 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1733 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1734 unsigned int fl0id, unsigned int fl1id); 1735 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1736 unsigned int vf, unsigned int eqid); 1737 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1738 unsigned int vf, unsigned int eqid); 1739 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1740 unsigned int vf, unsigned int eqid); 1741 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1742 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1743 int t4_update_port_info(struct port_info *pi); 1744 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1745 unsigned int *speedp, unsigned int *mtup); 1746 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1747 void t4_db_full(struct adapter *adapter); 1748 void t4_db_dropped(struct adapter *adapter); 1749 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1750 int filter_index, int enable); 1751 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1752 int filter_index, int *enabled); 1753 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1754 u32 addr, u32 val); 1755 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1756 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1757 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1758 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1759 enum ctxt_type ctype, u32 *data); 1760 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1761 enum ctxt_type ctype, u32 *data); 1762 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1763 int rateunit, int ratemode, int channel, int class, 1764 int minrate, int maxrate, int weight, int pktsize); 1765 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1766 void t4_idma_monitor_init(struct adapter *adapter, 1767 struct sge_idma_monitor_state *idma); 1768 void t4_idma_monitor(struct adapter *adapter, 1769 struct sge_idma_monitor_state *idma, 1770 int hz, int ticks); 1771 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1772 unsigned int naddr, u8 *addr); 1773 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1774 u32 start_index, bool sleep_ok); 1775 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1776 u32 start_index, bool sleep_ok); 1777 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1778 u32 start_index, bool sleep_ok); 1779 1780 void t4_uld_mem_free(struct adapter *adap); 1781 int t4_uld_mem_alloc(struct adapter *adap); 1782 void t4_uld_clean_up(struct adapter *adap); 1783 void t4_register_netevent_notifier(void); 1784 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1785 unsigned int devid, unsigned int offset, 1786 unsigned int len, u8 *buf); 1787 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1788 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1789 unsigned int n, bool unmap); 1790 void free_txq(struct adapter *adap, struct sge_txq *q); 1791 void cxgb4_reclaim_completed_tx(struct adapter *adap, 1792 struct sge_txq *q, bool unmap); 1793 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1794 dma_addr_t *addr); 1795 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1796 void *pos); 1797 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1798 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1799 const dma_addr_t *addr); 1800 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 1801 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 1802 u16 vlan); 1803 #endif /* __CXGB4_H__ */ 1804