1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <asm/io.h> 50 #include "cxgb4_uld.h" 51 52 #define T4FW_VERSION_MAJOR 0x01 53 #define T4FW_VERSION_MINOR 0x0C 54 #define T4FW_VERSION_MICRO 0x19 55 #define T4FW_VERSION_BUILD 0x00 56 57 #define T5FW_VERSION_MAJOR 0x01 58 #define T5FW_VERSION_MINOR 0x0C 59 #define T5FW_VERSION_MICRO 0x19 60 #define T5FW_VERSION_BUILD 0x00 61 62 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 63 64 enum { 65 MAX_NPORTS = 4, /* max # of ports */ 66 SERNUM_LEN = 24, /* Serial # length */ 67 EC_LEN = 16, /* E/C length */ 68 ID_LEN = 16, /* ID length */ 69 PN_LEN = 16, /* Part Number length */ 70 }; 71 72 enum { 73 MEM_EDC0, 74 MEM_EDC1, 75 MEM_MC, 76 MEM_MC0 = MEM_MC, 77 MEM_MC1 78 }; 79 80 enum { 81 MEMWIN0_APERTURE = 2048, 82 MEMWIN0_BASE = 0x1b800, 83 MEMWIN1_APERTURE = 32768, 84 MEMWIN1_BASE = 0x28000, 85 MEMWIN1_BASE_T5 = 0x52000, 86 MEMWIN2_APERTURE = 65536, 87 MEMWIN2_BASE = 0x30000, 88 MEMWIN2_APERTURE_T5 = 131072, 89 MEMWIN2_BASE_T5 = 0x60000, 90 }; 91 92 enum dev_master { 93 MASTER_CANT, 94 MASTER_MAY, 95 MASTER_MUST 96 }; 97 98 enum dev_state { 99 DEV_STATE_UNINIT, 100 DEV_STATE_INIT, 101 DEV_STATE_ERR 102 }; 103 104 enum { 105 PAUSE_RX = 1 << 0, 106 PAUSE_TX = 1 << 1, 107 PAUSE_AUTONEG = 1 << 2 108 }; 109 110 struct port_stats { 111 u64 tx_octets; /* total # of octets in good frames */ 112 u64 tx_frames; /* all good frames */ 113 u64 tx_bcast_frames; /* all broadcast frames */ 114 u64 tx_mcast_frames; /* all multicast frames */ 115 u64 tx_ucast_frames; /* all unicast frames */ 116 u64 tx_error_frames; /* all error frames */ 117 118 u64 tx_frames_64; /* # of Tx frames in a particular range */ 119 u64 tx_frames_65_127; 120 u64 tx_frames_128_255; 121 u64 tx_frames_256_511; 122 u64 tx_frames_512_1023; 123 u64 tx_frames_1024_1518; 124 u64 tx_frames_1519_max; 125 126 u64 tx_drop; /* # of dropped Tx frames */ 127 u64 tx_pause; /* # of transmitted pause frames */ 128 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 129 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 130 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 131 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 132 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 133 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 134 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 135 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 136 137 u64 rx_octets; /* total # of octets in good frames */ 138 u64 rx_frames; /* all good frames */ 139 u64 rx_bcast_frames; /* all broadcast frames */ 140 u64 rx_mcast_frames; /* all multicast frames */ 141 u64 rx_ucast_frames; /* all unicast frames */ 142 u64 rx_too_long; /* # of frames exceeding MTU */ 143 u64 rx_jabber; /* # of jabber frames */ 144 u64 rx_fcs_err; /* # of received frames with bad FCS */ 145 u64 rx_len_err; /* # of received frames with length error */ 146 u64 rx_symbol_err; /* symbol errors */ 147 u64 rx_runt; /* # of short frames */ 148 149 u64 rx_frames_64; /* # of Rx frames in a particular range */ 150 u64 rx_frames_65_127; 151 u64 rx_frames_128_255; 152 u64 rx_frames_256_511; 153 u64 rx_frames_512_1023; 154 u64 rx_frames_1024_1518; 155 u64 rx_frames_1519_max; 156 157 u64 rx_pause; /* # of received pause frames */ 158 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 159 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 160 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 161 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 162 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 163 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 164 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 165 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 166 167 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 168 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 169 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 170 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 171 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 172 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 173 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 174 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 175 }; 176 177 struct lb_port_stats { 178 u64 octets; 179 u64 frames; 180 u64 bcast_frames; 181 u64 mcast_frames; 182 u64 ucast_frames; 183 u64 error_frames; 184 185 u64 frames_64; 186 u64 frames_65_127; 187 u64 frames_128_255; 188 u64 frames_256_511; 189 u64 frames_512_1023; 190 u64 frames_1024_1518; 191 u64 frames_1519_max; 192 193 u64 drop; 194 195 u64 ovflow0; 196 u64 ovflow1; 197 u64 ovflow2; 198 u64 ovflow3; 199 u64 trunc0; 200 u64 trunc1; 201 u64 trunc2; 202 u64 trunc3; 203 }; 204 205 struct tp_tcp_stats { 206 u32 tcpOutRsts; 207 u64 tcpInSegs; 208 u64 tcpOutSegs; 209 u64 tcpRetransSegs; 210 }; 211 212 struct tp_err_stats { 213 u32 macInErrs[4]; 214 u32 hdrInErrs[4]; 215 u32 tcpInErrs[4]; 216 u32 tnlCongDrops[4]; 217 u32 ofldChanDrops[4]; 218 u32 tnlTxDrops[4]; 219 u32 ofldVlanDrops[4]; 220 u32 tcp6InErrs[4]; 221 u32 ofldNoNeigh; 222 u32 ofldCongDefer; 223 }; 224 225 struct sge_params { 226 u32 hps; /* host page size for our PF/VF */ 227 u32 eq_qpp; /* egress queues/page for our PF/VF */ 228 u32 iq_qpp; /* egress queues/page for our PF/VF */ 229 }; 230 231 struct tp_params { 232 unsigned int ntxchan; /* # of Tx channels */ 233 unsigned int tre; /* log2 of core clocks per TP tick */ 234 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 235 /* channel map */ 236 237 uint32_t dack_re; /* DACK timer resolution */ 238 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 239 240 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 241 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 242 243 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 244 * subset of the set of fields which may be present in the Compressed 245 * Filter Tuple portion of filters and TCP TCB connections. The 246 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 247 * Since a variable number of fields may or may not be present, their 248 * shifted field positions within the Compressed Filter Tuple may 249 * vary, or not even be present if the field isn't selected in 250 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 251 * places we store their offsets here, or a -1 if the field isn't 252 * present. 253 */ 254 int vlan_shift; 255 int vnic_shift; 256 int port_shift; 257 int protocol_shift; 258 }; 259 260 struct vpd_params { 261 unsigned int cclk; 262 u8 ec[EC_LEN + 1]; 263 u8 sn[SERNUM_LEN + 1]; 264 u8 id[ID_LEN + 1]; 265 u8 pn[PN_LEN + 1]; 266 }; 267 268 struct pci_params { 269 unsigned char speed; 270 unsigned char width; 271 }; 272 273 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) 274 #define CHELSIO_CHIP_FPGA 0x100 275 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) 276 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) 277 278 #define CHELSIO_T4 0x4 279 #define CHELSIO_T5 0x5 280 281 enum chip_type { 282 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 283 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), 284 T4_FIRST_REV = T4_A1, 285 T4_LAST_REV = T4_A2, 286 287 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 288 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), 289 T5_FIRST_REV = T5_A0, 290 T5_LAST_REV = T5_A1, 291 }; 292 293 struct adapter_params { 294 struct sge_params sge; 295 struct tp_params tp; 296 struct vpd_params vpd; 297 struct pci_params pci; 298 299 unsigned int sf_size; /* serial flash size in bytes */ 300 unsigned int sf_nsec; /* # of flash sectors */ 301 unsigned int sf_fw_start; /* start of FW image in flash */ 302 303 unsigned int fw_vers; 304 unsigned int tp_vers; 305 u8 api_vers[7]; 306 307 unsigned short mtus[NMTUS]; 308 unsigned short a_wnd[NCCTRL_WIN]; 309 unsigned short b_wnd[NCCTRL_WIN]; 310 311 unsigned char nports; /* # of ethernet ports */ 312 unsigned char portvec; 313 enum chip_type chip; /* chip code */ 314 unsigned char offload; 315 316 unsigned char bypass; 317 318 unsigned int ofldq_wr_cred; 319 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 320 321 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 322 unsigned int max_ird_adapter; /* Max read depth per adapter */ 323 }; 324 325 #include "t4fw_api.h" 326 327 #define FW_VERSION(chip) ( \ 328 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 329 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 330 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 331 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 332 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 333 334 struct fw_info { 335 u8 chip; 336 char *fs_name; 337 char *fw_mod_name; 338 struct fw_hdr fw_hdr; 339 }; 340 341 342 struct trace_params { 343 u32 data[TRACE_LEN / 4]; 344 u32 mask[TRACE_LEN / 4]; 345 unsigned short snap_len; 346 unsigned short min_len; 347 unsigned char skip_ofst; 348 unsigned char skip_len; 349 unsigned char invert; 350 unsigned char port; 351 }; 352 353 struct link_config { 354 unsigned short supported; /* link capabilities */ 355 unsigned short advertising; /* advertised capabilities */ 356 unsigned short requested_speed; /* speed user has requested */ 357 unsigned short speed; /* actual link speed */ 358 unsigned char requested_fc; /* flow control user has requested */ 359 unsigned char fc; /* actual link flow control */ 360 unsigned char autoneg; /* autonegotiating? */ 361 unsigned char link_ok; /* link up? */ 362 }; 363 364 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 365 366 enum { 367 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 368 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 369 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 370 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 371 MAX_RDMA_CIQS = NCHAN, /* # of RDMA concentrator IQs */ 372 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */ 373 }; 374 375 enum { 376 INGQ_EXTRAS = 2, /* firmware event queue and */ 377 /* forwarded interrupts */ 378 MAX_EGRQ = MAX_ETH_QSETS*2 + MAX_OFLD_QSETS*2 379 + MAX_CTRL_QUEUES + MAX_RDMA_QUEUES + MAX_ISCSI_QUEUES, 380 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES 381 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS, 382 }; 383 384 struct adapter; 385 struct sge_rspq; 386 387 #include "cxgb4_dcb.h" 388 389 struct port_info { 390 struct adapter *adapter; 391 u16 viid; 392 s16 xact_addr_filt; /* index of exact MAC address filter */ 393 u16 rss_size; /* size of VI's RSS table slice */ 394 s8 mdio_addr; 395 enum fw_port_type port_type; 396 u8 mod_type; 397 u8 port_id; 398 u8 tx_chan; 399 u8 lport; /* associated offload logical port */ 400 u8 nqsets; /* # of qsets */ 401 u8 first_qset; /* index of first qset */ 402 u8 rss_mode; 403 struct link_config link_cfg; 404 u16 *rss; 405 #ifdef CONFIG_CHELSIO_T4_DCB 406 struct port_dcb_info dcb; /* Data Center Bridging support */ 407 #endif 408 }; 409 410 struct dentry; 411 struct work_struct; 412 413 enum { /* adapter flags */ 414 FULL_INIT_DONE = (1 << 0), 415 DEV_ENABLED = (1 << 1), 416 USING_MSI = (1 << 2), 417 USING_MSIX = (1 << 3), 418 FW_OK = (1 << 4), 419 RSS_TNLALLLOOKUP = (1 << 5), 420 USING_SOFT_PARAMS = (1 << 6), 421 MASTER_PF = (1 << 7), 422 FW_OFLD_CONN = (1 << 9), 423 }; 424 425 struct rx_sw_desc; 426 427 struct sge_fl { /* SGE free-buffer queue state */ 428 unsigned int avail; /* # of available Rx buffers */ 429 unsigned int pend_cred; /* new buffers since last FL DB ring */ 430 unsigned int cidx; /* consumer index */ 431 unsigned int pidx; /* producer index */ 432 unsigned long alloc_failed; /* # of times buffer allocation failed */ 433 unsigned long large_alloc_failed; 434 unsigned long starving; 435 /* RO fields */ 436 unsigned int cntxt_id; /* SGE context id for the free list */ 437 unsigned int size; /* capacity of free list */ 438 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 439 __be64 *desc; /* address of HW Rx descriptor ring */ 440 dma_addr_t addr; /* bus address of HW ring start */ 441 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 442 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 443 }; 444 445 /* A packet gather list */ 446 struct pkt_gl { 447 struct page_frag frags[MAX_SKB_FRAGS]; 448 void *va; /* virtual address of first byte */ 449 unsigned int nfrags; /* # of fragments */ 450 unsigned int tot_len; /* total length of fragments */ 451 }; 452 453 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 454 const struct pkt_gl *gl); 455 456 struct sge_rspq { /* state for an SGE response queue */ 457 struct napi_struct napi; 458 const __be64 *cur_desc; /* current descriptor in queue */ 459 unsigned int cidx; /* consumer index */ 460 u8 gen; /* current generation bit */ 461 u8 intr_params; /* interrupt holdoff parameters */ 462 u8 next_intr_params; /* holdoff params for next interrupt */ 463 u8 adaptive_rx; 464 u8 pktcnt_idx; /* interrupt packet threshold */ 465 u8 uld; /* ULD handling this queue */ 466 u8 idx; /* queue index within its group */ 467 int offset; /* offset into current Rx buffer */ 468 u16 cntxt_id; /* SGE context id for the response q */ 469 u16 abs_id; /* absolute SGE id for the response q */ 470 __be64 *desc; /* address of HW response ring */ 471 dma_addr_t phys_addr; /* physical address of the ring */ 472 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 473 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 474 unsigned int iqe_len; /* entry size */ 475 unsigned int size; /* capacity of response queue */ 476 struct adapter *adap; 477 struct net_device *netdev; /* associated net device */ 478 rspq_handler_t handler; 479 }; 480 481 struct sge_eth_stats { /* Ethernet queue statistics */ 482 unsigned long pkts; /* # of ethernet packets */ 483 unsigned long lro_pkts; /* # of LRO super packets */ 484 unsigned long lro_merged; /* # of wire packets merged by LRO */ 485 unsigned long rx_cso; /* # of Rx checksum offloads */ 486 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 487 unsigned long rx_drops; /* # of packets dropped due to no mem */ 488 }; 489 490 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 491 struct sge_rspq rspq; 492 struct sge_fl fl; 493 struct sge_eth_stats stats; 494 } ____cacheline_aligned_in_smp; 495 496 struct sge_ofld_stats { /* offload queue statistics */ 497 unsigned long pkts; /* # of packets */ 498 unsigned long imm; /* # of immediate-data packets */ 499 unsigned long an; /* # of asynchronous notifications */ 500 unsigned long nomem; /* # of responses deferred due to no mem */ 501 }; 502 503 struct sge_ofld_rxq { /* SW offload Rx queue */ 504 struct sge_rspq rspq; 505 struct sge_fl fl; 506 struct sge_ofld_stats stats; 507 } ____cacheline_aligned_in_smp; 508 509 struct tx_desc { 510 __be64 flit[8]; 511 }; 512 513 struct tx_sw_desc; 514 515 struct sge_txq { 516 unsigned int in_use; /* # of in-use Tx descriptors */ 517 unsigned int size; /* # of descriptors */ 518 unsigned int cidx; /* SW consumer index */ 519 unsigned int pidx; /* producer index */ 520 unsigned long stops; /* # of times q has been stopped */ 521 unsigned long restarts; /* # of queue restarts */ 522 unsigned int cntxt_id; /* SGE context id for the Tx q */ 523 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 524 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 525 struct sge_qstat *stat; /* queue status entry */ 526 dma_addr_t phys_addr; /* physical address of the ring */ 527 spinlock_t db_lock; 528 int db_disabled; 529 unsigned short db_pidx; 530 unsigned short db_pidx_inc; 531 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 532 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 533 }; 534 535 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 536 struct sge_txq q; 537 struct netdev_queue *txq; /* associated netdev TX queue */ 538 #ifdef CONFIG_CHELSIO_T4_DCB 539 u8 dcb_prio; /* DCB Priority bound to queue */ 540 #endif 541 unsigned long tso; /* # of TSO requests */ 542 unsigned long tx_cso; /* # of Tx checksum offloads */ 543 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 544 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 545 } ____cacheline_aligned_in_smp; 546 547 struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 548 struct sge_txq q; 549 struct adapter *adap; 550 struct sk_buff_head sendq; /* list of backpressured packets */ 551 struct tasklet_struct qresume_tsk; /* restarts the queue */ 552 u8 full; /* the Tx ring is full */ 553 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 554 } ____cacheline_aligned_in_smp; 555 556 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 557 struct sge_txq q; 558 struct adapter *adap; 559 struct sk_buff_head sendq; /* list of backpressured packets */ 560 struct tasklet_struct qresume_tsk; /* restarts the queue */ 561 u8 full; /* the Tx ring is full */ 562 } ____cacheline_aligned_in_smp; 563 564 struct sge { 565 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 566 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 567 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 568 569 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 570 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 571 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 572 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 573 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 574 575 struct sge_rspq intrq ____cacheline_aligned_in_smp; 576 spinlock_t intrq_lock; 577 578 u16 max_ethqsets; /* # of available Ethernet queue sets */ 579 u16 ethqsets; /* # of active Ethernet queue sets */ 580 u16 ethtxq_rover; /* Tx queue to clean up next */ 581 u16 ofldqsets; /* # of active offload queue sets */ 582 u16 rdmaqs; /* # of available RDMA Rx queues */ 583 u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 584 u16 ofld_rxq[MAX_OFLD_QSETS]; 585 u16 rdma_rxq[NCHAN]; 586 u16 rdma_ciq[NCHAN]; 587 u16 timer_val[SGE_NTIMERS]; 588 u8 counter_val[SGE_NCOUNTERS]; 589 u32 fl_pg_order; /* large page allocation size */ 590 u32 stat_len; /* length of status page at ring end */ 591 u32 pktshift; /* padding between CPL & packet data */ 592 u32 fl_align; /* response queue message alignment */ 593 u32 fl_starve_thres; /* Free List starvation threshold */ 594 595 /* State variables for detecting an SGE Ingress DMA hang */ 596 unsigned int idma_1s_thresh;/* SGE same State Counter 1s threshold */ 597 unsigned int idma_stalled[2];/* SGE synthesized stalled timers in HZ */ 598 unsigned int idma_state[2]; /* SGE IDMA Hang detect state */ 599 unsigned int idma_qid[2]; /* SGE IDMA Hung Ingress Queue ID */ 600 601 unsigned int egr_start; 602 unsigned int ingr_start; 603 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */ 604 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */ 605 DECLARE_BITMAP(starving_fl, MAX_EGRQ); 606 DECLARE_BITMAP(txq_maperr, MAX_EGRQ); 607 struct timer_list rx_timer; /* refills starving FLs */ 608 struct timer_list tx_timer; /* checks Tx queues */ 609 }; 610 611 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 612 #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 613 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 614 #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 615 616 struct l2t_data; 617 618 #ifdef CONFIG_PCI_IOV 619 620 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 621 * Configuration initialization for T5 only has SR-IOV functionality enabled 622 * on PF0-3 in order to simplify everything. 623 */ 624 #define NUM_OF_PF_WITH_SRIOV 4 625 626 #endif 627 628 struct adapter { 629 void __iomem *regs; 630 void __iomem *bar2; 631 u32 t4_bar0; 632 struct pci_dev *pdev; 633 struct device *pdev_dev; 634 unsigned int mbox; 635 unsigned int fn; 636 unsigned int flags; 637 enum chip_type chip; 638 639 int msg_enable; 640 641 struct adapter_params params; 642 struct cxgb4_virt_res vres; 643 unsigned int swintr; 644 645 unsigned int wol; 646 647 struct { 648 unsigned short vec; 649 char desc[IFNAMSIZ + 10]; 650 } msix_info[MAX_INGQ + 1]; 651 652 struct sge sge; 653 654 struct net_device *port[MAX_NPORTS]; 655 u8 chan_map[NCHAN]; /* channel -> port map */ 656 657 u32 filter_mode; 658 unsigned int l2t_start; 659 unsigned int l2t_end; 660 struct l2t_data *l2t; 661 void *uld_handle[CXGB4_ULD_MAX]; 662 struct list_head list_node; 663 struct list_head rcu_node; 664 665 struct tid_info tids; 666 void **tid_release_head; 667 spinlock_t tid_release_lock; 668 struct workqueue_struct *workq; 669 struct work_struct tid_release_task; 670 struct work_struct db_full_task; 671 struct work_struct db_drop_task; 672 bool tid_release_task_busy; 673 674 struct dentry *debugfs_root; 675 676 spinlock_t stats_lock; 677 spinlock_t win0_lock ____cacheline_aligned_in_smp; 678 }; 679 680 /* Defined bit width of user definable filter tuples 681 */ 682 #define ETHTYPE_BITWIDTH 16 683 #define FRAG_BITWIDTH 1 684 #define MACIDX_BITWIDTH 9 685 #define FCOE_BITWIDTH 1 686 #define IPORT_BITWIDTH 3 687 #define MATCHTYPE_BITWIDTH 3 688 #define PROTO_BITWIDTH 8 689 #define TOS_BITWIDTH 8 690 #define PF_BITWIDTH 8 691 #define VF_BITWIDTH 8 692 #define IVLAN_BITWIDTH 16 693 #define OVLAN_BITWIDTH 16 694 695 /* Filter matching rules. These consist of a set of ingress packet field 696 * (value, mask) tuples. The associated ingress packet field matches the 697 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 698 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 699 * matches an ingress packet when all of the individual individual field 700 * matching rules are true. 701 * 702 * Partial field masks are always valid, however, while it may be easy to 703 * understand their meanings for some fields (e.g. IP address to match a 704 * subnet), for others making sensible partial masks is less intuitive (e.g. 705 * MPS match type) ... 706 * 707 * Most of the following data structures are modeled on T4 capabilities. 708 * Drivers for earlier chips use the subsets which make sense for those chips. 709 * We really need to come up with a hardware-independent mechanism to 710 * represent hardware filter capabilities ... 711 */ 712 struct ch_filter_tuple { 713 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 714 * register selects which of these fields will participate in the 715 * filter match rules -- up to a maximum of 36 bits. Because 716 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 717 * set of fields. 718 */ 719 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 720 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 721 uint32_t ivlan_vld:1; /* inner VLAN valid */ 722 uint32_t ovlan_vld:1; /* outer VLAN valid */ 723 uint32_t pfvf_vld:1; /* PF/VF valid */ 724 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 725 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 726 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 727 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 728 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 729 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 730 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 731 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 732 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 733 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 734 735 /* Uncompressed header matching field rules. These are always 736 * available for field rules. 737 */ 738 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 739 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 740 uint16_t lport; /* local port */ 741 uint16_t fport; /* foreign port */ 742 }; 743 744 /* A filter ioctl command. 745 */ 746 struct ch_filter_specification { 747 /* Administrative fields for filter. 748 */ 749 uint32_t hitcnts:1; /* count filter hits in TCB */ 750 uint32_t prio:1; /* filter has priority over active/server */ 751 752 /* Fundamental filter typing. This is the one element of filter 753 * matching that doesn't exist as a (value, mask) tuple. 754 */ 755 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 756 757 /* Packet dispatch information. Ingress packets which match the 758 * filter rules will be dropped, passed to the host or switched back 759 * out as egress packets. 760 */ 761 uint32_t action:2; /* drop, pass, switch */ 762 763 uint32_t rpttid:1; /* report TID in RSS hash field */ 764 765 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 766 uint32_t iq:10; /* ingress queue */ 767 768 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 769 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 770 /* 1 => TCB contains IQ ID */ 771 772 /* Switch proxy/rewrite fields. An ingress packet which matches a 773 * filter with "switch" set will be looped back out as an egress 774 * packet -- potentially with some Ethernet header rewriting. 775 */ 776 uint32_t eport:2; /* egress port to switch packet out */ 777 uint32_t newdmac:1; /* rewrite destination MAC address */ 778 uint32_t newsmac:1; /* rewrite source MAC address */ 779 uint32_t newvlan:2; /* rewrite VLAN Tag */ 780 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 781 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 782 uint16_t vlan; /* VLAN Tag to insert */ 783 784 /* Filter rule value/mask pairs. 785 */ 786 struct ch_filter_tuple val; 787 struct ch_filter_tuple mask; 788 }; 789 790 enum { 791 FILTER_PASS = 0, /* default */ 792 FILTER_DROP, 793 FILTER_SWITCH 794 }; 795 796 enum { 797 VLAN_NOCHANGE = 0, /* default */ 798 VLAN_REMOVE, 799 VLAN_INSERT, 800 VLAN_REWRITE 801 }; 802 803 static inline int is_t5(enum chip_type chip) 804 { 805 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5; 806 } 807 808 static inline int is_t4(enum chip_type chip) 809 { 810 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; 811 } 812 813 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 814 { 815 return readl(adap->regs + reg_addr); 816 } 817 818 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 819 { 820 writel(val, adap->regs + reg_addr); 821 } 822 823 #ifndef readq 824 static inline u64 readq(const volatile void __iomem *addr) 825 { 826 return readl(addr) + ((u64)readl(addr + 4) << 32); 827 } 828 829 static inline void writeq(u64 val, volatile void __iomem *addr) 830 { 831 writel(val, addr); 832 writel(val >> 32, addr + 4); 833 } 834 #endif 835 836 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 837 { 838 return readq(adap->regs + reg_addr); 839 } 840 841 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 842 { 843 writeq(val, adap->regs + reg_addr); 844 } 845 846 /** 847 * netdev2pinfo - return the port_info structure associated with a net_device 848 * @dev: the netdev 849 * 850 * Return the struct port_info associated with a net_device 851 */ 852 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 853 { 854 return netdev_priv(dev); 855 } 856 857 /** 858 * adap2pinfo - return the port_info of a port 859 * @adap: the adapter 860 * @idx: the port index 861 * 862 * Return the port_info structure for the port of the given index. 863 */ 864 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 865 { 866 return netdev_priv(adap->port[idx]); 867 } 868 869 /** 870 * netdev2adap - return the adapter structure associated with a net_device 871 * @dev: the netdev 872 * 873 * Return the struct adapter associated with a net_device 874 */ 875 static inline struct adapter *netdev2adap(const struct net_device *dev) 876 { 877 return netdev2pinfo(dev)->adapter; 878 } 879 880 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 881 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 882 883 void *t4_alloc_mem(size_t size); 884 885 void t4_free_sge_resources(struct adapter *adap); 886 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 887 irq_handler_t t4_intr_handler(struct adapter *adap); 888 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 889 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 890 const struct pkt_gl *gl); 891 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 892 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 893 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 894 struct net_device *dev, int intr_idx, 895 struct sge_fl *fl, rspq_handler_t hnd); 896 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 897 struct net_device *dev, struct netdev_queue *netdevq, 898 unsigned int iqid); 899 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 900 struct net_device *dev, unsigned int iqid, 901 unsigned int cmplqid); 902 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 903 struct net_device *dev, unsigned int iqid); 904 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 905 int t4_sge_init(struct adapter *adap); 906 void t4_sge_start(struct adapter *adap); 907 void t4_sge_stop(struct adapter *adap); 908 extern int dbfifo_int_thresh; 909 910 #define for_each_port(adapter, iter) \ 911 for (iter = 0; iter < (adapter)->params.nports; ++iter) 912 913 static inline int is_bypass(struct adapter *adap) 914 { 915 return adap->params.bypass; 916 } 917 918 static inline int is_bypass_device(int device) 919 { 920 /* this should be set based upon device capabilities */ 921 switch (device) { 922 case 0x440b: 923 case 0x440c: 924 return 1; 925 default: 926 return 0; 927 } 928 } 929 930 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 931 { 932 return adap->params.vpd.cclk / 1000; 933 } 934 935 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 936 unsigned int us) 937 { 938 return (us * adap->params.vpd.cclk) / 1000; 939 } 940 941 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 942 unsigned int ticks) 943 { 944 /* add Core Clock / 2 to round ticks to nearest uS */ 945 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 946 adapter->params.vpd.cclk); 947 } 948 949 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 950 u32 val); 951 952 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 953 void *rpl, bool sleep_ok); 954 955 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 956 int size, void *rpl) 957 { 958 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 959 } 960 961 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 962 int size, void *rpl) 963 { 964 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 965 } 966 967 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 968 unsigned int data_reg, const u32 *vals, 969 unsigned int nregs, unsigned int start_idx); 970 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 971 unsigned int data_reg, u32 *vals, unsigned int nregs, 972 unsigned int start_idx); 973 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 974 975 struct fw_filter_wr; 976 977 void t4_intr_enable(struct adapter *adapter); 978 void t4_intr_disable(struct adapter *adapter); 979 int t4_slow_intr_handler(struct adapter *adapter); 980 981 int t4_wait_dev_ready(void __iomem *regs); 982 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 983 struct link_config *lc); 984 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 985 986 #define T4_MEMORY_WRITE 0 987 #define T4_MEMORY_READ 1 988 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 989 __be32 *buf, int dir); 990 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 991 u32 len, __be32 *buf) 992 { 993 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 994 } 995 996 int t4_seeprom_wp(struct adapter *adapter, bool enable); 997 int get_vpd_params(struct adapter *adapter, struct vpd_params *p); 998 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 999 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1000 const u8 *fw_data, unsigned int size, int force); 1001 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1002 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1003 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1004 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1005 const u8 *fw_data, unsigned int fw_size, 1006 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1007 int t4_prep_adapter(struct adapter *adapter); 1008 1009 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1010 int cxgb4_t4_bar2_sge_qregs(struct adapter *adapter, 1011 unsigned int qid, 1012 enum t4_bar2_qtype qtype, 1013 u64 *pbar2_qoffset, 1014 unsigned int *pbar2_qid); 1015 1016 int t4_init_sge_params(struct adapter *adapter); 1017 int t4_init_tp_params(struct adapter *adap); 1018 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1019 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1020 void t4_fatal_err(struct adapter *adapter); 1021 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1022 int start, int n, const u16 *rspq, unsigned int nrspq); 1023 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1024 unsigned int flags); 1025 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 1026 u64 *parity); 1027 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 1028 u64 *parity); 1029 const char *t4_get_port_type_description(enum fw_port_type port_type); 1030 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1031 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1032 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1033 unsigned int mask, unsigned int val); 1034 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1035 struct tp_tcp_stats *v6); 1036 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1037 const unsigned short *alpha, const unsigned short *beta); 1038 1039 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1040 1041 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1042 const u8 *addr); 1043 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1044 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1045 1046 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1047 enum dev_master master, enum dev_state *state); 1048 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1049 int t4_early_init(struct adapter *adap, unsigned int mbox); 1050 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1051 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1052 unsigned int cache_line_size); 1053 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1054 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1055 unsigned int vf, unsigned int nparams, const u32 *params, 1056 u32 *val); 1057 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1058 unsigned int vf, unsigned int nparams, const u32 *params, 1059 const u32 *val); 1060 int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox, 1061 unsigned int pf, unsigned int vf, 1062 unsigned int nparams, const u32 *params, 1063 const u32 *val); 1064 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1065 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1066 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1067 unsigned int vi, unsigned int cmask, unsigned int pmask, 1068 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1069 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1070 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1071 unsigned int *rss_size); 1072 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1073 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1074 bool sleep_ok); 1075 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1076 unsigned int viid, bool free, unsigned int naddr, 1077 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1078 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1079 int idx, const u8 *addr, bool persist, bool add_smt); 1080 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1081 bool ucast, u64 vec, bool sleep_ok); 1082 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1083 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1084 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1085 bool rx_en, bool tx_en); 1086 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1087 unsigned int nblinks); 1088 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1089 unsigned int mmd, unsigned int reg, u16 *valp); 1090 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1091 unsigned int mmd, unsigned int reg, u16 val); 1092 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1093 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1094 unsigned int fl0id, unsigned int fl1id); 1095 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1096 unsigned int vf, unsigned int eqid); 1097 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1098 unsigned int vf, unsigned int eqid); 1099 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1100 unsigned int vf, unsigned int eqid); 1101 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1102 void t4_db_full(struct adapter *adapter); 1103 void t4_db_dropped(struct adapter *adapter); 1104 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1105 u32 addr, u32 val); 1106 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1107 void t4_free_mem(void *addr); 1108 #endif /* __CXGB4_H__ */ 1109