1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <linux/ptp_clock_kernel.h> 52 #include <linux/ptp_classify.h> 53 #include <asm/io.h> 54 #include "t4_chip_type.h" 55 #include "cxgb4_uld.h" 56 57 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 58 extern struct list_head adapter_list; 59 extern struct mutex uld_mutex; 60 61 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 62 * This is the same as calc_tx_descs() for a TSO packet with 63 * nr_frags == MAX_SKB_FRAGS. 64 */ 65 #define ETHTXQ_STOP_THRES \ 66 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 67 68 enum { 69 MAX_NPORTS = 4, /* max # of ports */ 70 SERNUM_LEN = 24, /* Serial # length */ 71 EC_LEN = 16, /* E/C length */ 72 ID_LEN = 16, /* ID length */ 73 PN_LEN = 16, /* Part Number length */ 74 MACADDR_LEN = 12, /* MAC Address length */ 75 }; 76 77 enum { 78 T4_REGMAP_SIZE = (160 * 1024), 79 T5_REGMAP_SIZE = (332 * 1024), 80 }; 81 82 enum { 83 MEM_EDC0, 84 MEM_EDC1, 85 MEM_MC, 86 MEM_MC0 = MEM_MC, 87 MEM_MC1, 88 MEM_HMA, 89 }; 90 91 enum { 92 MEMWIN0_APERTURE = 2048, 93 MEMWIN0_BASE = 0x1b800, 94 MEMWIN1_APERTURE = 32768, 95 MEMWIN1_BASE = 0x28000, 96 MEMWIN1_BASE_T5 = 0x52000, 97 MEMWIN2_APERTURE = 65536, 98 MEMWIN2_BASE = 0x30000, 99 MEMWIN2_APERTURE_T5 = 131072, 100 MEMWIN2_BASE_T5 = 0x60000, 101 }; 102 103 enum dev_master { 104 MASTER_CANT, 105 MASTER_MAY, 106 MASTER_MUST 107 }; 108 109 enum dev_state { 110 DEV_STATE_UNINIT, 111 DEV_STATE_INIT, 112 DEV_STATE_ERR 113 }; 114 115 enum cc_pause { 116 PAUSE_RX = 1 << 0, 117 PAUSE_TX = 1 << 1, 118 PAUSE_AUTONEG = 1 << 2 119 }; 120 121 enum cc_fec { 122 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 123 FEC_RS = 1 << 1, /* Reed-Solomon */ 124 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 125 }; 126 127 struct port_stats { 128 u64 tx_octets; /* total # of octets in good frames */ 129 u64 tx_frames; /* all good frames */ 130 u64 tx_bcast_frames; /* all broadcast frames */ 131 u64 tx_mcast_frames; /* all multicast frames */ 132 u64 tx_ucast_frames; /* all unicast frames */ 133 u64 tx_error_frames; /* all error frames */ 134 135 u64 tx_frames_64; /* # of Tx frames in a particular range */ 136 u64 tx_frames_65_127; 137 u64 tx_frames_128_255; 138 u64 tx_frames_256_511; 139 u64 tx_frames_512_1023; 140 u64 tx_frames_1024_1518; 141 u64 tx_frames_1519_max; 142 143 u64 tx_drop; /* # of dropped Tx frames */ 144 u64 tx_pause; /* # of transmitted pause frames */ 145 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 146 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 147 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 148 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 149 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 150 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 151 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 152 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 153 154 u64 rx_octets; /* total # of octets in good frames */ 155 u64 rx_frames; /* all good frames */ 156 u64 rx_bcast_frames; /* all broadcast frames */ 157 u64 rx_mcast_frames; /* all multicast frames */ 158 u64 rx_ucast_frames; /* all unicast frames */ 159 u64 rx_too_long; /* # of frames exceeding MTU */ 160 u64 rx_jabber; /* # of jabber frames */ 161 u64 rx_fcs_err; /* # of received frames with bad FCS */ 162 u64 rx_len_err; /* # of received frames with length error */ 163 u64 rx_symbol_err; /* symbol errors */ 164 u64 rx_runt; /* # of short frames */ 165 166 u64 rx_frames_64; /* # of Rx frames in a particular range */ 167 u64 rx_frames_65_127; 168 u64 rx_frames_128_255; 169 u64 rx_frames_256_511; 170 u64 rx_frames_512_1023; 171 u64 rx_frames_1024_1518; 172 u64 rx_frames_1519_max; 173 174 u64 rx_pause; /* # of received pause frames */ 175 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 176 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 177 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 178 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 179 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 180 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 181 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 182 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 183 184 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 185 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 186 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 187 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 188 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 189 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 190 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 191 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 192 }; 193 194 struct lb_port_stats { 195 u64 octets; 196 u64 frames; 197 u64 bcast_frames; 198 u64 mcast_frames; 199 u64 ucast_frames; 200 u64 error_frames; 201 202 u64 frames_64; 203 u64 frames_65_127; 204 u64 frames_128_255; 205 u64 frames_256_511; 206 u64 frames_512_1023; 207 u64 frames_1024_1518; 208 u64 frames_1519_max; 209 210 u64 drop; 211 212 u64 ovflow0; 213 u64 ovflow1; 214 u64 ovflow2; 215 u64 ovflow3; 216 u64 trunc0; 217 u64 trunc1; 218 u64 trunc2; 219 u64 trunc3; 220 }; 221 222 struct tp_tcp_stats { 223 u32 tcp_out_rsts; 224 u64 tcp_in_segs; 225 u64 tcp_out_segs; 226 u64 tcp_retrans_segs; 227 }; 228 229 struct tp_usm_stats { 230 u32 frames; 231 u32 drops; 232 u64 octets; 233 }; 234 235 struct tp_fcoe_stats { 236 u32 frames_ddp; 237 u32 frames_drop; 238 u64 octets_ddp; 239 }; 240 241 struct tp_err_stats { 242 u32 mac_in_errs[4]; 243 u32 hdr_in_errs[4]; 244 u32 tcp_in_errs[4]; 245 u32 tnl_cong_drops[4]; 246 u32 ofld_chan_drops[4]; 247 u32 tnl_tx_drops[4]; 248 u32 ofld_vlan_drops[4]; 249 u32 tcp6_in_errs[4]; 250 u32 ofld_no_neigh; 251 u32 ofld_cong_defer; 252 }; 253 254 struct tp_cpl_stats { 255 u32 req[4]; 256 u32 rsp[4]; 257 }; 258 259 struct tp_rdma_stats { 260 u32 rqe_dfr_pkt; 261 u32 rqe_dfr_mod; 262 }; 263 264 struct sge_params { 265 u32 hps; /* host page size for our PF/VF */ 266 u32 eq_qpp; /* egress queues/page for our PF/VF */ 267 u32 iq_qpp; /* egress queues/page for our PF/VF */ 268 }; 269 270 struct tp_params { 271 unsigned int tre; /* log2 of core clocks per TP tick */ 272 unsigned int la_mask; /* what events are recorded by TP LA */ 273 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 274 /* channel map */ 275 276 uint32_t dack_re; /* DACK timer resolution */ 277 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 278 279 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 280 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 281 282 /* cached TP_OUT_CONFIG compressed error vector 283 * and passing outer header info for encapsulated packets. 284 */ 285 int rx_pkt_encap; 286 287 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 288 * subset of the set of fields which may be present in the Compressed 289 * Filter Tuple portion of filters and TCP TCB connections. The 290 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 291 * Since a variable number of fields may or may not be present, their 292 * shifted field positions within the Compressed Filter Tuple may 293 * vary, or not even be present if the field isn't selected in 294 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 295 * places we store their offsets here, or a -1 if the field isn't 296 * present. 297 */ 298 int fcoe_shift; 299 int port_shift; 300 int vnic_shift; 301 int vlan_shift; 302 int tos_shift; 303 int protocol_shift; 304 int ethertype_shift; 305 int macmatch_shift; 306 int matchtype_shift; 307 int frag_shift; 308 309 u64 hash_filter_mask; 310 }; 311 312 struct vpd_params { 313 unsigned int cclk; 314 u8 ec[EC_LEN + 1]; 315 u8 sn[SERNUM_LEN + 1]; 316 u8 id[ID_LEN + 1]; 317 u8 pn[PN_LEN + 1]; 318 u8 na[MACADDR_LEN + 1]; 319 }; 320 321 struct pci_params { 322 unsigned int vpd_cap_addr; 323 unsigned char speed; 324 unsigned char width; 325 }; 326 327 struct devlog_params { 328 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 329 u32 start; /* start of log in firmware memory */ 330 u32 size; /* size of log */ 331 }; 332 333 /* Stores chip specific parameters */ 334 struct arch_specific_params { 335 u8 nchan; 336 u8 pm_stats_cnt; 337 u8 cng_ch_bits_log; /* congestion channel map bits width */ 338 u16 mps_rplc_size; 339 u16 vfcount; 340 u32 sge_fl_db; 341 u16 mps_tcam_size; 342 }; 343 344 struct adapter_params { 345 struct sge_params sge; 346 struct tp_params tp; 347 struct vpd_params vpd; 348 struct pci_params pci; 349 struct devlog_params devlog; 350 enum pcie_memwin drv_memwin; 351 352 unsigned int cim_la_size; 353 354 unsigned int sf_size; /* serial flash size in bytes */ 355 unsigned int sf_nsec; /* # of flash sectors */ 356 357 unsigned int fw_vers; /* firmware version */ 358 unsigned int bs_vers; /* bootstrap version */ 359 unsigned int tp_vers; /* TP microcode version */ 360 unsigned int er_vers; /* expansion ROM version */ 361 unsigned int scfg_vers; /* Serial Configuration version */ 362 unsigned int vpd_vers; /* VPD Version */ 363 u8 api_vers[7]; 364 365 unsigned short mtus[NMTUS]; 366 unsigned short a_wnd[NCCTRL_WIN]; 367 unsigned short b_wnd[NCCTRL_WIN]; 368 369 unsigned char nports; /* # of ethernet ports */ 370 unsigned char portvec; 371 enum chip_type chip; /* chip code */ 372 struct arch_specific_params arch; /* chip specific params */ 373 unsigned char offload; 374 unsigned char crypto; /* HW capability for crypto */ 375 376 unsigned char bypass; 377 unsigned char hash_filter; 378 379 unsigned int ofldq_wr_cred; 380 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 381 382 unsigned int nsched_cls; /* number of traffic classes */ 383 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 384 unsigned int max_ird_adapter; /* Max read depth per adapter */ 385 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 386 u8 fw_caps_support; /* 32-bit Port Capabilities */ 387 bool filter2_wr_support; /* FW support for FILTER2_WR */ 388 389 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 390 * used by the Port 391 */ 392 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 393 }; 394 395 /* State needed to monitor the forward progress of SGE Ingress DMA activities 396 * and possible hangs. 397 */ 398 struct sge_idma_monitor_state { 399 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 400 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 401 unsigned int idma_state[2]; /* IDMA Hang detect state */ 402 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 403 unsigned int idma_warn[2]; /* time to warning in HZ */ 404 }; 405 406 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 407 * The access and execute times are signed in order to accommodate negative 408 * error returns. 409 */ 410 struct mbox_cmd { 411 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 412 u64 timestamp; /* OS-dependent timestamp */ 413 u32 seqno; /* sequence number */ 414 s16 access; /* time (ms) to access mailbox */ 415 s16 execute; /* time (ms) to execute */ 416 }; 417 418 struct mbox_cmd_log { 419 unsigned int size; /* number of entries in the log */ 420 unsigned int cursor; /* next position in the log to write */ 421 u32 seqno; /* next sequence number */ 422 /* variable length mailbox command log starts here */ 423 }; 424 425 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 426 * return a pointer to the specified entry. 427 */ 428 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 429 unsigned int entry_idx) 430 { 431 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 432 } 433 434 #include "t4fw_api.h" 435 436 #define FW_VERSION(chip) ( \ 437 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 438 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 439 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 440 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 441 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 442 443 struct fw_info { 444 u8 chip; 445 char *fs_name; 446 char *fw_mod_name; 447 struct fw_hdr fw_hdr; 448 }; 449 450 struct trace_params { 451 u32 data[TRACE_LEN / 4]; 452 u32 mask[TRACE_LEN / 4]; 453 unsigned short snap_len; 454 unsigned short min_len; 455 unsigned char skip_ofst; 456 unsigned char skip_len; 457 unsigned char invert; 458 unsigned char port; 459 }; 460 461 /* Firmware Port Capabilities types. */ 462 463 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 464 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 465 466 enum fw_caps { 467 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 468 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 469 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 470 }; 471 472 struct link_config { 473 fw_port_cap32_t pcaps; /* link capabilities */ 474 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 475 fw_port_cap32_t acaps; /* advertised capabilities */ 476 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 477 478 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 479 unsigned int speed; /* actual link speed (Mb/s) */ 480 481 enum cc_pause requested_fc; /* flow control user has requested */ 482 enum cc_pause fc; /* actual link flow control */ 483 484 enum cc_fec requested_fec; /* Forward Error Correction: */ 485 enum cc_fec fec; /* requested and actual in use */ 486 487 unsigned char autoneg; /* autonegotiating? */ 488 489 unsigned char link_ok; /* link up? */ 490 unsigned char link_down_rc; /* link down reason */ 491 }; 492 493 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 494 495 enum { 496 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 497 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 498 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 499 }; 500 501 enum { 502 MAX_TXQ_ENTRIES = 16384, 503 MAX_CTRL_TXQ_ENTRIES = 1024, 504 MAX_RSPQ_ENTRIES = 16384, 505 MAX_RX_BUFFERS = 16384, 506 MIN_TXQ_ENTRIES = 32, 507 MIN_CTRL_TXQ_ENTRIES = 32, 508 MIN_RSPQ_ENTRIES = 128, 509 MIN_FL_ENTRIES = 16 510 }; 511 512 enum { 513 INGQ_EXTRAS = 2, /* firmware event queue and */ 514 /* forwarded interrupts */ 515 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 516 }; 517 518 struct adapter; 519 struct sge_rspq; 520 521 #include "cxgb4_dcb.h" 522 523 #ifdef CONFIG_CHELSIO_T4_FCOE 524 #include "cxgb4_fcoe.h" 525 #endif /* CONFIG_CHELSIO_T4_FCOE */ 526 527 struct port_info { 528 struct adapter *adapter; 529 u16 viid; 530 s16 xact_addr_filt; /* index of exact MAC address filter */ 531 u16 rss_size; /* size of VI's RSS table slice */ 532 s8 mdio_addr; 533 enum fw_port_type port_type; 534 u8 mod_type; 535 u8 port_id; 536 u8 tx_chan; 537 u8 lport; /* associated offload logical port */ 538 u8 nqsets; /* # of qsets */ 539 u8 first_qset; /* index of first qset */ 540 u8 rss_mode; 541 struct link_config link_cfg; 542 u16 *rss; 543 struct port_stats stats_base; 544 #ifdef CONFIG_CHELSIO_T4_DCB 545 struct port_dcb_info dcb; /* Data Center Bridging support */ 546 #endif 547 #ifdef CONFIG_CHELSIO_T4_FCOE 548 struct cxgb_fcoe fcoe; 549 #endif /* CONFIG_CHELSIO_T4_FCOE */ 550 bool rxtstamp; /* Enable TS */ 551 struct hwtstamp_config tstamp_config; 552 bool ptp_enable; 553 struct sched_table *sched_tbl; 554 }; 555 556 struct dentry; 557 struct work_struct; 558 559 enum { /* adapter flags */ 560 FULL_INIT_DONE = (1 << 0), 561 DEV_ENABLED = (1 << 1), 562 USING_MSI = (1 << 2), 563 USING_MSIX = (1 << 3), 564 FW_OK = (1 << 4), 565 RSS_TNLALLLOOKUP = (1 << 5), 566 USING_SOFT_PARAMS = (1 << 6), 567 MASTER_PF = (1 << 7), 568 FW_OFLD_CONN = (1 << 9), 569 ROOT_NO_RELAXED_ORDERING = (1 << 10), 570 SHUTTING_DOWN = (1 << 11), 571 }; 572 573 enum { 574 ULP_CRYPTO_LOOKASIDE = 1 << 0, 575 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 576 }; 577 578 struct rx_sw_desc; 579 580 struct sge_fl { /* SGE free-buffer queue state */ 581 unsigned int avail; /* # of available Rx buffers */ 582 unsigned int pend_cred; /* new buffers since last FL DB ring */ 583 unsigned int cidx; /* consumer index */ 584 unsigned int pidx; /* producer index */ 585 unsigned long alloc_failed; /* # of times buffer allocation failed */ 586 unsigned long large_alloc_failed; 587 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 588 unsigned long low; /* # of times momentarily starving */ 589 unsigned long starving; 590 /* RO fields */ 591 unsigned int cntxt_id; /* SGE context id for the free list */ 592 unsigned int size; /* capacity of free list */ 593 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 594 __be64 *desc; /* address of HW Rx descriptor ring */ 595 dma_addr_t addr; /* bus address of HW ring start */ 596 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 597 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 598 }; 599 600 /* A packet gather list */ 601 struct pkt_gl { 602 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 603 struct page_frag frags[MAX_SKB_FRAGS]; 604 void *va; /* virtual address of first byte */ 605 unsigned int nfrags; /* # of fragments */ 606 unsigned int tot_len; /* total length of fragments */ 607 }; 608 609 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 610 const struct pkt_gl *gl); 611 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 612 /* LRO related declarations for ULD */ 613 struct t4_lro_mgr { 614 #define MAX_LRO_SESSIONS 64 615 u8 lro_session_cnt; /* # of sessions to aggregate */ 616 unsigned long lro_pkts; /* # of LRO super packets */ 617 unsigned long lro_merged; /* # of wire packets merged by LRO */ 618 struct sk_buff_head lroq; /* list of aggregated sessions */ 619 }; 620 621 struct sge_rspq { /* state for an SGE response queue */ 622 struct napi_struct napi; 623 const __be64 *cur_desc; /* current descriptor in queue */ 624 unsigned int cidx; /* consumer index */ 625 u8 gen; /* current generation bit */ 626 u8 intr_params; /* interrupt holdoff parameters */ 627 u8 next_intr_params; /* holdoff params for next interrupt */ 628 u8 adaptive_rx; 629 u8 pktcnt_idx; /* interrupt packet threshold */ 630 u8 uld; /* ULD handling this queue */ 631 u8 idx; /* queue index within its group */ 632 int offset; /* offset into current Rx buffer */ 633 u16 cntxt_id; /* SGE context id for the response q */ 634 u16 abs_id; /* absolute SGE id for the response q */ 635 __be64 *desc; /* address of HW response ring */ 636 dma_addr_t phys_addr; /* physical address of the ring */ 637 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 638 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 639 unsigned int iqe_len; /* entry size */ 640 unsigned int size; /* capacity of response queue */ 641 struct adapter *adap; 642 struct net_device *netdev; /* associated net device */ 643 rspq_handler_t handler; 644 rspq_flush_handler_t flush_handler; 645 struct t4_lro_mgr lro_mgr; 646 }; 647 648 struct sge_eth_stats { /* Ethernet queue statistics */ 649 unsigned long pkts; /* # of ethernet packets */ 650 unsigned long lro_pkts; /* # of LRO super packets */ 651 unsigned long lro_merged; /* # of wire packets merged by LRO */ 652 unsigned long rx_cso; /* # of Rx checksum offloads */ 653 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 654 unsigned long rx_drops; /* # of packets dropped due to no mem */ 655 }; 656 657 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 658 struct sge_rspq rspq; 659 struct sge_fl fl; 660 struct sge_eth_stats stats; 661 } ____cacheline_aligned_in_smp; 662 663 struct sge_ofld_stats { /* offload queue statistics */ 664 unsigned long pkts; /* # of packets */ 665 unsigned long imm; /* # of immediate-data packets */ 666 unsigned long an; /* # of asynchronous notifications */ 667 unsigned long nomem; /* # of responses deferred due to no mem */ 668 }; 669 670 struct sge_ofld_rxq { /* SW offload Rx queue */ 671 struct sge_rspq rspq; 672 struct sge_fl fl; 673 struct sge_ofld_stats stats; 674 } ____cacheline_aligned_in_smp; 675 676 struct tx_desc { 677 __be64 flit[8]; 678 }; 679 680 struct tx_sw_desc; 681 682 struct sge_txq { 683 unsigned int in_use; /* # of in-use Tx descriptors */ 684 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 685 unsigned int size; /* # of descriptors */ 686 unsigned int cidx; /* SW consumer index */ 687 unsigned int pidx; /* producer index */ 688 unsigned long stops; /* # of times q has been stopped */ 689 unsigned long restarts; /* # of queue restarts */ 690 unsigned int cntxt_id; /* SGE context id for the Tx q */ 691 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 692 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 693 struct sge_qstat *stat; /* queue status entry */ 694 dma_addr_t phys_addr; /* physical address of the ring */ 695 spinlock_t db_lock; 696 int db_disabled; 697 unsigned short db_pidx; 698 unsigned short db_pidx_inc; 699 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 700 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 701 }; 702 703 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 704 struct sge_txq q; 705 struct netdev_queue *txq; /* associated netdev TX queue */ 706 #ifdef CONFIG_CHELSIO_T4_DCB 707 u8 dcb_prio; /* DCB Priority bound to queue */ 708 #endif 709 unsigned long tso; /* # of TSO requests */ 710 unsigned long tx_cso; /* # of Tx checksum offloads */ 711 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 712 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 713 } ____cacheline_aligned_in_smp; 714 715 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 716 struct sge_txq q; 717 struct adapter *adap; 718 struct sk_buff_head sendq; /* list of backpressured packets */ 719 struct tasklet_struct qresume_tsk; /* restarts the queue */ 720 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 721 u8 full; /* the Tx ring is full */ 722 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 723 } ____cacheline_aligned_in_smp; 724 725 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 726 struct sge_txq q; 727 struct adapter *adap; 728 struct sk_buff_head sendq; /* list of backpressured packets */ 729 struct tasklet_struct qresume_tsk; /* restarts the queue */ 730 u8 full; /* the Tx ring is full */ 731 } ____cacheline_aligned_in_smp; 732 733 struct sge_uld_rxq_info { 734 char name[IFNAMSIZ]; /* name of ULD driver */ 735 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 736 u16 *msix_tbl; /* msix_tbl for uld */ 737 u16 *rspq_id; /* response queue id's of rxq */ 738 u16 nrxq; /* # of ingress uld queues */ 739 u16 nciq; /* # of completion queues */ 740 u8 uld; /* uld type */ 741 }; 742 743 struct sge_uld_txq_info { 744 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 745 atomic_t users; /* num users */ 746 u16 ntxq; /* # of egress uld queues */ 747 }; 748 749 struct sge { 750 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 751 struct sge_eth_txq ptptxq; 752 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 753 754 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 755 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 756 struct sge_uld_rxq_info **uld_rxq_info; 757 struct sge_uld_txq_info **uld_txq_info; 758 759 struct sge_rspq intrq ____cacheline_aligned_in_smp; 760 spinlock_t intrq_lock; 761 762 u16 max_ethqsets; /* # of available Ethernet queue sets */ 763 u16 ethqsets; /* # of active Ethernet queue sets */ 764 u16 ethtxq_rover; /* Tx queue to clean up next */ 765 u16 ofldqsets; /* # of active ofld queue sets */ 766 u16 nqs_per_uld; /* # of Rx queues per ULD */ 767 u16 timer_val[SGE_NTIMERS]; 768 u8 counter_val[SGE_NCOUNTERS]; 769 u32 fl_pg_order; /* large page allocation size */ 770 u32 stat_len; /* length of status page at ring end */ 771 u32 pktshift; /* padding between CPL & packet data */ 772 u32 fl_align; /* response queue message alignment */ 773 u32 fl_starve_thres; /* Free List starvation threshold */ 774 775 struct sge_idma_monitor_state idma_monitor; 776 unsigned int egr_start; 777 unsigned int egr_sz; 778 unsigned int ingr_start; 779 unsigned int ingr_sz; 780 void **egr_map; /* qid->queue egress queue map */ 781 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 782 unsigned long *starving_fl; 783 unsigned long *txq_maperr; 784 unsigned long *blocked_fl; 785 struct timer_list rx_timer; /* refills starving FLs */ 786 struct timer_list tx_timer; /* checks Tx queues */ 787 }; 788 789 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 790 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 791 792 struct l2t_data; 793 794 #ifdef CONFIG_PCI_IOV 795 796 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 797 * Configuration initialization for T5 only has SR-IOV functionality enabled 798 * on PF0-3 in order to simplify everything. 799 */ 800 #define NUM_OF_PF_WITH_SRIOV 4 801 802 #endif 803 804 struct doorbell_stats { 805 u32 db_drop; 806 u32 db_empty; 807 u32 db_full; 808 }; 809 810 struct hash_mac_addr { 811 struct list_head list; 812 u8 addr[ETH_ALEN]; 813 }; 814 815 struct uld_msix_bmap { 816 unsigned long *msix_bmap; 817 unsigned int mapsize; 818 spinlock_t lock; /* lock for acquiring bitmap */ 819 }; 820 821 struct uld_msix_info { 822 unsigned short vec; 823 char desc[IFNAMSIZ + 10]; 824 unsigned int idx; 825 }; 826 827 struct vf_info { 828 unsigned char vf_mac_addr[ETH_ALEN]; 829 unsigned int tx_rate; 830 bool pf_set_mac; 831 u16 vlan; 832 }; 833 834 struct mbox_list { 835 struct list_head list; 836 }; 837 838 struct mps_encap_entry { 839 atomic_t refcnt; 840 }; 841 842 struct adapter { 843 void __iomem *regs; 844 void __iomem *bar2; 845 u32 t4_bar0; 846 struct pci_dev *pdev; 847 struct device *pdev_dev; 848 const char *name; 849 unsigned int mbox; 850 unsigned int pf; 851 unsigned int flags; 852 unsigned int adap_idx; 853 enum chip_type chip; 854 855 int msg_enable; 856 __be16 vxlan_port; 857 u8 vxlan_port_cnt; 858 __be16 geneve_port; 859 u8 geneve_port_cnt; 860 861 struct adapter_params params; 862 struct cxgb4_virt_res vres; 863 unsigned int swintr; 864 865 struct { 866 unsigned short vec; 867 char desc[IFNAMSIZ + 10]; 868 } msix_info[MAX_INGQ + 1]; 869 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 870 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 871 int msi_idx; 872 873 struct doorbell_stats db_stats; 874 struct sge sge; 875 876 struct net_device *port[MAX_NPORTS]; 877 u8 chan_map[NCHAN]; /* channel -> port map */ 878 879 struct vf_info *vfinfo; 880 u8 num_vfs; 881 882 u32 filter_mode; 883 unsigned int l2t_start; 884 unsigned int l2t_end; 885 struct l2t_data *l2t; 886 unsigned int clipt_start; 887 unsigned int clipt_end; 888 struct clip_tbl *clipt; 889 unsigned int rawf_start; 890 unsigned int rawf_cnt; 891 struct smt_data *smt; 892 struct mps_encap_entry *mps_encap; 893 struct cxgb4_uld_info *uld; 894 void *uld_handle[CXGB4_ULD_MAX]; 895 unsigned int num_uld; 896 unsigned int num_ofld_uld; 897 struct list_head list_node; 898 struct list_head rcu_node; 899 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 900 901 void *iscsi_ppm; 902 903 struct tid_info tids; 904 void **tid_release_head; 905 spinlock_t tid_release_lock; 906 struct workqueue_struct *workq; 907 struct work_struct tid_release_task; 908 struct work_struct db_full_task; 909 struct work_struct db_drop_task; 910 bool tid_release_task_busy; 911 912 /* lock for mailbox cmd list */ 913 spinlock_t mbox_lock; 914 struct mbox_list mlist; 915 916 /* support for mailbox command/reply logging */ 917 #define T4_OS_LOG_MBOX_CMDS 256 918 struct mbox_cmd_log *mbox_log; 919 920 struct mutex uld_mutex; 921 922 struct dentry *debugfs_root; 923 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 924 bool trace_rss; /* 1 implies that different RSS flit per filter is 925 * used per filter else if 0 default RSS flit is 926 * used for all 4 filters. 927 */ 928 929 struct ptp_clock *ptp_clock; 930 struct ptp_clock_info ptp_clock_info; 931 struct sk_buff *ptp_tx_skb; 932 /* ptp lock */ 933 spinlock_t ptp_lock; 934 spinlock_t stats_lock; 935 spinlock_t win0_lock ____cacheline_aligned_in_smp; 936 937 /* TC u32 offload */ 938 struct cxgb4_tc_u32_table *tc_u32; 939 struct chcr_stats_debug chcr_stats; 940 941 /* TC flower offload */ 942 struct rhashtable flower_tbl; 943 struct rhashtable_params flower_ht_params; 944 struct timer_list flower_stats_timer; 945 struct work_struct flower_stats_work; 946 947 /* Ethtool Dump */ 948 struct ethtool_dump eth_dump; 949 }; 950 951 /* Support for "sched-class" command to allow a TX Scheduling Class to be 952 * programmed with various parameters. 953 */ 954 struct ch_sched_params { 955 s8 type; /* packet or flow */ 956 union { 957 struct { 958 s8 level; /* scheduler hierarchy level */ 959 s8 mode; /* per-class or per-flow */ 960 s8 rateunit; /* bit or packet rate */ 961 s8 ratemode; /* %port relative or kbps absolute */ 962 s8 channel; /* scheduler channel [0..N] */ 963 s8 class; /* scheduler class [0..N] */ 964 s32 minrate; /* minimum rate */ 965 s32 maxrate; /* maximum rate */ 966 s16 weight; /* percent weight */ 967 s16 pktsize; /* average packet size */ 968 } params; 969 } u; 970 }; 971 972 enum { 973 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 974 }; 975 976 enum { 977 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 978 }; 979 980 enum { 981 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 982 }; 983 984 enum { 985 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 986 }; 987 988 enum { 989 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 990 }; 991 992 struct tx_sw_desc { /* SW state per Tx descriptor */ 993 struct sk_buff *skb; 994 struct ulptx_sgl *sgl; 995 }; 996 997 /* Support for "sched_queue" command to allow one or more NIC TX Queues 998 * to be bound to a TX Scheduling Class. 999 */ 1000 struct ch_sched_queue { 1001 s8 queue; /* queue index */ 1002 s8 class; /* class index */ 1003 }; 1004 1005 /* Defined bit width of user definable filter tuples 1006 */ 1007 #define ETHTYPE_BITWIDTH 16 1008 #define FRAG_BITWIDTH 1 1009 #define MACIDX_BITWIDTH 9 1010 #define FCOE_BITWIDTH 1 1011 #define IPORT_BITWIDTH 3 1012 #define MATCHTYPE_BITWIDTH 3 1013 #define PROTO_BITWIDTH 8 1014 #define TOS_BITWIDTH 8 1015 #define PF_BITWIDTH 8 1016 #define VF_BITWIDTH 8 1017 #define IVLAN_BITWIDTH 16 1018 #define OVLAN_BITWIDTH 16 1019 1020 /* Filter matching rules. These consist of a set of ingress packet field 1021 * (value, mask) tuples. The associated ingress packet field matches the 1022 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1023 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1024 * matches an ingress packet when all of the individual individual field 1025 * matching rules are true. 1026 * 1027 * Partial field masks are always valid, however, while it may be easy to 1028 * understand their meanings for some fields (e.g. IP address to match a 1029 * subnet), for others making sensible partial masks is less intuitive (e.g. 1030 * MPS match type) ... 1031 * 1032 * Most of the following data structures are modeled on T4 capabilities. 1033 * Drivers for earlier chips use the subsets which make sense for those chips. 1034 * We really need to come up with a hardware-independent mechanism to 1035 * represent hardware filter capabilities ... 1036 */ 1037 struct ch_filter_tuple { 1038 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1039 * register selects which of these fields will participate in the 1040 * filter match rules -- up to a maximum of 36 bits. Because 1041 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1042 * set of fields. 1043 */ 1044 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1045 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1046 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1047 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1048 uint32_t pfvf_vld:1; /* PF/VF valid */ 1049 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1050 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1051 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1052 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1053 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1054 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1055 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1056 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1057 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1058 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1059 1060 /* Uncompressed header matching field rules. These are always 1061 * available for field rules. 1062 */ 1063 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1064 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1065 uint16_t lport; /* local port */ 1066 uint16_t fport; /* foreign port */ 1067 }; 1068 1069 /* A filter ioctl command. 1070 */ 1071 struct ch_filter_specification { 1072 /* Administrative fields for filter. 1073 */ 1074 uint32_t hitcnts:1; /* count filter hits in TCB */ 1075 uint32_t prio:1; /* filter has priority over active/server */ 1076 1077 /* Fundamental filter typing. This is the one element of filter 1078 * matching that doesn't exist as a (value, mask) tuple. 1079 */ 1080 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1081 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1082 1083 /* Packet dispatch information. Ingress packets which match the 1084 * filter rules will be dropped, passed to the host or switched back 1085 * out as egress packets. 1086 */ 1087 uint32_t action:2; /* drop, pass, switch */ 1088 1089 uint32_t rpttid:1; /* report TID in RSS hash field */ 1090 1091 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1092 uint32_t iq:10; /* ingress queue */ 1093 1094 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1095 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1096 /* 1 => TCB contains IQ ID */ 1097 1098 /* Switch proxy/rewrite fields. An ingress packet which matches a 1099 * filter with "switch" set will be looped back out as an egress 1100 * packet -- potentially with some Ethernet header rewriting. 1101 */ 1102 uint32_t eport:2; /* egress port to switch packet out */ 1103 uint32_t newdmac:1; /* rewrite destination MAC address */ 1104 uint32_t newsmac:1; /* rewrite source MAC address */ 1105 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1106 uint32_t nat_mode:3; /* specify NAT operation mode */ 1107 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1108 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1109 uint16_t vlan; /* VLAN Tag to insert */ 1110 1111 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1112 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1113 u16 nat_lport; /* local port to use after NAT'ing */ 1114 u16 nat_fport; /* foreign port to use after NAT'ing */ 1115 1116 /* reservation for future additions */ 1117 u8 rsvd[24]; 1118 1119 /* Filter rule value/mask pairs. 1120 */ 1121 struct ch_filter_tuple val; 1122 struct ch_filter_tuple mask; 1123 }; 1124 1125 enum { 1126 FILTER_PASS = 0, /* default */ 1127 FILTER_DROP, 1128 FILTER_SWITCH 1129 }; 1130 1131 enum { 1132 VLAN_NOCHANGE = 0, /* default */ 1133 VLAN_REMOVE, 1134 VLAN_INSERT, 1135 VLAN_REWRITE 1136 }; 1137 1138 enum { 1139 NAT_MODE_NONE = 0, /* No NAT performed */ 1140 NAT_MODE_DIP, /* NAT on Dst IP */ 1141 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1142 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1143 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1144 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1145 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1146 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1147 }; 1148 1149 /* Host shadow copy of ingress filter entry. This is in host native format 1150 * and doesn't match the ordering or bit order, etc. of the hardware of the 1151 * firmware command. The use of bit-field structure elements is purely to 1152 * remind ourselves of the field size limitations and save memory in the case 1153 * where the filter table is large. 1154 */ 1155 struct filter_entry { 1156 /* Administrative fields for filter. */ 1157 u32 valid:1; /* filter allocated and valid */ 1158 u32 locked:1; /* filter is administratively locked */ 1159 1160 u32 pending:1; /* filter action is pending firmware reply */ 1161 struct filter_ctx *ctx; /* Caller's completion hook */ 1162 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1163 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1164 struct net_device *dev; /* Associated net device */ 1165 u32 tid; /* This will store the actual tid */ 1166 1167 /* The filter itself. Most of this is a straight copy of information 1168 * provided by the extended ioctl(). Some fields are translated to 1169 * internal forms -- for instance the Ingress Queue ID passed in from 1170 * the ioctl() is translated into the Absolute Ingress Queue ID. 1171 */ 1172 struct ch_filter_specification fs; 1173 }; 1174 1175 static inline int is_offload(const struct adapter *adap) 1176 { 1177 return adap->params.offload; 1178 } 1179 1180 static inline int is_hashfilter(const struct adapter *adap) 1181 { 1182 return adap->params.hash_filter; 1183 } 1184 1185 static inline int is_pci_uld(const struct adapter *adap) 1186 { 1187 return adap->params.crypto; 1188 } 1189 1190 static inline int is_uld(const struct adapter *adap) 1191 { 1192 return (adap->params.offload || adap->params.crypto); 1193 } 1194 1195 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1196 { 1197 return readl(adap->regs + reg_addr); 1198 } 1199 1200 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1201 { 1202 writel(val, adap->regs + reg_addr); 1203 } 1204 1205 #ifndef readq 1206 static inline u64 readq(const volatile void __iomem *addr) 1207 { 1208 return readl(addr) + ((u64)readl(addr + 4) << 32); 1209 } 1210 1211 static inline void writeq(u64 val, volatile void __iomem *addr) 1212 { 1213 writel(val, addr); 1214 writel(val >> 32, addr + 4); 1215 } 1216 #endif 1217 1218 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1219 { 1220 return readq(adap->regs + reg_addr); 1221 } 1222 1223 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1224 { 1225 writeq(val, adap->regs + reg_addr); 1226 } 1227 1228 /** 1229 * t4_set_hw_addr - store a port's MAC address in SW 1230 * @adapter: the adapter 1231 * @port_idx: the port index 1232 * @hw_addr: the Ethernet address 1233 * 1234 * Store the Ethernet address of the given port in SW. Called by the common 1235 * code when it retrieves a port's Ethernet address from EEPROM. 1236 */ 1237 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1238 u8 hw_addr[]) 1239 { 1240 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1241 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1242 } 1243 1244 /** 1245 * netdev2pinfo - return the port_info structure associated with a net_device 1246 * @dev: the netdev 1247 * 1248 * Return the struct port_info associated with a net_device 1249 */ 1250 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1251 { 1252 return netdev_priv(dev); 1253 } 1254 1255 /** 1256 * adap2pinfo - return the port_info of a port 1257 * @adap: the adapter 1258 * @idx: the port index 1259 * 1260 * Return the port_info structure for the port of the given index. 1261 */ 1262 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1263 { 1264 return netdev_priv(adap->port[idx]); 1265 } 1266 1267 /** 1268 * netdev2adap - return the adapter structure associated with a net_device 1269 * @dev: the netdev 1270 * 1271 * Return the struct adapter associated with a net_device 1272 */ 1273 static inline struct adapter *netdev2adap(const struct net_device *dev) 1274 { 1275 return netdev2pinfo(dev)->adapter; 1276 } 1277 1278 /* Return a version number to identify the type of adapter. The scheme is: 1279 * - bits 0..9: chip version 1280 * - bits 10..15: chip revision 1281 * - bits 16..23: register dump version 1282 */ 1283 static inline unsigned int mk_adap_vers(struct adapter *ap) 1284 { 1285 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1286 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1287 } 1288 1289 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1290 static inline unsigned int qtimer_val(const struct adapter *adap, 1291 const struct sge_rspq *q) 1292 { 1293 unsigned int idx = q->intr_params >> 1; 1294 1295 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1296 } 1297 1298 /* driver version & name used for ethtool_drvinfo */ 1299 extern char cxgb4_driver_name[]; 1300 extern const char cxgb4_driver_version[]; 1301 1302 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1303 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1304 1305 void t4_free_sge_resources(struct adapter *adap); 1306 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1307 irq_handler_t t4_intr_handler(struct adapter *adap); 1308 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1309 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1310 const struct pkt_gl *gl); 1311 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1312 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1313 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1314 struct net_device *dev, int intr_idx, 1315 struct sge_fl *fl, rspq_handler_t hnd, 1316 rspq_flush_handler_t flush_handler, int cong); 1317 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1318 struct net_device *dev, struct netdev_queue *netdevq, 1319 unsigned int iqid); 1320 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1321 struct net_device *dev, unsigned int iqid, 1322 unsigned int cmplqid); 1323 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1324 unsigned int cmplqid); 1325 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1326 struct net_device *dev, unsigned int iqid, 1327 unsigned int uld_type); 1328 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1329 int t4_sge_init(struct adapter *adap); 1330 void t4_sge_start(struct adapter *adap); 1331 void t4_sge_stop(struct adapter *adap); 1332 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1333 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1334 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1335 extern int dbfifo_int_thresh; 1336 1337 #define for_each_port(adapter, iter) \ 1338 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1339 1340 static inline int is_bypass(struct adapter *adap) 1341 { 1342 return adap->params.bypass; 1343 } 1344 1345 static inline int is_bypass_device(int device) 1346 { 1347 /* this should be set based upon device capabilities */ 1348 switch (device) { 1349 case 0x440b: 1350 case 0x440c: 1351 return 1; 1352 default: 1353 return 0; 1354 } 1355 } 1356 1357 static inline int is_10gbt_device(int device) 1358 { 1359 /* this should be set based upon device capabilities */ 1360 switch (device) { 1361 case 0x4409: 1362 case 0x4486: 1363 return 1; 1364 1365 default: 1366 return 0; 1367 } 1368 } 1369 1370 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1371 { 1372 return adap->params.vpd.cclk / 1000; 1373 } 1374 1375 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1376 unsigned int us) 1377 { 1378 return (us * adap->params.vpd.cclk) / 1000; 1379 } 1380 1381 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1382 unsigned int ticks) 1383 { 1384 /* add Core Clock / 2 to round ticks to nearest uS */ 1385 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1386 adapter->params.vpd.cclk); 1387 } 1388 1389 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1390 unsigned int ticks) 1391 { 1392 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1393 } 1394 1395 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1396 u32 val); 1397 1398 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1399 int size, void *rpl, bool sleep_ok, int timeout); 1400 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1401 void *rpl, bool sleep_ok); 1402 1403 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1404 const void *cmd, int size, void *rpl, 1405 int timeout) 1406 { 1407 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1408 timeout); 1409 } 1410 1411 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1412 int size, void *rpl) 1413 { 1414 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1415 } 1416 1417 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1418 int size, void *rpl) 1419 { 1420 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1421 } 1422 1423 /** 1424 * hash_mac_addr - return the hash value of a MAC address 1425 * @addr: the 48-bit Ethernet MAC address 1426 * 1427 * Hashes a MAC address according to the hash function used by HW inexact 1428 * (hash) address matching. 1429 */ 1430 static inline int hash_mac_addr(const u8 *addr) 1431 { 1432 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1433 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1434 1435 a ^= b; 1436 a ^= (a >> 12); 1437 a ^= (a >> 6); 1438 return a & 0x3f; 1439 } 1440 1441 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1442 unsigned int cnt); 1443 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1444 unsigned int us, unsigned int cnt, 1445 unsigned int size, unsigned int iqe_size) 1446 { 1447 q->adap = adap; 1448 cxgb4_set_rspq_intr_params(q, us, cnt); 1449 q->iqe_len = iqe_size; 1450 q->size = size; 1451 } 1452 1453 /** 1454 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1455 * @fw_mod_type: the Firmware Mofule Type 1456 * 1457 * Return whether the Firmware Module Type represents a real Transceiver 1458 * Module/Cable Module Type which has been inserted. 1459 */ 1460 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1461 { 1462 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1463 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1464 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1465 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1466 } 1467 1468 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1469 unsigned int data_reg, const u32 *vals, 1470 unsigned int nregs, unsigned int start_idx); 1471 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1472 unsigned int data_reg, u32 *vals, unsigned int nregs, 1473 unsigned int start_idx); 1474 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1475 1476 struct fw_filter_wr; 1477 1478 void t4_intr_enable(struct adapter *adapter); 1479 void t4_intr_disable(struct adapter *adapter); 1480 int t4_slow_intr_handler(struct adapter *adapter); 1481 1482 int t4_wait_dev_ready(void __iomem *regs); 1483 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1484 struct link_config *lc); 1485 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1486 1487 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1488 u32 t4_get_util_window(struct adapter *adap); 1489 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1490 1491 #define T4_MEMORY_WRITE 0 1492 #define T4_MEMORY_READ 1 1493 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1494 void *buf, int dir); 1495 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1496 u32 len, __be32 *buf) 1497 { 1498 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1499 } 1500 1501 unsigned int t4_get_regs_len(struct adapter *adapter); 1502 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1503 1504 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1505 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1506 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1507 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1508 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1509 unsigned int nwords, u32 *data, int byte_oriented); 1510 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1511 int t4_load_phy_fw(struct adapter *adap, 1512 int win, spinlock_t *lock, 1513 int (*phy_fw_version)(const u8 *, size_t), 1514 const u8 *phy_fw_data, size_t phy_fw_size); 1515 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1516 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1517 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1518 const u8 *fw_data, unsigned int size, int force); 1519 int t4_fl_pkt_align(struct adapter *adap); 1520 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1521 int t4_check_fw_version(struct adapter *adap); 1522 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1523 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1524 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1525 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1526 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1527 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1528 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1529 int t4_get_version_info(struct adapter *adapter); 1530 void t4_dump_version_info(struct adapter *adapter); 1531 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1532 const u8 *fw_data, unsigned int fw_size, 1533 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1534 int t4_prep_adapter(struct adapter *adapter); 1535 int t4_shutdown_adapter(struct adapter *adapter); 1536 1537 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1538 int t4_bar2_sge_qregs(struct adapter *adapter, 1539 unsigned int qid, 1540 enum t4_bar2_qtype qtype, 1541 int user, 1542 u64 *pbar2_qoffset, 1543 unsigned int *pbar2_qid); 1544 1545 unsigned int qtimer_val(const struct adapter *adap, 1546 const struct sge_rspq *q); 1547 1548 int t4_init_devlog_params(struct adapter *adapter); 1549 int t4_init_sge_params(struct adapter *adapter); 1550 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1551 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1552 int t4_init_rss_mode(struct adapter *adap, int mbox); 1553 int t4_init_portinfo(struct port_info *pi, int mbox, 1554 int port, int pf, int vf, u8 mac[]); 1555 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1556 void t4_fatal_err(struct adapter *adapter); 1557 unsigned int t4_chip_rss_size(struct adapter *adapter); 1558 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1559 int start, int n, const u16 *rspq, unsigned int nrspq); 1560 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1561 unsigned int flags); 1562 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1563 unsigned int flags, unsigned int defq); 1564 int t4_read_rss(struct adapter *adapter, u16 *entries); 1565 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1566 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1567 bool sleep_ok); 1568 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1569 u32 *valp, bool sleep_ok); 1570 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1571 u32 *vfl, u32 *vfh, bool sleep_ok); 1572 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1573 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1574 1575 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1576 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1577 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1578 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1579 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1580 size_t n); 1581 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1582 size_t n); 1583 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1584 unsigned int *valp); 1585 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1586 const unsigned int *valp); 1587 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1588 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1589 unsigned int *pif_req_wrptr, 1590 unsigned int *pif_rsp_wrptr); 1591 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1592 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1593 const char *t4_get_port_type_description(enum fw_port_type port_type); 1594 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1595 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1596 struct port_stats *stats, 1597 struct port_stats *offset); 1598 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1599 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1600 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1601 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1602 unsigned int mask, unsigned int val); 1603 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1604 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1605 bool sleep_ok); 1606 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1607 bool sleep_ok); 1608 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1609 bool sleep_ok); 1610 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1611 bool sleep_ok); 1612 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1613 struct tp_tcp_stats *v6, bool sleep_ok); 1614 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1615 struct tp_fcoe_stats *st, bool sleep_ok); 1616 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1617 const unsigned short *alpha, const unsigned short *beta); 1618 1619 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1620 1621 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1622 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1623 1624 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1625 const u8 *addr); 1626 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1627 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1628 1629 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1630 enum dev_master master, enum dev_state *state); 1631 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1632 int t4_early_init(struct adapter *adap, unsigned int mbox); 1633 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1634 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1635 unsigned int cache_line_size); 1636 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1637 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1638 unsigned int vf, unsigned int nparams, const u32 *params, 1639 u32 *val); 1640 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1641 unsigned int vf, unsigned int nparams, const u32 *params, 1642 u32 *val); 1643 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1644 unsigned int vf, unsigned int nparams, const u32 *params, 1645 u32 *val, int rw, bool sleep_ok); 1646 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1647 unsigned int pf, unsigned int vf, 1648 unsigned int nparams, const u32 *params, 1649 const u32 *val, int timeout); 1650 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1651 unsigned int vf, unsigned int nparams, const u32 *params, 1652 const u32 *val); 1653 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1654 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1655 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1656 unsigned int vi, unsigned int cmask, unsigned int pmask, 1657 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1658 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1659 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1660 unsigned int *rss_size); 1661 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1662 unsigned int pf, unsigned int vf, 1663 unsigned int viid); 1664 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1665 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1666 bool sleep_ok); 1667 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1668 const u8 *addr, const u8 *mask, unsigned int idx, 1669 u8 lookup_type, u8 port_id, bool sleep_ok); 1670 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1671 const u8 *addr, const u8 *mask, unsigned int idx, 1672 u8 lookup_type, u8 port_id, bool sleep_ok); 1673 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1674 unsigned int viid, bool free, unsigned int naddr, 1675 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1676 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1677 unsigned int viid, unsigned int naddr, 1678 const u8 **addr, bool sleep_ok); 1679 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1680 int idx, const u8 *addr, bool persist, bool add_smt); 1681 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1682 bool ucast, u64 vec, bool sleep_ok); 1683 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1684 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1685 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1686 bool rx_en, bool tx_en); 1687 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1688 unsigned int nblinks); 1689 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1690 unsigned int mmd, unsigned int reg, u16 *valp); 1691 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1692 unsigned int mmd, unsigned int reg, u16 val); 1693 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1694 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1695 unsigned int fl0id, unsigned int fl1id); 1696 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1697 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1698 unsigned int fl0id, unsigned int fl1id); 1699 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1700 unsigned int vf, unsigned int eqid); 1701 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1702 unsigned int vf, unsigned int eqid); 1703 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1704 unsigned int vf, unsigned int eqid); 1705 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1706 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1707 int t4_update_port_info(struct port_info *pi); 1708 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1709 unsigned int *speedp, unsigned int *mtup); 1710 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1711 void t4_db_full(struct adapter *adapter); 1712 void t4_db_dropped(struct adapter *adapter); 1713 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1714 int filter_index, int enable); 1715 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1716 int filter_index, int *enabled); 1717 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1718 u32 addr, u32 val); 1719 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1720 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1721 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1722 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1723 enum ctxt_type ctype, u32 *data); 1724 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1725 enum ctxt_type ctype, u32 *data); 1726 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1727 int rateunit, int ratemode, int channel, int class, 1728 int minrate, int maxrate, int weight, int pktsize); 1729 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1730 void t4_idma_monitor_init(struct adapter *adapter, 1731 struct sge_idma_monitor_state *idma); 1732 void t4_idma_monitor(struct adapter *adapter, 1733 struct sge_idma_monitor_state *idma, 1734 int hz, int ticks); 1735 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1736 unsigned int naddr, u8 *addr); 1737 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1738 u32 start_index, bool sleep_ok); 1739 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1740 u32 start_index, bool sleep_ok); 1741 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1742 u32 start_index, bool sleep_ok); 1743 1744 void t4_uld_mem_free(struct adapter *adap); 1745 int t4_uld_mem_alloc(struct adapter *adap); 1746 void t4_uld_clean_up(struct adapter *adap); 1747 void t4_register_netevent_notifier(void); 1748 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1749 unsigned int devid, unsigned int offset, 1750 unsigned int len, u8 *buf); 1751 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1752 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1753 unsigned int n, bool unmap); 1754 void free_txq(struct adapter *adap, struct sge_txq *q); 1755 void cxgb4_reclaim_completed_tx(struct adapter *adap, 1756 struct sge_txq *q, bool unmap); 1757 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1758 dma_addr_t *addr); 1759 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1760 void *pos); 1761 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1762 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1763 const dma_addr_t *addr); 1764 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 1765 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 1766 u16 vlan); 1767 #endif /* __CXGB4_H__ */ 1768