1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <asm/io.h> 50 #include "cxgb4_uld.h" 51 52 #define T4FW_VERSION_MAJOR 0x01 53 #define T4FW_VERSION_MINOR 0x09 54 #define T4FW_VERSION_MICRO 0x17 55 #define T4FW_VERSION_BUILD 0x00 56 57 #define T5FW_VERSION_MAJOR 0x01 58 #define T5FW_VERSION_MINOR 0x09 59 #define T5FW_VERSION_MICRO 0x17 60 #define T5FW_VERSION_BUILD 0x00 61 62 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 63 64 enum { 65 MAX_NPORTS = 4, /* max # of ports */ 66 SERNUM_LEN = 24, /* Serial # length */ 67 EC_LEN = 16, /* E/C length */ 68 ID_LEN = 16, /* ID length */ 69 PN_LEN = 16, /* Part Number length */ 70 }; 71 72 enum { 73 MEM_EDC0, 74 MEM_EDC1, 75 MEM_MC, 76 MEM_MC0 = MEM_MC, 77 MEM_MC1 78 }; 79 80 enum { 81 MEMWIN0_APERTURE = 2048, 82 MEMWIN0_BASE = 0x1b800, 83 MEMWIN1_APERTURE = 32768, 84 MEMWIN1_BASE = 0x28000, 85 MEMWIN1_BASE_T5 = 0x52000, 86 MEMWIN2_APERTURE = 65536, 87 MEMWIN2_BASE = 0x30000, 88 MEMWIN2_BASE_T5 = 0x54000, 89 }; 90 91 enum dev_master { 92 MASTER_CANT, 93 MASTER_MAY, 94 MASTER_MUST 95 }; 96 97 enum dev_state { 98 DEV_STATE_UNINIT, 99 DEV_STATE_INIT, 100 DEV_STATE_ERR 101 }; 102 103 enum { 104 PAUSE_RX = 1 << 0, 105 PAUSE_TX = 1 << 1, 106 PAUSE_AUTONEG = 1 << 2 107 }; 108 109 struct port_stats { 110 u64 tx_octets; /* total # of octets in good frames */ 111 u64 tx_frames; /* all good frames */ 112 u64 tx_bcast_frames; /* all broadcast frames */ 113 u64 tx_mcast_frames; /* all multicast frames */ 114 u64 tx_ucast_frames; /* all unicast frames */ 115 u64 tx_error_frames; /* all error frames */ 116 117 u64 tx_frames_64; /* # of Tx frames in a particular range */ 118 u64 tx_frames_65_127; 119 u64 tx_frames_128_255; 120 u64 tx_frames_256_511; 121 u64 tx_frames_512_1023; 122 u64 tx_frames_1024_1518; 123 u64 tx_frames_1519_max; 124 125 u64 tx_drop; /* # of dropped Tx frames */ 126 u64 tx_pause; /* # of transmitted pause frames */ 127 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 128 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 129 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 130 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 131 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 132 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 133 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 134 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 135 136 u64 rx_octets; /* total # of octets in good frames */ 137 u64 rx_frames; /* all good frames */ 138 u64 rx_bcast_frames; /* all broadcast frames */ 139 u64 rx_mcast_frames; /* all multicast frames */ 140 u64 rx_ucast_frames; /* all unicast frames */ 141 u64 rx_too_long; /* # of frames exceeding MTU */ 142 u64 rx_jabber; /* # of jabber frames */ 143 u64 rx_fcs_err; /* # of received frames with bad FCS */ 144 u64 rx_len_err; /* # of received frames with length error */ 145 u64 rx_symbol_err; /* symbol errors */ 146 u64 rx_runt; /* # of short frames */ 147 148 u64 rx_frames_64; /* # of Rx frames in a particular range */ 149 u64 rx_frames_65_127; 150 u64 rx_frames_128_255; 151 u64 rx_frames_256_511; 152 u64 rx_frames_512_1023; 153 u64 rx_frames_1024_1518; 154 u64 rx_frames_1519_max; 155 156 u64 rx_pause; /* # of received pause frames */ 157 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 158 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 159 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 160 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 161 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 162 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 163 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 164 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 165 166 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 167 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 168 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 169 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 170 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 171 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 172 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 173 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 174 }; 175 176 struct lb_port_stats { 177 u64 octets; 178 u64 frames; 179 u64 bcast_frames; 180 u64 mcast_frames; 181 u64 ucast_frames; 182 u64 error_frames; 183 184 u64 frames_64; 185 u64 frames_65_127; 186 u64 frames_128_255; 187 u64 frames_256_511; 188 u64 frames_512_1023; 189 u64 frames_1024_1518; 190 u64 frames_1519_max; 191 192 u64 drop; 193 194 u64 ovflow0; 195 u64 ovflow1; 196 u64 ovflow2; 197 u64 ovflow3; 198 u64 trunc0; 199 u64 trunc1; 200 u64 trunc2; 201 u64 trunc3; 202 }; 203 204 struct tp_tcp_stats { 205 u32 tcpOutRsts; 206 u64 tcpInSegs; 207 u64 tcpOutSegs; 208 u64 tcpRetransSegs; 209 }; 210 211 struct tp_err_stats { 212 u32 macInErrs[4]; 213 u32 hdrInErrs[4]; 214 u32 tcpInErrs[4]; 215 u32 tnlCongDrops[4]; 216 u32 ofldChanDrops[4]; 217 u32 tnlTxDrops[4]; 218 u32 ofldVlanDrops[4]; 219 u32 tcp6InErrs[4]; 220 u32 ofldNoNeigh; 221 u32 ofldCongDefer; 222 }; 223 224 struct tp_params { 225 unsigned int ntxchan; /* # of Tx channels */ 226 unsigned int tre; /* log2 of core clocks per TP tick */ 227 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 228 /* channel map */ 229 230 uint32_t dack_re; /* DACK timer resolution */ 231 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 232 233 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 234 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 235 236 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 237 * subset of the set of fields which may be present in the Compressed 238 * Filter Tuple portion of filters and TCP TCB connections. The 239 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 240 * Since a variable number of fields may or may not be present, their 241 * shifted field positions within the Compressed Filter Tuple may 242 * vary, or not even be present if the field isn't selected in 243 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 244 * places we store their offsets here, or a -1 if the field isn't 245 * present. 246 */ 247 int vlan_shift; 248 int vnic_shift; 249 int port_shift; 250 int protocol_shift; 251 }; 252 253 struct vpd_params { 254 unsigned int cclk; 255 u8 ec[EC_LEN + 1]; 256 u8 sn[SERNUM_LEN + 1]; 257 u8 id[ID_LEN + 1]; 258 u8 pn[PN_LEN + 1]; 259 }; 260 261 struct pci_params { 262 unsigned char speed; 263 unsigned char width; 264 }; 265 266 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) 267 #define CHELSIO_CHIP_FPGA 0x100 268 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) 269 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) 270 271 #define CHELSIO_T4 0x4 272 #define CHELSIO_T5 0x5 273 274 enum chip_type { 275 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 276 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), 277 T4_FIRST_REV = T4_A1, 278 T4_LAST_REV = T4_A2, 279 280 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 281 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), 282 T5_FIRST_REV = T5_A0, 283 T5_LAST_REV = T5_A1, 284 }; 285 286 struct adapter_params { 287 struct tp_params tp; 288 struct vpd_params vpd; 289 struct pci_params pci; 290 291 unsigned int sf_size; /* serial flash size in bytes */ 292 unsigned int sf_nsec; /* # of flash sectors */ 293 unsigned int sf_fw_start; /* start of FW image in flash */ 294 295 unsigned int fw_vers; 296 unsigned int tp_vers; 297 u8 api_vers[7]; 298 299 unsigned short mtus[NMTUS]; 300 unsigned short a_wnd[NCCTRL_WIN]; 301 unsigned short b_wnd[NCCTRL_WIN]; 302 303 unsigned char nports; /* # of ethernet ports */ 304 unsigned char portvec; 305 enum chip_type chip; /* chip code */ 306 unsigned char offload; 307 308 unsigned char bypass; 309 310 unsigned int ofldq_wr_cred; 311 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 312 }; 313 314 #include "t4fw_api.h" 315 316 #define FW_VERSION(chip) ( \ 317 FW_HDR_FW_VER_MAJOR_GET(chip##FW_VERSION_MAJOR) | \ 318 FW_HDR_FW_VER_MINOR_GET(chip##FW_VERSION_MINOR) | \ 319 FW_HDR_FW_VER_MICRO_GET(chip##FW_VERSION_MICRO) | \ 320 FW_HDR_FW_VER_BUILD_GET(chip##FW_VERSION_BUILD)) 321 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 322 323 struct fw_info { 324 u8 chip; 325 char *fs_name; 326 char *fw_mod_name; 327 struct fw_hdr fw_hdr; 328 }; 329 330 331 struct trace_params { 332 u32 data[TRACE_LEN / 4]; 333 u32 mask[TRACE_LEN / 4]; 334 unsigned short snap_len; 335 unsigned short min_len; 336 unsigned char skip_ofst; 337 unsigned char skip_len; 338 unsigned char invert; 339 unsigned char port; 340 }; 341 342 struct link_config { 343 unsigned short supported; /* link capabilities */ 344 unsigned short advertising; /* advertised capabilities */ 345 unsigned short requested_speed; /* speed user has requested */ 346 unsigned short speed; /* actual link speed */ 347 unsigned char requested_fc; /* flow control user has requested */ 348 unsigned char fc; /* actual link flow control */ 349 unsigned char autoneg; /* autonegotiating? */ 350 unsigned char link_ok; /* link up? */ 351 }; 352 353 #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16) 354 355 enum { 356 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 357 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 358 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 359 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 360 }; 361 362 enum { 363 MAX_EGRQ = 128, /* max # of egress queues, including FLs */ 364 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */ 365 }; 366 367 struct adapter; 368 struct sge_rspq; 369 370 struct port_info { 371 struct adapter *adapter; 372 u16 viid; 373 s16 xact_addr_filt; /* index of exact MAC address filter */ 374 u16 rss_size; /* size of VI's RSS table slice */ 375 s8 mdio_addr; 376 u8 port_type; 377 u8 mod_type; 378 u8 port_id; 379 u8 tx_chan; 380 u8 lport; /* associated offload logical port */ 381 u8 nqsets; /* # of qsets */ 382 u8 first_qset; /* index of first qset */ 383 u8 rss_mode; 384 struct link_config link_cfg; 385 u16 *rss; 386 }; 387 388 struct dentry; 389 struct work_struct; 390 391 enum { /* adapter flags */ 392 FULL_INIT_DONE = (1 << 0), 393 DEV_ENABLED = (1 << 1), 394 USING_MSI = (1 << 2), 395 USING_MSIX = (1 << 3), 396 FW_OK = (1 << 4), 397 RSS_TNLALLLOOKUP = (1 << 5), 398 USING_SOFT_PARAMS = (1 << 6), 399 MASTER_PF = (1 << 7), 400 FW_OFLD_CONN = (1 << 9), 401 }; 402 403 struct rx_sw_desc; 404 405 struct sge_fl { /* SGE free-buffer queue state */ 406 unsigned int avail; /* # of available Rx buffers */ 407 unsigned int pend_cred; /* new buffers since last FL DB ring */ 408 unsigned int cidx; /* consumer index */ 409 unsigned int pidx; /* producer index */ 410 unsigned long alloc_failed; /* # of times buffer allocation failed */ 411 unsigned long large_alloc_failed; 412 unsigned long starving; 413 /* RO fields */ 414 unsigned int cntxt_id; /* SGE context id for the free list */ 415 unsigned int size; /* capacity of free list */ 416 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 417 __be64 *desc; /* address of HW Rx descriptor ring */ 418 dma_addr_t addr; /* bus address of HW ring start */ 419 }; 420 421 /* A packet gather list */ 422 struct pkt_gl { 423 struct page_frag frags[MAX_SKB_FRAGS]; 424 void *va; /* virtual address of first byte */ 425 unsigned int nfrags; /* # of fragments */ 426 unsigned int tot_len; /* total length of fragments */ 427 }; 428 429 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 430 const struct pkt_gl *gl); 431 432 struct sge_rspq { /* state for an SGE response queue */ 433 struct napi_struct napi; 434 const __be64 *cur_desc; /* current descriptor in queue */ 435 unsigned int cidx; /* consumer index */ 436 u8 gen; /* current generation bit */ 437 u8 intr_params; /* interrupt holdoff parameters */ 438 u8 next_intr_params; /* holdoff params for next interrupt */ 439 u8 pktcnt_idx; /* interrupt packet threshold */ 440 u8 uld; /* ULD handling this queue */ 441 u8 idx; /* queue index within its group */ 442 int offset; /* offset into current Rx buffer */ 443 u16 cntxt_id; /* SGE context id for the response q */ 444 u16 abs_id; /* absolute SGE id for the response q */ 445 __be64 *desc; /* address of HW response ring */ 446 dma_addr_t phys_addr; /* physical address of the ring */ 447 unsigned int iqe_len; /* entry size */ 448 unsigned int size; /* capacity of response queue */ 449 struct adapter *adap; 450 struct net_device *netdev; /* associated net device */ 451 rspq_handler_t handler; 452 }; 453 454 struct sge_eth_stats { /* Ethernet queue statistics */ 455 unsigned long pkts; /* # of ethernet packets */ 456 unsigned long lro_pkts; /* # of LRO super packets */ 457 unsigned long lro_merged; /* # of wire packets merged by LRO */ 458 unsigned long rx_cso; /* # of Rx checksum offloads */ 459 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 460 unsigned long rx_drops; /* # of packets dropped due to no mem */ 461 }; 462 463 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 464 struct sge_rspq rspq; 465 struct sge_fl fl; 466 struct sge_eth_stats stats; 467 } ____cacheline_aligned_in_smp; 468 469 struct sge_ofld_stats { /* offload queue statistics */ 470 unsigned long pkts; /* # of packets */ 471 unsigned long imm; /* # of immediate-data packets */ 472 unsigned long an; /* # of asynchronous notifications */ 473 unsigned long nomem; /* # of responses deferred due to no mem */ 474 }; 475 476 struct sge_ofld_rxq { /* SW offload Rx queue */ 477 struct sge_rspq rspq; 478 struct sge_fl fl; 479 struct sge_ofld_stats stats; 480 } ____cacheline_aligned_in_smp; 481 482 struct tx_desc { 483 __be64 flit[8]; 484 }; 485 486 struct tx_sw_desc; 487 488 struct sge_txq { 489 unsigned int in_use; /* # of in-use Tx descriptors */ 490 unsigned int size; /* # of descriptors */ 491 unsigned int cidx; /* SW consumer index */ 492 unsigned int pidx; /* producer index */ 493 unsigned long stops; /* # of times q has been stopped */ 494 unsigned long restarts; /* # of queue restarts */ 495 unsigned int cntxt_id; /* SGE context id for the Tx q */ 496 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 497 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 498 struct sge_qstat *stat; /* queue status entry */ 499 dma_addr_t phys_addr; /* physical address of the ring */ 500 spinlock_t db_lock; 501 int db_disabled; 502 unsigned short db_pidx; 503 unsigned short db_pidx_inc; 504 u64 udb; 505 }; 506 507 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 508 struct sge_txq q; 509 struct netdev_queue *txq; /* associated netdev TX queue */ 510 unsigned long tso; /* # of TSO requests */ 511 unsigned long tx_cso; /* # of Tx checksum offloads */ 512 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 513 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 514 } ____cacheline_aligned_in_smp; 515 516 struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 517 struct sge_txq q; 518 struct adapter *adap; 519 struct sk_buff_head sendq; /* list of backpressured packets */ 520 struct tasklet_struct qresume_tsk; /* restarts the queue */ 521 u8 full; /* the Tx ring is full */ 522 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 523 } ____cacheline_aligned_in_smp; 524 525 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 526 struct sge_txq q; 527 struct adapter *adap; 528 struct sk_buff_head sendq; /* list of backpressured packets */ 529 struct tasklet_struct qresume_tsk; /* restarts the queue */ 530 u8 full; /* the Tx ring is full */ 531 } ____cacheline_aligned_in_smp; 532 533 struct sge { 534 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 535 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 536 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 537 538 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 539 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 540 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 541 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 542 543 struct sge_rspq intrq ____cacheline_aligned_in_smp; 544 spinlock_t intrq_lock; 545 546 u16 max_ethqsets; /* # of available Ethernet queue sets */ 547 u16 ethqsets; /* # of active Ethernet queue sets */ 548 u16 ethtxq_rover; /* Tx queue to clean up next */ 549 u16 ofldqsets; /* # of active offload queue sets */ 550 u16 rdmaqs; /* # of available RDMA Rx queues */ 551 u16 ofld_rxq[MAX_OFLD_QSETS]; 552 u16 rdma_rxq[NCHAN]; 553 u16 timer_val[SGE_NTIMERS]; 554 u8 counter_val[SGE_NCOUNTERS]; 555 u32 fl_pg_order; /* large page allocation size */ 556 u32 stat_len; /* length of status page at ring end */ 557 u32 pktshift; /* padding between CPL & packet data */ 558 u32 fl_align; /* response queue message alignment */ 559 u32 fl_starve_thres; /* Free List starvation threshold */ 560 561 /* State variables for detecting an SGE Ingress DMA hang */ 562 unsigned int idma_1s_thresh;/* SGE same State Counter 1s threshold */ 563 unsigned int idma_stalled[2];/* SGE synthesized stalled timers in HZ */ 564 unsigned int idma_state[2]; /* SGE IDMA Hang detect state */ 565 unsigned int idma_qid[2]; /* SGE IDMA Hung Ingress Queue ID */ 566 567 unsigned int egr_start; 568 unsigned int ingr_start; 569 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */ 570 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */ 571 DECLARE_BITMAP(starving_fl, MAX_EGRQ); 572 DECLARE_BITMAP(txq_maperr, MAX_EGRQ); 573 struct timer_list rx_timer; /* refills starving FLs */ 574 struct timer_list tx_timer; /* checks Tx queues */ 575 }; 576 577 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 578 #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 579 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 580 581 struct l2t_data; 582 583 #ifdef CONFIG_PCI_IOV 584 585 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 586 * Configuration initialization for T5 only has SR-IOV functionality enabled 587 * on PF0-3 in order to simplify everything. 588 */ 589 #define NUM_OF_PF_WITH_SRIOV 4 590 591 #endif 592 593 struct adapter { 594 void __iomem *regs; 595 void __iomem *bar2; 596 struct pci_dev *pdev; 597 struct device *pdev_dev; 598 unsigned int mbox; 599 unsigned int fn; 600 unsigned int flags; 601 enum chip_type chip; 602 603 int msg_enable; 604 605 struct adapter_params params; 606 struct cxgb4_virt_res vres; 607 unsigned int swintr; 608 609 unsigned int wol; 610 611 struct { 612 unsigned short vec; 613 char desc[IFNAMSIZ + 10]; 614 } msix_info[MAX_INGQ + 1]; 615 616 struct sge sge; 617 618 struct net_device *port[MAX_NPORTS]; 619 u8 chan_map[NCHAN]; /* channel -> port map */ 620 621 u32 filter_mode; 622 unsigned int l2t_start; 623 unsigned int l2t_end; 624 struct l2t_data *l2t; 625 void *uld_handle[CXGB4_ULD_MAX]; 626 struct list_head list_node; 627 struct list_head rcu_node; 628 629 struct tid_info tids; 630 void **tid_release_head; 631 spinlock_t tid_release_lock; 632 struct work_struct tid_release_task; 633 struct work_struct db_full_task; 634 struct work_struct db_drop_task; 635 bool tid_release_task_busy; 636 637 struct dentry *debugfs_root; 638 639 spinlock_t stats_lock; 640 }; 641 642 /* Defined bit width of user definable filter tuples 643 */ 644 #define ETHTYPE_BITWIDTH 16 645 #define FRAG_BITWIDTH 1 646 #define MACIDX_BITWIDTH 9 647 #define FCOE_BITWIDTH 1 648 #define IPORT_BITWIDTH 3 649 #define MATCHTYPE_BITWIDTH 3 650 #define PROTO_BITWIDTH 8 651 #define TOS_BITWIDTH 8 652 #define PF_BITWIDTH 8 653 #define VF_BITWIDTH 8 654 #define IVLAN_BITWIDTH 16 655 #define OVLAN_BITWIDTH 16 656 657 /* Filter matching rules. These consist of a set of ingress packet field 658 * (value, mask) tuples. The associated ingress packet field matches the 659 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 660 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 661 * matches an ingress packet when all of the individual individual field 662 * matching rules are true. 663 * 664 * Partial field masks are always valid, however, while it may be easy to 665 * understand their meanings for some fields (e.g. IP address to match a 666 * subnet), for others making sensible partial masks is less intuitive (e.g. 667 * MPS match type) ... 668 * 669 * Most of the following data structures are modeled on T4 capabilities. 670 * Drivers for earlier chips use the subsets which make sense for those chips. 671 * We really need to come up with a hardware-independent mechanism to 672 * represent hardware filter capabilities ... 673 */ 674 struct ch_filter_tuple { 675 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 676 * register selects which of these fields will participate in the 677 * filter match rules -- up to a maximum of 36 bits. Because 678 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 679 * set of fields. 680 */ 681 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 682 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 683 uint32_t ivlan_vld:1; /* inner VLAN valid */ 684 uint32_t ovlan_vld:1; /* outer VLAN valid */ 685 uint32_t pfvf_vld:1; /* PF/VF valid */ 686 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 687 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 688 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 689 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 690 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 691 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 692 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 693 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 694 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 695 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 696 697 /* Uncompressed header matching field rules. These are always 698 * available for field rules. 699 */ 700 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 701 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 702 uint16_t lport; /* local port */ 703 uint16_t fport; /* foreign port */ 704 }; 705 706 /* A filter ioctl command. 707 */ 708 struct ch_filter_specification { 709 /* Administrative fields for filter. 710 */ 711 uint32_t hitcnts:1; /* count filter hits in TCB */ 712 uint32_t prio:1; /* filter has priority over active/server */ 713 714 /* Fundamental filter typing. This is the one element of filter 715 * matching that doesn't exist as a (value, mask) tuple. 716 */ 717 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 718 719 /* Packet dispatch information. Ingress packets which match the 720 * filter rules will be dropped, passed to the host or switched back 721 * out as egress packets. 722 */ 723 uint32_t action:2; /* drop, pass, switch */ 724 725 uint32_t rpttid:1; /* report TID in RSS hash field */ 726 727 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 728 uint32_t iq:10; /* ingress queue */ 729 730 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 731 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 732 /* 1 => TCB contains IQ ID */ 733 734 /* Switch proxy/rewrite fields. An ingress packet which matches a 735 * filter with "switch" set will be looped back out as an egress 736 * packet -- potentially with some Ethernet header rewriting. 737 */ 738 uint32_t eport:2; /* egress port to switch packet out */ 739 uint32_t newdmac:1; /* rewrite destination MAC address */ 740 uint32_t newsmac:1; /* rewrite source MAC address */ 741 uint32_t newvlan:2; /* rewrite VLAN Tag */ 742 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 743 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 744 uint16_t vlan; /* VLAN Tag to insert */ 745 746 /* Filter rule value/mask pairs. 747 */ 748 struct ch_filter_tuple val; 749 struct ch_filter_tuple mask; 750 }; 751 752 enum { 753 FILTER_PASS = 0, /* default */ 754 FILTER_DROP, 755 FILTER_SWITCH 756 }; 757 758 enum { 759 VLAN_NOCHANGE = 0, /* default */ 760 VLAN_REMOVE, 761 VLAN_INSERT, 762 VLAN_REWRITE 763 }; 764 765 static inline int is_t5(enum chip_type chip) 766 { 767 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5; 768 } 769 770 static inline int is_t4(enum chip_type chip) 771 { 772 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; 773 } 774 775 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 776 { 777 return readl(adap->regs + reg_addr); 778 } 779 780 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 781 { 782 writel(val, adap->regs + reg_addr); 783 } 784 785 #ifndef readq 786 static inline u64 readq(const volatile void __iomem *addr) 787 { 788 return readl(addr) + ((u64)readl(addr + 4) << 32); 789 } 790 791 static inline void writeq(u64 val, volatile void __iomem *addr) 792 { 793 writel(val, addr); 794 writel(val >> 32, addr + 4); 795 } 796 #endif 797 798 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 799 { 800 return readq(adap->regs + reg_addr); 801 } 802 803 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 804 { 805 writeq(val, adap->regs + reg_addr); 806 } 807 808 /** 809 * netdev2pinfo - return the port_info structure associated with a net_device 810 * @dev: the netdev 811 * 812 * Return the struct port_info associated with a net_device 813 */ 814 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 815 { 816 return netdev_priv(dev); 817 } 818 819 /** 820 * adap2pinfo - return the port_info of a port 821 * @adap: the adapter 822 * @idx: the port index 823 * 824 * Return the port_info structure for the port of the given index. 825 */ 826 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 827 { 828 return netdev_priv(adap->port[idx]); 829 } 830 831 /** 832 * netdev2adap - return the adapter structure associated with a net_device 833 * @dev: the netdev 834 * 835 * Return the struct adapter associated with a net_device 836 */ 837 static inline struct adapter *netdev2adap(const struct net_device *dev) 838 { 839 return netdev2pinfo(dev)->adapter; 840 } 841 842 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 843 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 844 845 void *t4_alloc_mem(size_t size); 846 847 void t4_free_sge_resources(struct adapter *adap); 848 irq_handler_t t4_intr_handler(struct adapter *adap); 849 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 850 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 851 const struct pkt_gl *gl); 852 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 853 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 854 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 855 struct net_device *dev, int intr_idx, 856 struct sge_fl *fl, rspq_handler_t hnd); 857 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 858 struct net_device *dev, struct netdev_queue *netdevq, 859 unsigned int iqid); 860 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 861 struct net_device *dev, unsigned int iqid, 862 unsigned int cmplqid); 863 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 864 struct net_device *dev, unsigned int iqid); 865 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 866 int t4_sge_init(struct adapter *adap); 867 void t4_sge_start(struct adapter *adap); 868 void t4_sge_stop(struct adapter *adap); 869 extern int dbfifo_int_thresh; 870 871 #define for_each_port(adapter, iter) \ 872 for (iter = 0; iter < (adapter)->params.nports; ++iter) 873 874 static inline int is_bypass(struct adapter *adap) 875 { 876 return adap->params.bypass; 877 } 878 879 static inline int is_bypass_device(int device) 880 { 881 /* this should be set based upon device capabilities */ 882 switch (device) { 883 case 0x440b: 884 case 0x440c: 885 return 1; 886 default: 887 return 0; 888 } 889 } 890 891 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 892 { 893 return adap->params.vpd.cclk / 1000; 894 } 895 896 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 897 unsigned int us) 898 { 899 return (us * adap->params.vpd.cclk) / 1000; 900 } 901 902 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 903 unsigned int ticks) 904 { 905 /* add Core Clock / 2 to round ticks to nearest uS */ 906 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 907 adapter->params.vpd.cclk); 908 } 909 910 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 911 u32 val); 912 913 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 914 void *rpl, bool sleep_ok); 915 916 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 917 int size, void *rpl) 918 { 919 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 920 } 921 922 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 923 int size, void *rpl) 924 { 925 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 926 } 927 928 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 929 unsigned int data_reg, const u32 *vals, 930 unsigned int nregs, unsigned int start_idx); 931 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 932 unsigned int data_reg, u32 *vals, unsigned int nregs, 933 unsigned int start_idx); 934 935 struct fw_filter_wr; 936 937 void t4_intr_enable(struct adapter *adapter); 938 void t4_intr_disable(struct adapter *adapter); 939 int t4_slow_intr_handler(struct adapter *adapter); 940 941 int t4_wait_dev_ready(struct adapter *adap); 942 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 943 struct link_config *lc); 944 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 945 int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len, 946 __be32 *buf); 947 int t4_seeprom_wp(struct adapter *adapter, bool enable); 948 int get_vpd_params(struct adapter *adapter, struct vpd_params *p); 949 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 950 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 951 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 952 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 953 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 954 const u8 *fw_data, unsigned int fw_size, 955 struct fw_hdr *card_fw, enum dev_state state, int *reset); 956 int t4_prep_adapter(struct adapter *adapter); 957 int t4_init_tp_params(struct adapter *adap); 958 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 959 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 960 void t4_fatal_err(struct adapter *adapter); 961 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 962 int start, int n, const u16 *rspq, unsigned int nrspq); 963 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 964 unsigned int flags); 965 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 966 u64 *parity); 967 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 968 u64 *parity); 969 const char *t4_get_port_type_description(enum fw_port_type port_type); 970 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 971 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 972 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 973 unsigned int mask, unsigned int val); 974 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 975 struct tp_tcp_stats *v6); 976 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 977 const unsigned short *alpha, const unsigned short *beta); 978 979 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 980 981 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 982 const u8 *addr); 983 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 984 u64 mask0, u64 mask1, unsigned int crc, bool enable); 985 986 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 987 enum dev_master master, enum dev_state *state); 988 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 989 int t4_early_init(struct adapter *adap, unsigned int mbox); 990 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 991 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 992 unsigned int cache_line_size); 993 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 994 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 995 unsigned int vf, unsigned int nparams, const u32 *params, 996 u32 *val); 997 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 998 unsigned int vf, unsigned int nparams, const u32 *params, 999 const u32 *val); 1000 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1001 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1002 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1003 unsigned int vi, unsigned int cmask, unsigned int pmask, 1004 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1005 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1006 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1007 unsigned int *rss_size); 1008 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1009 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1010 bool sleep_ok); 1011 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1012 unsigned int viid, bool free, unsigned int naddr, 1013 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1014 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1015 int idx, const u8 *addr, bool persist, bool add_smt); 1016 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1017 bool ucast, u64 vec, bool sleep_ok); 1018 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1019 bool rx_en, bool tx_en); 1020 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1021 unsigned int nblinks); 1022 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1023 unsigned int mmd, unsigned int reg, u16 *valp); 1024 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1025 unsigned int mmd, unsigned int reg, u16 val); 1026 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1027 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1028 unsigned int fl0id, unsigned int fl1id); 1029 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1030 unsigned int vf, unsigned int eqid); 1031 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1032 unsigned int vf, unsigned int eqid); 1033 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1034 unsigned int vf, unsigned int eqid); 1035 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1036 void t4_db_full(struct adapter *adapter); 1037 void t4_db_dropped(struct adapter *adapter); 1038 int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len); 1039 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1040 u32 addr, u32 val); 1041 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1042 #endif /* __CXGB4_H__ */ 1043