1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <linux/ptp_clock_kernel.h> 52 #include <linux/ptp_classify.h> 53 #include <asm/io.h> 54 #include "t4_chip_type.h" 55 #include "cxgb4_uld.h" 56 57 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 58 extern struct list_head adapter_list; 59 extern struct mutex uld_mutex; 60 61 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 62 * This is the same as calc_tx_descs() for a TSO packet with 63 * nr_frags == MAX_SKB_FRAGS. 64 */ 65 #define ETHTXQ_STOP_THRES \ 66 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 67 68 enum { 69 MAX_NPORTS = 4, /* max # of ports */ 70 SERNUM_LEN = 24, /* Serial # length */ 71 EC_LEN = 16, /* E/C length */ 72 ID_LEN = 16, /* ID length */ 73 PN_LEN = 16, /* Part Number length */ 74 MACADDR_LEN = 12, /* MAC Address length */ 75 }; 76 77 enum { 78 T4_REGMAP_SIZE = (160 * 1024), 79 T5_REGMAP_SIZE = (332 * 1024), 80 }; 81 82 enum { 83 MEM_EDC0, 84 MEM_EDC1, 85 MEM_MC, 86 MEM_MC0 = MEM_MC, 87 MEM_MC1, 88 MEM_HMA, 89 }; 90 91 enum { 92 MEMWIN0_APERTURE = 2048, 93 MEMWIN0_BASE = 0x1b800, 94 MEMWIN1_APERTURE = 32768, 95 MEMWIN1_BASE = 0x28000, 96 MEMWIN1_BASE_T5 = 0x52000, 97 MEMWIN2_APERTURE = 65536, 98 MEMWIN2_BASE = 0x30000, 99 MEMWIN2_APERTURE_T5 = 131072, 100 MEMWIN2_BASE_T5 = 0x60000, 101 }; 102 103 enum dev_master { 104 MASTER_CANT, 105 MASTER_MAY, 106 MASTER_MUST 107 }; 108 109 enum dev_state { 110 DEV_STATE_UNINIT, 111 DEV_STATE_INIT, 112 DEV_STATE_ERR 113 }; 114 115 enum cc_pause { 116 PAUSE_RX = 1 << 0, 117 PAUSE_TX = 1 << 1, 118 PAUSE_AUTONEG = 1 << 2 119 }; 120 121 enum cc_fec { 122 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 123 FEC_RS = 1 << 1, /* Reed-Solomon */ 124 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 125 }; 126 127 struct port_stats { 128 u64 tx_octets; /* total # of octets in good frames */ 129 u64 tx_frames; /* all good frames */ 130 u64 tx_bcast_frames; /* all broadcast frames */ 131 u64 tx_mcast_frames; /* all multicast frames */ 132 u64 tx_ucast_frames; /* all unicast frames */ 133 u64 tx_error_frames; /* all error frames */ 134 135 u64 tx_frames_64; /* # of Tx frames in a particular range */ 136 u64 tx_frames_65_127; 137 u64 tx_frames_128_255; 138 u64 tx_frames_256_511; 139 u64 tx_frames_512_1023; 140 u64 tx_frames_1024_1518; 141 u64 tx_frames_1519_max; 142 143 u64 tx_drop; /* # of dropped Tx frames */ 144 u64 tx_pause; /* # of transmitted pause frames */ 145 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 146 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 147 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 148 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 149 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 150 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 151 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 152 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 153 154 u64 rx_octets; /* total # of octets in good frames */ 155 u64 rx_frames; /* all good frames */ 156 u64 rx_bcast_frames; /* all broadcast frames */ 157 u64 rx_mcast_frames; /* all multicast frames */ 158 u64 rx_ucast_frames; /* all unicast frames */ 159 u64 rx_too_long; /* # of frames exceeding MTU */ 160 u64 rx_jabber; /* # of jabber frames */ 161 u64 rx_fcs_err; /* # of received frames with bad FCS */ 162 u64 rx_len_err; /* # of received frames with length error */ 163 u64 rx_symbol_err; /* symbol errors */ 164 u64 rx_runt; /* # of short frames */ 165 166 u64 rx_frames_64; /* # of Rx frames in a particular range */ 167 u64 rx_frames_65_127; 168 u64 rx_frames_128_255; 169 u64 rx_frames_256_511; 170 u64 rx_frames_512_1023; 171 u64 rx_frames_1024_1518; 172 u64 rx_frames_1519_max; 173 174 u64 rx_pause; /* # of received pause frames */ 175 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 176 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 177 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 178 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 179 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 180 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 181 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 182 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 183 184 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 185 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 186 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 187 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 188 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 189 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 190 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 191 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 192 }; 193 194 struct lb_port_stats { 195 u64 octets; 196 u64 frames; 197 u64 bcast_frames; 198 u64 mcast_frames; 199 u64 ucast_frames; 200 u64 error_frames; 201 202 u64 frames_64; 203 u64 frames_65_127; 204 u64 frames_128_255; 205 u64 frames_256_511; 206 u64 frames_512_1023; 207 u64 frames_1024_1518; 208 u64 frames_1519_max; 209 210 u64 drop; 211 212 u64 ovflow0; 213 u64 ovflow1; 214 u64 ovflow2; 215 u64 ovflow3; 216 u64 trunc0; 217 u64 trunc1; 218 u64 trunc2; 219 u64 trunc3; 220 }; 221 222 struct tp_tcp_stats { 223 u32 tcp_out_rsts; 224 u64 tcp_in_segs; 225 u64 tcp_out_segs; 226 u64 tcp_retrans_segs; 227 }; 228 229 struct tp_usm_stats { 230 u32 frames; 231 u32 drops; 232 u64 octets; 233 }; 234 235 struct tp_fcoe_stats { 236 u32 frames_ddp; 237 u32 frames_drop; 238 u64 octets_ddp; 239 }; 240 241 struct tp_err_stats { 242 u32 mac_in_errs[4]; 243 u32 hdr_in_errs[4]; 244 u32 tcp_in_errs[4]; 245 u32 tnl_cong_drops[4]; 246 u32 ofld_chan_drops[4]; 247 u32 tnl_tx_drops[4]; 248 u32 ofld_vlan_drops[4]; 249 u32 tcp6_in_errs[4]; 250 u32 ofld_no_neigh; 251 u32 ofld_cong_defer; 252 }; 253 254 struct tp_cpl_stats { 255 u32 req[4]; 256 u32 rsp[4]; 257 }; 258 259 struct tp_rdma_stats { 260 u32 rqe_dfr_pkt; 261 u32 rqe_dfr_mod; 262 }; 263 264 struct sge_params { 265 u32 hps; /* host page size for our PF/VF */ 266 u32 eq_qpp; /* egress queues/page for our PF/VF */ 267 u32 iq_qpp; /* egress queues/page for our PF/VF */ 268 }; 269 270 struct tp_params { 271 unsigned int tre; /* log2 of core clocks per TP tick */ 272 unsigned int la_mask; /* what events are recorded by TP LA */ 273 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 274 /* channel map */ 275 276 uint32_t dack_re; /* DACK timer resolution */ 277 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 278 279 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 280 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 281 282 /* cached TP_OUT_CONFIG compressed error vector 283 * and passing outer header info for encapsulated packets. 284 */ 285 int rx_pkt_encap; 286 287 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 288 * subset of the set of fields which may be present in the Compressed 289 * Filter Tuple portion of filters and TCP TCB connections. The 290 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 291 * Since a variable number of fields may or may not be present, their 292 * shifted field positions within the Compressed Filter Tuple may 293 * vary, or not even be present if the field isn't selected in 294 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 295 * places we store their offsets here, or a -1 if the field isn't 296 * present. 297 */ 298 int fcoe_shift; 299 int port_shift; 300 int vnic_shift; 301 int vlan_shift; 302 int tos_shift; 303 int protocol_shift; 304 int ethertype_shift; 305 int macmatch_shift; 306 int matchtype_shift; 307 int frag_shift; 308 309 u64 hash_filter_mask; 310 }; 311 312 struct vpd_params { 313 unsigned int cclk; 314 u8 ec[EC_LEN + 1]; 315 u8 sn[SERNUM_LEN + 1]; 316 u8 id[ID_LEN + 1]; 317 u8 pn[PN_LEN + 1]; 318 u8 na[MACADDR_LEN + 1]; 319 }; 320 321 struct pci_params { 322 unsigned int vpd_cap_addr; 323 unsigned char speed; 324 unsigned char width; 325 }; 326 327 struct devlog_params { 328 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 329 u32 start; /* start of log in firmware memory */ 330 u32 size; /* size of log */ 331 }; 332 333 /* Stores chip specific parameters */ 334 struct arch_specific_params { 335 u8 nchan; 336 u8 pm_stats_cnt; 337 u8 cng_ch_bits_log; /* congestion channel map bits width */ 338 u16 mps_rplc_size; 339 u16 vfcount; 340 u32 sge_fl_db; 341 u16 mps_tcam_size; 342 }; 343 344 struct adapter_params { 345 struct sge_params sge; 346 struct tp_params tp; 347 struct vpd_params vpd; 348 struct pci_params pci; 349 struct devlog_params devlog; 350 enum pcie_memwin drv_memwin; 351 352 unsigned int cim_la_size; 353 354 unsigned int sf_size; /* serial flash size in bytes */ 355 unsigned int sf_nsec; /* # of flash sectors */ 356 357 unsigned int fw_vers; /* firmware version */ 358 unsigned int bs_vers; /* bootstrap version */ 359 unsigned int tp_vers; /* TP microcode version */ 360 unsigned int er_vers; /* expansion ROM version */ 361 unsigned int scfg_vers; /* Serial Configuration version */ 362 unsigned int vpd_vers; /* VPD Version */ 363 u8 api_vers[7]; 364 365 unsigned short mtus[NMTUS]; 366 unsigned short a_wnd[NCCTRL_WIN]; 367 unsigned short b_wnd[NCCTRL_WIN]; 368 369 unsigned char nports; /* # of ethernet ports */ 370 unsigned char portvec; 371 enum chip_type chip; /* chip code */ 372 struct arch_specific_params arch; /* chip specific params */ 373 unsigned char offload; 374 unsigned char crypto; /* HW capability for crypto */ 375 376 unsigned char bypass; 377 unsigned char hash_filter; 378 379 unsigned int ofldq_wr_cred; 380 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 381 382 unsigned int nsched_cls; /* number of traffic classes */ 383 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 384 unsigned int max_ird_adapter; /* Max read depth per adapter */ 385 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 386 u8 fw_caps_support; /* 32-bit Port Capabilities */ 387 bool filter2_wr_support; /* FW support for FILTER2_WR */ 388 389 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 390 * used by the Port 391 */ 392 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 393 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 394 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 395 }; 396 397 /* State needed to monitor the forward progress of SGE Ingress DMA activities 398 * and possible hangs. 399 */ 400 struct sge_idma_monitor_state { 401 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 402 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 403 unsigned int idma_state[2]; /* IDMA Hang detect state */ 404 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 405 unsigned int idma_warn[2]; /* time to warning in HZ */ 406 }; 407 408 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 409 * The access and execute times are signed in order to accommodate negative 410 * error returns. 411 */ 412 struct mbox_cmd { 413 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 414 u64 timestamp; /* OS-dependent timestamp */ 415 u32 seqno; /* sequence number */ 416 s16 access; /* time (ms) to access mailbox */ 417 s16 execute; /* time (ms) to execute */ 418 }; 419 420 struct mbox_cmd_log { 421 unsigned int size; /* number of entries in the log */ 422 unsigned int cursor; /* next position in the log to write */ 423 u32 seqno; /* next sequence number */ 424 /* variable length mailbox command log starts here */ 425 }; 426 427 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 428 * return a pointer to the specified entry. 429 */ 430 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 431 unsigned int entry_idx) 432 { 433 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 434 } 435 436 #include "t4fw_api.h" 437 438 #define FW_VERSION(chip) ( \ 439 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 440 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 441 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 442 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 443 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 444 445 struct fw_info { 446 u8 chip; 447 char *fs_name; 448 char *fw_mod_name; 449 struct fw_hdr fw_hdr; 450 }; 451 452 struct trace_params { 453 u32 data[TRACE_LEN / 4]; 454 u32 mask[TRACE_LEN / 4]; 455 unsigned short snap_len; 456 unsigned short min_len; 457 unsigned char skip_ofst; 458 unsigned char skip_len; 459 unsigned char invert; 460 unsigned char port; 461 }; 462 463 /* Firmware Port Capabilities types. */ 464 465 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 466 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 467 468 enum fw_caps { 469 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 470 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 471 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 472 }; 473 474 struct link_config { 475 fw_port_cap32_t pcaps; /* link capabilities */ 476 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 477 fw_port_cap32_t acaps; /* advertised capabilities */ 478 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 479 480 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 481 unsigned int speed; /* actual link speed (Mb/s) */ 482 483 enum cc_pause requested_fc; /* flow control user has requested */ 484 enum cc_pause fc; /* actual link flow control */ 485 486 enum cc_fec requested_fec; /* Forward Error Correction: */ 487 enum cc_fec fec; /* requested and actual in use */ 488 489 unsigned char autoneg; /* autonegotiating? */ 490 491 unsigned char link_ok; /* link up? */ 492 unsigned char link_down_rc; /* link down reason */ 493 }; 494 495 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 496 497 enum { 498 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 499 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 500 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 501 }; 502 503 enum { 504 MAX_TXQ_ENTRIES = 16384, 505 MAX_CTRL_TXQ_ENTRIES = 1024, 506 MAX_RSPQ_ENTRIES = 16384, 507 MAX_RX_BUFFERS = 16384, 508 MIN_TXQ_ENTRIES = 32, 509 MIN_CTRL_TXQ_ENTRIES = 32, 510 MIN_RSPQ_ENTRIES = 128, 511 MIN_FL_ENTRIES = 16 512 }; 513 514 enum { 515 INGQ_EXTRAS = 2, /* firmware event queue and */ 516 /* forwarded interrupts */ 517 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 518 }; 519 520 struct adapter; 521 struct sge_rspq; 522 523 #include "cxgb4_dcb.h" 524 525 #ifdef CONFIG_CHELSIO_T4_FCOE 526 #include "cxgb4_fcoe.h" 527 #endif /* CONFIG_CHELSIO_T4_FCOE */ 528 529 struct port_info { 530 struct adapter *adapter; 531 u16 viid; 532 s16 xact_addr_filt; /* index of exact MAC address filter */ 533 u16 rss_size; /* size of VI's RSS table slice */ 534 s8 mdio_addr; 535 enum fw_port_type port_type; 536 u8 mod_type; 537 u8 port_id; 538 u8 tx_chan; 539 u8 lport; /* associated offload logical port */ 540 u8 nqsets; /* # of qsets */ 541 u8 first_qset; /* index of first qset */ 542 u8 rss_mode; 543 struct link_config link_cfg; 544 u16 *rss; 545 struct port_stats stats_base; 546 #ifdef CONFIG_CHELSIO_T4_DCB 547 struct port_dcb_info dcb; /* Data Center Bridging support */ 548 #endif 549 #ifdef CONFIG_CHELSIO_T4_FCOE 550 struct cxgb_fcoe fcoe; 551 #endif /* CONFIG_CHELSIO_T4_FCOE */ 552 bool rxtstamp; /* Enable TS */ 553 struct hwtstamp_config tstamp_config; 554 bool ptp_enable; 555 struct sched_table *sched_tbl; 556 }; 557 558 struct dentry; 559 struct work_struct; 560 561 enum { /* adapter flags */ 562 FULL_INIT_DONE = (1 << 0), 563 DEV_ENABLED = (1 << 1), 564 USING_MSI = (1 << 2), 565 USING_MSIX = (1 << 3), 566 FW_OK = (1 << 4), 567 RSS_TNLALLLOOKUP = (1 << 5), 568 USING_SOFT_PARAMS = (1 << 6), 569 MASTER_PF = (1 << 7), 570 FW_OFLD_CONN = (1 << 9), 571 ROOT_NO_RELAXED_ORDERING = (1 << 10), 572 SHUTTING_DOWN = (1 << 11), 573 }; 574 575 enum { 576 ULP_CRYPTO_LOOKASIDE = 1 << 0, 577 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 578 }; 579 580 struct rx_sw_desc; 581 582 struct sge_fl { /* SGE free-buffer queue state */ 583 unsigned int avail; /* # of available Rx buffers */ 584 unsigned int pend_cred; /* new buffers since last FL DB ring */ 585 unsigned int cidx; /* consumer index */ 586 unsigned int pidx; /* producer index */ 587 unsigned long alloc_failed; /* # of times buffer allocation failed */ 588 unsigned long large_alloc_failed; 589 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 590 unsigned long low; /* # of times momentarily starving */ 591 unsigned long starving; 592 /* RO fields */ 593 unsigned int cntxt_id; /* SGE context id for the free list */ 594 unsigned int size; /* capacity of free list */ 595 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 596 __be64 *desc; /* address of HW Rx descriptor ring */ 597 dma_addr_t addr; /* bus address of HW ring start */ 598 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 599 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 600 }; 601 602 /* A packet gather list */ 603 struct pkt_gl { 604 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 605 struct page_frag frags[MAX_SKB_FRAGS]; 606 void *va; /* virtual address of first byte */ 607 unsigned int nfrags; /* # of fragments */ 608 unsigned int tot_len; /* total length of fragments */ 609 }; 610 611 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 612 const struct pkt_gl *gl); 613 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 614 /* LRO related declarations for ULD */ 615 struct t4_lro_mgr { 616 #define MAX_LRO_SESSIONS 64 617 u8 lro_session_cnt; /* # of sessions to aggregate */ 618 unsigned long lro_pkts; /* # of LRO super packets */ 619 unsigned long lro_merged; /* # of wire packets merged by LRO */ 620 struct sk_buff_head lroq; /* list of aggregated sessions */ 621 }; 622 623 struct sge_rspq { /* state for an SGE response queue */ 624 struct napi_struct napi; 625 const __be64 *cur_desc; /* current descriptor in queue */ 626 unsigned int cidx; /* consumer index */ 627 u8 gen; /* current generation bit */ 628 u8 intr_params; /* interrupt holdoff parameters */ 629 u8 next_intr_params; /* holdoff params for next interrupt */ 630 u8 adaptive_rx; 631 u8 pktcnt_idx; /* interrupt packet threshold */ 632 u8 uld; /* ULD handling this queue */ 633 u8 idx; /* queue index within its group */ 634 int offset; /* offset into current Rx buffer */ 635 u16 cntxt_id; /* SGE context id for the response q */ 636 u16 abs_id; /* absolute SGE id for the response q */ 637 __be64 *desc; /* address of HW response ring */ 638 dma_addr_t phys_addr; /* physical address of the ring */ 639 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 640 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 641 unsigned int iqe_len; /* entry size */ 642 unsigned int size; /* capacity of response queue */ 643 struct adapter *adap; 644 struct net_device *netdev; /* associated net device */ 645 rspq_handler_t handler; 646 rspq_flush_handler_t flush_handler; 647 struct t4_lro_mgr lro_mgr; 648 }; 649 650 struct sge_eth_stats { /* Ethernet queue statistics */ 651 unsigned long pkts; /* # of ethernet packets */ 652 unsigned long lro_pkts; /* # of LRO super packets */ 653 unsigned long lro_merged; /* # of wire packets merged by LRO */ 654 unsigned long rx_cso; /* # of Rx checksum offloads */ 655 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 656 unsigned long rx_drops; /* # of packets dropped due to no mem */ 657 }; 658 659 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 660 struct sge_rspq rspq; 661 struct sge_fl fl; 662 struct sge_eth_stats stats; 663 } ____cacheline_aligned_in_smp; 664 665 struct sge_ofld_stats { /* offload queue statistics */ 666 unsigned long pkts; /* # of packets */ 667 unsigned long imm; /* # of immediate-data packets */ 668 unsigned long an; /* # of asynchronous notifications */ 669 unsigned long nomem; /* # of responses deferred due to no mem */ 670 }; 671 672 struct sge_ofld_rxq { /* SW offload Rx queue */ 673 struct sge_rspq rspq; 674 struct sge_fl fl; 675 struct sge_ofld_stats stats; 676 } ____cacheline_aligned_in_smp; 677 678 struct tx_desc { 679 __be64 flit[8]; 680 }; 681 682 struct tx_sw_desc; 683 684 struct sge_txq { 685 unsigned int in_use; /* # of in-use Tx descriptors */ 686 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 687 unsigned int size; /* # of descriptors */ 688 unsigned int cidx; /* SW consumer index */ 689 unsigned int pidx; /* producer index */ 690 unsigned long stops; /* # of times q has been stopped */ 691 unsigned long restarts; /* # of queue restarts */ 692 unsigned int cntxt_id; /* SGE context id for the Tx q */ 693 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 694 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 695 struct sge_qstat *stat; /* queue status entry */ 696 dma_addr_t phys_addr; /* physical address of the ring */ 697 spinlock_t db_lock; 698 int db_disabled; 699 unsigned short db_pidx; 700 unsigned short db_pidx_inc; 701 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 702 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 703 }; 704 705 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 706 struct sge_txq q; 707 struct netdev_queue *txq; /* associated netdev TX queue */ 708 #ifdef CONFIG_CHELSIO_T4_DCB 709 u8 dcb_prio; /* DCB Priority bound to queue */ 710 #endif 711 unsigned long tso; /* # of TSO requests */ 712 unsigned long tx_cso; /* # of Tx checksum offloads */ 713 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 714 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 715 } ____cacheline_aligned_in_smp; 716 717 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 718 struct sge_txq q; 719 struct adapter *adap; 720 struct sk_buff_head sendq; /* list of backpressured packets */ 721 struct tasklet_struct qresume_tsk; /* restarts the queue */ 722 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 723 u8 full; /* the Tx ring is full */ 724 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 725 } ____cacheline_aligned_in_smp; 726 727 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 728 struct sge_txq q; 729 struct adapter *adap; 730 struct sk_buff_head sendq; /* list of backpressured packets */ 731 struct tasklet_struct qresume_tsk; /* restarts the queue */ 732 u8 full; /* the Tx ring is full */ 733 } ____cacheline_aligned_in_smp; 734 735 struct sge_uld_rxq_info { 736 char name[IFNAMSIZ]; /* name of ULD driver */ 737 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 738 u16 *msix_tbl; /* msix_tbl for uld */ 739 u16 *rspq_id; /* response queue id's of rxq */ 740 u16 nrxq; /* # of ingress uld queues */ 741 u16 nciq; /* # of completion queues */ 742 u8 uld; /* uld type */ 743 }; 744 745 struct sge_uld_txq_info { 746 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 747 atomic_t users; /* num users */ 748 u16 ntxq; /* # of egress uld queues */ 749 }; 750 751 struct sge { 752 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 753 struct sge_eth_txq ptptxq; 754 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 755 756 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 757 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 758 struct sge_uld_rxq_info **uld_rxq_info; 759 struct sge_uld_txq_info **uld_txq_info; 760 761 struct sge_rspq intrq ____cacheline_aligned_in_smp; 762 spinlock_t intrq_lock; 763 764 u16 max_ethqsets; /* # of available Ethernet queue sets */ 765 u16 ethqsets; /* # of active Ethernet queue sets */ 766 u16 ethtxq_rover; /* Tx queue to clean up next */ 767 u16 ofldqsets; /* # of active ofld queue sets */ 768 u16 nqs_per_uld; /* # of Rx queues per ULD */ 769 u16 timer_val[SGE_NTIMERS]; 770 u8 counter_val[SGE_NCOUNTERS]; 771 u32 fl_pg_order; /* large page allocation size */ 772 u32 stat_len; /* length of status page at ring end */ 773 u32 pktshift; /* padding between CPL & packet data */ 774 u32 fl_align; /* response queue message alignment */ 775 u32 fl_starve_thres; /* Free List starvation threshold */ 776 777 struct sge_idma_monitor_state idma_monitor; 778 unsigned int egr_start; 779 unsigned int egr_sz; 780 unsigned int ingr_start; 781 unsigned int ingr_sz; 782 void **egr_map; /* qid->queue egress queue map */ 783 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 784 unsigned long *starving_fl; 785 unsigned long *txq_maperr; 786 unsigned long *blocked_fl; 787 struct timer_list rx_timer; /* refills starving FLs */ 788 struct timer_list tx_timer; /* checks Tx queues */ 789 }; 790 791 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 792 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 793 794 struct l2t_data; 795 796 #ifdef CONFIG_PCI_IOV 797 798 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 799 * Configuration initialization for T5 only has SR-IOV functionality enabled 800 * on PF0-3 in order to simplify everything. 801 */ 802 #define NUM_OF_PF_WITH_SRIOV 4 803 804 #endif 805 806 struct doorbell_stats { 807 u32 db_drop; 808 u32 db_empty; 809 u32 db_full; 810 }; 811 812 struct hash_mac_addr { 813 struct list_head list; 814 u8 addr[ETH_ALEN]; 815 }; 816 817 struct uld_msix_bmap { 818 unsigned long *msix_bmap; 819 unsigned int mapsize; 820 spinlock_t lock; /* lock for acquiring bitmap */ 821 }; 822 823 struct uld_msix_info { 824 unsigned short vec; 825 char desc[IFNAMSIZ + 10]; 826 unsigned int idx; 827 }; 828 829 struct vf_info { 830 unsigned char vf_mac_addr[ETH_ALEN]; 831 unsigned int tx_rate; 832 bool pf_set_mac; 833 u16 vlan; 834 }; 835 836 enum { 837 HMA_DMA_MAPPED_FLAG = 1 838 }; 839 840 struct hma_data { 841 unsigned char flags; 842 struct sg_table *sgt; 843 dma_addr_t *phy_addr; /* physical address of the page */ 844 }; 845 846 struct mbox_list { 847 struct list_head list; 848 }; 849 850 struct mps_encap_entry { 851 atomic_t refcnt; 852 }; 853 854 struct adapter { 855 void __iomem *regs; 856 void __iomem *bar2; 857 u32 t4_bar0; 858 struct pci_dev *pdev; 859 struct device *pdev_dev; 860 const char *name; 861 unsigned int mbox; 862 unsigned int pf; 863 unsigned int flags; 864 unsigned int adap_idx; 865 enum chip_type chip; 866 867 int msg_enable; 868 __be16 vxlan_port; 869 u8 vxlan_port_cnt; 870 __be16 geneve_port; 871 u8 geneve_port_cnt; 872 873 struct adapter_params params; 874 struct cxgb4_virt_res vres; 875 unsigned int swintr; 876 877 struct { 878 unsigned short vec; 879 char desc[IFNAMSIZ + 10]; 880 } msix_info[MAX_INGQ + 1]; 881 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 882 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 883 int msi_idx; 884 885 struct doorbell_stats db_stats; 886 struct sge sge; 887 888 struct net_device *port[MAX_NPORTS]; 889 u8 chan_map[NCHAN]; /* channel -> port map */ 890 891 struct vf_info *vfinfo; 892 u8 num_vfs; 893 894 u32 filter_mode; 895 unsigned int l2t_start; 896 unsigned int l2t_end; 897 struct l2t_data *l2t; 898 unsigned int clipt_start; 899 unsigned int clipt_end; 900 struct clip_tbl *clipt; 901 unsigned int rawf_start; 902 unsigned int rawf_cnt; 903 struct smt_data *smt; 904 struct mps_encap_entry *mps_encap; 905 struct cxgb4_uld_info *uld; 906 void *uld_handle[CXGB4_ULD_MAX]; 907 unsigned int num_uld; 908 unsigned int num_ofld_uld; 909 struct list_head list_node; 910 struct list_head rcu_node; 911 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 912 913 void *iscsi_ppm; 914 915 struct tid_info tids; 916 void **tid_release_head; 917 spinlock_t tid_release_lock; 918 struct workqueue_struct *workq; 919 struct work_struct tid_release_task; 920 struct work_struct db_full_task; 921 struct work_struct db_drop_task; 922 struct work_struct fatal_err_notify_task; 923 bool tid_release_task_busy; 924 925 /* lock for mailbox cmd list */ 926 spinlock_t mbox_lock; 927 struct mbox_list mlist; 928 929 /* support for mailbox command/reply logging */ 930 #define T4_OS_LOG_MBOX_CMDS 256 931 struct mbox_cmd_log *mbox_log; 932 933 struct mutex uld_mutex; 934 935 struct dentry *debugfs_root; 936 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 937 bool trace_rss; /* 1 implies that different RSS flit per filter is 938 * used per filter else if 0 default RSS flit is 939 * used for all 4 filters. 940 */ 941 942 struct ptp_clock *ptp_clock; 943 struct ptp_clock_info ptp_clock_info; 944 struct sk_buff *ptp_tx_skb; 945 /* ptp lock */ 946 spinlock_t ptp_lock; 947 spinlock_t stats_lock; 948 spinlock_t win0_lock ____cacheline_aligned_in_smp; 949 950 /* TC u32 offload */ 951 struct cxgb4_tc_u32_table *tc_u32; 952 struct chcr_stats_debug chcr_stats; 953 954 /* TC flower offload */ 955 struct rhashtable flower_tbl; 956 struct rhashtable_params flower_ht_params; 957 struct timer_list flower_stats_timer; 958 struct work_struct flower_stats_work; 959 960 /* Ethtool Dump */ 961 struct ethtool_dump eth_dump; 962 963 /* HMA */ 964 struct hma_data hma; 965 966 struct srq_data *srq; 967 }; 968 969 /* Support for "sched-class" command to allow a TX Scheduling Class to be 970 * programmed with various parameters. 971 */ 972 struct ch_sched_params { 973 s8 type; /* packet or flow */ 974 union { 975 struct { 976 s8 level; /* scheduler hierarchy level */ 977 s8 mode; /* per-class or per-flow */ 978 s8 rateunit; /* bit or packet rate */ 979 s8 ratemode; /* %port relative or kbps absolute */ 980 s8 channel; /* scheduler channel [0..N] */ 981 s8 class; /* scheduler class [0..N] */ 982 s32 minrate; /* minimum rate */ 983 s32 maxrate; /* maximum rate */ 984 s16 weight; /* percent weight */ 985 s16 pktsize; /* average packet size */ 986 } params; 987 } u; 988 }; 989 990 enum { 991 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 992 }; 993 994 enum { 995 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 996 }; 997 998 enum { 999 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1000 }; 1001 1002 enum { 1003 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1004 }; 1005 1006 enum { 1007 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1008 }; 1009 1010 struct tx_sw_desc { /* SW state per Tx descriptor */ 1011 struct sk_buff *skb; 1012 struct ulptx_sgl *sgl; 1013 }; 1014 1015 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1016 * to be bound to a TX Scheduling Class. 1017 */ 1018 struct ch_sched_queue { 1019 s8 queue; /* queue index */ 1020 s8 class; /* class index */ 1021 }; 1022 1023 /* Defined bit width of user definable filter tuples 1024 */ 1025 #define ETHTYPE_BITWIDTH 16 1026 #define FRAG_BITWIDTH 1 1027 #define MACIDX_BITWIDTH 9 1028 #define FCOE_BITWIDTH 1 1029 #define IPORT_BITWIDTH 3 1030 #define MATCHTYPE_BITWIDTH 3 1031 #define PROTO_BITWIDTH 8 1032 #define TOS_BITWIDTH 8 1033 #define PF_BITWIDTH 8 1034 #define VF_BITWIDTH 8 1035 #define IVLAN_BITWIDTH 16 1036 #define OVLAN_BITWIDTH 16 1037 1038 /* Filter matching rules. These consist of a set of ingress packet field 1039 * (value, mask) tuples. The associated ingress packet field matches the 1040 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1041 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1042 * matches an ingress packet when all of the individual individual field 1043 * matching rules are true. 1044 * 1045 * Partial field masks are always valid, however, while it may be easy to 1046 * understand their meanings for some fields (e.g. IP address to match a 1047 * subnet), for others making sensible partial masks is less intuitive (e.g. 1048 * MPS match type) ... 1049 * 1050 * Most of the following data structures are modeled on T4 capabilities. 1051 * Drivers for earlier chips use the subsets which make sense for those chips. 1052 * We really need to come up with a hardware-independent mechanism to 1053 * represent hardware filter capabilities ... 1054 */ 1055 struct ch_filter_tuple { 1056 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1057 * register selects which of these fields will participate in the 1058 * filter match rules -- up to a maximum of 36 bits. Because 1059 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1060 * set of fields. 1061 */ 1062 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1063 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1064 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1065 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1066 uint32_t pfvf_vld:1; /* PF/VF valid */ 1067 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1068 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1069 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1070 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1071 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1072 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1073 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1074 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1075 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1076 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1077 1078 /* Uncompressed header matching field rules. These are always 1079 * available for field rules. 1080 */ 1081 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1082 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1083 uint16_t lport; /* local port */ 1084 uint16_t fport; /* foreign port */ 1085 }; 1086 1087 /* A filter ioctl command. 1088 */ 1089 struct ch_filter_specification { 1090 /* Administrative fields for filter. 1091 */ 1092 uint32_t hitcnts:1; /* count filter hits in TCB */ 1093 uint32_t prio:1; /* filter has priority over active/server */ 1094 1095 /* Fundamental filter typing. This is the one element of filter 1096 * matching that doesn't exist as a (value, mask) tuple. 1097 */ 1098 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1099 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1100 1101 /* Packet dispatch information. Ingress packets which match the 1102 * filter rules will be dropped, passed to the host or switched back 1103 * out as egress packets. 1104 */ 1105 uint32_t action:2; /* drop, pass, switch */ 1106 1107 uint32_t rpttid:1; /* report TID in RSS hash field */ 1108 1109 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1110 uint32_t iq:10; /* ingress queue */ 1111 1112 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1113 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1114 /* 1 => TCB contains IQ ID */ 1115 1116 /* Switch proxy/rewrite fields. An ingress packet which matches a 1117 * filter with "switch" set will be looped back out as an egress 1118 * packet -- potentially with some Ethernet header rewriting. 1119 */ 1120 uint32_t eport:2; /* egress port to switch packet out */ 1121 uint32_t newdmac:1; /* rewrite destination MAC address */ 1122 uint32_t newsmac:1; /* rewrite source MAC address */ 1123 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1124 uint32_t nat_mode:3; /* specify NAT operation mode */ 1125 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1126 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1127 uint16_t vlan; /* VLAN Tag to insert */ 1128 1129 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1130 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1131 u16 nat_lport; /* local port to use after NAT'ing */ 1132 u16 nat_fport; /* foreign port to use after NAT'ing */ 1133 1134 /* reservation for future additions */ 1135 u8 rsvd[24]; 1136 1137 /* Filter rule value/mask pairs. 1138 */ 1139 struct ch_filter_tuple val; 1140 struct ch_filter_tuple mask; 1141 }; 1142 1143 enum { 1144 FILTER_PASS = 0, /* default */ 1145 FILTER_DROP, 1146 FILTER_SWITCH 1147 }; 1148 1149 enum { 1150 VLAN_NOCHANGE = 0, /* default */ 1151 VLAN_REMOVE, 1152 VLAN_INSERT, 1153 VLAN_REWRITE 1154 }; 1155 1156 enum { 1157 NAT_MODE_NONE = 0, /* No NAT performed */ 1158 NAT_MODE_DIP, /* NAT on Dst IP */ 1159 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1160 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1161 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1162 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1163 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1164 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1165 }; 1166 1167 /* Host shadow copy of ingress filter entry. This is in host native format 1168 * and doesn't match the ordering or bit order, etc. of the hardware of the 1169 * firmware command. The use of bit-field structure elements is purely to 1170 * remind ourselves of the field size limitations and save memory in the case 1171 * where the filter table is large. 1172 */ 1173 struct filter_entry { 1174 /* Administrative fields for filter. */ 1175 u32 valid:1; /* filter allocated and valid */ 1176 u32 locked:1; /* filter is administratively locked */ 1177 1178 u32 pending:1; /* filter action is pending firmware reply */ 1179 struct filter_ctx *ctx; /* Caller's completion hook */ 1180 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1181 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1182 struct net_device *dev; /* Associated net device */ 1183 u32 tid; /* This will store the actual tid */ 1184 1185 /* The filter itself. Most of this is a straight copy of information 1186 * provided by the extended ioctl(). Some fields are translated to 1187 * internal forms -- for instance the Ingress Queue ID passed in from 1188 * the ioctl() is translated into the Absolute Ingress Queue ID. 1189 */ 1190 struct ch_filter_specification fs; 1191 }; 1192 1193 static inline int is_offload(const struct adapter *adap) 1194 { 1195 return adap->params.offload; 1196 } 1197 1198 static inline int is_hashfilter(const struct adapter *adap) 1199 { 1200 return adap->params.hash_filter; 1201 } 1202 1203 static inline int is_pci_uld(const struct adapter *adap) 1204 { 1205 return adap->params.crypto; 1206 } 1207 1208 static inline int is_uld(const struct adapter *adap) 1209 { 1210 return (adap->params.offload || adap->params.crypto); 1211 } 1212 1213 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1214 { 1215 return readl(adap->regs + reg_addr); 1216 } 1217 1218 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1219 { 1220 writel(val, adap->regs + reg_addr); 1221 } 1222 1223 #ifndef readq 1224 static inline u64 readq(const volatile void __iomem *addr) 1225 { 1226 return readl(addr) + ((u64)readl(addr + 4) << 32); 1227 } 1228 1229 static inline void writeq(u64 val, volatile void __iomem *addr) 1230 { 1231 writel(val, addr); 1232 writel(val >> 32, addr + 4); 1233 } 1234 #endif 1235 1236 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1237 { 1238 return readq(adap->regs + reg_addr); 1239 } 1240 1241 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1242 { 1243 writeq(val, adap->regs + reg_addr); 1244 } 1245 1246 /** 1247 * t4_set_hw_addr - store a port's MAC address in SW 1248 * @adapter: the adapter 1249 * @port_idx: the port index 1250 * @hw_addr: the Ethernet address 1251 * 1252 * Store the Ethernet address of the given port in SW. Called by the common 1253 * code when it retrieves a port's Ethernet address from EEPROM. 1254 */ 1255 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1256 u8 hw_addr[]) 1257 { 1258 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1259 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1260 } 1261 1262 /** 1263 * netdev2pinfo - return the port_info structure associated with a net_device 1264 * @dev: the netdev 1265 * 1266 * Return the struct port_info associated with a net_device 1267 */ 1268 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1269 { 1270 return netdev_priv(dev); 1271 } 1272 1273 /** 1274 * adap2pinfo - return the port_info of a port 1275 * @adap: the adapter 1276 * @idx: the port index 1277 * 1278 * Return the port_info structure for the port of the given index. 1279 */ 1280 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1281 { 1282 return netdev_priv(adap->port[idx]); 1283 } 1284 1285 /** 1286 * netdev2adap - return the adapter structure associated with a net_device 1287 * @dev: the netdev 1288 * 1289 * Return the struct adapter associated with a net_device 1290 */ 1291 static inline struct adapter *netdev2adap(const struct net_device *dev) 1292 { 1293 return netdev2pinfo(dev)->adapter; 1294 } 1295 1296 /* Return a version number to identify the type of adapter. The scheme is: 1297 * - bits 0..9: chip version 1298 * - bits 10..15: chip revision 1299 * - bits 16..23: register dump version 1300 */ 1301 static inline unsigned int mk_adap_vers(struct adapter *ap) 1302 { 1303 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1304 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1305 } 1306 1307 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1308 static inline unsigned int qtimer_val(const struct adapter *adap, 1309 const struct sge_rspq *q) 1310 { 1311 unsigned int idx = q->intr_params >> 1; 1312 1313 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1314 } 1315 1316 /* driver version & name used for ethtool_drvinfo */ 1317 extern char cxgb4_driver_name[]; 1318 extern const char cxgb4_driver_version[]; 1319 1320 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1321 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1322 1323 void t4_free_sge_resources(struct adapter *adap); 1324 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1325 irq_handler_t t4_intr_handler(struct adapter *adap); 1326 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1327 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1328 const struct pkt_gl *gl); 1329 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1330 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1331 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1332 struct net_device *dev, int intr_idx, 1333 struct sge_fl *fl, rspq_handler_t hnd, 1334 rspq_flush_handler_t flush_handler, int cong); 1335 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1336 struct net_device *dev, struct netdev_queue *netdevq, 1337 unsigned int iqid); 1338 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1339 struct net_device *dev, unsigned int iqid, 1340 unsigned int cmplqid); 1341 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1342 unsigned int cmplqid); 1343 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1344 struct net_device *dev, unsigned int iqid, 1345 unsigned int uld_type); 1346 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1347 int t4_sge_init(struct adapter *adap); 1348 void t4_sge_start(struct adapter *adap); 1349 void t4_sge_stop(struct adapter *adap); 1350 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1351 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1352 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1353 extern int dbfifo_int_thresh; 1354 1355 #define for_each_port(adapter, iter) \ 1356 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1357 1358 static inline int is_bypass(struct adapter *adap) 1359 { 1360 return adap->params.bypass; 1361 } 1362 1363 static inline int is_bypass_device(int device) 1364 { 1365 /* this should be set based upon device capabilities */ 1366 switch (device) { 1367 case 0x440b: 1368 case 0x440c: 1369 return 1; 1370 default: 1371 return 0; 1372 } 1373 } 1374 1375 static inline int is_10gbt_device(int device) 1376 { 1377 /* this should be set based upon device capabilities */ 1378 switch (device) { 1379 case 0x4409: 1380 case 0x4486: 1381 return 1; 1382 1383 default: 1384 return 0; 1385 } 1386 } 1387 1388 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1389 { 1390 return adap->params.vpd.cclk / 1000; 1391 } 1392 1393 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1394 unsigned int us) 1395 { 1396 return (us * adap->params.vpd.cclk) / 1000; 1397 } 1398 1399 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1400 unsigned int ticks) 1401 { 1402 /* add Core Clock / 2 to round ticks to nearest uS */ 1403 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1404 adapter->params.vpd.cclk); 1405 } 1406 1407 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1408 unsigned int ticks) 1409 { 1410 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1411 } 1412 1413 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1414 u32 val); 1415 1416 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1417 int size, void *rpl, bool sleep_ok, int timeout); 1418 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1419 void *rpl, bool sleep_ok); 1420 1421 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1422 const void *cmd, int size, void *rpl, 1423 int timeout) 1424 { 1425 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1426 timeout); 1427 } 1428 1429 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1430 int size, void *rpl) 1431 { 1432 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1433 } 1434 1435 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1436 int size, void *rpl) 1437 { 1438 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1439 } 1440 1441 /** 1442 * hash_mac_addr - return the hash value of a MAC address 1443 * @addr: the 48-bit Ethernet MAC address 1444 * 1445 * Hashes a MAC address according to the hash function used by HW inexact 1446 * (hash) address matching. 1447 */ 1448 static inline int hash_mac_addr(const u8 *addr) 1449 { 1450 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1451 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1452 1453 a ^= b; 1454 a ^= (a >> 12); 1455 a ^= (a >> 6); 1456 return a & 0x3f; 1457 } 1458 1459 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1460 unsigned int cnt); 1461 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1462 unsigned int us, unsigned int cnt, 1463 unsigned int size, unsigned int iqe_size) 1464 { 1465 q->adap = adap; 1466 cxgb4_set_rspq_intr_params(q, us, cnt); 1467 q->iqe_len = iqe_size; 1468 q->size = size; 1469 } 1470 1471 /** 1472 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1473 * @fw_mod_type: the Firmware Mofule Type 1474 * 1475 * Return whether the Firmware Module Type represents a real Transceiver 1476 * Module/Cable Module Type which has been inserted. 1477 */ 1478 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1479 { 1480 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1481 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1482 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1483 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1484 } 1485 1486 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1487 unsigned int data_reg, const u32 *vals, 1488 unsigned int nregs, unsigned int start_idx); 1489 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1490 unsigned int data_reg, u32 *vals, unsigned int nregs, 1491 unsigned int start_idx); 1492 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1493 1494 struct fw_filter_wr; 1495 1496 void t4_intr_enable(struct adapter *adapter); 1497 void t4_intr_disable(struct adapter *adapter); 1498 int t4_slow_intr_handler(struct adapter *adapter); 1499 1500 int t4_wait_dev_ready(void __iomem *regs); 1501 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1502 struct link_config *lc); 1503 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1504 1505 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1506 u32 t4_get_util_window(struct adapter *adap); 1507 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1508 1509 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1510 u32 *mem_base, u32 *mem_aperture); 1511 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1512 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1513 int dir); 1514 #define T4_MEMORY_WRITE 0 1515 #define T4_MEMORY_READ 1 1516 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1517 void *buf, int dir); 1518 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1519 u32 len, __be32 *buf) 1520 { 1521 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1522 } 1523 1524 unsigned int t4_get_regs_len(struct adapter *adapter); 1525 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1526 1527 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1528 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1529 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1530 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1531 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1532 unsigned int nwords, u32 *data, int byte_oriented); 1533 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1534 int t4_load_phy_fw(struct adapter *adap, 1535 int win, spinlock_t *lock, 1536 int (*phy_fw_version)(const u8 *, size_t), 1537 const u8 *phy_fw_data, size_t phy_fw_size); 1538 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1539 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1540 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1541 const u8 *fw_data, unsigned int size, int force); 1542 int t4_fl_pkt_align(struct adapter *adap); 1543 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1544 int t4_check_fw_version(struct adapter *adap); 1545 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1546 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1547 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1548 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1549 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1550 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1551 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1552 int t4_get_version_info(struct adapter *adapter); 1553 void t4_dump_version_info(struct adapter *adapter); 1554 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1555 const u8 *fw_data, unsigned int fw_size, 1556 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1557 int t4_prep_adapter(struct adapter *adapter); 1558 int t4_shutdown_adapter(struct adapter *adapter); 1559 1560 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1561 int t4_bar2_sge_qregs(struct adapter *adapter, 1562 unsigned int qid, 1563 enum t4_bar2_qtype qtype, 1564 int user, 1565 u64 *pbar2_qoffset, 1566 unsigned int *pbar2_qid); 1567 1568 unsigned int qtimer_val(const struct adapter *adap, 1569 const struct sge_rspq *q); 1570 1571 int t4_init_devlog_params(struct adapter *adapter); 1572 int t4_init_sge_params(struct adapter *adapter); 1573 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1574 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1575 int t4_init_rss_mode(struct adapter *adap, int mbox); 1576 int t4_init_portinfo(struct port_info *pi, int mbox, 1577 int port, int pf, int vf, u8 mac[]); 1578 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1579 void t4_fatal_err(struct adapter *adapter); 1580 unsigned int t4_chip_rss_size(struct adapter *adapter); 1581 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1582 int start, int n, const u16 *rspq, unsigned int nrspq); 1583 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1584 unsigned int flags); 1585 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1586 unsigned int flags, unsigned int defq); 1587 int t4_read_rss(struct adapter *adapter, u16 *entries); 1588 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1589 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1590 bool sleep_ok); 1591 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1592 u32 *valp, bool sleep_ok); 1593 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1594 u32 *vfl, u32 *vfh, bool sleep_ok); 1595 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1596 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1597 1598 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1599 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1600 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1601 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1602 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1603 size_t n); 1604 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1605 size_t n); 1606 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1607 unsigned int *valp); 1608 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1609 const unsigned int *valp); 1610 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1611 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1612 unsigned int *pif_req_wrptr, 1613 unsigned int *pif_rsp_wrptr); 1614 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1615 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1616 const char *t4_get_port_type_description(enum fw_port_type port_type); 1617 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1618 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1619 struct port_stats *stats, 1620 struct port_stats *offset); 1621 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1622 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1623 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1624 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1625 unsigned int mask, unsigned int val); 1626 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1627 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1628 bool sleep_ok); 1629 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1630 bool sleep_ok); 1631 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1632 bool sleep_ok); 1633 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1634 bool sleep_ok); 1635 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1636 struct tp_tcp_stats *v6, bool sleep_ok); 1637 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1638 struct tp_fcoe_stats *st, bool sleep_ok); 1639 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1640 const unsigned short *alpha, const unsigned short *beta); 1641 1642 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1643 1644 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1645 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1646 1647 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1648 const u8 *addr); 1649 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1650 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1651 1652 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1653 enum dev_master master, enum dev_state *state); 1654 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1655 int t4_early_init(struct adapter *adap, unsigned int mbox); 1656 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1657 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1658 unsigned int cache_line_size); 1659 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1660 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1661 unsigned int vf, unsigned int nparams, const u32 *params, 1662 u32 *val); 1663 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1664 unsigned int vf, unsigned int nparams, const u32 *params, 1665 u32 *val); 1666 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1667 unsigned int vf, unsigned int nparams, const u32 *params, 1668 u32 *val, int rw, bool sleep_ok); 1669 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1670 unsigned int pf, unsigned int vf, 1671 unsigned int nparams, const u32 *params, 1672 const u32 *val, int timeout); 1673 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1674 unsigned int vf, unsigned int nparams, const u32 *params, 1675 const u32 *val); 1676 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1677 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1678 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1679 unsigned int vi, unsigned int cmask, unsigned int pmask, 1680 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1681 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1682 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1683 unsigned int *rss_size); 1684 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1685 unsigned int pf, unsigned int vf, 1686 unsigned int viid); 1687 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1688 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1689 bool sleep_ok); 1690 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1691 const u8 *addr, const u8 *mask, unsigned int idx, 1692 u8 lookup_type, u8 port_id, bool sleep_ok); 1693 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1694 const u8 *addr, const u8 *mask, unsigned int idx, 1695 u8 lookup_type, u8 port_id, bool sleep_ok); 1696 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1697 unsigned int viid, bool free, unsigned int naddr, 1698 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1699 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1700 unsigned int viid, unsigned int naddr, 1701 const u8 **addr, bool sleep_ok); 1702 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1703 int idx, const u8 *addr, bool persist, bool add_smt); 1704 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1705 bool ucast, u64 vec, bool sleep_ok); 1706 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1707 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1708 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1709 bool rx_en, bool tx_en); 1710 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1711 unsigned int nblinks); 1712 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1713 unsigned int mmd, unsigned int reg, u16 *valp); 1714 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1715 unsigned int mmd, unsigned int reg, u16 val); 1716 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1717 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1718 unsigned int fl0id, unsigned int fl1id); 1719 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1720 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1721 unsigned int fl0id, unsigned int fl1id); 1722 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1723 unsigned int vf, unsigned int eqid); 1724 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1725 unsigned int vf, unsigned int eqid); 1726 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1727 unsigned int vf, unsigned int eqid); 1728 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1729 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1730 int t4_update_port_info(struct port_info *pi); 1731 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1732 unsigned int *speedp, unsigned int *mtup); 1733 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1734 void t4_db_full(struct adapter *adapter); 1735 void t4_db_dropped(struct adapter *adapter); 1736 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1737 int filter_index, int enable); 1738 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1739 int filter_index, int *enabled); 1740 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1741 u32 addr, u32 val); 1742 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1743 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1744 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1745 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1746 enum ctxt_type ctype, u32 *data); 1747 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1748 enum ctxt_type ctype, u32 *data); 1749 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1750 int rateunit, int ratemode, int channel, int class, 1751 int minrate, int maxrate, int weight, int pktsize); 1752 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1753 void t4_idma_monitor_init(struct adapter *adapter, 1754 struct sge_idma_monitor_state *idma); 1755 void t4_idma_monitor(struct adapter *adapter, 1756 struct sge_idma_monitor_state *idma, 1757 int hz, int ticks); 1758 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1759 unsigned int naddr, u8 *addr); 1760 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1761 u32 start_index, bool sleep_ok); 1762 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1763 u32 start_index, bool sleep_ok); 1764 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1765 u32 start_index, bool sleep_ok); 1766 1767 void t4_uld_mem_free(struct adapter *adap); 1768 int t4_uld_mem_alloc(struct adapter *adap); 1769 void t4_uld_clean_up(struct adapter *adap); 1770 void t4_register_netevent_notifier(void); 1771 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1772 unsigned int devid, unsigned int offset, 1773 unsigned int len, u8 *buf); 1774 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1775 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1776 unsigned int n, bool unmap); 1777 void free_txq(struct adapter *adap, struct sge_txq *q); 1778 void cxgb4_reclaim_completed_tx(struct adapter *adap, 1779 struct sge_txq *q, bool unmap); 1780 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1781 dma_addr_t *addr); 1782 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1783 void *pos); 1784 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1785 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1786 const dma_addr_t *addr); 1787 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 1788 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 1789 u16 vlan); 1790 #endif /* __CXGB4_H__ */ 1791