1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <linux/ptp_clock_kernel.h> 52 #include <linux/ptp_classify.h> 53 #include <asm/io.h> 54 #include "t4_chip_type.h" 55 #include "cxgb4_uld.h" 56 57 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 58 extern struct list_head adapter_list; 59 extern struct mutex uld_mutex; 60 61 enum { 62 MAX_NPORTS = 4, /* max # of ports */ 63 SERNUM_LEN = 24, /* Serial # length */ 64 EC_LEN = 16, /* E/C length */ 65 ID_LEN = 16, /* ID length */ 66 PN_LEN = 16, /* Part Number length */ 67 MACADDR_LEN = 12, /* MAC Address length */ 68 }; 69 70 enum { 71 T4_REGMAP_SIZE = (160 * 1024), 72 T5_REGMAP_SIZE = (332 * 1024), 73 }; 74 75 enum { 76 MEM_EDC0, 77 MEM_EDC1, 78 MEM_MC, 79 MEM_MC0 = MEM_MC, 80 MEM_MC1, 81 MEM_HMA, 82 }; 83 84 enum { 85 MEMWIN0_APERTURE = 2048, 86 MEMWIN0_BASE = 0x1b800, 87 MEMWIN1_APERTURE = 32768, 88 MEMWIN1_BASE = 0x28000, 89 MEMWIN1_BASE_T5 = 0x52000, 90 MEMWIN2_APERTURE = 65536, 91 MEMWIN2_BASE = 0x30000, 92 MEMWIN2_APERTURE_T5 = 131072, 93 MEMWIN2_BASE_T5 = 0x60000, 94 }; 95 96 enum dev_master { 97 MASTER_CANT, 98 MASTER_MAY, 99 MASTER_MUST 100 }; 101 102 enum dev_state { 103 DEV_STATE_UNINIT, 104 DEV_STATE_INIT, 105 DEV_STATE_ERR 106 }; 107 108 enum cc_pause { 109 PAUSE_RX = 1 << 0, 110 PAUSE_TX = 1 << 1, 111 PAUSE_AUTONEG = 1 << 2 112 }; 113 114 enum cc_fec { 115 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 116 FEC_RS = 1 << 1, /* Reed-Solomon */ 117 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 118 }; 119 120 struct port_stats { 121 u64 tx_octets; /* total # of octets in good frames */ 122 u64 tx_frames; /* all good frames */ 123 u64 tx_bcast_frames; /* all broadcast frames */ 124 u64 tx_mcast_frames; /* all multicast frames */ 125 u64 tx_ucast_frames; /* all unicast frames */ 126 u64 tx_error_frames; /* all error frames */ 127 128 u64 tx_frames_64; /* # of Tx frames in a particular range */ 129 u64 tx_frames_65_127; 130 u64 tx_frames_128_255; 131 u64 tx_frames_256_511; 132 u64 tx_frames_512_1023; 133 u64 tx_frames_1024_1518; 134 u64 tx_frames_1519_max; 135 136 u64 tx_drop; /* # of dropped Tx frames */ 137 u64 tx_pause; /* # of transmitted pause frames */ 138 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 139 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 140 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 141 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 142 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 143 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 144 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 145 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 146 147 u64 rx_octets; /* total # of octets in good frames */ 148 u64 rx_frames; /* all good frames */ 149 u64 rx_bcast_frames; /* all broadcast frames */ 150 u64 rx_mcast_frames; /* all multicast frames */ 151 u64 rx_ucast_frames; /* all unicast frames */ 152 u64 rx_too_long; /* # of frames exceeding MTU */ 153 u64 rx_jabber; /* # of jabber frames */ 154 u64 rx_fcs_err; /* # of received frames with bad FCS */ 155 u64 rx_len_err; /* # of received frames with length error */ 156 u64 rx_symbol_err; /* symbol errors */ 157 u64 rx_runt; /* # of short frames */ 158 159 u64 rx_frames_64; /* # of Rx frames in a particular range */ 160 u64 rx_frames_65_127; 161 u64 rx_frames_128_255; 162 u64 rx_frames_256_511; 163 u64 rx_frames_512_1023; 164 u64 rx_frames_1024_1518; 165 u64 rx_frames_1519_max; 166 167 u64 rx_pause; /* # of received pause frames */ 168 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 169 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 170 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 171 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 172 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 173 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 174 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 175 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 176 177 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 178 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 179 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 180 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 181 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 182 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 183 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 184 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 185 }; 186 187 struct lb_port_stats { 188 u64 octets; 189 u64 frames; 190 u64 bcast_frames; 191 u64 mcast_frames; 192 u64 ucast_frames; 193 u64 error_frames; 194 195 u64 frames_64; 196 u64 frames_65_127; 197 u64 frames_128_255; 198 u64 frames_256_511; 199 u64 frames_512_1023; 200 u64 frames_1024_1518; 201 u64 frames_1519_max; 202 203 u64 drop; 204 205 u64 ovflow0; 206 u64 ovflow1; 207 u64 ovflow2; 208 u64 ovflow3; 209 u64 trunc0; 210 u64 trunc1; 211 u64 trunc2; 212 u64 trunc3; 213 }; 214 215 struct tp_tcp_stats { 216 u32 tcp_out_rsts; 217 u64 tcp_in_segs; 218 u64 tcp_out_segs; 219 u64 tcp_retrans_segs; 220 }; 221 222 struct tp_usm_stats { 223 u32 frames; 224 u32 drops; 225 u64 octets; 226 }; 227 228 struct tp_fcoe_stats { 229 u32 frames_ddp; 230 u32 frames_drop; 231 u64 octets_ddp; 232 }; 233 234 struct tp_err_stats { 235 u32 mac_in_errs[4]; 236 u32 hdr_in_errs[4]; 237 u32 tcp_in_errs[4]; 238 u32 tnl_cong_drops[4]; 239 u32 ofld_chan_drops[4]; 240 u32 tnl_tx_drops[4]; 241 u32 ofld_vlan_drops[4]; 242 u32 tcp6_in_errs[4]; 243 u32 ofld_no_neigh; 244 u32 ofld_cong_defer; 245 }; 246 247 struct tp_cpl_stats { 248 u32 req[4]; 249 u32 rsp[4]; 250 }; 251 252 struct tp_rdma_stats { 253 u32 rqe_dfr_pkt; 254 u32 rqe_dfr_mod; 255 }; 256 257 struct sge_params { 258 u32 hps; /* host page size for our PF/VF */ 259 u32 eq_qpp; /* egress queues/page for our PF/VF */ 260 u32 iq_qpp; /* egress queues/page for our PF/VF */ 261 }; 262 263 struct tp_params { 264 unsigned int tre; /* log2 of core clocks per TP tick */ 265 unsigned int la_mask; /* what events are recorded by TP LA */ 266 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 267 /* channel map */ 268 269 uint32_t dack_re; /* DACK timer resolution */ 270 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 271 272 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 273 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 274 275 /* cached TP_OUT_CONFIG compressed error vector 276 * and passing outer header info for encapsulated packets. 277 */ 278 int rx_pkt_encap; 279 280 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 281 * subset of the set of fields which may be present in the Compressed 282 * Filter Tuple portion of filters and TCP TCB connections. The 283 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 284 * Since a variable number of fields may or may not be present, their 285 * shifted field positions within the Compressed Filter Tuple may 286 * vary, or not even be present if the field isn't selected in 287 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 288 * places we store their offsets here, or a -1 if the field isn't 289 * present. 290 */ 291 int fcoe_shift; 292 int port_shift; 293 int vnic_shift; 294 int vlan_shift; 295 int tos_shift; 296 int protocol_shift; 297 int ethertype_shift; 298 int macmatch_shift; 299 int matchtype_shift; 300 int frag_shift; 301 302 u64 hash_filter_mask; 303 }; 304 305 struct vpd_params { 306 unsigned int cclk; 307 u8 ec[EC_LEN + 1]; 308 u8 sn[SERNUM_LEN + 1]; 309 u8 id[ID_LEN + 1]; 310 u8 pn[PN_LEN + 1]; 311 u8 na[MACADDR_LEN + 1]; 312 }; 313 314 struct pci_params { 315 unsigned char speed; 316 unsigned char width; 317 }; 318 319 struct devlog_params { 320 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 321 u32 start; /* start of log in firmware memory */ 322 u32 size; /* size of log */ 323 }; 324 325 /* Stores chip specific parameters */ 326 struct arch_specific_params { 327 u8 nchan; 328 u8 pm_stats_cnt; 329 u8 cng_ch_bits_log; /* congestion channel map bits width */ 330 u16 mps_rplc_size; 331 u16 vfcount; 332 u32 sge_fl_db; 333 u16 mps_tcam_size; 334 }; 335 336 struct adapter_params { 337 struct sge_params sge; 338 struct tp_params tp; 339 struct vpd_params vpd; 340 struct pci_params pci; 341 struct devlog_params devlog; 342 enum pcie_memwin drv_memwin; 343 344 unsigned int cim_la_size; 345 346 unsigned int sf_size; /* serial flash size in bytes */ 347 unsigned int sf_nsec; /* # of flash sectors */ 348 unsigned int sf_fw_start; /* start of FW image in flash */ 349 350 unsigned int fw_vers; /* firmware version */ 351 unsigned int bs_vers; /* bootstrap version */ 352 unsigned int tp_vers; /* TP microcode version */ 353 unsigned int er_vers; /* expansion ROM version */ 354 unsigned int scfg_vers; /* Serial Configuration version */ 355 unsigned int vpd_vers; /* VPD Version */ 356 u8 api_vers[7]; 357 358 unsigned short mtus[NMTUS]; 359 unsigned short a_wnd[NCCTRL_WIN]; 360 unsigned short b_wnd[NCCTRL_WIN]; 361 362 unsigned char nports; /* # of ethernet ports */ 363 unsigned char portvec; 364 enum chip_type chip; /* chip code */ 365 struct arch_specific_params arch; /* chip specific params */ 366 unsigned char offload; 367 unsigned char crypto; /* HW capability for crypto */ 368 369 unsigned char bypass; 370 unsigned char hash_filter; 371 372 unsigned int ofldq_wr_cred; 373 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 374 375 unsigned int nsched_cls; /* number of traffic classes */ 376 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 377 unsigned int max_ird_adapter; /* Max read depth per adapter */ 378 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 379 u8 fw_caps_support; /* 32-bit Port Capabilities */ 380 bool filter2_wr_support; /* FW support for FILTER2_WR */ 381 382 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 383 * used by the Port 384 */ 385 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 386 }; 387 388 /* State needed to monitor the forward progress of SGE Ingress DMA activities 389 * and possible hangs. 390 */ 391 struct sge_idma_monitor_state { 392 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 393 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 394 unsigned int idma_state[2]; /* IDMA Hang detect state */ 395 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 396 unsigned int idma_warn[2]; /* time to warning in HZ */ 397 }; 398 399 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 400 * The access and execute times are signed in order to accommodate negative 401 * error returns. 402 */ 403 struct mbox_cmd { 404 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 405 u64 timestamp; /* OS-dependent timestamp */ 406 u32 seqno; /* sequence number */ 407 s16 access; /* time (ms) to access mailbox */ 408 s16 execute; /* time (ms) to execute */ 409 }; 410 411 struct mbox_cmd_log { 412 unsigned int size; /* number of entries in the log */ 413 unsigned int cursor; /* next position in the log to write */ 414 u32 seqno; /* next sequence number */ 415 /* variable length mailbox command log starts here */ 416 }; 417 418 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 419 * return a pointer to the specified entry. 420 */ 421 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 422 unsigned int entry_idx) 423 { 424 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 425 } 426 427 #include "t4fw_api.h" 428 429 #define FW_VERSION(chip) ( \ 430 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 431 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 432 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 433 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 434 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 435 436 struct fw_info { 437 u8 chip; 438 char *fs_name; 439 char *fw_mod_name; 440 struct fw_hdr fw_hdr; 441 }; 442 443 struct trace_params { 444 u32 data[TRACE_LEN / 4]; 445 u32 mask[TRACE_LEN / 4]; 446 unsigned short snap_len; 447 unsigned short min_len; 448 unsigned char skip_ofst; 449 unsigned char skip_len; 450 unsigned char invert; 451 unsigned char port; 452 }; 453 454 /* Firmware Port Capabilities types. */ 455 456 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 457 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 458 459 enum fw_caps { 460 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 461 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 462 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 463 }; 464 465 struct link_config { 466 fw_port_cap32_t pcaps; /* link capabilities */ 467 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 468 fw_port_cap32_t acaps; /* advertised capabilities */ 469 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 470 471 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 472 unsigned int speed; /* actual link speed (Mb/s) */ 473 474 enum cc_pause requested_fc; /* flow control user has requested */ 475 enum cc_pause fc; /* actual link flow control */ 476 477 enum cc_fec requested_fec; /* Forward Error Correction: */ 478 enum cc_fec fec; /* requested and actual in use */ 479 480 unsigned char autoneg; /* autonegotiating? */ 481 482 unsigned char link_ok; /* link up? */ 483 unsigned char link_down_rc; /* link down reason */ 484 }; 485 486 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 487 488 enum { 489 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 490 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 491 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 492 }; 493 494 enum { 495 MAX_TXQ_ENTRIES = 16384, 496 MAX_CTRL_TXQ_ENTRIES = 1024, 497 MAX_RSPQ_ENTRIES = 16384, 498 MAX_RX_BUFFERS = 16384, 499 MIN_TXQ_ENTRIES = 32, 500 MIN_CTRL_TXQ_ENTRIES = 32, 501 MIN_RSPQ_ENTRIES = 128, 502 MIN_FL_ENTRIES = 16 503 }; 504 505 enum { 506 INGQ_EXTRAS = 2, /* firmware event queue and */ 507 /* forwarded interrupts */ 508 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 509 }; 510 511 struct adapter; 512 struct sge_rspq; 513 514 #include "cxgb4_dcb.h" 515 516 #ifdef CONFIG_CHELSIO_T4_FCOE 517 #include "cxgb4_fcoe.h" 518 #endif /* CONFIG_CHELSIO_T4_FCOE */ 519 520 struct port_info { 521 struct adapter *adapter; 522 u16 viid; 523 s16 xact_addr_filt; /* index of exact MAC address filter */ 524 u16 rss_size; /* size of VI's RSS table slice */ 525 s8 mdio_addr; 526 enum fw_port_type port_type; 527 u8 mod_type; 528 u8 port_id; 529 u8 tx_chan; 530 u8 lport; /* associated offload logical port */ 531 u8 nqsets; /* # of qsets */ 532 u8 first_qset; /* index of first qset */ 533 u8 rss_mode; 534 struct link_config link_cfg; 535 u16 *rss; 536 struct port_stats stats_base; 537 #ifdef CONFIG_CHELSIO_T4_DCB 538 struct port_dcb_info dcb; /* Data Center Bridging support */ 539 #endif 540 #ifdef CONFIG_CHELSIO_T4_FCOE 541 struct cxgb_fcoe fcoe; 542 #endif /* CONFIG_CHELSIO_T4_FCOE */ 543 bool rxtstamp; /* Enable TS */ 544 struct hwtstamp_config tstamp_config; 545 bool ptp_enable; 546 struct sched_table *sched_tbl; 547 }; 548 549 struct dentry; 550 struct work_struct; 551 552 enum { /* adapter flags */ 553 FULL_INIT_DONE = (1 << 0), 554 DEV_ENABLED = (1 << 1), 555 USING_MSI = (1 << 2), 556 USING_MSIX = (1 << 3), 557 FW_OK = (1 << 4), 558 RSS_TNLALLLOOKUP = (1 << 5), 559 USING_SOFT_PARAMS = (1 << 6), 560 MASTER_PF = (1 << 7), 561 FW_OFLD_CONN = (1 << 9), 562 ROOT_NO_RELAXED_ORDERING = (1 << 10), 563 SHUTTING_DOWN = (1 << 11), 564 }; 565 566 enum { 567 ULP_CRYPTO_LOOKASIDE = 1 << 0, 568 }; 569 570 struct rx_sw_desc; 571 572 struct sge_fl { /* SGE free-buffer queue state */ 573 unsigned int avail; /* # of available Rx buffers */ 574 unsigned int pend_cred; /* new buffers since last FL DB ring */ 575 unsigned int cidx; /* consumer index */ 576 unsigned int pidx; /* producer index */ 577 unsigned long alloc_failed; /* # of times buffer allocation failed */ 578 unsigned long large_alloc_failed; 579 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 580 unsigned long low; /* # of times momentarily starving */ 581 unsigned long starving; 582 /* RO fields */ 583 unsigned int cntxt_id; /* SGE context id for the free list */ 584 unsigned int size; /* capacity of free list */ 585 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 586 __be64 *desc; /* address of HW Rx descriptor ring */ 587 dma_addr_t addr; /* bus address of HW ring start */ 588 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 589 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 590 }; 591 592 /* A packet gather list */ 593 struct pkt_gl { 594 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 595 struct page_frag frags[MAX_SKB_FRAGS]; 596 void *va; /* virtual address of first byte */ 597 unsigned int nfrags; /* # of fragments */ 598 unsigned int tot_len; /* total length of fragments */ 599 }; 600 601 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 602 const struct pkt_gl *gl); 603 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 604 /* LRO related declarations for ULD */ 605 struct t4_lro_mgr { 606 #define MAX_LRO_SESSIONS 64 607 u8 lro_session_cnt; /* # of sessions to aggregate */ 608 unsigned long lro_pkts; /* # of LRO super packets */ 609 unsigned long lro_merged; /* # of wire packets merged by LRO */ 610 struct sk_buff_head lroq; /* list of aggregated sessions */ 611 }; 612 613 struct sge_rspq { /* state for an SGE response queue */ 614 struct napi_struct napi; 615 const __be64 *cur_desc; /* current descriptor in queue */ 616 unsigned int cidx; /* consumer index */ 617 u8 gen; /* current generation bit */ 618 u8 intr_params; /* interrupt holdoff parameters */ 619 u8 next_intr_params; /* holdoff params for next interrupt */ 620 u8 adaptive_rx; 621 u8 pktcnt_idx; /* interrupt packet threshold */ 622 u8 uld; /* ULD handling this queue */ 623 u8 idx; /* queue index within its group */ 624 int offset; /* offset into current Rx buffer */ 625 u16 cntxt_id; /* SGE context id for the response q */ 626 u16 abs_id; /* absolute SGE id for the response q */ 627 __be64 *desc; /* address of HW response ring */ 628 dma_addr_t phys_addr; /* physical address of the ring */ 629 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 630 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 631 unsigned int iqe_len; /* entry size */ 632 unsigned int size; /* capacity of response queue */ 633 struct adapter *adap; 634 struct net_device *netdev; /* associated net device */ 635 rspq_handler_t handler; 636 rspq_flush_handler_t flush_handler; 637 struct t4_lro_mgr lro_mgr; 638 }; 639 640 struct sge_eth_stats { /* Ethernet queue statistics */ 641 unsigned long pkts; /* # of ethernet packets */ 642 unsigned long lro_pkts; /* # of LRO super packets */ 643 unsigned long lro_merged; /* # of wire packets merged by LRO */ 644 unsigned long rx_cso; /* # of Rx checksum offloads */ 645 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 646 unsigned long rx_drops; /* # of packets dropped due to no mem */ 647 }; 648 649 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 650 struct sge_rspq rspq; 651 struct sge_fl fl; 652 struct sge_eth_stats stats; 653 } ____cacheline_aligned_in_smp; 654 655 struct sge_ofld_stats { /* offload queue statistics */ 656 unsigned long pkts; /* # of packets */ 657 unsigned long imm; /* # of immediate-data packets */ 658 unsigned long an; /* # of asynchronous notifications */ 659 unsigned long nomem; /* # of responses deferred due to no mem */ 660 }; 661 662 struct sge_ofld_rxq { /* SW offload Rx queue */ 663 struct sge_rspq rspq; 664 struct sge_fl fl; 665 struct sge_ofld_stats stats; 666 } ____cacheline_aligned_in_smp; 667 668 struct tx_desc { 669 __be64 flit[8]; 670 }; 671 672 struct tx_sw_desc; 673 674 struct sge_txq { 675 unsigned int in_use; /* # of in-use Tx descriptors */ 676 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 677 unsigned int size; /* # of descriptors */ 678 unsigned int cidx; /* SW consumer index */ 679 unsigned int pidx; /* producer index */ 680 unsigned long stops; /* # of times q has been stopped */ 681 unsigned long restarts; /* # of queue restarts */ 682 unsigned int cntxt_id; /* SGE context id for the Tx q */ 683 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 684 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 685 struct sge_qstat *stat; /* queue status entry */ 686 dma_addr_t phys_addr; /* physical address of the ring */ 687 spinlock_t db_lock; 688 int db_disabled; 689 unsigned short db_pidx; 690 unsigned short db_pidx_inc; 691 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 692 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 693 }; 694 695 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 696 struct sge_txq q; 697 struct netdev_queue *txq; /* associated netdev TX queue */ 698 #ifdef CONFIG_CHELSIO_T4_DCB 699 u8 dcb_prio; /* DCB Priority bound to queue */ 700 #endif 701 unsigned long tso; /* # of TSO requests */ 702 unsigned long tx_cso; /* # of Tx checksum offloads */ 703 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 704 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 705 } ____cacheline_aligned_in_smp; 706 707 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 708 struct sge_txq q; 709 struct adapter *adap; 710 struct sk_buff_head sendq; /* list of backpressured packets */ 711 struct tasklet_struct qresume_tsk; /* restarts the queue */ 712 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 713 u8 full; /* the Tx ring is full */ 714 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 715 } ____cacheline_aligned_in_smp; 716 717 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 718 struct sge_txq q; 719 struct adapter *adap; 720 struct sk_buff_head sendq; /* list of backpressured packets */ 721 struct tasklet_struct qresume_tsk; /* restarts the queue */ 722 u8 full; /* the Tx ring is full */ 723 } ____cacheline_aligned_in_smp; 724 725 struct sge_uld_rxq_info { 726 char name[IFNAMSIZ]; /* name of ULD driver */ 727 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 728 u16 *msix_tbl; /* msix_tbl for uld */ 729 u16 *rspq_id; /* response queue id's of rxq */ 730 u16 nrxq; /* # of ingress uld queues */ 731 u16 nciq; /* # of completion queues */ 732 u8 uld; /* uld type */ 733 }; 734 735 struct sge_uld_txq_info { 736 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 737 atomic_t users; /* num users */ 738 u16 ntxq; /* # of egress uld queues */ 739 }; 740 741 struct sge { 742 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 743 struct sge_eth_txq ptptxq; 744 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 745 746 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 747 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 748 struct sge_uld_rxq_info **uld_rxq_info; 749 struct sge_uld_txq_info **uld_txq_info; 750 751 struct sge_rspq intrq ____cacheline_aligned_in_smp; 752 spinlock_t intrq_lock; 753 754 u16 max_ethqsets; /* # of available Ethernet queue sets */ 755 u16 ethqsets; /* # of active Ethernet queue sets */ 756 u16 ethtxq_rover; /* Tx queue to clean up next */ 757 u16 ofldqsets; /* # of active ofld queue sets */ 758 u16 nqs_per_uld; /* # of Rx queues per ULD */ 759 u16 timer_val[SGE_NTIMERS]; 760 u8 counter_val[SGE_NCOUNTERS]; 761 u32 fl_pg_order; /* large page allocation size */ 762 u32 stat_len; /* length of status page at ring end */ 763 u32 pktshift; /* padding between CPL & packet data */ 764 u32 fl_align; /* response queue message alignment */ 765 u32 fl_starve_thres; /* Free List starvation threshold */ 766 767 struct sge_idma_monitor_state idma_monitor; 768 unsigned int egr_start; 769 unsigned int egr_sz; 770 unsigned int ingr_start; 771 unsigned int ingr_sz; 772 void **egr_map; /* qid->queue egress queue map */ 773 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 774 unsigned long *starving_fl; 775 unsigned long *txq_maperr; 776 unsigned long *blocked_fl; 777 struct timer_list rx_timer; /* refills starving FLs */ 778 struct timer_list tx_timer; /* checks Tx queues */ 779 }; 780 781 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 782 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 783 784 struct l2t_data; 785 786 #ifdef CONFIG_PCI_IOV 787 788 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 789 * Configuration initialization for T5 only has SR-IOV functionality enabled 790 * on PF0-3 in order to simplify everything. 791 */ 792 #define NUM_OF_PF_WITH_SRIOV 4 793 794 #endif 795 796 struct doorbell_stats { 797 u32 db_drop; 798 u32 db_empty; 799 u32 db_full; 800 }; 801 802 struct hash_mac_addr { 803 struct list_head list; 804 u8 addr[ETH_ALEN]; 805 }; 806 807 struct uld_msix_bmap { 808 unsigned long *msix_bmap; 809 unsigned int mapsize; 810 spinlock_t lock; /* lock for acquiring bitmap */ 811 }; 812 813 struct uld_msix_info { 814 unsigned short vec; 815 char desc[IFNAMSIZ + 10]; 816 unsigned int idx; 817 }; 818 819 struct vf_info { 820 unsigned char vf_mac_addr[ETH_ALEN]; 821 unsigned int tx_rate; 822 bool pf_set_mac; 823 }; 824 825 struct mbox_list { 826 struct list_head list; 827 }; 828 829 struct adapter { 830 void __iomem *regs; 831 void __iomem *bar2; 832 u32 t4_bar0; 833 struct pci_dev *pdev; 834 struct device *pdev_dev; 835 const char *name; 836 unsigned int mbox; 837 unsigned int pf; 838 unsigned int flags; 839 unsigned int adap_idx; 840 enum chip_type chip; 841 842 int msg_enable; 843 844 struct adapter_params params; 845 struct cxgb4_virt_res vres; 846 unsigned int swintr; 847 848 struct { 849 unsigned short vec; 850 char desc[IFNAMSIZ + 10]; 851 } msix_info[MAX_INGQ + 1]; 852 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 853 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 854 int msi_idx; 855 856 struct doorbell_stats db_stats; 857 struct sge sge; 858 859 struct net_device *port[MAX_NPORTS]; 860 u8 chan_map[NCHAN]; /* channel -> port map */ 861 862 struct vf_info *vfinfo; 863 u8 num_vfs; 864 865 u32 filter_mode; 866 unsigned int l2t_start; 867 unsigned int l2t_end; 868 struct l2t_data *l2t; 869 unsigned int clipt_start; 870 unsigned int clipt_end; 871 struct clip_tbl *clipt; 872 struct smt_data *smt; 873 struct cxgb4_uld_info *uld; 874 void *uld_handle[CXGB4_ULD_MAX]; 875 unsigned int num_uld; 876 unsigned int num_ofld_uld; 877 struct list_head list_node; 878 struct list_head rcu_node; 879 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 880 881 void *iscsi_ppm; 882 883 struct tid_info tids; 884 void **tid_release_head; 885 spinlock_t tid_release_lock; 886 struct workqueue_struct *workq; 887 struct work_struct tid_release_task; 888 struct work_struct db_full_task; 889 struct work_struct db_drop_task; 890 bool tid_release_task_busy; 891 892 /* lock for mailbox cmd list */ 893 spinlock_t mbox_lock; 894 struct mbox_list mlist; 895 896 /* support for mailbox command/reply logging */ 897 #define T4_OS_LOG_MBOX_CMDS 256 898 struct mbox_cmd_log *mbox_log; 899 900 struct mutex uld_mutex; 901 902 struct dentry *debugfs_root; 903 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 904 bool trace_rss; /* 1 implies that different RSS flit per filter is 905 * used per filter else if 0 default RSS flit is 906 * used for all 4 filters. 907 */ 908 909 struct ptp_clock *ptp_clock; 910 struct ptp_clock_info ptp_clock_info; 911 struct sk_buff *ptp_tx_skb; 912 /* ptp lock */ 913 spinlock_t ptp_lock; 914 spinlock_t stats_lock; 915 spinlock_t win0_lock ____cacheline_aligned_in_smp; 916 917 /* TC u32 offload */ 918 struct cxgb4_tc_u32_table *tc_u32; 919 struct chcr_stats_debug chcr_stats; 920 921 /* TC flower offload */ 922 struct rhashtable flower_tbl; 923 struct rhashtable_params flower_ht_params; 924 struct timer_list flower_stats_timer; 925 struct work_struct flower_stats_work; 926 927 /* Ethtool Dump */ 928 struct ethtool_dump eth_dump; 929 }; 930 931 /* Support for "sched-class" command to allow a TX Scheduling Class to be 932 * programmed with various parameters. 933 */ 934 struct ch_sched_params { 935 s8 type; /* packet or flow */ 936 union { 937 struct { 938 s8 level; /* scheduler hierarchy level */ 939 s8 mode; /* per-class or per-flow */ 940 s8 rateunit; /* bit or packet rate */ 941 s8 ratemode; /* %port relative or kbps absolute */ 942 s8 channel; /* scheduler channel [0..N] */ 943 s8 class; /* scheduler class [0..N] */ 944 s32 minrate; /* minimum rate */ 945 s32 maxrate; /* maximum rate */ 946 s16 weight; /* percent weight */ 947 s16 pktsize; /* average packet size */ 948 } params; 949 } u; 950 }; 951 952 enum { 953 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 954 }; 955 956 enum { 957 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 958 }; 959 960 enum { 961 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 962 }; 963 964 enum { 965 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 966 }; 967 968 enum { 969 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 970 }; 971 972 /* Support for "sched_queue" command to allow one or more NIC TX Queues 973 * to be bound to a TX Scheduling Class. 974 */ 975 struct ch_sched_queue { 976 s8 queue; /* queue index */ 977 s8 class; /* class index */ 978 }; 979 980 /* Defined bit width of user definable filter tuples 981 */ 982 #define ETHTYPE_BITWIDTH 16 983 #define FRAG_BITWIDTH 1 984 #define MACIDX_BITWIDTH 9 985 #define FCOE_BITWIDTH 1 986 #define IPORT_BITWIDTH 3 987 #define MATCHTYPE_BITWIDTH 3 988 #define PROTO_BITWIDTH 8 989 #define TOS_BITWIDTH 8 990 #define PF_BITWIDTH 8 991 #define VF_BITWIDTH 8 992 #define IVLAN_BITWIDTH 16 993 #define OVLAN_BITWIDTH 16 994 995 /* Filter matching rules. These consist of a set of ingress packet field 996 * (value, mask) tuples. The associated ingress packet field matches the 997 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 998 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 999 * matches an ingress packet when all of the individual individual field 1000 * matching rules are true. 1001 * 1002 * Partial field masks are always valid, however, while it may be easy to 1003 * understand their meanings for some fields (e.g. IP address to match a 1004 * subnet), for others making sensible partial masks is less intuitive (e.g. 1005 * MPS match type) ... 1006 * 1007 * Most of the following data structures are modeled on T4 capabilities. 1008 * Drivers for earlier chips use the subsets which make sense for those chips. 1009 * We really need to come up with a hardware-independent mechanism to 1010 * represent hardware filter capabilities ... 1011 */ 1012 struct ch_filter_tuple { 1013 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1014 * register selects which of these fields will participate in the 1015 * filter match rules -- up to a maximum of 36 bits. Because 1016 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1017 * set of fields. 1018 */ 1019 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1020 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1021 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1022 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1023 uint32_t pfvf_vld:1; /* PF/VF valid */ 1024 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1025 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1026 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1027 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1028 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1029 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1030 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1031 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1032 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1033 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1034 1035 /* Uncompressed header matching field rules. These are always 1036 * available for field rules. 1037 */ 1038 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1039 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1040 uint16_t lport; /* local port */ 1041 uint16_t fport; /* foreign port */ 1042 }; 1043 1044 /* A filter ioctl command. 1045 */ 1046 struct ch_filter_specification { 1047 /* Administrative fields for filter. 1048 */ 1049 uint32_t hitcnts:1; /* count filter hits in TCB */ 1050 uint32_t prio:1; /* filter has priority over active/server */ 1051 1052 /* Fundamental filter typing. This is the one element of filter 1053 * matching that doesn't exist as a (value, mask) tuple. 1054 */ 1055 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1056 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1057 1058 /* Packet dispatch information. Ingress packets which match the 1059 * filter rules will be dropped, passed to the host or switched back 1060 * out as egress packets. 1061 */ 1062 uint32_t action:2; /* drop, pass, switch */ 1063 1064 uint32_t rpttid:1; /* report TID in RSS hash field */ 1065 1066 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1067 uint32_t iq:10; /* ingress queue */ 1068 1069 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1070 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1071 /* 1 => TCB contains IQ ID */ 1072 1073 /* Switch proxy/rewrite fields. An ingress packet which matches a 1074 * filter with "switch" set will be looped back out as an egress 1075 * packet -- potentially with some Ethernet header rewriting. 1076 */ 1077 uint32_t eport:2; /* egress port to switch packet out */ 1078 uint32_t newdmac:1; /* rewrite destination MAC address */ 1079 uint32_t newsmac:1; /* rewrite source MAC address */ 1080 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1081 uint32_t nat_mode:3; /* specify NAT operation mode */ 1082 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1083 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1084 uint16_t vlan; /* VLAN Tag to insert */ 1085 1086 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1087 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1088 u16 nat_lport; /* local port to use after NAT'ing */ 1089 u16 nat_fport; /* foreign port to use after NAT'ing */ 1090 1091 /* reservation for future additions */ 1092 u8 rsvd[24]; 1093 1094 /* Filter rule value/mask pairs. 1095 */ 1096 struct ch_filter_tuple val; 1097 struct ch_filter_tuple mask; 1098 }; 1099 1100 enum { 1101 FILTER_PASS = 0, /* default */ 1102 FILTER_DROP, 1103 FILTER_SWITCH 1104 }; 1105 1106 enum { 1107 VLAN_NOCHANGE = 0, /* default */ 1108 VLAN_REMOVE, 1109 VLAN_INSERT, 1110 VLAN_REWRITE 1111 }; 1112 1113 enum { 1114 NAT_MODE_NONE = 0, /* No NAT performed */ 1115 NAT_MODE_DIP, /* NAT on Dst IP */ 1116 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1117 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1118 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1119 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1120 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1121 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1122 }; 1123 1124 /* Host shadow copy of ingress filter entry. This is in host native format 1125 * and doesn't match the ordering or bit order, etc. of the hardware of the 1126 * firmware command. The use of bit-field structure elements is purely to 1127 * remind ourselves of the field size limitations and save memory in the case 1128 * where the filter table is large. 1129 */ 1130 struct filter_entry { 1131 /* Administrative fields for filter. */ 1132 u32 valid:1; /* filter allocated and valid */ 1133 u32 locked:1; /* filter is administratively locked */ 1134 1135 u32 pending:1; /* filter action is pending firmware reply */ 1136 struct filter_ctx *ctx; /* Caller's completion hook */ 1137 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1138 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1139 struct net_device *dev; /* Associated net device */ 1140 u32 tid; /* This will store the actual tid */ 1141 1142 /* The filter itself. Most of this is a straight copy of information 1143 * provided by the extended ioctl(). Some fields are translated to 1144 * internal forms -- for instance the Ingress Queue ID passed in from 1145 * the ioctl() is translated into the Absolute Ingress Queue ID. 1146 */ 1147 struct ch_filter_specification fs; 1148 }; 1149 1150 static inline int is_offload(const struct adapter *adap) 1151 { 1152 return adap->params.offload; 1153 } 1154 1155 static inline int is_hashfilter(const struct adapter *adap) 1156 { 1157 return adap->params.hash_filter; 1158 } 1159 1160 static inline int is_pci_uld(const struct adapter *adap) 1161 { 1162 return adap->params.crypto; 1163 } 1164 1165 static inline int is_uld(const struct adapter *adap) 1166 { 1167 return (adap->params.offload || adap->params.crypto); 1168 } 1169 1170 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1171 { 1172 return readl(adap->regs + reg_addr); 1173 } 1174 1175 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1176 { 1177 writel(val, adap->regs + reg_addr); 1178 } 1179 1180 #ifndef readq 1181 static inline u64 readq(const volatile void __iomem *addr) 1182 { 1183 return readl(addr) + ((u64)readl(addr + 4) << 32); 1184 } 1185 1186 static inline void writeq(u64 val, volatile void __iomem *addr) 1187 { 1188 writel(val, addr); 1189 writel(val >> 32, addr + 4); 1190 } 1191 #endif 1192 1193 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1194 { 1195 return readq(adap->regs + reg_addr); 1196 } 1197 1198 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1199 { 1200 writeq(val, adap->regs + reg_addr); 1201 } 1202 1203 /** 1204 * t4_set_hw_addr - store a port's MAC address in SW 1205 * @adapter: the adapter 1206 * @port_idx: the port index 1207 * @hw_addr: the Ethernet address 1208 * 1209 * Store the Ethernet address of the given port in SW. Called by the common 1210 * code when it retrieves a port's Ethernet address from EEPROM. 1211 */ 1212 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1213 u8 hw_addr[]) 1214 { 1215 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1216 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1217 } 1218 1219 /** 1220 * netdev2pinfo - return the port_info structure associated with a net_device 1221 * @dev: the netdev 1222 * 1223 * Return the struct port_info associated with a net_device 1224 */ 1225 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1226 { 1227 return netdev_priv(dev); 1228 } 1229 1230 /** 1231 * adap2pinfo - return the port_info of a port 1232 * @adap: the adapter 1233 * @idx: the port index 1234 * 1235 * Return the port_info structure for the port of the given index. 1236 */ 1237 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1238 { 1239 return netdev_priv(adap->port[idx]); 1240 } 1241 1242 /** 1243 * netdev2adap - return the adapter structure associated with a net_device 1244 * @dev: the netdev 1245 * 1246 * Return the struct adapter associated with a net_device 1247 */ 1248 static inline struct adapter *netdev2adap(const struct net_device *dev) 1249 { 1250 return netdev2pinfo(dev)->adapter; 1251 } 1252 1253 /* Return a version number to identify the type of adapter. The scheme is: 1254 * - bits 0..9: chip version 1255 * - bits 10..15: chip revision 1256 * - bits 16..23: register dump version 1257 */ 1258 static inline unsigned int mk_adap_vers(struct adapter *ap) 1259 { 1260 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1261 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1262 } 1263 1264 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1265 static inline unsigned int qtimer_val(const struct adapter *adap, 1266 const struct sge_rspq *q) 1267 { 1268 unsigned int idx = q->intr_params >> 1; 1269 1270 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1271 } 1272 1273 /* driver version & name used for ethtool_drvinfo */ 1274 extern char cxgb4_driver_name[]; 1275 extern const char cxgb4_driver_version[]; 1276 1277 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1278 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1279 1280 void t4_free_sge_resources(struct adapter *adap); 1281 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1282 irq_handler_t t4_intr_handler(struct adapter *adap); 1283 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1284 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1285 const struct pkt_gl *gl); 1286 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1287 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1288 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1289 struct net_device *dev, int intr_idx, 1290 struct sge_fl *fl, rspq_handler_t hnd, 1291 rspq_flush_handler_t flush_handler, int cong); 1292 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1293 struct net_device *dev, struct netdev_queue *netdevq, 1294 unsigned int iqid); 1295 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1296 struct net_device *dev, unsigned int iqid, 1297 unsigned int cmplqid); 1298 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1299 unsigned int cmplqid); 1300 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1301 struct net_device *dev, unsigned int iqid, 1302 unsigned int uld_type); 1303 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1304 int t4_sge_init(struct adapter *adap); 1305 void t4_sge_start(struct adapter *adap); 1306 void t4_sge_stop(struct adapter *adap); 1307 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1308 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1309 extern int dbfifo_int_thresh; 1310 1311 #define for_each_port(adapter, iter) \ 1312 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1313 1314 static inline int is_bypass(struct adapter *adap) 1315 { 1316 return adap->params.bypass; 1317 } 1318 1319 static inline int is_bypass_device(int device) 1320 { 1321 /* this should be set based upon device capabilities */ 1322 switch (device) { 1323 case 0x440b: 1324 case 0x440c: 1325 return 1; 1326 default: 1327 return 0; 1328 } 1329 } 1330 1331 static inline int is_10gbt_device(int device) 1332 { 1333 /* this should be set based upon device capabilities */ 1334 switch (device) { 1335 case 0x4409: 1336 case 0x4486: 1337 return 1; 1338 1339 default: 1340 return 0; 1341 } 1342 } 1343 1344 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1345 { 1346 return adap->params.vpd.cclk / 1000; 1347 } 1348 1349 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1350 unsigned int us) 1351 { 1352 return (us * adap->params.vpd.cclk) / 1000; 1353 } 1354 1355 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1356 unsigned int ticks) 1357 { 1358 /* add Core Clock / 2 to round ticks to nearest uS */ 1359 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1360 adapter->params.vpd.cclk); 1361 } 1362 1363 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1364 unsigned int ticks) 1365 { 1366 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1367 } 1368 1369 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1370 u32 val); 1371 1372 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1373 int size, void *rpl, bool sleep_ok, int timeout); 1374 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1375 void *rpl, bool sleep_ok); 1376 1377 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1378 const void *cmd, int size, void *rpl, 1379 int timeout) 1380 { 1381 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1382 timeout); 1383 } 1384 1385 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1386 int size, void *rpl) 1387 { 1388 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1389 } 1390 1391 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1392 int size, void *rpl) 1393 { 1394 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1395 } 1396 1397 /** 1398 * hash_mac_addr - return the hash value of a MAC address 1399 * @addr: the 48-bit Ethernet MAC address 1400 * 1401 * Hashes a MAC address according to the hash function used by HW inexact 1402 * (hash) address matching. 1403 */ 1404 static inline int hash_mac_addr(const u8 *addr) 1405 { 1406 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1407 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1408 1409 a ^= b; 1410 a ^= (a >> 12); 1411 a ^= (a >> 6); 1412 return a & 0x3f; 1413 } 1414 1415 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1416 unsigned int cnt); 1417 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1418 unsigned int us, unsigned int cnt, 1419 unsigned int size, unsigned int iqe_size) 1420 { 1421 q->adap = adap; 1422 cxgb4_set_rspq_intr_params(q, us, cnt); 1423 q->iqe_len = iqe_size; 1424 q->size = size; 1425 } 1426 1427 /** 1428 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1429 * @fw_mod_type: the Firmware Mofule Type 1430 * 1431 * Return whether the Firmware Module Type represents a real Transceiver 1432 * Module/Cable Module Type which has been inserted. 1433 */ 1434 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1435 { 1436 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1437 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1438 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1439 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1440 } 1441 1442 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1443 unsigned int data_reg, const u32 *vals, 1444 unsigned int nregs, unsigned int start_idx); 1445 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1446 unsigned int data_reg, u32 *vals, unsigned int nregs, 1447 unsigned int start_idx); 1448 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1449 1450 struct fw_filter_wr; 1451 1452 void t4_intr_enable(struct adapter *adapter); 1453 void t4_intr_disable(struct adapter *adapter); 1454 int t4_slow_intr_handler(struct adapter *adapter); 1455 1456 int t4_wait_dev_ready(void __iomem *regs); 1457 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1458 struct link_config *lc); 1459 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1460 1461 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1462 u32 t4_get_util_window(struct adapter *adap); 1463 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1464 1465 #define T4_MEMORY_WRITE 0 1466 #define T4_MEMORY_READ 1 1467 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1468 void *buf, int dir); 1469 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1470 u32 len, __be32 *buf) 1471 { 1472 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1473 } 1474 1475 unsigned int t4_get_regs_len(struct adapter *adapter); 1476 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1477 1478 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1479 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1480 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1481 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1482 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1483 unsigned int nwords, u32 *data, int byte_oriented); 1484 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1485 int t4_load_phy_fw(struct adapter *adap, 1486 int win, spinlock_t *lock, 1487 int (*phy_fw_version)(const u8 *, size_t), 1488 const u8 *phy_fw_data, size_t phy_fw_size); 1489 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1490 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1491 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1492 const u8 *fw_data, unsigned int size, int force); 1493 int t4_fl_pkt_align(struct adapter *adap); 1494 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1495 int t4_check_fw_version(struct adapter *adap); 1496 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1497 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1498 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1499 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1500 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1501 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1502 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1503 int t4_get_version_info(struct adapter *adapter); 1504 void t4_dump_version_info(struct adapter *adapter); 1505 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1506 const u8 *fw_data, unsigned int fw_size, 1507 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1508 int t4_prep_adapter(struct adapter *adapter); 1509 int t4_shutdown_adapter(struct adapter *adapter); 1510 1511 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1512 int t4_bar2_sge_qregs(struct adapter *adapter, 1513 unsigned int qid, 1514 enum t4_bar2_qtype qtype, 1515 int user, 1516 u64 *pbar2_qoffset, 1517 unsigned int *pbar2_qid); 1518 1519 unsigned int qtimer_val(const struct adapter *adap, 1520 const struct sge_rspq *q); 1521 1522 int t4_init_devlog_params(struct adapter *adapter); 1523 int t4_init_sge_params(struct adapter *adapter); 1524 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1525 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1526 int t4_init_rss_mode(struct adapter *adap, int mbox); 1527 int t4_init_portinfo(struct port_info *pi, int mbox, 1528 int port, int pf, int vf, u8 mac[]); 1529 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1530 void t4_fatal_err(struct adapter *adapter); 1531 unsigned int t4_chip_rss_size(struct adapter *adapter); 1532 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1533 int start, int n, const u16 *rspq, unsigned int nrspq); 1534 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1535 unsigned int flags); 1536 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1537 unsigned int flags, unsigned int defq); 1538 int t4_read_rss(struct adapter *adapter, u16 *entries); 1539 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1540 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1541 bool sleep_ok); 1542 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1543 u32 *valp, bool sleep_ok); 1544 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1545 u32 *vfl, u32 *vfh, bool sleep_ok); 1546 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1547 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1548 1549 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1550 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1551 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1552 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1553 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1554 size_t n); 1555 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1556 size_t n); 1557 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1558 unsigned int *valp); 1559 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1560 const unsigned int *valp); 1561 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1562 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1563 unsigned int *pif_req_wrptr, 1564 unsigned int *pif_rsp_wrptr); 1565 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1566 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1567 const char *t4_get_port_type_description(enum fw_port_type port_type); 1568 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1569 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1570 struct port_stats *stats, 1571 struct port_stats *offset); 1572 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1573 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1574 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1575 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1576 unsigned int mask, unsigned int val); 1577 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1578 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1579 bool sleep_ok); 1580 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1581 bool sleep_ok); 1582 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1583 bool sleep_ok); 1584 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1585 bool sleep_ok); 1586 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1587 struct tp_tcp_stats *v6, bool sleep_ok); 1588 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1589 struct tp_fcoe_stats *st, bool sleep_ok); 1590 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1591 const unsigned short *alpha, const unsigned short *beta); 1592 1593 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1594 1595 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1596 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1597 1598 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1599 const u8 *addr); 1600 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1601 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1602 1603 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1604 enum dev_master master, enum dev_state *state); 1605 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1606 int t4_early_init(struct adapter *adap, unsigned int mbox); 1607 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1608 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1609 unsigned int cache_line_size); 1610 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1611 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1612 unsigned int vf, unsigned int nparams, const u32 *params, 1613 u32 *val); 1614 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1615 unsigned int vf, unsigned int nparams, const u32 *params, 1616 u32 *val); 1617 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1618 unsigned int vf, unsigned int nparams, const u32 *params, 1619 u32 *val, int rw, bool sleep_ok); 1620 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1621 unsigned int pf, unsigned int vf, 1622 unsigned int nparams, const u32 *params, 1623 const u32 *val, int timeout); 1624 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1625 unsigned int vf, unsigned int nparams, const u32 *params, 1626 const u32 *val); 1627 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1628 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1629 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1630 unsigned int vi, unsigned int cmask, unsigned int pmask, 1631 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1632 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1633 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1634 unsigned int *rss_size); 1635 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1636 unsigned int pf, unsigned int vf, 1637 unsigned int viid); 1638 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1639 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1640 bool sleep_ok); 1641 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1642 unsigned int viid, bool free, unsigned int naddr, 1643 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1644 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1645 unsigned int viid, unsigned int naddr, 1646 const u8 **addr, bool sleep_ok); 1647 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1648 int idx, const u8 *addr, bool persist, bool add_smt); 1649 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1650 bool ucast, u64 vec, bool sleep_ok); 1651 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1652 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1653 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1654 bool rx_en, bool tx_en); 1655 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1656 unsigned int nblinks); 1657 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1658 unsigned int mmd, unsigned int reg, u16 *valp); 1659 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1660 unsigned int mmd, unsigned int reg, u16 val); 1661 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1662 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1663 unsigned int fl0id, unsigned int fl1id); 1664 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1665 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1666 unsigned int fl0id, unsigned int fl1id); 1667 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1668 unsigned int vf, unsigned int eqid); 1669 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1670 unsigned int vf, unsigned int eqid); 1671 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1672 unsigned int vf, unsigned int eqid); 1673 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1674 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1675 int t4_update_port_info(struct port_info *pi); 1676 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1677 unsigned int *speedp, unsigned int *mtup); 1678 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1679 void t4_db_full(struct adapter *adapter); 1680 void t4_db_dropped(struct adapter *adapter); 1681 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1682 int filter_index, int enable); 1683 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1684 int filter_index, int *enabled); 1685 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1686 u32 addr, u32 val); 1687 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1688 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1689 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1690 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1691 enum ctxt_type ctype, u32 *data); 1692 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1693 enum ctxt_type ctype, u32 *data); 1694 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1695 int rateunit, int ratemode, int channel, int class, 1696 int minrate, int maxrate, int weight, int pktsize); 1697 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1698 void t4_idma_monitor_init(struct adapter *adapter, 1699 struct sge_idma_monitor_state *idma); 1700 void t4_idma_monitor(struct adapter *adapter, 1701 struct sge_idma_monitor_state *idma, 1702 int hz, int ticks); 1703 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1704 unsigned int naddr, u8 *addr); 1705 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1706 u32 start_index, bool sleep_ok); 1707 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1708 u32 start_index, bool sleep_ok); 1709 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1710 u32 start_index, bool sleep_ok); 1711 1712 void t4_uld_mem_free(struct adapter *adap); 1713 int t4_uld_mem_alloc(struct adapter *adap); 1714 void t4_uld_clean_up(struct adapter *adap); 1715 void t4_register_netevent_notifier(void); 1716 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1717 unsigned int devid, unsigned int offset, 1718 unsigned int len, u8 *buf); 1719 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1720 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1721 unsigned int n, bool unmap); 1722 void free_txq(struct adapter *adap, struct sge_txq *q); 1723 #endif /* __CXGB4_H__ */ 1724