1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <asm/io.h> 50 #include "cxgb4_uld.h" 51 #include "t4_hw.h" 52 53 #define FW_VERSION_MAJOR 1 54 #define FW_VERSION_MINOR 1 55 #define FW_VERSION_MICRO 0 56 57 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 58 59 enum { 60 MAX_NPORTS = 4, /* max # of ports */ 61 SERNUM_LEN = 24, /* Serial # length */ 62 EC_LEN = 16, /* E/C length */ 63 ID_LEN = 16, /* ID length */ 64 }; 65 66 enum { 67 MEM_EDC0, 68 MEM_EDC1, 69 MEM_MC 70 }; 71 72 enum { 73 MEMWIN0_APERTURE = 2048, 74 MEMWIN0_BASE = 0x1b800, 75 MEMWIN1_APERTURE = 32768, 76 MEMWIN1_BASE = 0x28000, 77 MEMWIN2_APERTURE = 65536, 78 MEMWIN2_BASE = 0x30000, 79 }; 80 81 enum dev_master { 82 MASTER_CANT, 83 MASTER_MAY, 84 MASTER_MUST 85 }; 86 87 enum dev_state { 88 DEV_STATE_UNINIT, 89 DEV_STATE_INIT, 90 DEV_STATE_ERR 91 }; 92 93 enum { 94 PAUSE_RX = 1 << 0, 95 PAUSE_TX = 1 << 1, 96 PAUSE_AUTONEG = 1 << 2 97 }; 98 99 struct port_stats { 100 u64 tx_octets; /* total # of octets in good frames */ 101 u64 tx_frames; /* all good frames */ 102 u64 tx_bcast_frames; /* all broadcast frames */ 103 u64 tx_mcast_frames; /* all multicast frames */ 104 u64 tx_ucast_frames; /* all unicast frames */ 105 u64 tx_error_frames; /* all error frames */ 106 107 u64 tx_frames_64; /* # of Tx frames in a particular range */ 108 u64 tx_frames_65_127; 109 u64 tx_frames_128_255; 110 u64 tx_frames_256_511; 111 u64 tx_frames_512_1023; 112 u64 tx_frames_1024_1518; 113 u64 tx_frames_1519_max; 114 115 u64 tx_drop; /* # of dropped Tx frames */ 116 u64 tx_pause; /* # of transmitted pause frames */ 117 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 118 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 119 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 120 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 121 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 122 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 123 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 124 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 125 126 u64 rx_octets; /* total # of octets in good frames */ 127 u64 rx_frames; /* all good frames */ 128 u64 rx_bcast_frames; /* all broadcast frames */ 129 u64 rx_mcast_frames; /* all multicast frames */ 130 u64 rx_ucast_frames; /* all unicast frames */ 131 u64 rx_too_long; /* # of frames exceeding MTU */ 132 u64 rx_jabber; /* # of jabber frames */ 133 u64 rx_fcs_err; /* # of received frames with bad FCS */ 134 u64 rx_len_err; /* # of received frames with length error */ 135 u64 rx_symbol_err; /* symbol errors */ 136 u64 rx_runt; /* # of short frames */ 137 138 u64 rx_frames_64; /* # of Rx frames in a particular range */ 139 u64 rx_frames_65_127; 140 u64 rx_frames_128_255; 141 u64 rx_frames_256_511; 142 u64 rx_frames_512_1023; 143 u64 rx_frames_1024_1518; 144 u64 rx_frames_1519_max; 145 146 u64 rx_pause; /* # of received pause frames */ 147 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 148 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 149 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 150 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 151 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 152 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 153 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 154 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 155 156 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 157 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 158 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 159 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 160 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 161 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 162 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 163 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 164 }; 165 166 struct lb_port_stats { 167 u64 octets; 168 u64 frames; 169 u64 bcast_frames; 170 u64 mcast_frames; 171 u64 ucast_frames; 172 u64 error_frames; 173 174 u64 frames_64; 175 u64 frames_65_127; 176 u64 frames_128_255; 177 u64 frames_256_511; 178 u64 frames_512_1023; 179 u64 frames_1024_1518; 180 u64 frames_1519_max; 181 182 u64 drop; 183 184 u64 ovflow0; 185 u64 ovflow1; 186 u64 ovflow2; 187 u64 ovflow3; 188 u64 trunc0; 189 u64 trunc1; 190 u64 trunc2; 191 u64 trunc3; 192 }; 193 194 struct tp_tcp_stats { 195 u32 tcpOutRsts; 196 u64 tcpInSegs; 197 u64 tcpOutSegs; 198 u64 tcpRetransSegs; 199 }; 200 201 struct tp_err_stats { 202 u32 macInErrs[4]; 203 u32 hdrInErrs[4]; 204 u32 tcpInErrs[4]; 205 u32 tnlCongDrops[4]; 206 u32 ofldChanDrops[4]; 207 u32 tnlTxDrops[4]; 208 u32 ofldVlanDrops[4]; 209 u32 tcp6InErrs[4]; 210 u32 ofldNoNeigh; 211 u32 ofldCongDefer; 212 }; 213 214 struct tp_params { 215 unsigned int ntxchan; /* # of Tx channels */ 216 unsigned int tre; /* log2 of core clocks per TP tick */ 217 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 218 /* channel map */ 219 220 uint32_t dack_re; /* DACK timer resolution */ 221 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 222 }; 223 224 struct vpd_params { 225 unsigned int cclk; 226 u8 ec[EC_LEN + 1]; 227 u8 sn[SERNUM_LEN + 1]; 228 u8 id[ID_LEN + 1]; 229 }; 230 231 struct pci_params { 232 unsigned char speed; 233 unsigned char width; 234 }; 235 236 struct adapter_params { 237 struct tp_params tp; 238 struct vpd_params vpd; 239 struct pci_params pci; 240 241 unsigned int sf_size; /* serial flash size in bytes */ 242 unsigned int sf_nsec; /* # of flash sectors */ 243 unsigned int sf_fw_start; /* start of FW image in flash */ 244 245 unsigned int fw_vers; 246 unsigned int tp_vers; 247 u8 api_vers[7]; 248 249 unsigned short mtus[NMTUS]; 250 unsigned short a_wnd[NCCTRL_WIN]; 251 unsigned short b_wnd[NCCTRL_WIN]; 252 253 unsigned char nports; /* # of ethernet ports */ 254 unsigned char portvec; 255 unsigned char rev; /* chip revision */ 256 unsigned char offload; 257 258 unsigned char bypass; 259 260 unsigned int ofldq_wr_cred; 261 }; 262 263 struct trace_params { 264 u32 data[TRACE_LEN / 4]; 265 u32 mask[TRACE_LEN / 4]; 266 unsigned short snap_len; 267 unsigned short min_len; 268 unsigned char skip_ofst; 269 unsigned char skip_len; 270 unsigned char invert; 271 unsigned char port; 272 }; 273 274 struct link_config { 275 unsigned short supported; /* link capabilities */ 276 unsigned short advertising; /* advertised capabilities */ 277 unsigned short requested_speed; /* speed user has requested */ 278 unsigned short speed; /* actual link speed */ 279 unsigned char requested_fc; /* flow control user has requested */ 280 unsigned char fc; /* actual link flow control */ 281 unsigned char autoneg; /* autonegotiating? */ 282 unsigned char link_ok; /* link up? */ 283 }; 284 285 #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16) 286 287 enum { 288 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 289 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 290 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 291 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 292 }; 293 294 enum { 295 MAX_EGRQ = 128, /* max # of egress queues, including FLs */ 296 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */ 297 }; 298 299 struct adapter; 300 struct sge_rspq; 301 302 struct port_info { 303 struct adapter *adapter; 304 u16 viid; 305 s16 xact_addr_filt; /* index of exact MAC address filter */ 306 u16 rss_size; /* size of VI's RSS table slice */ 307 s8 mdio_addr; 308 u8 port_type; 309 u8 mod_type; 310 u8 port_id; 311 u8 tx_chan; 312 u8 lport; /* associated offload logical port */ 313 u8 nqsets; /* # of qsets */ 314 u8 first_qset; /* index of first qset */ 315 u8 rss_mode; 316 struct link_config link_cfg; 317 u16 *rss; 318 }; 319 320 struct dentry; 321 struct work_struct; 322 323 enum { /* adapter flags */ 324 FULL_INIT_DONE = (1 << 0), 325 USING_MSI = (1 << 1), 326 USING_MSIX = (1 << 2), 327 FW_OK = (1 << 4), 328 RSS_TNLALLLOOKUP = (1 << 5), 329 USING_SOFT_PARAMS = (1 << 6), 330 MASTER_PF = (1 << 7), 331 FW_OFLD_CONN = (1 << 9), 332 }; 333 334 struct rx_sw_desc; 335 336 struct sge_fl { /* SGE free-buffer queue state */ 337 unsigned int avail; /* # of available Rx buffers */ 338 unsigned int pend_cred; /* new buffers since last FL DB ring */ 339 unsigned int cidx; /* consumer index */ 340 unsigned int pidx; /* producer index */ 341 unsigned long alloc_failed; /* # of times buffer allocation failed */ 342 unsigned long large_alloc_failed; 343 unsigned long starving; 344 /* RO fields */ 345 unsigned int cntxt_id; /* SGE context id for the free list */ 346 unsigned int size; /* capacity of free list */ 347 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 348 __be64 *desc; /* address of HW Rx descriptor ring */ 349 dma_addr_t addr; /* bus address of HW ring start */ 350 }; 351 352 /* A packet gather list */ 353 struct pkt_gl { 354 struct page_frag frags[MAX_SKB_FRAGS]; 355 void *va; /* virtual address of first byte */ 356 unsigned int nfrags; /* # of fragments */ 357 unsigned int tot_len; /* total length of fragments */ 358 }; 359 360 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 361 const struct pkt_gl *gl); 362 363 struct sge_rspq { /* state for an SGE response queue */ 364 struct napi_struct napi; 365 const __be64 *cur_desc; /* current descriptor in queue */ 366 unsigned int cidx; /* consumer index */ 367 u8 gen; /* current generation bit */ 368 u8 intr_params; /* interrupt holdoff parameters */ 369 u8 next_intr_params; /* holdoff params for next interrupt */ 370 u8 pktcnt_idx; /* interrupt packet threshold */ 371 u8 uld; /* ULD handling this queue */ 372 u8 idx; /* queue index within its group */ 373 int offset; /* offset into current Rx buffer */ 374 u16 cntxt_id; /* SGE context id for the response q */ 375 u16 abs_id; /* absolute SGE id for the response q */ 376 __be64 *desc; /* address of HW response ring */ 377 dma_addr_t phys_addr; /* physical address of the ring */ 378 unsigned int iqe_len; /* entry size */ 379 unsigned int size; /* capacity of response queue */ 380 struct adapter *adap; 381 struct net_device *netdev; /* associated net device */ 382 rspq_handler_t handler; 383 }; 384 385 struct sge_eth_stats { /* Ethernet queue statistics */ 386 unsigned long pkts; /* # of ethernet packets */ 387 unsigned long lro_pkts; /* # of LRO super packets */ 388 unsigned long lro_merged; /* # of wire packets merged by LRO */ 389 unsigned long rx_cso; /* # of Rx checksum offloads */ 390 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 391 unsigned long rx_drops; /* # of packets dropped due to no mem */ 392 }; 393 394 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 395 struct sge_rspq rspq; 396 struct sge_fl fl; 397 struct sge_eth_stats stats; 398 } ____cacheline_aligned_in_smp; 399 400 struct sge_ofld_stats { /* offload queue statistics */ 401 unsigned long pkts; /* # of packets */ 402 unsigned long imm; /* # of immediate-data packets */ 403 unsigned long an; /* # of asynchronous notifications */ 404 unsigned long nomem; /* # of responses deferred due to no mem */ 405 }; 406 407 struct sge_ofld_rxq { /* SW offload Rx queue */ 408 struct sge_rspq rspq; 409 struct sge_fl fl; 410 struct sge_ofld_stats stats; 411 } ____cacheline_aligned_in_smp; 412 413 struct tx_desc { 414 __be64 flit[8]; 415 }; 416 417 struct tx_sw_desc; 418 419 struct sge_txq { 420 unsigned int in_use; /* # of in-use Tx descriptors */ 421 unsigned int size; /* # of descriptors */ 422 unsigned int cidx; /* SW consumer index */ 423 unsigned int pidx; /* producer index */ 424 unsigned long stops; /* # of times q has been stopped */ 425 unsigned long restarts; /* # of queue restarts */ 426 unsigned int cntxt_id; /* SGE context id for the Tx q */ 427 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 428 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 429 struct sge_qstat *stat; /* queue status entry */ 430 dma_addr_t phys_addr; /* physical address of the ring */ 431 spinlock_t db_lock; 432 int db_disabled; 433 unsigned short db_pidx; 434 }; 435 436 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 437 struct sge_txq q; 438 struct netdev_queue *txq; /* associated netdev TX queue */ 439 unsigned long tso; /* # of TSO requests */ 440 unsigned long tx_cso; /* # of Tx checksum offloads */ 441 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 442 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 443 } ____cacheline_aligned_in_smp; 444 445 struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 446 struct sge_txq q; 447 struct adapter *adap; 448 struct sk_buff_head sendq; /* list of backpressured packets */ 449 struct tasklet_struct qresume_tsk; /* restarts the queue */ 450 u8 full; /* the Tx ring is full */ 451 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 452 } ____cacheline_aligned_in_smp; 453 454 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 455 struct sge_txq q; 456 struct adapter *adap; 457 struct sk_buff_head sendq; /* list of backpressured packets */ 458 struct tasklet_struct qresume_tsk; /* restarts the queue */ 459 u8 full; /* the Tx ring is full */ 460 } ____cacheline_aligned_in_smp; 461 462 struct sge { 463 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 464 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 465 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 466 467 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 468 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 469 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 470 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 471 472 struct sge_rspq intrq ____cacheline_aligned_in_smp; 473 spinlock_t intrq_lock; 474 475 u16 max_ethqsets; /* # of available Ethernet queue sets */ 476 u16 ethqsets; /* # of active Ethernet queue sets */ 477 u16 ethtxq_rover; /* Tx queue to clean up next */ 478 u16 ofldqsets; /* # of active offload queue sets */ 479 u16 rdmaqs; /* # of available RDMA Rx queues */ 480 u16 ofld_rxq[MAX_OFLD_QSETS]; 481 u16 rdma_rxq[NCHAN]; 482 u16 timer_val[SGE_NTIMERS]; 483 u8 counter_val[SGE_NCOUNTERS]; 484 u32 fl_pg_order; /* large page allocation size */ 485 u32 stat_len; /* length of status page at ring end */ 486 u32 pktshift; /* padding between CPL & packet data */ 487 u32 fl_align; /* response queue message alignment */ 488 u32 fl_starve_thres; /* Free List starvation threshold */ 489 unsigned int starve_thres; 490 u8 idma_state[2]; 491 unsigned int egr_start; 492 unsigned int ingr_start; 493 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */ 494 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */ 495 DECLARE_BITMAP(starving_fl, MAX_EGRQ); 496 DECLARE_BITMAP(txq_maperr, MAX_EGRQ); 497 struct timer_list rx_timer; /* refills starving FLs */ 498 struct timer_list tx_timer; /* checks Tx queues */ 499 }; 500 501 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 502 #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 503 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 504 505 struct l2t_data; 506 507 struct adapter { 508 void __iomem *regs; 509 struct pci_dev *pdev; 510 struct device *pdev_dev; 511 unsigned int mbox; 512 unsigned int fn; 513 unsigned int flags; 514 515 int msg_enable; 516 517 struct adapter_params params; 518 struct cxgb4_virt_res vres; 519 unsigned int swintr; 520 521 unsigned int wol; 522 523 struct { 524 unsigned short vec; 525 char desc[IFNAMSIZ + 10]; 526 } msix_info[MAX_INGQ + 1]; 527 528 struct sge sge; 529 530 struct net_device *port[MAX_NPORTS]; 531 u8 chan_map[NCHAN]; /* channel -> port map */ 532 533 u32 filter_mode; 534 unsigned int l2t_start; 535 unsigned int l2t_end; 536 struct l2t_data *l2t; 537 void *uld_handle[CXGB4_ULD_MAX]; 538 struct list_head list_node; 539 540 struct tid_info tids; 541 void **tid_release_head; 542 spinlock_t tid_release_lock; 543 struct work_struct tid_release_task; 544 struct work_struct db_full_task; 545 struct work_struct db_drop_task; 546 bool tid_release_task_busy; 547 548 struct dentry *debugfs_root; 549 550 spinlock_t stats_lock; 551 }; 552 553 /* Defined bit width of user definable filter tuples 554 */ 555 #define ETHTYPE_BITWIDTH 16 556 #define FRAG_BITWIDTH 1 557 #define MACIDX_BITWIDTH 9 558 #define FCOE_BITWIDTH 1 559 #define IPORT_BITWIDTH 3 560 #define MATCHTYPE_BITWIDTH 3 561 #define PROTO_BITWIDTH 8 562 #define TOS_BITWIDTH 8 563 #define PF_BITWIDTH 8 564 #define VF_BITWIDTH 8 565 #define IVLAN_BITWIDTH 16 566 #define OVLAN_BITWIDTH 16 567 568 /* Filter matching rules. These consist of a set of ingress packet field 569 * (value, mask) tuples. The associated ingress packet field matches the 570 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 571 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 572 * matches an ingress packet when all of the individual individual field 573 * matching rules are true. 574 * 575 * Partial field masks are always valid, however, while it may be easy to 576 * understand their meanings for some fields (e.g. IP address to match a 577 * subnet), for others making sensible partial masks is less intuitive (e.g. 578 * MPS match type) ... 579 * 580 * Most of the following data structures are modeled on T4 capabilities. 581 * Drivers for earlier chips use the subsets which make sense for those chips. 582 * We really need to come up with a hardware-independent mechanism to 583 * represent hardware filter capabilities ... 584 */ 585 struct ch_filter_tuple { 586 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 587 * register selects which of these fields will participate in the 588 * filter match rules -- up to a maximum of 36 bits. Because 589 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 590 * set of fields. 591 */ 592 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 593 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 594 uint32_t ivlan_vld:1; /* inner VLAN valid */ 595 uint32_t ovlan_vld:1; /* outer VLAN valid */ 596 uint32_t pfvf_vld:1; /* PF/VF valid */ 597 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 598 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 599 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 600 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 601 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 602 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 603 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 604 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 605 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 606 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 607 608 /* Uncompressed header matching field rules. These are always 609 * available for field rules. 610 */ 611 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 612 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 613 uint16_t lport; /* local port */ 614 uint16_t fport; /* foreign port */ 615 }; 616 617 /* A filter ioctl command. 618 */ 619 struct ch_filter_specification { 620 /* Administrative fields for filter. 621 */ 622 uint32_t hitcnts:1; /* count filter hits in TCB */ 623 uint32_t prio:1; /* filter has priority over active/server */ 624 625 /* Fundamental filter typing. This is the one element of filter 626 * matching that doesn't exist as a (value, mask) tuple. 627 */ 628 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 629 630 /* Packet dispatch information. Ingress packets which match the 631 * filter rules will be dropped, passed to the host or switched back 632 * out as egress packets. 633 */ 634 uint32_t action:2; /* drop, pass, switch */ 635 636 uint32_t rpttid:1; /* report TID in RSS hash field */ 637 638 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 639 uint32_t iq:10; /* ingress queue */ 640 641 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 642 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 643 /* 1 => TCB contains IQ ID */ 644 645 /* Switch proxy/rewrite fields. An ingress packet which matches a 646 * filter with "switch" set will be looped back out as an egress 647 * packet -- potentially with some Ethernet header rewriting. 648 */ 649 uint32_t eport:2; /* egress port to switch packet out */ 650 uint32_t newdmac:1; /* rewrite destination MAC address */ 651 uint32_t newsmac:1; /* rewrite source MAC address */ 652 uint32_t newvlan:2; /* rewrite VLAN Tag */ 653 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 654 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 655 uint16_t vlan; /* VLAN Tag to insert */ 656 657 /* Filter rule value/mask pairs. 658 */ 659 struct ch_filter_tuple val; 660 struct ch_filter_tuple mask; 661 }; 662 663 enum { 664 FILTER_PASS = 0, /* default */ 665 FILTER_DROP, 666 FILTER_SWITCH 667 }; 668 669 enum { 670 VLAN_NOCHANGE = 0, /* default */ 671 VLAN_REMOVE, 672 VLAN_INSERT, 673 VLAN_REWRITE 674 }; 675 676 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 677 { 678 return readl(adap->regs + reg_addr); 679 } 680 681 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 682 { 683 writel(val, adap->regs + reg_addr); 684 } 685 686 #ifndef readq 687 static inline u64 readq(const volatile void __iomem *addr) 688 { 689 return readl(addr) + ((u64)readl(addr + 4) << 32); 690 } 691 692 static inline void writeq(u64 val, volatile void __iomem *addr) 693 { 694 writel(val, addr); 695 writel(val >> 32, addr + 4); 696 } 697 #endif 698 699 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 700 { 701 return readq(adap->regs + reg_addr); 702 } 703 704 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 705 { 706 writeq(val, adap->regs + reg_addr); 707 } 708 709 /** 710 * netdev2pinfo - return the port_info structure associated with a net_device 711 * @dev: the netdev 712 * 713 * Return the struct port_info associated with a net_device 714 */ 715 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 716 { 717 return netdev_priv(dev); 718 } 719 720 /** 721 * adap2pinfo - return the port_info of a port 722 * @adap: the adapter 723 * @idx: the port index 724 * 725 * Return the port_info structure for the port of the given index. 726 */ 727 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 728 { 729 return netdev_priv(adap->port[idx]); 730 } 731 732 /** 733 * netdev2adap - return the adapter structure associated with a net_device 734 * @dev: the netdev 735 * 736 * Return the struct adapter associated with a net_device 737 */ 738 static inline struct adapter *netdev2adap(const struct net_device *dev) 739 { 740 return netdev2pinfo(dev)->adapter; 741 } 742 743 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 744 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 745 746 void *t4_alloc_mem(size_t size); 747 748 void t4_free_sge_resources(struct adapter *adap); 749 irq_handler_t t4_intr_handler(struct adapter *adap); 750 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 751 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 752 const struct pkt_gl *gl); 753 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 754 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 755 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 756 struct net_device *dev, int intr_idx, 757 struct sge_fl *fl, rspq_handler_t hnd); 758 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 759 struct net_device *dev, struct netdev_queue *netdevq, 760 unsigned int iqid); 761 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 762 struct net_device *dev, unsigned int iqid, 763 unsigned int cmplqid); 764 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 765 struct net_device *dev, unsigned int iqid); 766 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 767 int t4_sge_init(struct adapter *adap); 768 void t4_sge_start(struct adapter *adap); 769 void t4_sge_stop(struct adapter *adap); 770 extern int dbfifo_int_thresh; 771 772 #define for_each_port(adapter, iter) \ 773 for (iter = 0; iter < (adapter)->params.nports; ++iter) 774 775 static inline int is_bypass(struct adapter *adap) 776 { 777 return adap->params.bypass; 778 } 779 780 static inline int is_bypass_device(int device) 781 { 782 /* this should be set based upon device capabilities */ 783 switch (device) { 784 case 0x440b: 785 case 0x440c: 786 return 1; 787 default: 788 return 0; 789 } 790 } 791 792 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 793 { 794 return adap->params.vpd.cclk / 1000; 795 } 796 797 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 798 unsigned int us) 799 { 800 return (us * adap->params.vpd.cclk) / 1000; 801 } 802 803 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 804 unsigned int ticks) 805 { 806 /* add Core Clock / 2 to round ticks to nearest uS */ 807 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 808 adapter->params.vpd.cclk); 809 } 810 811 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 812 u32 val); 813 814 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 815 void *rpl, bool sleep_ok); 816 817 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 818 int size, void *rpl) 819 { 820 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 821 } 822 823 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 824 int size, void *rpl) 825 { 826 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 827 } 828 829 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 830 unsigned int data_reg, const u32 *vals, 831 unsigned int nregs, unsigned int start_idx); 832 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 833 unsigned int data_reg, u32 *vals, unsigned int nregs, 834 unsigned int start_idx); 835 836 struct fw_filter_wr; 837 838 void t4_intr_enable(struct adapter *adapter); 839 void t4_intr_disable(struct adapter *adapter); 840 int t4_slow_intr_handler(struct adapter *adapter); 841 842 int t4_wait_dev_ready(struct adapter *adap); 843 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 844 struct link_config *lc); 845 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 846 int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len, 847 __be32 *buf); 848 int t4_seeprom_wp(struct adapter *adapter, bool enable); 849 int get_vpd_params(struct adapter *adapter, struct vpd_params *p); 850 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 851 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 852 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 853 int t4_check_fw_version(struct adapter *adapter); 854 int t4_prep_adapter(struct adapter *adapter); 855 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 856 void t4_fatal_err(struct adapter *adapter); 857 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 858 int start, int n, const u16 *rspq, unsigned int nrspq); 859 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 860 unsigned int flags); 861 int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity); 862 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 863 u64 *parity); 864 865 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 866 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 867 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 868 unsigned int mask, unsigned int val); 869 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 870 struct tp_tcp_stats *v6); 871 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 872 const unsigned short *alpha, const unsigned short *beta); 873 874 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 875 876 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 877 const u8 *addr); 878 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 879 u64 mask0, u64 mask1, unsigned int crc, bool enable); 880 881 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 882 enum dev_master master, enum dev_state *state); 883 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 884 int t4_early_init(struct adapter *adap, unsigned int mbox); 885 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 886 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 887 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 888 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 889 const u8 *fw_data, unsigned int size, int force); 890 int t4_fw_config_file(struct adapter *adap, unsigned int mbox, 891 unsigned int mtype, unsigned int maddr, 892 u32 *finiver, u32 *finicsum, u32 *cfcsum); 893 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 894 unsigned int cache_line_size); 895 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 896 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 897 unsigned int vf, unsigned int nparams, const u32 *params, 898 u32 *val); 899 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 900 unsigned int vf, unsigned int nparams, const u32 *params, 901 const u32 *val); 902 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 903 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 904 unsigned int rxqi, unsigned int rxq, unsigned int tc, 905 unsigned int vi, unsigned int cmask, unsigned int pmask, 906 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 907 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 908 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 909 unsigned int *rss_size); 910 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 911 int mtu, int promisc, int all_multi, int bcast, int vlanex, 912 bool sleep_ok); 913 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 914 unsigned int viid, bool free, unsigned int naddr, 915 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 916 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 917 int idx, const u8 *addr, bool persist, bool add_smt); 918 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 919 bool ucast, u64 vec, bool sleep_ok); 920 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 921 bool rx_en, bool tx_en); 922 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 923 unsigned int nblinks); 924 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 925 unsigned int mmd, unsigned int reg, u16 *valp); 926 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 927 unsigned int mmd, unsigned int reg, u16 val); 928 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 929 unsigned int vf, unsigned int iqtype, unsigned int iqid, 930 unsigned int fl0id, unsigned int fl1id); 931 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 932 unsigned int vf, unsigned int eqid); 933 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 934 unsigned int vf, unsigned int eqid); 935 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 936 unsigned int vf, unsigned int eqid); 937 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 938 void t4_db_full(struct adapter *adapter); 939 void t4_db_dropped(struct adapter *adapter); 940 int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len); 941 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 942 u32 addr, u32 val); 943 #endif /* __CXGB4_H__ */ 944