1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <asm/io.h> 52 #include "t4_chip_type.h" 53 #include "cxgb4_uld.h" 54 55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 56 extern struct list_head adapter_list; 57 extern struct mutex uld_mutex; 58 59 enum { 60 MAX_NPORTS = 4, /* max # of ports */ 61 SERNUM_LEN = 24, /* Serial # length */ 62 EC_LEN = 16, /* E/C length */ 63 ID_LEN = 16, /* ID length */ 64 PN_LEN = 16, /* Part Number length */ 65 MACADDR_LEN = 12, /* MAC Address length */ 66 }; 67 68 enum { 69 T4_REGMAP_SIZE = (160 * 1024), 70 T5_REGMAP_SIZE = (332 * 1024), 71 }; 72 73 enum { 74 MEM_EDC0, 75 MEM_EDC1, 76 MEM_MC, 77 MEM_MC0 = MEM_MC, 78 MEM_MC1 79 }; 80 81 enum { 82 MEMWIN0_APERTURE = 2048, 83 MEMWIN0_BASE = 0x1b800, 84 MEMWIN1_APERTURE = 32768, 85 MEMWIN1_BASE = 0x28000, 86 MEMWIN1_BASE_T5 = 0x52000, 87 MEMWIN2_APERTURE = 65536, 88 MEMWIN2_BASE = 0x30000, 89 MEMWIN2_APERTURE_T5 = 131072, 90 MEMWIN2_BASE_T5 = 0x60000, 91 }; 92 93 enum dev_master { 94 MASTER_CANT, 95 MASTER_MAY, 96 MASTER_MUST 97 }; 98 99 enum dev_state { 100 DEV_STATE_UNINIT, 101 DEV_STATE_INIT, 102 DEV_STATE_ERR 103 }; 104 105 enum { 106 PAUSE_RX = 1 << 0, 107 PAUSE_TX = 1 << 1, 108 PAUSE_AUTONEG = 1 << 2 109 }; 110 111 struct port_stats { 112 u64 tx_octets; /* total # of octets in good frames */ 113 u64 tx_frames; /* all good frames */ 114 u64 tx_bcast_frames; /* all broadcast frames */ 115 u64 tx_mcast_frames; /* all multicast frames */ 116 u64 tx_ucast_frames; /* all unicast frames */ 117 u64 tx_error_frames; /* all error frames */ 118 119 u64 tx_frames_64; /* # of Tx frames in a particular range */ 120 u64 tx_frames_65_127; 121 u64 tx_frames_128_255; 122 u64 tx_frames_256_511; 123 u64 tx_frames_512_1023; 124 u64 tx_frames_1024_1518; 125 u64 tx_frames_1519_max; 126 127 u64 tx_drop; /* # of dropped Tx frames */ 128 u64 tx_pause; /* # of transmitted pause frames */ 129 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 130 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 131 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 132 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 133 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 134 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 135 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 136 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 137 138 u64 rx_octets; /* total # of octets in good frames */ 139 u64 rx_frames; /* all good frames */ 140 u64 rx_bcast_frames; /* all broadcast frames */ 141 u64 rx_mcast_frames; /* all multicast frames */ 142 u64 rx_ucast_frames; /* all unicast frames */ 143 u64 rx_too_long; /* # of frames exceeding MTU */ 144 u64 rx_jabber; /* # of jabber frames */ 145 u64 rx_fcs_err; /* # of received frames with bad FCS */ 146 u64 rx_len_err; /* # of received frames with length error */ 147 u64 rx_symbol_err; /* symbol errors */ 148 u64 rx_runt; /* # of short frames */ 149 150 u64 rx_frames_64; /* # of Rx frames in a particular range */ 151 u64 rx_frames_65_127; 152 u64 rx_frames_128_255; 153 u64 rx_frames_256_511; 154 u64 rx_frames_512_1023; 155 u64 rx_frames_1024_1518; 156 u64 rx_frames_1519_max; 157 158 u64 rx_pause; /* # of received pause frames */ 159 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 160 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 161 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 162 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 163 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 164 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 165 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 166 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 167 168 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 169 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 170 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 171 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 172 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 173 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 174 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 175 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 176 }; 177 178 struct lb_port_stats { 179 u64 octets; 180 u64 frames; 181 u64 bcast_frames; 182 u64 mcast_frames; 183 u64 ucast_frames; 184 u64 error_frames; 185 186 u64 frames_64; 187 u64 frames_65_127; 188 u64 frames_128_255; 189 u64 frames_256_511; 190 u64 frames_512_1023; 191 u64 frames_1024_1518; 192 u64 frames_1519_max; 193 194 u64 drop; 195 196 u64 ovflow0; 197 u64 ovflow1; 198 u64 ovflow2; 199 u64 ovflow3; 200 u64 trunc0; 201 u64 trunc1; 202 u64 trunc2; 203 u64 trunc3; 204 }; 205 206 struct tp_tcp_stats { 207 u32 tcp_out_rsts; 208 u64 tcp_in_segs; 209 u64 tcp_out_segs; 210 u64 tcp_retrans_segs; 211 }; 212 213 struct tp_usm_stats { 214 u32 frames; 215 u32 drops; 216 u64 octets; 217 }; 218 219 struct tp_fcoe_stats { 220 u32 frames_ddp; 221 u32 frames_drop; 222 u64 octets_ddp; 223 }; 224 225 struct tp_err_stats { 226 u32 mac_in_errs[4]; 227 u32 hdr_in_errs[4]; 228 u32 tcp_in_errs[4]; 229 u32 tnl_cong_drops[4]; 230 u32 ofld_chan_drops[4]; 231 u32 tnl_tx_drops[4]; 232 u32 ofld_vlan_drops[4]; 233 u32 tcp6_in_errs[4]; 234 u32 ofld_no_neigh; 235 u32 ofld_cong_defer; 236 }; 237 238 struct tp_cpl_stats { 239 u32 req[4]; 240 u32 rsp[4]; 241 }; 242 243 struct tp_rdma_stats { 244 u32 rqe_dfr_pkt; 245 u32 rqe_dfr_mod; 246 }; 247 248 struct sge_params { 249 u32 hps; /* host page size for our PF/VF */ 250 u32 eq_qpp; /* egress queues/page for our PF/VF */ 251 u32 iq_qpp; /* egress queues/page for our PF/VF */ 252 }; 253 254 struct tp_params { 255 unsigned int tre; /* log2 of core clocks per TP tick */ 256 unsigned int la_mask; /* what events are recorded by TP LA */ 257 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 258 /* channel map */ 259 260 uint32_t dack_re; /* DACK timer resolution */ 261 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 262 263 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 264 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 265 266 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 267 * subset of the set of fields which may be present in the Compressed 268 * Filter Tuple portion of filters and TCP TCB connections. The 269 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 270 * Since a variable number of fields may or may not be present, their 271 * shifted field positions within the Compressed Filter Tuple may 272 * vary, or not even be present if the field isn't selected in 273 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 274 * places we store their offsets here, or a -1 if the field isn't 275 * present. 276 */ 277 int vlan_shift; 278 int vnic_shift; 279 int port_shift; 280 int protocol_shift; 281 }; 282 283 struct vpd_params { 284 unsigned int cclk; 285 u8 ec[EC_LEN + 1]; 286 u8 sn[SERNUM_LEN + 1]; 287 u8 id[ID_LEN + 1]; 288 u8 pn[PN_LEN + 1]; 289 u8 na[MACADDR_LEN + 1]; 290 }; 291 292 struct pci_params { 293 unsigned char speed; 294 unsigned char width; 295 }; 296 297 struct devlog_params { 298 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 299 u32 start; /* start of log in firmware memory */ 300 u32 size; /* size of log */ 301 }; 302 303 /* Stores chip specific parameters */ 304 struct arch_specific_params { 305 u8 nchan; 306 u8 pm_stats_cnt; 307 u8 cng_ch_bits_log; /* congestion channel map bits width */ 308 u16 mps_rplc_size; 309 u16 vfcount; 310 u32 sge_fl_db; 311 u16 mps_tcam_size; 312 }; 313 314 struct adapter_params { 315 struct sge_params sge; 316 struct tp_params tp; 317 struct vpd_params vpd; 318 struct pci_params pci; 319 struct devlog_params devlog; 320 enum pcie_memwin drv_memwin; 321 322 unsigned int cim_la_size; 323 324 unsigned int sf_size; /* serial flash size in bytes */ 325 unsigned int sf_nsec; /* # of flash sectors */ 326 unsigned int sf_fw_start; /* start of FW image in flash */ 327 328 unsigned int fw_vers; 329 unsigned int bs_vers; /* bootstrap version */ 330 unsigned int tp_vers; 331 unsigned int er_vers; /* expansion ROM version */ 332 u8 api_vers[7]; 333 334 unsigned short mtus[NMTUS]; 335 unsigned short a_wnd[NCCTRL_WIN]; 336 unsigned short b_wnd[NCCTRL_WIN]; 337 338 unsigned char nports; /* # of ethernet ports */ 339 unsigned char portvec; 340 enum chip_type chip; /* chip code */ 341 struct arch_specific_params arch; /* chip specific params */ 342 unsigned char offload; 343 unsigned char crypto; /* HW capability for crypto */ 344 345 unsigned char bypass; 346 347 unsigned int ofldq_wr_cred; 348 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 349 350 unsigned int nsched_cls; /* number of traffic classes */ 351 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 352 unsigned int max_ird_adapter; /* Max read depth per adapter */ 353 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 354 }; 355 356 /* State needed to monitor the forward progress of SGE Ingress DMA activities 357 * and possible hangs. 358 */ 359 struct sge_idma_monitor_state { 360 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 361 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 362 unsigned int idma_state[2]; /* IDMA Hang detect state */ 363 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 364 unsigned int idma_warn[2]; /* time to warning in HZ */ 365 }; 366 367 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 368 * The access and execute times are signed in order to accommodate negative 369 * error returns. 370 */ 371 struct mbox_cmd { 372 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 373 u64 timestamp; /* OS-dependent timestamp */ 374 u32 seqno; /* sequence number */ 375 s16 access; /* time (ms) to access mailbox */ 376 s16 execute; /* time (ms) to execute */ 377 }; 378 379 struct mbox_cmd_log { 380 unsigned int size; /* number of entries in the log */ 381 unsigned int cursor; /* next position in the log to write */ 382 u32 seqno; /* next sequence number */ 383 /* variable length mailbox command log starts here */ 384 }; 385 386 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 387 * return a pointer to the specified entry. 388 */ 389 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 390 unsigned int entry_idx) 391 { 392 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 393 } 394 395 #include "t4fw_api.h" 396 397 #define FW_VERSION(chip) ( \ 398 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 399 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 400 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 401 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 402 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 403 404 struct fw_info { 405 u8 chip; 406 char *fs_name; 407 char *fw_mod_name; 408 struct fw_hdr fw_hdr; 409 }; 410 411 struct trace_params { 412 u32 data[TRACE_LEN / 4]; 413 u32 mask[TRACE_LEN / 4]; 414 unsigned short snap_len; 415 unsigned short min_len; 416 unsigned char skip_ofst; 417 unsigned char skip_len; 418 unsigned char invert; 419 unsigned char port; 420 }; 421 422 struct link_config { 423 unsigned short supported; /* link capabilities */ 424 unsigned short advertising; /* advertised capabilities */ 425 unsigned short lp_advertising; /* peer advertised capabilities */ 426 unsigned int requested_speed; /* speed user has requested */ 427 unsigned int speed; /* actual link speed */ 428 unsigned char requested_fc; /* flow control user has requested */ 429 unsigned char fc; /* actual link flow control */ 430 unsigned char autoneg; /* autonegotiating? */ 431 unsigned char link_ok; /* link up? */ 432 unsigned char link_down_rc; /* link down reason */ 433 }; 434 435 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 436 437 enum { 438 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 439 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 440 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 441 }; 442 443 enum { 444 MAX_TXQ_ENTRIES = 16384, 445 MAX_CTRL_TXQ_ENTRIES = 1024, 446 MAX_RSPQ_ENTRIES = 16384, 447 MAX_RX_BUFFERS = 16384, 448 MIN_TXQ_ENTRIES = 32, 449 MIN_CTRL_TXQ_ENTRIES = 32, 450 MIN_RSPQ_ENTRIES = 128, 451 MIN_FL_ENTRIES = 16 452 }; 453 454 enum { 455 INGQ_EXTRAS = 2, /* firmware event queue and */ 456 /* forwarded interrupts */ 457 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 458 }; 459 460 struct adapter; 461 struct sge_rspq; 462 463 #include "cxgb4_dcb.h" 464 465 #ifdef CONFIG_CHELSIO_T4_FCOE 466 #include "cxgb4_fcoe.h" 467 #endif /* CONFIG_CHELSIO_T4_FCOE */ 468 469 struct port_info { 470 struct adapter *adapter; 471 u16 viid; 472 s16 xact_addr_filt; /* index of exact MAC address filter */ 473 u16 rss_size; /* size of VI's RSS table slice */ 474 s8 mdio_addr; 475 enum fw_port_type port_type; 476 u8 mod_type; 477 u8 port_id; 478 u8 tx_chan; 479 u8 lport; /* associated offload logical port */ 480 u8 nqsets; /* # of qsets */ 481 u8 first_qset; /* index of first qset */ 482 u8 rss_mode; 483 struct link_config link_cfg; 484 u16 *rss; 485 struct port_stats stats_base; 486 #ifdef CONFIG_CHELSIO_T4_DCB 487 struct port_dcb_info dcb; /* Data Center Bridging support */ 488 #endif 489 #ifdef CONFIG_CHELSIO_T4_FCOE 490 struct cxgb_fcoe fcoe; 491 #endif /* CONFIG_CHELSIO_T4_FCOE */ 492 bool rxtstamp; /* Enable TS */ 493 struct hwtstamp_config tstamp_config; 494 struct sched_table *sched_tbl; 495 }; 496 497 struct dentry; 498 struct work_struct; 499 500 enum { /* adapter flags */ 501 FULL_INIT_DONE = (1 << 0), 502 DEV_ENABLED = (1 << 1), 503 USING_MSI = (1 << 2), 504 USING_MSIX = (1 << 3), 505 FW_OK = (1 << 4), 506 RSS_TNLALLLOOKUP = (1 << 5), 507 USING_SOFT_PARAMS = (1 << 6), 508 MASTER_PF = (1 << 7), 509 FW_OFLD_CONN = (1 << 9), 510 }; 511 512 enum { 513 ULP_CRYPTO_LOOKASIDE = 1 << 0, 514 }; 515 516 struct rx_sw_desc; 517 518 struct sge_fl { /* SGE free-buffer queue state */ 519 unsigned int avail; /* # of available Rx buffers */ 520 unsigned int pend_cred; /* new buffers since last FL DB ring */ 521 unsigned int cidx; /* consumer index */ 522 unsigned int pidx; /* producer index */ 523 unsigned long alloc_failed; /* # of times buffer allocation failed */ 524 unsigned long large_alloc_failed; 525 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 526 unsigned long low; /* # of times momentarily starving */ 527 unsigned long starving; 528 /* RO fields */ 529 unsigned int cntxt_id; /* SGE context id for the free list */ 530 unsigned int size; /* capacity of free list */ 531 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 532 __be64 *desc; /* address of HW Rx descriptor ring */ 533 dma_addr_t addr; /* bus address of HW ring start */ 534 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 535 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 536 }; 537 538 /* A packet gather list */ 539 struct pkt_gl { 540 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 541 struct page_frag frags[MAX_SKB_FRAGS]; 542 void *va; /* virtual address of first byte */ 543 unsigned int nfrags; /* # of fragments */ 544 unsigned int tot_len; /* total length of fragments */ 545 }; 546 547 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 548 const struct pkt_gl *gl); 549 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 550 /* LRO related declarations for ULD */ 551 struct t4_lro_mgr { 552 #define MAX_LRO_SESSIONS 64 553 u8 lro_session_cnt; /* # of sessions to aggregate */ 554 unsigned long lro_pkts; /* # of LRO super packets */ 555 unsigned long lro_merged; /* # of wire packets merged by LRO */ 556 struct sk_buff_head lroq; /* list of aggregated sessions */ 557 }; 558 559 struct sge_rspq { /* state for an SGE response queue */ 560 struct napi_struct napi; 561 const __be64 *cur_desc; /* current descriptor in queue */ 562 unsigned int cidx; /* consumer index */ 563 u8 gen; /* current generation bit */ 564 u8 intr_params; /* interrupt holdoff parameters */ 565 u8 next_intr_params; /* holdoff params for next interrupt */ 566 u8 adaptive_rx; 567 u8 pktcnt_idx; /* interrupt packet threshold */ 568 u8 uld; /* ULD handling this queue */ 569 u8 idx; /* queue index within its group */ 570 int offset; /* offset into current Rx buffer */ 571 u16 cntxt_id; /* SGE context id for the response q */ 572 u16 abs_id; /* absolute SGE id for the response q */ 573 __be64 *desc; /* address of HW response ring */ 574 dma_addr_t phys_addr; /* physical address of the ring */ 575 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 576 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 577 unsigned int iqe_len; /* entry size */ 578 unsigned int size; /* capacity of response queue */ 579 struct adapter *adap; 580 struct net_device *netdev; /* associated net device */ 581 rspq_handler_t handler; 582 rspq_flush_handler_t flush_handler; 583 struct t4_lro_mgr lro_mgr; 584 #ifdef CONFIG_NET_RX_BUSY_POLL 585 #define CXGB_POLL_STATE_IDLE 0 586 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 587 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 588 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 589 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 590 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 591 CXGB_POLL_STATE_POLL_YIELD) 592 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 593 CXGB_POLL_STATE_POLL) 594 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 595 CXGB_POLL_STATE_POLL_YIELD) 596 unsigned int bpoll_state; 597 spinlock_t bpoll_lock; /* lock for busy poll */ 598 #endif /* CONFIG_NET_RX_BUSY_POLL */ 599 600 }; 601 602 struct sge_eth_stats { /* Ethernet queue statistics */ 603 unsigned long pkts; /* # of ethernet packets */ 604 unsigned long lro_pkts; /* # of LRO super packets */ 605 unsigned long lro_merged; /* # of wire packets merged by LRO */ 606 unsigned long rx_cso; /* # of Rx checksum offloads */ 607 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 608 unsigned long rx_drops; /* # of packets dropped due to no mem */ 609 }; 610 611 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 612 struct sge_rspq rspq; 613 struct sge_fl fl; 614 struct sge_eth_stats stats; 615 } ____cacheline_aligned_in_smp; 616 617 struct sge_ofld_stats { /* offload queue statistics */ 618 unsigned long pkts; /* # of packets */ 619 unsigned long imm; /* # of immediate-data packets */ 620 unsigned long an; /* # of asynchronous notifications */ 621 unsigned long nomem; /* # of responses deferred due to no mem */ 622 }; 623 624 struct sge_ofld_rxq { /* SW offload Rx queue */ 625 struct sge_rspq rspq; 626 struct sge_fl fl; 627 struct sge_ofld_stats stats; 628 } ____cacheline_aligned_in_smp; 629 630 struct tx_desc { 631 __be64 flit[8]; 632 }; 633 634 struct tx_sw_desc; 635 636 struct sge_txq { 637 unsigned int in_use; /* # of in-use Tx descriptors */ 638 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 639 unsigned int size; /* # of descriptors */ 640 unsigned int cidx; /* SW consumer index */ 641 unsigned int pidx; /* producer index */ 642 unsigned long stops; /* # of times q has been stopped */ 643 unsigned long restarts; /* # of queue restarts */ 644 unsigned int cntxt_id; /* SGE context id for the Tx q */ 645 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 646 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 647 struct sge_qstat *stat; /* queue status entry */ 648 dma_addr_t phys_addr; /* physical address of the ring */ 649 spinlock_t db_lock; 650 int db_disabled; 651 unsigned short db_pidx; 652 unsigned short db_pidx_inc; 653 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 654 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 655 }; 656 657 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 658 struct sge_txq q; 659 struct netdev_queue *txq; /* associated netdev TX queue */ 660 #ifdef CONFIG_CHELSIO_T4_DCB 661 u8 dcb_prio; /* DCB Priority bound to queue */ 662 #endif 663 unsigned long tso; /* # of TSO requests */ 664 unsigned long tx_cso; /* # of Tx checksum offloads */ 665 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 666 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 667 } ____cacheline_aligned_in_smp; 668 669 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 670 struct sge_txq q; 671 struct adapter *adap; 672 struct sk_buff_head sendq; /* list of backpressured packets */ 673 struct tasklet_struct qresume_tsk; /* restarts the queue */ 674 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 675 u8 full; /* the Tx ring is full */ 676 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 677 } ____cacheline_aligned_in_smp; 678 679 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 680 struct sge_txq q; 681 struct adapter *adap; 682 struct sk_buff_head sendq; /* list of backpressured packets */ 683 struct tasklet_struct qresume_tsk; /* restarts the queue */ 684 u8 full; /* the Tx ring is full */ 685 } ____cacheline_aligned_in_smp; 686 687 struct sge_uld_rxq_info { 688 char name[IFNAMSIZ]; /* name of ULD driver */ 689 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 690 u16 *msix_tbl; /* msix_tbl for uld */ 691 u16 *rspq_id; /* response queue id's of rxq */ 692 u16 nrxq; /* # of ingress uld queues */ 693 u16 nciq; /* # of completion queues */ 694 u8 uld; /* uld type */ 695 }; 696 697 struct sge_uld_txq_info { 698 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 699 atomic_t users; /* num users */ 700 u16 ntxq; /* # of egress uld queues */ 701 }; 702 703 struct sge { 704 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 705 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 706 707 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 708 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 709 struct sge_uld_rxq_info **uld_rxq_info; 710 struct sge_uld_txq_info **uld_txq_info; 711 712 struct sge_rspq intrq ____cacheline_aligned_in_smp; 713 spinlock_t intrq_lock; 714 715 u16 max_ethqsets; /* # of available Ethernet queue sets */ 716 u16 ethqsets; /* # of active Ethernet queue sets */ 717 u16 ethtxq_rover; /* Tx queue to clean up next */ 718 u16 ofldqsets; /* # of active ofld queue sets */ 719 u16 nqs_per_uld; /* # of Rx queues per ULD */ 720 u16 timer_val[SGE_NTIMERS]; 721 u8 counter_val[SGE_NCOUNTERS]; 722 u32 fl_pg_order; /* large page allocation size */ 723 u32 stat_len; /* length of status page at ring end */ 724 u32 pktshift; /* padding between CPL & packet data */ 725 u32 fl_align; /* response queue message alignment */ 726 u32 fl_starve_thres; /* Free List starvation threshold */ 727 728 struct sge_idma_monitor_state idma_monitor; 729 unsigned int egr_start; 730 unsigned int egr_sz; 731 unsigned int ingr_start; 732 unsigned int ingr_sz; 733 void **egr_map; /* qid->queue egress queue map */ 734 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 735 unsigned long *starving_fl; 736 unsigned long *txq_maperr; 737 unsigned long *blocked_fl; 738 struct timer_list rx_timer; /* refills starving FLs */ 739 struct timer_list tx_timer; /* checks Tx queues */ 740 }; 741 742 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 743 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 744 745 struct l2t_data; 746 747 #ifdef CONFIG_PCI_IOV 748 749 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 750 * Configuration initialization for T5 only has SR-IOV functionality enabled 751 * on PF0-3 in order to simplify everything. 752 */ 753 #define NUM_OF_PF_WITH_SRIOV 4 754 755 #endif 756 757 struct doorbell_stats { 758 u32 db_drop; 759 u32 db_empty; 760 u32 db_full; 761 }; 762 763 struct hash_mac_addr { 764 struct list_head list; 765 u8 addr[ETH_ALEN]; 766 }; 767 768 struct uld_msix_bmap { 769 unsigned long *msix_bmap; 770 unsigned int mapsize; 771 spinlock_t lock; /* lock for acquiring bitmap */ 772 }; 773 774 struct uld_msix_info { 775 unsigned short vec; 776 char desc[IFNAMSIZ + 10]; 777 unsigned int idx; 778 }; 779 780 struct vf_info { 781 unsigned char vf_mac_addr[ETH_ALEN]; 782 bool pf_set_mac; 783 }; 784 785 struct adapter { 786 void __iomem *regs; 787 void __iomem *bar2; 788 u32 t4_bar0; 789 struct pci_dev *pdev; 790 struct device *pdev_dev; 791 const char *name; 792 unsigned int mbox; 793 unsigned int pf; 794 unsigned int flags; 795 unsigned int adap_idx; 796 enum chip_type chip; 797 798 int msg_enable; 799 800 struct adapter_params params; 801 struct cxgb4_virt_res vres; 802 unsigned int swintr; 803 804 struct { 805 unsigned short vec; 806 char desc[IFNAMSIZ + 10]; 807 } msix_info[MAX_INGQ + 1]; 808 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 809 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 810 int msi_idx; 811 812 struct doorbell_stats db_stats; 813 struct sge sge; 814 815 struct net_device *port[MAX_NPORTS]; 816 u8 chan_map[NCHAN]; /* channel -> port map */ 817 818 struct vf_info *vfinfo; 819 u8 num_vfs; 820 821 u32 filter_mode; 822 unsigned int l2t_start; 823 unsigned int l2t_end; 824 struct l2t_data *l2t; 825 unsigned int clipt_start; 826 unsigned int clipt_end; 827 struct clip_tbl *clipt; 828 struct cxgb4_uld_info *uld; 829 void *uld_handle[CXGB4_ULD_MAX]; 830 unsigned int num_uld; 831 unsigned int num_ofld_uld; 832 struct list_head list_node; 833 struct list_head rcu_node; 834 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 835 836 void *iscsi_ppm; 837 838 struct tid_info tids; 839 void **tid_release_head; 840 spinlock_t tid_release_lock; 841 struct workqueue_struct *workq; 842 struct work_struct tid_release_task; 843 struct work_struct db_full_task; 844 struct work_struct db_drop_task; 845 bool tid_release_task_busy; 846 847 /* support for mailbox command/reply logging */ 848 #define T4_OS_LOG_MBOX_CMDS 256 849 struct mbox_cmd_log *mbox_log; 850 851 struct mutex uld_mutex; 852 853 struct dentry *debugfs_root; 854 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 855 bool trace_rss; /* 1 implies that different RSS flit per filter is 856 * used per filter else if 0 default RSS flit is 857 * used for all 4 filters. 858 */ 859 860 spinlock_t stats_lock; 861 spinlock_t win0_lock ____cacheline_aligned_in_smp; 862 863 /* TC u32 offload */ 864 struct cxgb4_tc_u32_table *tc_u32; 865 }; 866 867 /* Support for "sched-class" command to allow a TX Scheduling Class to be 868 * programmed with various parameters. 869 */ 870 struct ch_sched_params { 871 s8 type; /* packet or flow */ 872 union { 873 struct { 874 s8 level; /* scheduler hierarchy level */ 875 s8 mode; /* per-class or per-flow */ 876 s8 rateunit; /* bit or packet rate */ 877 s8 ratemode; /* %port relative or kbps absolute */ 878 s8 channel; /* scheduler channel [0..N] */ 879 s8 class; /* scheduler class [0..N] */ 880 s32 minrate; /* minimum rate */ 881 s32 maxrate; /* maximum rate */ 882 s16 weight; /* percent weight */ 883 s16 pktsize; /* average packet size */ 884 } params; 885 } u; 886 }; 887 888 enum { 889 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 890 }; 891 892 enum { 893 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 894 }; 895 896 enum { 897 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 898 }; 899 900 enum { 901 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 902 }; 903 904 enum { 905 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 906 }; 907 908 /* Support for "sched_queue" command to allow one or more NIC TX Queues 909 * to be bound to a TX Scheduling Class. 910 */ 911 struct ch_sched_queue { 912 s8 queue; /* queue index */ 913 s8 class; /* class index */ 914 }; 915 916 /* Defined bit width of user definable filter tuples 917 */ 918 #define ETHTYPE_BITWIDTH 16 919 #define FRAG_BITWIDTH 1 920 #define MACIDX_BITWIDTH 9 921 #define FCOE_BITWIDTH 1 922 #define IPORT_BITWIDTH 3 923 #define MATCHTYPE_BITWIDTH 3 924 #define PROTO_BITWIDTH 8 925 #define TOS_BITWIDTH 8 926 #define PF_BITWIDTH 8 927 #define VF_BITWIDTH 8 928 #define IVLAN_BITWIDTH 16 929 #define OVLAN_BITWIDTH 16 930 931 /* Filter matching rules. These consist of a set of ingress packet field 932 * (value, mask) tuples. The associated ingress packet field matches the 933 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 934 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 935 * matches an ingress packet when all of the individual individual field 936 * matching rules are true. 937 * 938 * Partial field masks are always valid, however, while it may be easy to 939 * understand their meanings for some fields (e.g. IP address to match a 940 * subnet), for others making sensible partial masks is less intuitive (e.g. 941 * MPS match type) ... 942 * 943 * Most of the following data structures are modeled on T4 capabilities. 944 * Drivers for earlier chips use the subsets which make sense for those chips. 945 * We really need to come up with a hardware-independent mechanism to 946 * represent hardware filter capabilities ... 947 */ 948 struct ch_filter_tuple { 949 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 950 * register selects which of these fields will participate in the 951 * filter match rules -- up to a maximum of 36 bits. Because 952 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 953 * set of fields. 954 */ 955 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 956 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 957 uint32_t ivlan_vld:1; /* inner VLAN valid */ 958 uint32_t ovlan_vld:1; /* outer VLAN valid */ 959 uint32_t pfvf_vld:1; /* PF/VF valid */ 960 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 961 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 962 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 963 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 964 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 965 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 966 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 967 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 968 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 969 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 970 971 /* Uncompressed header matching field rules. These are always 972 * available for field rules. 973 */ 974 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 975 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 976 uint16_t lport; /* local port */ 977 uint16_t fport; /* foreign port */ 978 }; 979 980 /* A filter ioctl command. 981 */ 982 struct ch_filter_specification { 983 /* Administrative fields for filter. 984 */ 985 uint32_t hitcnts:1; /* count filter hits in TCB */ 986 uint32_t prio:1; /* filter has priority over active/server */ 987 988 /* Fundamental filter typing. This is the one element of filter 989 * matching that doesn't exist as a (value, mask) tuple. 990 */ 991 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 992 993 /* Packet dispatch information. Ingress packets which match the 994 * filter rules will be dropped, passed to the host or switched back 995 * out as egress packets. 996 */ 997 uint32_t action:2; /* drop, pass, switch */ 998 999 uint32_t rpttid:1; /* report TID in RSS hash field */ 1000 1001 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1002 uint32_t iq:10; /* ingress queue */ 1003 1004 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1005 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1006 /* 1 => TCB contains IQ ID */ 1007 1008 /* Switch proxy/rewrite fields. An ingress packet which matches a 1009 * filter with "switch" set will be looped back out as an egress 1010 * packet -- potentially with some Ethernet header rewriting. 1011 */ 1012 uint32_t eport:2; /* egress port to switch packet out */ 1013 uint32_t newdmac:1; /* rewrite destination MAC address */ 1014 uint32_t newsmac:1; /* rewrite source MAC address */ 1015 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1016 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1017 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1018 uint16_t vlan; /* VLAN Tag to insert */ 1019 1020 /* Filter rule value/mask pairs. 1021 */ 1022 struct ch_filter_tuple val; 1023 struct ch_filter_tuple mask; 1024 }; 1025 1026 enum { 1027 FILTER_PASS = 0, /* default */ 1028 FILTER_DROP, 1029 FILTER_SWITCH 1030 }; 1031 1032 enum { 1033 VLAN_NOCHANGE = 0, /* default */ 1034 VLAN_REMOVE, 1035 VLAN_INSERT, 1036 VLAN_REWRITE 1037 }; 1038 1039 /* Host shadow copy of ingress filter entry. This is in host native format 1040 * and doesn't match the ordering or bit order, etc. of the hardware of the 1041 * firmware command. The use of bit-field structure elements is purely to 1042 * remind ourselves of the field size limitations and save memory in the case 1043 * where the filter table is large. 1044 */ 1045 struct filter_entry { 1046 /* Administrative fields for filter. */ 1047 u32 valid:1; /* filter allocated and valid */ 1048 u32 locked:1; /* filter is administratively locked */ 1049 1050 u32 pending:1; /* filter action is pending firmware reply */ 1051 u32 smtidx:8; /* Source MAC Table index for smac */ 1052 struct filter_ctx *ctx; /* Caller's completion hook */ 1053 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1054 struct net_device *dev; /* Associated net device */ 1055 u32 tid; /* This will store the actual tid */ 1056 1057 /* The filter itself. Most of this is a straight copy of information 1058 * provided by the extended ioctl(). Some fields are translated to 1059 * internal forms -- for instance the Ingress Queue ID passed in from 1060 * the ioctl() is translated into the Absolute Ingress Queue ID. 1061 */ 1062 struct ch_filter_specification fs; 1063 }; 1064 1065 static inline int is_offload(const struct adapter *adap) 1066 { 1067 return adap->params.offload; 1068 } 1069 1070 static inline int is_pci_uld(const struct adapter *adap) 1071 { 1072 return adap->params.crypto; 1073 } 1074 1075 static inline int is_uld(const struct adapter *adap) 1076 { 1077 return (adap->params.offload || adap->params.crypto); 1078 } 1079 1080 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1081 { 1082 return readl(adap->regs + reg_addr); 1083 } 1084 1085 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1086 { 1087 writel(val, adap->regs + reg_addr); 1088 } 1089 1090 #ifndef readq 1091 static inline u64 readq(const volatile void __iomem *addr) 1092 { 1093 return readl(addr) + ((u64)readl(addr + 4) << 32); 1094 } 1095 1096 static inline void writeq(u64 val, volatile void __iomem *addr) 1097 { 1098 writel(val, addr); 1099 writel(val >> 32, addr + 4); 1100 } 1101 #endif 1102 1103 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1104 { 1105 return readq(adap->regs + reg_addr); 1106 } 1107 1108 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1109 { 1110 writeq(val, adap->regs + reg_addr); 1111 } 1112 1113 /** 1114 * t4_set_hw_addr - store a port's MAC address in SW 1115 * @adapter: the adapter 1116 * @port_idx: the port index 1117 * @hw_addr: the Ethernet address 1118 * 1119 * Store the Ethernet address of the given port in SW. Called by the common 1120 * code when it retrieves a port's Ethernet address from EEPROM. 1121 */ 1122 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1123 u8 hw_addr[]) 1124 { 1125 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1126 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1127 } 1128 1129 /** 1130 * netdev2pinfo - return the port_info structure associated with a net_device 1131 * @dev: the netdev 1132 * 1133 * Return the struct port_info associated with a net_device 1134 */ 1135 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1136 { 1137 return netdev_priv(dev); 1138 } 1139 1140 /** 1141 * adap2pinfo - return the port_info of a port 1142 * @adap: the adapter 1143 * @idx: the port index 1144 * 1145 * Return the port_info structure for the port of the given index. 1146 */ 1147 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1148 { 1149 return netdev_priv(adap->port[idx]); 1150 } 1151 1152 /** 1153 * netdev2adap - return the adapter structure associated with a net_device 1154 * @dev: the netdev 1155 * 1156 * Return the struct adapter associated with a net_device 1157 */ 1158 static inline struct adapter *netdev2adap(const struct net_device *dev) 1159 { 1160 return netdev2pinfo(dev)->adapter; 1161 } 1162 1163 #ifdef CONFIG_NET_RX_BUSY_POLL 1164 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 1165 { 1166 spin_lock_init(&q->bpoll_lock); 1167 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1168 } 1169 1170 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 1171 { 1172 bool rc = true; 1173 1174 spin_lock(&q->bpoll_lock); 1175 if (q->bpoll_state & CXGB_POLL_LOCKED) { 1176 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 1177 rc = false; 1178 } else { 1179 q->bpoll_state = CXGB_POLL_STATE_NAPI; 1180 } 1181 spin_unlock(&q->bpoll_lock); 1182 return rc; 1183 } 1184 1185 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 1186 { 1187 bool rc = false; 1188 1189 spin_lock(&q->bpoll_lock); 1190 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 1191 rc = true; 1192 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1193 spin_unlock(&q->bpoll_lock); 1194 return rc; 1195 } 1196 1197 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 1198 { 1199 bool rc = true; 1200 1201 spin_lock_bh(&q->bpoll_lock); 1202 if (q->bpoll_state & CXGB_POLL_LOCKED) { 1203 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 1204 rc = false; 1205 } else { 1206 q->bpoll_state |= CXGB_POLL_STATE_POLL; 1207 } 1208 spin_unlock_bh(&q->bpoll_lock); 1209 return rc; 1210 } 1211 1212 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 1213 { 1214 bool rc = false; 1215 1216 spin_lock_bh(&q->bpoll_lock); 1217 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 1218 rc = true; 1219 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1220 spin_unlock_bh(&q->bpoll_lock); 1221 return rc; 1222 } 1223 1224 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 1225 { 1226 return q->bpoll_state & CXGB_POLL_USER_PEND; 1227 } 1228 #else 1229 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 1230 { 1231 } 1232 1233 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 1234 { 1235 return true; 1236 } 1237 1238 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 1239 { 1240 return false; 1241 } 1242 1243 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 1244 { 1245 return false; 1246 } 1247 1248 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 1249 { 1250 return false; 1251 } 1252 1253 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 1254 { 1255 return false; 1256 } 1257 #endif /* CONFIG_NET_RX_BUSY_POLL */ 1258 1259 /* Return a version number to identify the type of adapter. The scheme is: 1260 * - bits 0..9: chip version 1261 * - bits 10..15: chip revision 1262 * - bits 16..23: register dump version 1263 */ 1264 static inline unsigned int mk_adap_vers(struct adapter *ap) 1265 { 1266 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1267 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1268 } 1269 1270 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1271 static inline unsigned int qtimer_val(const struct adapter *adap, 1272 const struct sge_rspq *q) 1273 { 1274 unsigned int idx = q->intr_params >> 1; 1275 1276 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1277 } 1278 1279 /* driver version & name used for ethtool_drvinfo */ 1280 extern char cxgb4_driver_name[]; 1281 extern const char cxgb4_driver_version[]; 1282 1283 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1284 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1285 1286 void *t4_alloc_mem(size_t size); 1287 1288 void t4_free_sge_resources(struct adapter *adap); 1289 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1290 irq_handler_t t4_intr_handler(struct adapter *adap); 1291 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1292 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1293 const struct pkt_gl *gl); 1294 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1295 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1296 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1297 struct net_device *dev, int intr_idx, 1298 struct sge_fl *fl, rspq_handler_t hnd, 1299 rspq_flush_handler_t flush_handler, int cong); 1300 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1301 struct net_device *dev, struct netdev_queue *netdevq, 1302 unsigned int iqid); 1303 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1304 struct net_device *dev, unsigned int iqid, 1305 unsigned int cmplqid); 1306 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1307 unsigned int cmplqid); 1308 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1309 struct net_device *dev, unsigned int iqid, 1310 unsigned int uld_type); 1311 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1312 int t4_sge_init(struct adapter *adap); 1313 void t4_sge_start(struct adapter *adap); 1314 void t4_sge_stop(struct adapter *adap); 1315 int cxgb_busy_poll(struct napi_struct *napi); 1316 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1317 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1318 extern int dbfifo_int_thresh; 1319 1320 #define for_each_port(adapter, iter) \ 1321 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1322 1323 static inline int is_bypass(struct adapter *adap) 1324 { 1325 return adap->params.bypass; 1326 } 1327 1328 static inline int is_bypass_device(int device) 1329 { 1330 /* this should be set based upon device capabilities */ 1331 switch (device) { 1332 case 0x440b: 1333 case 0x440c: 1334 return 1; 1335 default: 1336 return 0; 1337 } 1338 } 1339 1340 static inline int is_10gbt_device(int device) 1341 { 1342 /* this should be set based upon device capabilities */ 1343 switch (device) { 1344 case 0x4409: 1345 case 0x4486: 1346 return 1; 1347 1348 default: 1349 return 0; 1350 } 1351 } 1352 1353 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1354 { 1355 return adap->params.vpd.cclk / 1000; 1356 } 1357 1358 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1359 unsigned int us) 1360 { 1361 return (us * adap->params.vpd.cclk) / 1000; 1362 } 1363 1364 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1365 unsigned int ticks) 1366 { 1367 /* add Core Clock / 2 to round ticks to nearest uS */ 1368 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1369 adapter->params.vpd.cclk); 1370 } 1371 1372 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1373 u32 val); 1374 1375 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1376 int size, void *rpl, bool sleep_ok, int timeout); 1377 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1378 void *rpl, bool sleep_ok); 1379 1380 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1381 const void *cmd, int size, void *rpl, 1382 int timeout) 1383 { 1384 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1385 timeout); 1386 } 1387 1388 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1389 int size, void *rpl) 1390 { 1391 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1392 } 1393 1394 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1395 int size, void *rpl) 1396 { 1397 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1398 } 1399 1400 /** 1401 * hash_mac_addr - return the hash value of a MAC address 1402 * @addr: the 48-bit Ethernet MAC address 1403 * 1404 * Hashes a MAC address according to the hash function used by HW inexact 1405 * (hash) address matching. 1406 */ 1407 static inline int hash_mac_addr(const u8 *addr) 1408 { 1409 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1410 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1411 1412 a ^= b; 1413 a ^= (a >> 12); 1414 a ^= (a >> 6); 1415 return a & 0x3f; 1416 } 1417 1418 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1419 unsigned int cnt); 1420 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1421 unsigned int us, unsigned int cnt, 1422 unsigned int size, unsigned int iqe_size) 1423 { 1424 q->adap = adap; 1425 cxgb4_set_rspq_intr_params(q, us, cnt); 1426 q->iqe_len = iqe_size; 1427 q->size = size; 1428 } 1429 1430 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1431 unsigned int data_reg, const u32 *vals, 1432 unsigned int nregs, unsigned int start_idx); 1433 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1434 unsigned int data_reg, u32 *vals, unsigned int nregs, 1435 unsigned int start_idx); 1436 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1437 1438 struct fw_filter_wr; 1439 1440 void t4_intr_enable(struct adapter *adapter); 1441 void t4_intr_disable(struct adapter *adapter); 1442 int t4_slow_intr_handler(struct adapter *adapter); 1443 1444 int t4_wait_dev_ready(void __iomem *regs); 1445 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1446 struct link_config *lc); 1447 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1448 1449 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1450 u32 t4_get_util_window(struct adapter *adap); 1451 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1452 1453 #define T4_MEMORY_WRITE 0 1454 #define T4_MEMORY_READ 1 1455 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1456 void *buf, int dir); 1457 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1458 u32 len, __be32 *buf) 1459 { 1460 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1461 } 1462 1463 unsigned int t4_get_regs_len(struct adapter *adapter); 1464 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1465 1466 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1467 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1468 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1469 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1470 unsigned int nwords, u32 *data, int byte_oriented); 1471 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1472 int t4_load_phy_fw(struct adapter *adap, 1473 int win, spinlock_t *lock, 1474 int (*phy_fw_version)(const u8 *, size_t), 1475 const u8 *phy_fw_data, size_t phy_fw_size); 1476 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1477 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1478 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1479 const u8 *fw_data, unsigned int size, int force); 1480 int t4_fl_pkt_align(struct adapter *adap); 1481 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1482 int t4_check_fw_version(struct adapter *adap); 1483 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1484 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1485 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1486 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1487 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1488 const u8 *fw_data, unsigned int fw_size, 1489 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1490 int t4_prep_adapter(struct adapter *adapter); 1491 1492 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1493 int t4_bar2_sge_qregs(struct adapter *adapter, 1494 unsigned int qid, 1495 enum t4_bar2_qtype qtype, 1496 int user, 1497 u64 *pbar2_qoffset, 1498 unsigned int *pbar2_qid); 1499 1500 unsigned int qtimer_val(const struct adapter *adap, 1501 const struct sge_rspq *q); 1502 1503 int t4_init_devlog_params(struct adapter *adapter); 1504 int t4_init_sge_params(struct adapter *adapter); 1505 int t4_init_tp_params(struct adapter *adap); 1506 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1507 int t4_init_rss_mode(struct adapter *adap, int mbox); 1508 int t4_init_portinfo(struct port_info *pi, int mbox, 1509 int port, int pf, int vf, u8 mac[]); 1510 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1511 void t4_fatal_err(struct adapter *adapter); 1512 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1513 int start, int n, const u16 *rspq, unsigned int nrspq); 1514 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1515 unsigned int flags); 1516 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1517 unsigned int flags, unsigned int defq); 1518 int t4_read_rss(struct adapter *adapter, u16 *entries); 1519 void t4_read_rss_key(struct adapter *adapter, u32 *key); 1520 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1521 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1522 u32 *valp); 1523 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1524 u32 *vfl, u32 *vfh); 1525 u32 t4_read_rss_pf_map(struct adapter *adapter); 1526 u32 t4_read_rss_pf_mask(struct adapter *adapter); 1527 1528 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1529 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1530 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1531 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1532 size_t n); 1533 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1534 size_t n); 1535 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1536 unsigned int *valp); 1537 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1538 const unsigned int *valp); 1539 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1540 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1541 unsigned int *pif_req_wrptr, 1542 unsigned int *pif_rsp_wrptr); 1543 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1544 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1545 const char *t4_get_port_type_description(enum fw_port_type port_type); 1546 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1547 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1548 struct port_stats *stats, 1549 struct port_stats *offset); 1550 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1551 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1552 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1553 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1554 unsigned int mask, unsigned int val); 1555 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1556 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1557 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1558 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1559 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1560 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1561 struct tp_tcp_stats *v6); 1562 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1563 struct tp_fcoe_stats *st); 1564 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1565 const unsigned short *alpha, const unsigned short *beta); 1566 1567 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1568 1569 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1570 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1571 1572 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1573 const u8 *addr); 1574 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1575 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1576 1577 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1578 enum dev_master master, enum dev_state *state); 1579 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1580 int t4_early_init(struct adapter *adap, unsigned int mbox); 1581 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1582 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1583 unsigned int cache_line_size); 1584 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1585 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1586 unsigned int vf, unsigned int nparams, const u32 *params, 1587 u32 *val); 1588 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1589 unsigned int vf, unsigned int nparams, const u32 *params, 1590 u32 *val, int rw); 1591 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1592 unsigned int pf, unsigned int vf, 1593 unsigned int nparams, const u32 *params, 1594 const u32 *val, int timeout); 1595 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1596 unsigned int vf, unsigned int nparams, const u32 *params, 1597 const u32 *val); 1598 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1599 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1600 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1601 unsigned int vi, unsigned int cmask, unsigned int pmask, 1602 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1603 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1604 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1605 unsigned int *rss_size); 1606 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1607 unsigned int pf, unsigned int vf, 1608 unsigned int viid); 1609 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1610 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1611 bool sleep_ok); 1612 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1613 unsigned int viid, bool free, unsigned int naddr, 1614 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1615 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1616 unsigned int viid, unsigned int naddr, 1617 const u8 **addr, bool sleep_ok); 1618 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1619 int idx, const u8 *addr, bool persist, bool add_smt); 1620 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1621 bool ucast, u64 vec, bool sleep_ok); 1622 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1623 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1624 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1625 bool rx_en, bool tx_en); 1626 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1627 unsigned int nblinks); 1628 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1629 unsigned int mmd, unsigned int reg, u16 *valp); 1630 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1631 unsigned int mmd, unsigned int reg, u16 val); 1632 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1633 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1634 unsigned int fl0id, unsigned int fl1id); 1635 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1636 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1637 unsigned int fl0id, unsigned int fl1id); 1638 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1639 unsigned int vf, unsigned int eqid); 1640 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1641 unsigned int vf, unsigned int eqid); 1642 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1643 unsigned int vf, unsigned int eqid); 1644 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1645 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1646 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1647 void t4_db_full(struct adapter *adapter); 1648 void t4_db_dropped(struct adapter *adapter); 1649 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1650 int filter_index, int enable); 1651 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1652 int filter_index, int *enabled); 1653 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1654 u32 addr, u32 val); 1655 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1656 int rateunit, int ratemode, int channel, int class, 1657 int minrate, int maxrate, int weight, int pktsize); 1658 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1659 void t4_free_mem(void *addr); 1660 void t4_idma_monitor_init(struct adapter *adapter, 1661 struct sge_idma_monitor_state *idma); 1662 void t4_idma_monitor(struct adapter *adapter, 1663 struct sge_idma_monitor_state *idma, 1664 int hz, int ticks); 1665 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1666 unsigned int naddr, u8 *addr); 1667 void t4_uld_mem_free(struct adapter *adap); 1668 int t4_uld_mem_alloc(struct adapter *adap); 1669 void t4_uld_clean_up(struct adapter *adap); 1670 void t4_register_netevent_notifier(void); 1671 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1672 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1673 unsigned int n, bool unmap); 1674 void free_txq(struct adapter *adap, struct sge_txq *q); 1675 #endif /* __CXGB4_H__ */ 1676