1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <linux/ptp_clock_kernel.h> 52 #include <linux/ptp_classify.h> 53 #include <asm/io.h> 54 #include "t4_chip_type.h" 55 #include "cxgb4_uld.h" 56 57 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 58 extern struct list_head adapter_list; 59 extern struct mutex uld_mutex; 60 61 enum { 62 MAX_NPORTS = 4, /* max # of ports */ 63 SERNUM_LEN = 24, /* Serial # length */ 64 EC_LEN = 16, /* E/C length */ 65 ID_LEN = 16, /* ID length */ 66 PN_LEN = 16, /* Part Number length */ 67 MACADDR_LEN = 12, /* MAC Address length */ 68 }; 69 70 enum { 71 T4_REGMAP_SIZE = (160 * 1024), 72 T5_REGMAP_SIZE = (332 * 1024), 73 }; 74 75 enum { 76 MEM_EDC0, 77 MEM_EDC1, 78 MEM_MC, 79 MEM_MC0 = MEM_MC, 80 MEM_MC1 81 }; 82 83 enum { 84 MEMWIN0_APERTURE = 2048, 85 MEMWIN0_BASE = 0x1b800, 86 MEMWIN1_APERTURE = 32768, 87 MEMWIN1_BASE = 0x28000, 88 MEMWIN1_BASE_T5 = 0x52000, 89 MEMWIN2_APERTURE = 65536, 90 MEMWIN2_BASE = 0x30000, 91 MEMWIN2_APERTURE_T5 = 131072, 92 MEMWIN2_BASE_T5 = 0x60000, 93 }; 94 95 enum dev_master { 96 MASTER_CANT, 97 MASTER_MAY, 98 MASTER_MUST 99 }; 100 101 enum dev_state { 102 DEV_STATE_UNINIT, 103 DEV_STATE_INIT, 104 DEV_STATE_ERR 105 }; 106 107 enum cc_pause { 108 PAUSE_RX = 1 << 0, 109 PAUSE_TX = 1 << 1, 110 PAUSE_AUTONEG = 1 << 2 111 }; 112 113 enum cc_fec { 114 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 115 FEC_RS = 1 << 1, /* Reed-Solomon */ 116 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 117 }; 118 119 struct port_stats { 120 u64 tx_octets; /* total # of octets in good frames */ 121 u64 tx_frames; /* all good frames */ 122 u64 tx_bcast_frames; /* all broadcast frames */ 123 u64 tx_mcast_frames; /* all multicast frames */ 124 u64 tx_ucast_frames; /* all unicast frames */ 125 u64 tx_error_frames; /* all error frames */ 126 127 u64 tx_frames_64; /* # of Tx frames in a particular range */ 128 u64 tx_frames_65_127; 129 u64 tx_frames_128_255; 130 u64 tx_frames_256_511; 131 u64 tx_frames_512_1023; 132 u64 tx_frames_1024_1518; 133 u64 tx_frames_1519_max; 134 135 u64 tx_drop; /* # of dropped Tx frames */ 136 u64 tx_pause; /* # of transmitted pause frames */ 137 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 138 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 139 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 140 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 141 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 142 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 143 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 144 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 145 146 u64 rx_octets; /* total # of octets in good frames */ 147 u64 rx_frames; /* all good frames */ 148 u64 rx_bcast_frames; /* all broadcast frames */ 149 u64 rx_mcast_frames; /* all multicast frames */ 150 u64 rx_ucast_frames; /* all unicast frames */ 151 u64 rx_too_long; /* # of frames exceeding MTU */ 152 u64 rx_jabber; /* # of jabber frames */ 153 u64 rx_fcs_err; /* # of received frames with bad FCS */ 154 u64 rx_len_err; /* # of received frames with length error */ 155 u64 rx_symbol_err; /* symbol errors */ 156 u64 rx_runt; /* # of short frames */ 157 158 u64 rx_frames_64; /* # of Rx frames in a particular range */ 159 u64 rx_frames_65_127; 160 u64 rx_frames_128_255; 161 u64 rx_frames_256_511; 162 u64 rx_frames_512_1023; 163 u64 rx_frames_1024_1518; 164 u64 rx_frames_1519_max; 165 166 u64 rx_pause; /* # of received pause frames */ 167 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 168 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 169 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 170 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 171 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 172 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 173 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 174 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 175 176 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 177 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 178 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 179 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 180 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 181 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 182 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 183 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 184 }; 185 186 struct lb_port_stats { 187 u64 octets; 188 u64 frames; 189 u64 bcast_frames; 190 u64 mcast_frames; 191 u64 ucast_frames; 192 u64 error_frames; 193 194 u64 frames_64; 195 u64 frames_65_127; 196 u64 frames_128_255; 197 u64 frames_256_511; 198 u64 frames_512_1023; 199 u64 frames_1024_1518; 200 u64 frames_1519_max; 201 202 u64 drop; 203 204 u64 ovflow0; 205 u64 ovflow1; 206 u64 ovflow2; 207 u64 ovflow3; 208 u64 trunc0; 209 u64 trunc1; 210 u64 trunc2; 211 u64 trunc3; 212 }; 213 214 struct tp_tcp_stats { 215 u32 tcp_out_rsts; 216 u64 tcp_in_segs; 217 u64 tcp_out_segs; 218 u64 tcp_retrans_segs; 219 }; 220 221 struct tp_usm_stats { 222 u32 frames; 223 u32 drops; 224 u64 octets; 225 }; 226 227 struct tp_fcoe_stats { 228 u32 frames_ddp; 229 u32 frames_drop; 230 u64 octets_ddp; 231 }; 232 233 struct tp_err_stats { 234 u32 mac_in_errs[4]; 235 u32 hdr_in_errs[4]; 236 u32 tcp_in_errs[4]; 237 u32 tnl_cong_drops[4]; 238 u32 ofld_chan_drops[4]; 239 u32 tnl_tx_drops[4]; 240 u32 ofld_vlan_drops[4]; 241 u32 tcp6_in_errs[4]; 242 u32 ofld_no_neigh; 243 u32 ofld_cong_defer; 244 }; 245 246 struct tp_cpl_stats { 247 u32 req[4]; 248 u32 rsp[4]; 249 }; 250 251 struct tp_rdma_stats { 252 u32 rqe_dfr_pkt; 253 u32 rqe_dfr_mod; 254 }; 255 256 struct sge_params { 257 u32 hps; /* host page size for our PF/VF */ 258 u32 eq_qpp; /* egress queues/page for our PF/VF */ 259 u32 iq_qpp; /* egress queues/page for our PF/VF */ 260 }; 261 262 struct tp_params { 263 unsigned int tre; /* log2 of core clocks per TP tick */ 264 unsigned int la_mask; /* what events are recorded by TP LA */ 265 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 266 /* channel map */ 267 268 uint32_t dack_re; /* DACK timer resolution */ 269 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 270 271 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 272 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 273 274 /* cached TP_OUT_CONFIG compressed error vector 275 * and passing outer header info for encapsulated packets. 276 */ 277 int rx_pkt_encap; 278 279 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 280 * subset of the set of fields which may be present in the Compressed 281 * Filter Tuple portion of filters and TCP TCB connections. The 282 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 283 * Since a variable number of fields may or may not be present, their 284 * shifted field positions within the Compressed Filter Tuple may 285 * vary, or not even be present if the field isn't selected in 286 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 287 * places we store their offsets here, or a -1 if the field isn't 288 * present. 289 */ 290 int fcoe_shift; 291 int port_shift; 292 int vnic_shift; 293 int vlan_shift; 294 int tos_shift; 295 int protocol_shift; 296 int ethertype_shift; 297 int macmatch_shift; 298 int matchtype_shift; 299 int frag_shift; 300 301 u64 hash_filter_mask; 302 }; 303 304 struct vpd_params { 305 unsigned int cclk; 306 u8 ec[EC_LEN + 1]; 307 u8 sn[SERNUM_LEN + 1]; 308 u8 id[ID_LEN + 1]; 309 u8 pn[PN_LEN + 1]; 310 u8 na[MACADDR_LEN + 1]; 311 }; 312 313 struct pci_params { 314 unsigned char speed; 315 unsigned char width; 316 }; 317 318 struct devlog_params { 319 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 320 u32 start; /* start of log in firmware memory */ 321 u32 size; /* size of log */ 322 }; 323 324 /* Stores chip specific parameters */ 325 struct arch_specific_params { 326 u8 nchan; 327 u8 pm_stats_cnt; 328 u8 cng_ch_bits_log; /* congestion channel map bits width */ 329 u16 mps_rplc_size; 330 u16 vfcount; 331 u32 sge_fl_db; 332 u16 mps_tcam_size; 333 }; 334 335 struct adapter_params { 336 struct sge_params sge; 337 struct tp_params tp; 338 struct vpd_params vpd; 339 struct pci_params pci; 340 struct devlog_params devlog; 341 enum pcie_memwin drv_memwin; 342 343 unsigned int cim_la_size; 344 345 unsigned int sf_size; /* serial flash size in bytes */ 346 unsigned int sf_nsec; /* # of flash sectors */ 347 unsigned int sf_fw_start; /* start of FW image in flash */ 348 349 unsigned int fw_vers; /* firmware version */ 350 unsigned int bs_vers; /* bootstrap version */ 351 unsigned int tp_vers; /* TP microcode version */ 352 unsigned int er_vers; /* expansion ROM version */ 353 unsigned int scfg_vers; /* Serial Configuration version */ 354 unsigned int vpd_vers; /* VPD Version */ 355 u8 api_vers[7]; 356 357 unsigned short mtus[NMTUS]; 358 unsigned short a_wnd[NCCTRL_WIN]; 359 unsigned short b_wnd[NCCTRL_WIN]; 360 361 unsigned char nports; /* # of ethernet ports */ 362 unsigned char portvec; 363 enum chip_type chip; /* chip code */ 364 struct arch_specific_params arch; /* chip specific params */ 365 unsigned char offload; 366 unsigned char crypto; /* HW capability for crypto */ 367 368 unsigned char bypass; 369 unsigned char hash_filter; 370 371 unsigned int ofldq_wr_cred; 372 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 373 374 unsigned int nsched_cls; /* number of traffic classes */ 375 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 376 unsigned int max_ird_adapter; /* Max read depth per adapter */ 377 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 378 u8 fw_caps_support; /* 32-bit Port Capabilities */ 379 bool filter2_wr_support; /* FW support for FILTER2_WR */ 380 381 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 382 * used by the Port 383 */ 384 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 385 }; 386 387 /* State needed to monitor the forward progress of SGE Ingress DMA activities 388 * and possible hangs. 389 */ 390 struct sge_idma_monitor_state { 391 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 392 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 393 unsigned int idma_state[2]; /* IDMA Hang detect state */ 394 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 395 unsigned int idma_warn[2]; /* time to warning in HZ */ 396 }; 397 398 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 399 * The access and execute times are signed in order to accommodate negative 400 * error returns. 401 */ 402 struct mbox_cmd { 403 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 404 u64 timestamp; /* OS-dependent timestamp */ 405 u32 seqno; /* sequence number */ 406 s16 access; /* time (ms) to access mailbox */ 407 s16 execute; /* time (ms) to execute */ 408 }; 409 410 struct mbox_cmd_log { 411 unsigned int size; /* number of entries in the log */ 412 unsigned int cursor; /* next position in the log to write */ 413 u32 seqno; /* next sequence number */ 414 /* variable length mailbox command log starts here */ 415 }; 416 417 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 418 * return a pointer to the specified entry. 419 */ 420 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 421 unsigned int entry_idx) 422 { 423 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 424 } 425 426 #include "t4fw_api.h" 427 428 #define FW_VERSION(chip) ( \ 429 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 430 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 431 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 432 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 433 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 434 435 struct fw_info { 436 u8 chip; 437 char *fs_name; 438 char *fw_mod_name; 439 struct fw_hdr fw_hdr; 440 }; 441 442 struct trace_params { 443 u32 data[TRACE_LEN / 4]; 444 u32 mask[TRACE_LEN / 4]; 445 unsigned short snap_len; 446 unsigned short min_len; 447 unsigned char skip_ofst; 448 unsigned char skip_len; 449 unsigned char invert; 450 unsigned char port; 451 }; 452 453 /* Firmware Port Capabilities types. */ 454 455 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 456 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 457 458 enum fw_caps { 459 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 460 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 461 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 462 }; 463 464 struct link_config { 465 fw_port_cap32_t pcaps; /* link capabilities */ 466 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 467 fw_port_cap32_t acaps; /* advertised capabilities */ 468 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 469 470 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 471 unsigned int speed; /* actual link speed (Mb/s) */ 472 473 enum cc_pause requested_fc; /* flow control user has requested */ 474 enum cc_pause fc; /* actual link flow control */ 475 476 enum cc_fec requested_fec; /* Forward Error Correction: */ 477 enum cc_fec fec; /* requested and actual in use */ 478 479 unsigned char autoneg; /* autonegotiating? */ 480 481 unsigned char link_ok; /* link up? */ 482 unsigned char link_down_rc; /* link down reason */ 483 }; 484 485 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 486 487 enum { 488 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 489 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 490 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 491 }; 492 493 enum { 494 MAX_TXQ_ENTRIES = 16384, 495 MAX_CTRL_TXQ_ENTRIES = 1024, 496 MAX_RSPQ_ENTRIES = 16384, 497 MAX_RX_BUFFERS = 16384, 498 MIN_TXQ_ENTRIES = 32, 499 MIN_CTRL_TXQ_ENTRIES = 32, 500 MIN_RSPQ_ENTRIES = 128, 501 MIN_FL_ENTRIES = 16 502 }; 503 504 enum { 505 INGQ_EXTRAS = 2, /* firmware event queue and */ 506 /* forwarded interrupts */ 507 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 508 }; 509 510 struct adapter; 511 struct sge_rspq; 512 513 #include "cxgb4_dcb.h" 514 515 #ifdef CONFIG_CHELSIO_T4_FCOE 516 #include "cxgb4_fcoe.h" 517 #endif /* CONFIG_CHELSIO_T4_FCOE */ 518 519 struct port_info { 520 struct adapter *adapter; 521 u16 viid; 522 s16 xact_addr_filt; /* index of exact MAC address filter */ 523 u16 rss_size; /* size of VI's RSS table slice */ 524 s8 mdio_addr; 525 enum fw_port_type port_type; 526 u8 mod_type; 527 u8 port_id; 528 u8 tx_chan; 529 u8 lport; /* associated offload logical port */ 530 u8 nqsets; /* # of qsets */ 531 u8 first_qset; /* index of first qset */ 532 u8 rss_mode; 533 struct link_config link_cfg; 534 u16 *rss; 535 struct port_stats stats_base; 536 #ifdef CONFIG_CHELSIO_T4_DCB 537 struct port_dcb_info dcb; /* Data Center Bridging support */ 538 #endif 539 #ifdef CONFIG_CHELSIO_T4_FCOE 540 struct cxgb_fcoe fcoe; 541 #endif /* CONFIG_CHELSIO_T4_FCOE */ 542 bool rxtstamp; /* Enable TS */ 543 struct hwtstamp_config tstamp_config; 544 bool ptp_enable; 545 struct sched_table *sched_tbl; 546 }; 547 548 struct dentry; 549 struct work_struct; 550 551 enum { /* adapter flags */ 552 FULL_INIT_DONE = (1 << 0), 553 DEV_ENABLED = (1 << 1), 554 USING_MSI = (1 << 2), 555 USING_MSIX = (1 << 3), 556 FW_OK = (1 << 4), 557 RSS_TNLALLLOOKUP = (1 << 5), 558 USING_SOFT_PARAMS = (1 << 6), 559 MASTER_PF = (1 << 7), 560 FW_OFLD_CONN = (1 << 9), 561 ROOT_NO_RELAXED_ORDERING = (1 << 10), 562 SHUTTING_DOWN = (1 << 11), 563 }; 564 565 enum { 566 ULP_CRYPTO_LOOKASIDE = 1 << 0, 567 }; 568 569 struct rx_sw_desc; 570 571 struct sge_fl { /* SGE free-buffer queue state */ 572 unsigned int avail; /* # of available Rx buffers */ 573 unsigned int pend_cred; /* new buffers since last FL DB ring */ 574 unsigned int cidx; /* consumer index */ 575 unsigned int pidx; /* producer index */ 576 unsigned long alloc_failed; /* # of times buffer allocation failed */ 577 unsigned long large_alloc_failed; 578 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 579 unsigned long low; /* # of times momentarily starving */ 580 unsigned long starving; 581 /* RO fields */ 582 unsigned int cntxt_id; /* SGE context id for the free list */ 583 unsigned int size; /* capacity of free list */ 584 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 585 __be64 *desc; /* address of HW Rx descriptor ring */ 586 dma_addr_t addr; /* bus address of HW ring start */ 587 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 588 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 589 }; 590 591 /* A packet gather list */ 592 struct pkt_gl { 593 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 594 struct page_frag frags[MAX_SKB_FRAGS]; 595 void *va; /* virtual address of first byte */ 596 unsigned int nfrags; /* # of fragments */ 597 unsigned int tot_len; /* total length of fragments */ 598 }; 599 600 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 601 const struct pkt_gl *gl); 602 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 603 /* LRO related declarations for ULD */ 604 struct t4_lro_mgr { 605 #define MAX_LRO_SESSIONS 64 606 u8 lro_session_cnt; /* # of sessions to aggregate */ 607 unsigned long lro_pkts; /* # of LRO super packets */ 608 unsigned long lro_merged; /* # of wire packets merged by LRO */ 609 struct sk_buff_head lroq; /* list of aggregated sessions */ 610 }; 611 612 struct sge_rspq { /* state for an SGE response queue */ 613 struct napi_struct napi; 614 const __be64 *cur_desc; /* current descriptor in queue */ 615 unsigned int cidx; /* consumer index */ 616 u8 gen; /* current generation bit */ 617 u8 intr_params; /* interrupt holdoff parameters */ 618 u8 next_intr_params; /* holdoff params for next interrupt */ 619 u8 adaptive_rx; 620 u8 pktcnt_idx; /* interrupt packet threshold */ 621 u8 uld; /* ULD handling this queue */ 622 u8 idx; /* queue index within its group */ 623 int offset; /* offset into current Rx buffer */ 624 u16 cntxt_id; /* SGE context id for the response q */ 625 u16 abs_id; /* absolute SGE id for the response q */ 626 __be64 *desc; /* address of HW response ring */ 627 dma_addr_t phys_addr; /* physical address of the ring */ 628 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 629 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 630 unsigned int iqe_len; /* entry size */ 631 unsigned int size; /* capacity of response queue */ 632 struct adapter *adap; 633 struct net_device *netdev; /* associated net device */ 634 rspq_handler_t handler; 635 rspq_flush_handler_t flush_handler; 636 struct t4_lro_mgr lro_mgr; 637 }; 638 639 struct sge_eth_stats { /* Ethernet queue statistics */ 640 unsigned long pkts; /* # of ethernet packets */ 641 unsigned long lro_pkts; /* # of LRO super packets */ 642 unsigned long lro_merged; /* # of wire packets merged by LRO */ 643 unsigned long rx_cso; /* # of Rx checksum offloads */ 644 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 645 unsigned long rx_drops; /* # of packets dropped due to no mem */ 646 }; 647 648 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 649 struct sge_rspq rspq; 650 struct sge_fl fl; 651 struct sge_eth_stats stats; 652 } ____cacheline_aligned_in_smp; 653 654 struct sge_ofld_stats { /* offload queue statistics */ 655 unsigned long pkts; /* # of packets */ 656 unsigned long imm; /* # of immediate-data packets */ 657 unsigned long an; /* # of asynchronous notifications */ 658 unsigned long nomem; /* # of responses deferred due to no mem */ 659 }; 660 661 struct sge_ofld_rxq { /* SW offload Rx queue */ 662 struct sge_rspq rspq; 663 struct sge_fl fl; 664 struct sge_ofld_stats stats; 665 } ____cacheline_aligned_in_smp; 666 667 struct tx_desc { 668 __be64 flit[8]; 669 }; 670 671 struct tx_sw_desc; 672 673 struct sge_txq { 674 unsigned int in_use; /* # of in-use Tx descriptors */ 675 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 676 unsigned int size; /* # of descriptors */ 677 unsigned int cidx; /* SW consumer index */ 678 unsigned int pidx; /* producer index */ 679 unsigned long stops; /* # of times q has been stopped */ 680 unsigned long restarts; /* # of queue restarts */ 681 unsigned int cntxt_id; /* SGE context id for the Tx q */ 682 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 683 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 684 struct sge_qstat *stat; /* queue status entry */ 685 dma_addr_t phys_addr; /* physical address of the ring */ 686 spinlock_t db_lock; 687 int db_disabled; 688 unsigned short db_pidx; 689 unsigned short db_pidx_inc; 690 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 691 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 692 }; 693 694 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 695 struct sge_txq q; 696 struct netdev_queue *txq; /* associated netdev TX queue */ 697 #ifdef CONFIG_CHELSIO_T4_DCB 698 u8 dcb_prio; /* DCB Priority bound to queue */ 699 #endif 700 unsigned long tso; /* # of TSO requests */ 701 unsigned long tx_cso; /* # of Tx checksum offloads */ 702 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 703 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 704 } ____cacheline_aligned_in_smp; 705 706 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 707 struct sge_txq q; 708 struct adapter *adap; 709 struct sk_buff_head sendq; /* list of backpressured packets */ 710 struct tasklet_struct qresume_tsk; /* restarts the queue */ 711 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 712 u8 full; /* the Tx ring is full */ 713 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 714 } ____cacheline_aligned_in_smp; 715 716 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 717 struct sge_txq q; 718 struct adapter *adap; 719 struct sk_buff_head sendq; /* list of backpressured packets */ 720 struct tasklet_struct qresume_tsk; /* restarts the queue */ 721 u8 full; /* the Tx ring is full */ 722 } ____cacheline_aligned_in_smp; 723 724 struct sge_uld_rxq_info { 725 char name[IFNAMSIZ]; /* name of ULD driver */ 726 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 727 u16 *msix_tbl; /* msix_tbl for uld */ 728 u16 *rspq_id; /* response queue id's of rxq */ 729 u16 nrxq; /* # of ingress uld queues */ 730 u16 nciq; /* # of completion queues */ 731 u8 uld; /* uld type */ 732 }; 733 734 struct sge_uld_txq_info { 735 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 736 atomic_t users; /* num users */ 737 u16 ntxq; /* # of egress uld queues */ 738 }; 739 740 struct sge { 741 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 742 struct sge_eth_txq ptptxq; 743 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 744 745 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 746 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 747 struct sge_uld_rxq_info **uld_rxq_info; 748 struct sge_uld_txq_info **uld_txq_info; 749 750 struct sge_rspq intrq ____cacheline_aligned_in_smp; 751 spinlock_t intrq_lock; 752 753 u16 max_ethqsets; /* # of available Ethernet queue sets */ 754 u16 ethqsets; /* # of active Ethernet queue sets */ 755 u16 ethtxq_rover; /* Tx queue to clean up next */ 756 u16 ofldqsets; /* # of active ofld queue sets */ 757 u16 nqs_per_uld; /* # of Rx queues per ULD */ 758 u16 timer_val[SGE_NTIMERS]; 759 u8 counter_val[SGE_NCOUNTERS]; 760 u32 fl_pg_order; /* large page allocation size */ 761 u32 stat_len; /* length of status page at ring end */ 762 u32 pktshift; /* padding between CPL & packet data */ 763 u32 fl_align; /* response queue message alignment */ 764 u32 fl_starve_thres; /* Free List starvation threshold */ 765 766 struct sge_idma_monitor_state idma_monitor; 767 unsigned int egr_start; 768 unsigned int egr_sz; 769 unsigned int ingr_start; 770 unsigned int ingr_sz; 771 void **egr_map; /* qid->queue egress queue map */ 772 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 773 unsigned long *starving_fl; 774 unsigned long *txq_maperr; 775 unsigned long *blocked_fl; 776 struct timer_list rx_timer; /* refills starving FLs */ 777 struct timer_list tx_timer; /* checks Tx queues */ 778 }; 779 780 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 781 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 782 783 struct l2t_data; 784 785 #ifdef CONFIG_PCI_IOV 786 787 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 788 * Configuration initialization for T5 only has SR-IOV functionality enabled 789 * on PF0-3 in order to simplify everything. 790 */ 791 #define NUM_OF_PF_WITH_SRIOV 4 792 793 #endif 794 795 struct doorbell_stats { 796 u32 db_drop; 797 u32 db_empty; 798 u32 db_full; 799 }; 800 801 struct hash_mac_addr { 802 struct list_head list; 803 u8 addr[ETH_ALEN]; 804 }; 805 806 struct uld_msix_bmap { 807 unsigned long *msix_bmap; 808 unsigned int mapsize; 809 spinlock_t lock; /* lock for acquiring bitmap */ 810 }; 811 812 struct uld_msix_info { 813 unsigned short vec; 814 char desc[IFNAMSIZ + 10]; 815 unsigned int idx; 816 }; 817 818 struct vf_info { 819 unsigned char vf_mac_addr[ETH_ALEN]; 820 unsigned int tx_rate; 821 bool pf_set_mac; 822 }; 823 824 struct mbox_list { 825 struct list_head list; 826 }; 827 828 struct adapter { 829 void __iomem *regs; 830 void __iomem *bar2; 831 u32 t4_bar0; 832 struct pci_dev *pdev; 833 struct device *pdev_dev; 834 const char *name; 835 unsigned int mbox; 836 unsigned int pf; 837 unsigned int flags; 838 unsigned int adap_idx; 839 enum chip_type chip; 840 841 int msg_enable; 842 843 struct adapter_params params; 844 struct cxgb4_virt_res vres; 845 unsigned int swintr; 846 847 struct { 848 unsigned short vec; 849 char desc[IFNAMSIZ + 10]; 850 } msix_info[MAX_INGQ + 1]; 851 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 852 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 853 int msi_idx; 854 855 struct doorbell_stats db_stats; 856 struct sge sge; 857 858 struct net_device *port[MAX_NPORTS]; 859 u8 chan_map[NCHAN]; /* channel -> port map */ 860 861 struct vf_info *vfinfo; 862 u8 num_vfs; 863 864 u32 filter_mode; 865 unsigned int l2t_start; 866 unsigned int l2t_end; 867 struct l2t_data *l2t; 868 unsigned int clipt_start; 869 unsigned int clipt_end; 870 struct clip_tbl *clipt; 871 struct smt_data *smt; 872 struct cxgb4_uld_info *uld; 873 void *uld_handle[CXGB4_ULD_MAX]; 874 unsigned int num_uld; 875 unsigned int num_ofld_uld; 876 struct list_head list_node; 877 struct list_head rcu_node; 878 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 879 880 void *iscsi_ppm; 881 882 struct tid_info tids; 883 void **tid_release_head; 884 spinlock_t tid_release_lock; 885 struct workqueue_struct *workq; 886 struct work_struct tid_release_task; 887 struct work_struct db_full_task; 888 struct work_struct db_drop_task; 889 bool tid_release_task_busy; 890 891 /* lock for mailbox cmd list */ 892 spinlock_t mbox_lock; 893 struct mbox_list mlist; 894 895 /* support for mailbox command/reply logging */ 896 #define T4_OS_LOG_MBOX_CMDS 256 897 struct mbox_cmd_log *mbox_log; 898 899 struct mutex uld_mutex; 900 901 struct dentry *debugfs_root; 902 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 903 bool trace_rss; /* 1 implies that different RSS flit per filter is 904 * used per filter else if 0 default RSS flit is 905 * used for all 4 filters. 906 */ 907 908 struct ptp_clock *ptp_clock; 909 struct ptp_clock_info ptp_clock_info; 910 struct sk_buff *ptp_tx_skb; 911 /* ptp lock */ 912 spinlock_t ptp_lock; 913 spinlock_t stats_lock; 914 spinlock_t win0_lock ____cacheline_aligned_in_smp; 915 916 /* TC u32 offload */ 917 struct cxgb4_tc_u32_table *tc_u32; 918 struct chcr_stats_debug chcr_stats; 919 920 /* TC flower offload */ 921 struct rhashtable flower_tbl; 922 struct rhashtable_params flower_ht_params; 923 struct timer_list flower_stats_timer; 924 struct work_struct flower_stats_work; 925 926 /* Ethtool Dump */ 927 struct ethtool_dump eth_dump; 928 }; 929 930 /* Support for "sched-class" command to allow a TX Scheduling Class to be 931 * programmed with various parameters. 932 */ 933 struct ch_sched_params { 934 s8 type; /* packet or flow */ 935 union { 936 struct { 937 s8 level; /* scheduler hierarchy level */ 938 s8 mode; /* per-class or per-flow */ 939 s8 rateunit; /* bit or packet rate */ 940 s8 ratemode; /* %port relative or kbps absolute */ 941 s8 channel; /* scheduler channel [0..N] */ 942 s8 class; /* scheduler class [0..N] */ 943 s32 minrate; /* minimum rate */ 944 s32 maxrate; /* maximum rate */ 945 s16 weight; /* percent weight */ 946 s16 pktsize; /* average packet size */ 947 } params; 948 } u; 949 }; 950 951 enum { 952 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 953 }; 954 955 enum { 956 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 957 }; 958 959 enum { 960 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 961 }; 962 963 enum { 964 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 965 }; 966 967 enum { 968 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 969 }; 970 971 /* Support for "sched_queue" command to allow one or more NIC TX Queues 972 * to be bound to a TX Scheduling Class. 973 */ 974 struct ch_sched_queue { 975 s8 queue; /* queue index */ 976 s8 class; /* class index */ 977 }; 978 979 /* Defined bit width of user definable filter tuples 980 */ 981 #define ETHTYPE_BITWIDTH 16 982 #define FRAG_BITWIDTH 1 983 #define MACIDX_BITWIDTH 9 984 #define FCOE_BITWIDTH 1 985 #define IPORT_BITWIDTH 3 986 #define MATCHTYPE_BITWIDTH 3 987 #define PROTO_BITWIDTH 8 988 #define TOS_BITWIDTH 8 989 #define PF_BITWIDTH 8 990 #define VF_BITWIDTH 8 991 #define IVLAN_BITWIDTH 16 992 #define OVLAN_BITWIDTH 16 993 994 /* Filter matching rules. These consist of a set of ingress packet field 995 * (value, mask) tuples. The associated ingress packet field matches the 996 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 997 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 998 * matches an ingress packet when all of the individual individual field 999 * matching rules are true. 1000 * 1001 * Partial field masks are always valid, however, while it may be easy to 1002 * understand their meanings for some fields (e.g. IP address to match a 1003 * subnet), for others making sensible partial masks is less intuitive (e.g. 1004 * MPS match type) ... 1005 * 1006 * Most of the following data structures are modeled on T4 capabilities. 1007 * Drivers for earlier chips use the subsets which make sense for those chips. 1008 * We really need to come up with a hardware-independent mechanism to 1009 * represent hardware filter capabilities ... 1010 */ 1011 struct ch_filter_tuple { 1012 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1013 * register selects which of these fields will participate in the 1014 * filter match rules -- up to a maximum of 36 bits. Because 1015 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1016 * set of fields. 1017 */ 1018 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1019 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1020 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1021 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1022 uint32_t pfvf_vld:1; /* PF/VF valid */ 1023 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1024 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1025 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1026 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1027 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1028 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1029 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1030 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1031 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1032 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1033 1034 /* Uncompressed header matching field rules. These are always 1035 * available for field rules. 1036 */ 1037 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1038 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1039 uint16_t lport; /* local port */ 1040 uint16_t fport; /* foreign port */ 1041 }; 1042 1043 /* A filter ioctl command. 1044 */ 1045 struct ch_filter_specification { 1046 /* Administrative fields for filter. 1047 */ 1048 uint32_t hitcnts:1; /* count filter hits in TCB */ 1049 uint32_t prio:1; /* filter has priority over active/server */ 1050 1051 /* Fundamental filter typing. This is the one element of filter 1052 * matching that doesn't exist as a (value, mask) tuple. 1053 */ 1054 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1055 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1056 1057 /* Packet dispatch information. Ingress packets which match the 1058 * filter rules will be dropped, passed to the host or switched back 1059 * out as egress packets. 1060 */ 1061 uint32_t action:2; /* drop, pass, switch */ 1062 1063 uint32_t rpttid:1; /* report TID in RSS hash field */ 1064 1065 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1066 uint32_t iq:10; /* ingress queue */ 1067 1068 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1069 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1070 /* 1 => TCB contains IQ ID */ 1071 1072 /* Switch proxy/rewrite fields. An ingress packet which matches a 1073 * filter with "switch" set will be looped back out as an egress 1074 * packet -- potentially with some Ethernet header rewriting. 1075 */ 1076 uint32_t eport:2; /* egress port to switch packet out */ 1077 uint32_t newdmac:1; /* rewrite destination MAC address */ 1078 uint32_t newsmac:1; /* rewrite source MAC address */ 1079 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1080 uint32_t nat_mode:3; /* specify NAT operation mode */ 1081 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1082 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1083 uint16_t vlan; /* VLAN Tag to insert */ 1084 1085 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1086 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1087 u16 nat_lport; /* local port to use after NAT'ing */ 1088 u16 nat_fport; /* foreign port to use after NAT'ing */ 1089 1090 /* reservation for future additions */ 1091 u8 rsvd[24]; 1092 1093 /* Filter rule value/mask pairs. 1094 */ 1095 struct ch_filter_tuple val; 1096 struct ch_filter_tuple mask; 1097 }; 1098 1099 enum { 1100 FILTER_PASS = 0, /* default */ 1101 FILTER_DROP, 1102 FILTER_SWITCH 1103 }; 1104 1105 enum { 1106 VLAN_NOCHANGE = 0, /* default */ 1107 VLAN_REMOVE, 1108 VLAN_INSERT, 1109 VLAN_REWRITE 1110 }; 1111 1112 enum { 1113 NAT_MODE_NONE = 0, /* No NAT performed */ 1114 NAT_MODE_DIP, /* NAT on Dst IP */ 1115 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1116 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1117 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1118 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1119 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1120 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1121 }; 1122 1123 /* Host shadow copy of ingress filter entry. This is in host native format 1124 * and doesn't match the ordering or bit order, etc. of the hardware of the 1125 * firmware command. The use of bit-field structure elements is purely to 1126 * remind ourselves of the field size limitations and save memory in the case 1127 * where the filter table is large. 1128 */ 1129 struct filter_entry { 1130 /* Administrative fields for filter. */ 1131 u32 valid:1; /* filter allocated and valid */ 1132 u32 locked:1; /* filter is administratively locked */ 1133 1134 u32 pending:1; /* filter action is pending firmware reply */ 1135 struct filter_ctx *ctx; /* Caller's completion hook */ 1136 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1137 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1138 struct net_device *dev; /* Associated net device */ 1139 u32 tid; /* This will store the actual tid */ 1140 1141 /* The filter itself. Most of this is a straight copy of information 1142 * provided by the extended ioctl(). Some fields are translated to 1143 * internal forms -- for instance the Ingress Queue ID passed in from 1144 * the ioctl() is translated into the Absolute Ingress Queue ID. 1145 */ 1146 struct ch_filter_specification fs; 1147 }; 1148 1149 static inline int is_offload(const struct adapter *adap) 1150 { 1151 return adap->params.offload; 1152 } 1153 1154 static inline int is_hashfilter(const struct adapter *adap) 1155 { 1156 return adap->params.hash_filter; 1157 } 1158 1159 static inline int is_pci_uld(const struct adapter *adap) 1160 { 1161 return adap->params.crypto; 1162 } 1163 1164 static inline int is_uld(const struct adapter *adap) 1165 { 1166 return (adap->params.offload || adap->params.crypto); 1167 } 1168 1169 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1170 { 1171 return readl(adap->regs + reg_addr); 1172 } 1173 1174 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1175 { 1176 writel(val, adap->regs + reg_addr); 1177 } 1178 1179 #ifndef readq 1180 static inline u64 readq(const volatile void __iomem *addr) 1181 { 1182 return readl(addr) + ((u64)readl(addr + 4) << 32); 1183 } 1184 1185 static inline void writeq(u64 val, volatile void __iomem *addr) 1186 { 1187 writel(val, addr); 1188 writel(val >> 32, addr + 4); 1189 } 1190 #endif 1191 1192 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1193 { 1194 return readq(adap->regs + reg_addr); 1195 } 1196 1197 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1198 { 1199 writeq(val, adap->regs + reg_addr); 1200 } 1201 1202 /** 1203 * t4_set_hw_addr - store a port's MAC address in SW 1204 * @adapter: the adapter 1205 * @port_idx: the port index 1206 * @hw_addr: the Ethernet address 1207 * 1208 * Store the Ethernet address of the given port in SW. Called by the common 1209 * code when it retrieves a port's Ethernet address from EEPROM. 1210 */ 1211 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1212 u8 hw_addr[]) 1213 { 1214 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1215 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1216 } 1217 1218 /** 1219 * netdev2pinfo - return the port_info structure associated with a net_device 1220 * @dev: the netdev 1221 * 1222 * Return the struct port_info associated with a net_device 1223 */ 1224 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1225 { 1226 return netdev_priv(dev); 1227 } 1228 1229 /** 1230 * adap2pinfo - return the port_info of a port 1231 * @adap: the adapter 1232 * @idx: the port index 1233 * 1234 * Return the port_info structure for the port of the given index. 1235 */ 1236 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1237 { 1238 return netdev_priv(adap->port[idx]); 1239 } 1240 1241 /** 1242 * netdev2adap - return the adapter structure associated with a net_device 1243 * @dev: the netdev 1244 * 1245 * Return the struct adapter associated with a net_device 1246 */ 1247 static inline struct adapter *netdev2adap(const struct net_device *dev) 1248 { 1249 return netdev2pinfo(dev)->adapter; 1250 } 1251 1252 /* Return a version number to identify the type of adapter. The scheme is: 1253 * - bits 0..9: chip version 1254 * - bits 10..15: chip revision 1255 * - bits 16..23: register dump version 1256 */ 1257 static inline unsigned int mk_adap_vers(struct adapter *ap) 1258 { 1259 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1260 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1261 } 1262 1263 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1264 static inline unsigned int qtimer_val(const struct adapter *adap, 1265 const struct sge_rspq *q) 1266 { 1267 unsigned int idx = q->intr_params >> 1; 1268 1269 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1270 } 1271 1272 /* driver version & name used for ethtool_drvinfo */ 1273 extern char cxgb4_driver_name[]; 1274 extern const char cxgb4_driver_version[]; 1275 1276 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1277 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1278 1279 void t4_free_sge_resources(struct adapter *adap); 1280 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1281 irq_handler_t t4_intr_handler(struct adapter *adap); 1282 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1283 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1284 const struct pkt_gl *gl); 1285 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1286 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1287 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1288 struct net_device *dev, int intr_idx, 1289 struct sge_fl *fl, rspq_handler_t hnd, 1290 rspq_flush_handler_t flush_handler, int cong); 1291 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1292 struct net_device *dev, struct netdev_queue *netdevq, 1293 unsigned int iqid); 1294 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1295 struct net_device *dev, unsigned int iqid, 1296 unsigned int cmplqid); 1297 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1298 unsigned int cmplqid); 1299 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1300 struct net_device *dev, unsigned int iqid, 1301 unsigned int uld_type); 1302 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1303 int t4_sge_init(struct adapter *adap); 1304 void t4_sge_start(struct adapter *adap); 1305 void t4_sge_stop(struct adapter *adap); 1306 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1307 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1308 extern int dbfifo_int_thresh; 1309 1310 #define for_each_port(adapter, iter) \ 1311 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1312 1313 static inline int is_bypass(struct adapter *adap) 1314 { 1315 return adap->params.bypass; 1316 } 1317 1318 static inline int is_bypass_device(int device) 1319 { 1320 /* this should be set based upon device capabilities */ 1321 switch (device) { 1322 case 0x440b: 1323 case 0x440c: 1324 return 1; 1325 default: 1326 return 0; 1327 } 1328 } 1329 1330 static inline int is_10gbt_device(int device) 1331 { 1332 /* this should be set based upon device capabilities */ 1333 switch (device) { 1334 case 0x4409: 1335 case 0x4486: 1336 return 1; 1337 1338 default: 1339 return 0; 1340 } 1341 } 1342 1343 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1344 { 1345 return adap->params.vpd.cclk / 1000; 1346 } 1347 1348 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1349 unsigned int us) 1350 { 1351 return (us * adap->params.vpd.cclk) / 1000; 1352 } 1353 1354 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1355 unsigned int ticks) 1356 { 1357 /* add Core Clock / 2 to round ticks to nearest uS */ 1358 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1359 adapter->params.vpd.cclk); 1360 } 1361 1362 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1363 unsigned int ticks) 1364 { 1365 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1366 } 1367 1368 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1369 u32 val); 1370 1371 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1372 int size, void *rpl, bool sleep_ok, int timeout); 1373 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1374 void *rpl, bool sleep_ok); 1375 1376 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1377 const void *cmd, int size, void *rpl, 1378 int timeout) 1379 { 1380 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1381 timeout); 1382 } 1383 1384 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1385 int size, void *rpl) 1386 { 1387 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1388 } 1389 1390 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1391 int size, void *rpl) 1392 { 1393 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1394 } 1395 1396 /** 1397 * hash_mac_addr - return the hash value of a MAC address 1398 * @addr: the 48-bit Ethernet MAC address 1399 * 1400 * Hashes a MAC address according to the hash function used by HW inexact 1401 * (hash) address matching. 1402 */ 1403 static inline int hash_mac_addr(const u8 *addr) 1404 { 1405 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1406 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1407 1408 a ^= b; 1409 a ^= (a >> 12); 1410 a ^= (a >> 6); 1411 return a & 0x3f; 1412 } 1413 1414 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1415 unsigned int cnt); 1416 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1417 unsigned int us, unsigned int cnt, 1418 unsigned int size, unsigned int iqe_size) 1419 { 1420 q->adap = adap; 1421 cxgb4_set_rspq_intr_params(q, us, cnt); 1422 q->iqe_len = iqe_size; 1423 q->size = size; 1424 } 1425 1426 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1427 unsigned int data_reg, const u32 *vals, 1428 unsigned int nregs, unsigned int start_idx); 1429 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1430 unsigned int data_reg, u32 *vals, unsigned int nregs, 1431 unsigned int start_idx); 1432 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1433 1434 struct fw_filter_wr; 1435 1436 void t4_intr_enable(struct adapter *adapter); 1437 void t4_intr_disable(struct adapter *adapter); 1438 int t4_slow_intr_handler(struct adapter *adapter); 1439 1440 int t4_wait_dev_ready(void __iomem *regs); 1441 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1442 struct link_config *lc); 1443 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1444 1445 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1446 u32 t4_get_util_window(struct adapter *adap); 1447 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1448 1449 #define T4_MEMORY_WRITE 0 1450 #define T4_MEMORY_READ 1 1451 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1452 void *buf, int dir); 1453 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1454 u32 len, __be32 *buf) 1455 { 1456 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1457 } 1458 1459 unsigned int t4_get_regs_len(struct adapter *adapter); 1460 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1461 1462 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1463 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1464 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1465 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1466 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1467 unsigned int nwords, u32 *data, int byte_oriented); 1468 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1469 int t4_load_phy_fw(struct adapter *adap, 1470 int win, spinlock_t *lock, 1471 int (*phy_fw_version)(const u8 *, size_t), 1472 const u8 *phy_fw_data, size_t phy_fw_size); 1473 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1474 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1475 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1476 const u8 *fw_data, unsigned int size, int force); 1477 int t4_fl_pkt_align(struct adapter *adap); 1478 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1479 int t4_check_fw_version(struct adapter *adap); 1480 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1481 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1482 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1483 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1484 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1485 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1486 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1487 int t4_get_version_info(struct adapter *adapter); 1488 void t4_dump_version_info(struct adapter *adapter); 1489 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1490 const u8 *fw_data, unsigned int fw_size, 1491 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1492 int t4_prep_adapter(struct adapter *adapter); 1493 int t4_shutdown_adapter(struct adapter *adapter); 1494 1495 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1496 int t4_bar2_sge_qregs(struct adapter *adapter, 1497 unsigned int qid, 1498 enum t4_bar2_qtype qtype, 1499 int user, 1500 u64 *pbar2_qoffset, 1501 unsigned int *pbar2_qid); 1502 1503 unsigned int qtimer_val(const struct adapter *adap, 1504 const struct sge_rspq *q); 1505 1506 int t4_init_devlog_params(struct adapter *adapter); 1507 int t4_init_sge_params(struct adapter *adapter); 1508 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1509 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1510 int t4_init_rss_mode(struct adapter *adap, int mbox); 1511 int t4_init_portinfo(struct port_info *pi, int mbox, 1512 int port, int pf, int vf, u8 mac[]); 1513 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1514 void t4_fatal_err(struct adapter *adapter); 1515 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1516 int start, int n, const u16 *rspq, unsigned int nrspq); 1517 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1518 unsigned int flags); 1519 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1520 unsigned int flags, unsigned int defq); 1521 int t4_read_rss(struct adapter *adapter, u16 *entries); 1522 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1523 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1524 bool sleep_ok); 1525 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1526 u32 *valp, bool sleep_ok); 1527 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1528 u32 *vfl, u32 *vfh, bool sleep_ok); 1529 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1530 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1531 1532 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1533 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1534 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1535 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1536 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1537 size_t n); 1538 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1539 size_t n); 1540 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1541 unsigned int *valp); 1542 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1543 const unsigned int *valp); 1544 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1545 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1546 unsigned int *pif_req_wrptr, 1547 unsigned int *pif_rsp_wrptr); 1548 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1549 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1550 const char *t4_get_port_type_description(enum fw_port_type port_type); 1551 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1552 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1553 struct port_stats *stats, 1554 struct port_stats *offset); 1555 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1556 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1557 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1558 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1559 unsigned int mask, unsigned int val); 1560 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1561 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1562 bool sleep_ok); 1563 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1564 bool sleep_ok); 1565 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1566 bool sleep_ok); 1567 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1568 bool sleep_ok); 1569 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1570 struct tp_tcp_stats *v6, bool sleep_ok); 1571 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1572 struct tp_fcoe_stats *st, bool sleep_ok); 1573 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1574 const unsigned short *alpha, const unsigned short *beta); 1575 1576 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1577 1578 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1579 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1580 1581 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1582 const u8 *addr); 1583 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1584 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1585 1586 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1587 enum dev_master master, enum dev_state *state); 1588 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1589 int t4_early_init(struct adapter *adap, unsigned int mbox); 1590 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1591 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1592 unsigned int cache_line_size); 1593 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1594 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1595 unsigned int vf, unsigned int nparams, const u32 *params, 1596 u32 *val); 1597 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1598 unsigned int vf, unsigned int nparams, const u32 *params, 1599 u32 *val); 1600 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1601 unsigned int vf, unsigned int nparams, const u32 *params, 1602 u32 *val, int rw, bool sleep_ok); 1603 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1604 unsigned int pf, unsigned int vf, 1605 unsigned int nparams, const u32 *params, 1606 const u32 *val, int timeout); 1607 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1608 unsigned int vf, unsigned int nparams, const u32 *params, 1609 const u32 *val); 1610 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1611 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1612 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1613 unsigned int vi, unsigned int cmask, unsigned int pmask, 1614 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1615 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1616 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1617 unsigned int *rss_size); 1618 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1619 unsigned int pf, unsigned int vf, 1620 unsigned int viid); 1621 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1622 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1623 bool sleep_ok); 1624 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1625 unsigned int viid, bool free, unsigned int naddr, 1626 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1627 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1628 unsigned int viid, unsigned int naddr, 1629 const u8 **addr, bool sleep_ok); 1630 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1631 int idx, const u8 *addr, bool persist, bool add_smt); 1632 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1633 bool ucast, u64 vec, bool sleep_ok); 1634 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1635 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1636 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1637 bool rx_en, bool tx_en); 1638 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1639 unsigned int nblinks); 1640 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1641 unsigned int mmd, unsigned int reg, u16 *valp); 1642 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1643 unsigned int mmd, unsigned int reg, u16 val); 1644 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1645 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1646 unsigned int fl0id, unsigned int fl1id); 1647 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1648 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1649 unsigned int fl0id, unsigned int fl1id); 1650 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1651 unsigned int vf, unsigned int eqid); 1652 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1653 unsigned int vf, unsigned int eqid); 1654 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1655 unsigned int vf, unsigned int eqid); 1656 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1657 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1658 int t4_update_port_info(struct port_info *pi); 1659 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1660 unsigned int *speedp, unsigned int *mtup); 1661 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1662 void t4_db_full(struct adapter *adapter); 1663 void t4_db_dropped(struct adapter *adapter); 1664 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1665 int filter_index, int enable); 1666 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1667 int filter_index, int *enabled); 1668 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1669 u32 addr, u32 val); 1670 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1671 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1672 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1673 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1674 enum ctxt_type ctype, u32 *data); 1675 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1676 enum ctxt_type ctype, u32 *data); 1677 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1678 int rateunit, int ratemode, int channel, int class, 1679 int minrate, int maxrate, int weight, int pktsize); 1680 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1681 void t4_idma_monitor_init(struct adapter *adapter, 1682 struct sge_idma_monitor_state *idma); 1683 void t4_idma_monitor(struct adapter *adapter, 1684 struct sge_idma_monitor_state *idma, 1685 int hz, int ticks); 1686 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1687 unsigned int naddr, u8 *addr); 1688 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1689 u32 start_index, bool sleep_ok); 1690 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1691 u32 start_index, bool sleep_ok); 1692 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1693 u32 start_index, bool sleep_ok); 1694 1695 void t4_uld_mem_free(struct adapter *adap); 1696 int t4_uld_mem_alloc(struct adapter *adap); 1697 void t4_uld_clean_up(struct adapter *adap); 1698 void t4_register_netevent_notifier(void); 1699 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1700 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1701 unsigned int n, bool unmap); 1702 void free_txq(struct adapter *adap, struct sge_txq *q); 1703 #endif /* __CXGB4_H__ */ 1704