1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/rhashtable.h> 50 #include <linux/etherdevice.h> 51 #include <linux/net_tstamp.h> 52 #include <linux/ptp_clock_kernel.h> 53 #include <linux/ptp_classify.h> 54 #include <linux/crash_dump.h> 55 #include <linux/thermal.h> 56 #include <asm/io.h> 57 #include "t4_chip_type.h" 58 #include "cxgb4_uld.h" 59 60 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 61 extern struct list_head adapter_list; 62 extern struct mutex uld_mutex; 63 64 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 65 * This is the same as calc_tx_descs() for a TSO packet with 66 * nr_frags == MAX_SKB_FRAGS. 67 */ 68 #define ETHTXQ_STOP_THRES \ 69 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 70 71 enum { 72 MAX_NPORTS = 4, /* max # of ports */ 73 SERNUM_LEN = 24, /* Serial # length */ 74 EC_LEN = 16, /* E/C length */ 75 ID_LEN = 16, /* ID length */ 76 PN_LEN = 16, /* Part Number length */ 77 MACADDR_LEN = 12, /* MAC Address length */ 78 }; 79 80 enum { 81 T4_REGMAP_SIZE = (160 * 1024), 82 T5_REGMAP_SIZE = (332 * 1024), 83 }; 84 85 enum { 86 MEM_EDC0, 87 MEM_EDC1, 88 MEM_MC, 89 MEM_MC0 = MEM_MC, 90 MEM_MC1, 91 MEM_HMA, 92 }; 93 94 enum { 95 MEMWIN0_APERTURE = 2048, 96 MEMWIN0_BASE = 0x1b800, 97 MEMWIN1_APERTURE = 32768, 98 MEMWIN1_BASE = 0x28000, 99 MEMWIN1_BASE_T5 = 0x52000, 100 MEMWIN2_APERTURE = 65536, 101 MEMWIN2_BASE = 0x30000, 102 MEMWIN2_APERTURE_T5 = 131072, 103 MEMWIN2_BASE_T5 = 0x60000, 104 }; 105 106 enum dev_master { 107 MASTER_CANT, 108 MASTER_MAY, 109 MASTER_MUST 110 }; 111 112 enum dev_state { 113 DEV_STATE_UNINIT, 114 DEV_STATE_INIT, 115 DEV_STATE_ERR 116 }; 117 118 enum cc_pause { 119 PAUSE_RX = 1 << 0, 120 PAUSE_TX = 1 << 1, 121 PAUSE_AUTONEG = 1 << 2 122 }; 123 124 enum cc_fec { 125 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 126 FEC_RS = 1 << 1, /* Reed-Solomon */ 127 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 128 }; 129 130 struct port_stats { 131 u64 tx_octets; /* total # of octets in good frames */ 132 u64 tx_frames; /* all good frames */ 133 u64 tx_bcast_frames; /* all broadcast frames */ 134 u64 tx_mcast_frames; /* all multicast frames */ 135 u64 tx_ucast_frames; /* all unicast frames */ 136 u64 tx_error_frames; /* all error frames */ 137 138 u64 tx_frames_64; /* # of Tx frames in a particular range */ 139 u64 tx_frames_65_127; 140 u64 tx_frames_128_255; 141 u64 tx_frames_256_511; 142 u64 tx_frames_512_1023; 143 u64 tx_frames_1024_1518; 144 u64 tx_frames_1519_max; 145 146 u64 tx_drop; /* # of dropped Tx frames */ 147 u64 tx_pause; /* # of transmitted pause frames */ 148 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 149 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 150 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 151 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 152 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 153 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 154 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 155 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 156 157 u64 rx_octets; /* total # of octets in good frames */ 158 u64 rx_frames; /* all good frames */ 159 u64 rx_bcast_frames; /* all broadcast frames */ 160 u64 rx_mcast_frames; /* all multicast frames */ 161 u64 rx_ucast_frames; /* all unicast frames */ 162 u64 rx_too_long; /* # of frames exceeding MTU */ 163 u64 rx_jabber; /* # of jabber frames */ 164 u64 rx_fcs_err; /* # of received frames with bad FCS */ 165 u64 rx_len_err; /* # of received frames with length error */ 166 u64 rx_symbol_err; /* symbol errors */ 167 u64 rx_runt; /* # of short frames */ 168 169 u64 rx_frames_64; /* # of Rx frames in a particular range */ 170 u64 rx_frames_65_127; 171 u64 rx_frames_128_255; 172 u64 rx_frames_256_511; 173 u64 rx_frames_512_1023; 174 u64 rx_frames_1024_1518; 175 u64 rx_frames_1519_max; 176 177 u64 rx_pause; /* # of received pause frames */ 178 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 179 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 180 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 181 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 182 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 183 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 184 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 185 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 186 187 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 188 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 189 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 190 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 191 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 192 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 193 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 194 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 195 }; 196 197 struct lb_port_stats { 198 u64 octets; 199 u64 frames; 200 u64 bcast_frames; 201 u64 mcast_frames; 202 u64 ucast_frames; 203 u64 error_frames; 204 205 u64 frames_64; 206 u64 frames_65_127; 207 u64 frames_128_255; 208 u64 frames_256_511; 209 u64 frames_512_1023; 210 u64 frames_1024_1518; 211 u64 frames_1519_max; 212 213 u64 drop; 214 215 u64 ovflow0; 216 u64 ovflow1; 217 u64 ovflow2; 218 u64 ovflow3; 219 u64 trunc0; 220 u64 trunc1; 221 u64 trunc2; 222 u64 trunc3; 223 }; 224 225 struct tp_tcp_stats { 226 u32 tcp_out_rsts; 227 u64 tcp_in_segs; 228 u64 tcp_out_segs; 229 u64 tcp_retrans_segs; 230 }; 231 232 struct tp_usm_stats { 233 u32 frames; 234 u32 drops; 235 u64 octets; 236 }; 237 238 struct tp_fcoe_stats { 239 u32 frames_ddp; 240 u32 frames_drop; 241 u64 octets_ddp; 242 }; 243 244 struct tp_err_stats { 245 u32 mac_in_errs[4]; 246 u32 hdr_in_errs[4]; 247 u32 tcp_in_errs[4]; 248 u32 tnl_cong_drops[4]; 249 u32 ofld_chan_drops[4]; 250 u32 tnl_tx_drops[4]; 251 u32 ofld_vlan_drops[4]; 252 u32 tcp6_in_errs[4]; 253 u32 ofld_no_neigh; 254 u32 ofld_cong_defer; 255 }; 256 257 struct tp_cpl_stats { 258 u32 req[4]; 259 u32 rsp[4]; 260 }; 261 262 struct tp_rdma_stats { 263 u32 rqe_dfr_pkt; 264 u32 rqe_dfr_mod; 265 }; 266 267 struct sge_params { 268 u32 hps; /* host page size for our PF/VF */ 269 u32 eq_qpp; /* egress queues/page for our PF/VF */ 270 u32 iq_qpp; /* egress queues/page for our PF/VF */ 271 }; 272 273 struct tp_params { 274 unsigned int tre; /* log2 of core clocks per TP tick */ 275 unsigned int la_mask; /* what events are recorded by TP LA */ 276 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 277 /* channel map */ 278 279 uint32_t dack_re; /* DACK timer resolution */ 280 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 281 282 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 283 u32 filter_mask; 284 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 285 286 /* cached TP_OUT_CONFIG compressed error vector 287 * and passing outer header info for encapsulated packets. 288 */ 289 int rx_pkt_encap; 290 291 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 292 * subset of the set of fields which may be present in the Compressed 293 * Filter Tuple portion of filters and TCP TCB connections. The 294 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 295 * Since a variable number of fields may or may not be present, their 296 * shifted field positions within the Compressed Filter Tuple may 297 * vary, or not even be present if the field isn't selected in 298 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 299 * places we store their offsets here, or a -1 if the field isn't 300 * present. 301 */ 302 int fcoe_shift; 303 int port_shift; 304 int vnic_shift; 305 int vlan_shift; 306 int tos_shift; 307 int protocol_shift; 308 int ethertype_shift; 309 int macmatch_shift; 310 int matchtype_shift; 311 int frag_shift; 312 313 u64 hash_filter_mask; 314 }; 315 316 struct vpd_params { 317 unsigned int cclk; 318 u8 ec[EC_LEN + 1]; 319 u8 sn[SERNUM_LEN + 1]; 320 u8 id[ID_LEN + 1]; 321 u8 pn[PN_LEN + 1]; 322 u8 na[MACADDR_LEN + 1]; 323 }; 324 325 /* Maximum resources provisioned for a PCI PF. 326 */ 327 struct pf_resources { 328 unsigned int nvi; /* N virtual interfaces */ 329 unsigned int neq; /* N egress Qs */ 330 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 331 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 332 unsigned int niq; /* N ingress Qs */ 333 unsigned int tc; /* PCI-E traffic class */ 334 unsigned int pmask; /* port access rights mask */ 335 unsigned int nexactf; /* N exact MPS filters */ 336 unsigned int r_caps; /* read capabilities */ 337 unsigned int wx_caps; /* write/execute capabilities */ 338 }; 339 340 struct pci_params { 341 unsigned int vpd_cap_addr; 342 unsigned char speed; 343 unsigned char width; 344 }; 345 346 struct devlog_params { 347 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 348 u32 start; /* start of log in firmware memory */ 349 u32 size; /* size of log */ 350 }; 351 352 /* Stores chip specific parameters */ 353 struct arch_specific_params { 354 u8 nchan; 355 u8 pm_stats_cnt; 356 u8 cng_ch_bits_log; /* congestion channel map bits width */ 357 u16 mps_rplc_size; 358 u16 vfcount; 359 u32 sge_fl_db; 360 u16 mps_tcam_size; 361 }; 362 363 struct adapter_params { 364 struct sge_params sge; 365 struct tp_params tp; 366 struct vpd_params vpd; 367 struct pf_resources pfres; 368 struct pci_params pci; 369 struct devlog_params devlog; 370 enum pcie_memwin drv_memwin; 371 372 unsigned int cim_la_size; 373 374 unsigned int sf_size; /* serial flash size in bytes */ 375 unsigned int sf_nsec; /* # of flash sectors */ 376 377 unsigned int fw_vers; /* firmware version */ 378 unsigned int bs_vers; /* bootstrap version */ 379 unsigned int tp_vers; /* TP microcode version */ 380 unsigned int er_vers; /* expansion ROM version */ 381 unsigned int scfg_vers; /* Serial Configuration version */ 382 unsigned int vpd_vers; /* VPD Version */ 383 u8 api_vers[7]; 384 385 unsigned short mtus[NMTUS]; 386 unsigned short a_wnd[NCCTRL_WIN]; 387 unsigned short b_wnd[NCCTRL_WIN]; 388 389 unsigned char nports; /* # of ethernet ports */ 390 unsigned char portvec; 391 enum chip_type chip; /* chip code */ 392 struct arch_specific_params arch; /* chip specific params */ 393 unsigned char offload; 394 unsigned char crypto; /* HW capability for crypto */ 395 unsigned char ethofld; /* QoS support */ 396 397 unsigned char bypass; 398 unsigned char hash_filter; 399 400 unsigned int ofldq_wr_cred; 401 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 402 403 unsigned int nsched_cls; /* number of traffic classes */ 404 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 405 unsigned int max_ird_adapter; /* Max read depth per adapter */ 406 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 407 u8 fw_caps_support; /* 32-bit Port Capabilities */ 408 bool filter2_wr_support; /* FW support for FILTER2_WR */ 409 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 410 411 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 412 * used by the Port 413 */ 414 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 415 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 416 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 417 }; 418 419 /* State needed to monitor the forward progress of SGE Ingress DMA activities 420 * and possible hangs. 421 */ 422 struct sge_idma_monitor_state { 423 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 424 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 425 unsigned int idma_state[2]; /* IDMA Hang detect state */ 426 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 427 unsigned int idma_warn[2]; /* time to warning in HZ */ 428 }; 429 430 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 431 * The access and execute times are signed in order to accommodate negative 432 * error returns. 433 */ 434 struct mbox_cmd { 435 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 436 u64 timestamp; /* OS-dependent timestamp */ 437 u32 seqno; /* sequence number */ 438 s16 access; /* time (ms) to access mailbox */ 439 s16 execute; /* time (ms) to execute */ 440 }; 441 442 struct mbox_cmd_log { 443 unsigned int size; /* number of entries in the log */ 444 unsigned int cursor; /* next position in the log to write */ 445 u32 seqno; /* next sequence number */ 446 /* variable length mailbox command log starts here */ 447 }; 448 449 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 450 * return a pointer to the specified entry. 451 */ 452 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 453 unsigned int entry_idx) 454 { 455 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 456 } 457 458 #include "t4fw_api.h" 459 460 #define FW_VERSION(chip) ( \ 461 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 462 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 463 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 464 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 465 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 466 467 struct fw_info { 468 u8 chip; 469 char *fs_name; 470 char *fw_mod_name; 471 struct fw_hdr fw_hdr; 472 }; 473 474 struct trace_params { 475 u32 data[TRACE_LEN / 4]; 476 u32 mask[TRACE_LEN / 4]; 477 unsigned short snap_len; 478 unsigned short min_len; 479 unsigned char skip_ofst; 480 unsigned char skip_len; 481 unsigned char invert; 482 unsigned char port; 483 }; 484 485 /* Firmware Port Capabilities types. */ 486 487 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 488 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 489 490 enum fw_caps { 491 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 492 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 493 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 494 }; 495 496 struct link_config { 497 fw_port_cap32_t pcaps; /* link capabilities */ 498 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 499 fw_port_cap32_t acaps; /* advertised capabilities */ 500 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 501 502 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 503 unsigned int speed; /* actual link speed (Mb/s) */ 504 505 enum cc_pause requested_fc; /* flow control user has requested */ 506 enum cc_pause fc; /* actual link flow control */ 507 enum cc_pause advertised_fc; /* actual advertised flow control */ 508 509 enum cc_fec requested_fec; /* Forward Error Correction: */ 510 enum cc_fec fec; /* requested and actual in use */ 511 512 unsigned char autoneg; /* autonegotiating? */ 513 514 unsigned char link_ok; /* link up? */ 515 unsigned char link_down_rc; /* link down reason */ 516 517 bool new_module; /* ->OS Transceiver Module inserted */ 518 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 519 }; 520 521 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 522 523 enum { 524 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 525 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 526 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 527 }; 528 529 enum { 530 MAX_TXQ_ENTRIES = 16384, 531 MAX_CTRL_TXQ_ENTRIES = 1024, 532 MAX_RSPQ_ENTRIES = 16384, 533 MAX_RX_BUFFERS = 16384, 534 MIN_TXQ_ENTRIES = 32, 535 MIN_CTRL_TXQ_ENTRIES = 32, 536 MIN_RSPQ_ENTRIES = 128, 537 MIN_FL_ENTRIES = 16 538 }; 539 540 enum { 541 MAX_TXQ_DESC_SIZE = 64, 542 MAX_RXQ_DESC_SIZE = 128, 543 MAX_FL_DESC_SIZE = 8, 544 MAX_CTRL_TXQ_DESC_SIZE = 64, 545 }; 546 547 enum { 548 INGQ_EXTRAS = 2, /* firmware event queue and */ 549 /* forwarded interrupts */ 550 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 551 }; 552 553 enum { 554 PRIV_FLAG_PORT_TX_VM_BIT, 555 }; 556 557 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 558 559 #define PRIV_FLAGS_ADAP 0 560 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 561 562 struct adapter; 563 struct sge_rspq; 564 565 #include "cxgb4_dcb.h" 566 567 #ifdef CONFIG_CHELSIO_T4_FCOE 568 #include "cxgb4_fcoe.h" 569 #endif /* CONFIG_CHELSIO_T4_FCOE */ 570 571 struct port_info { 572 struct adapter *adapter; 573 u16 viid; 574 int xact_addr_filt; /* index of exact MAC address filter */ 575 u16 rss_size; /* size of VI's RSS table slice */ 576 s8 mdio_addr; 577 enum fw_port_type port_type; 578 u8 mod_type; 579 u8 port_id; 580 u8 tx_chan; 581 u8 lport; /* associated offload logical port */ 582 u8 nqsets; /* # of qsets */ 583 u8 first_qset; /* index of first qset */ 584 u8 rss_mode; 585 struct link_config link_cfg; 586 u16 *rss; 587 struct port_stats stats_base; 588 #ifdef CONFIG_CHELSIO_T4_DCB 589 struct port_dcb_info dcb; /* Data Center Bridging support */ 590 #endif 591 #ifdef CONFIG_CHELSIO_T4_FCOE 592 struct cxgb_fcoe fcoe; 593 #endif /* CONFIG_CHELSIO_T4_FCOE */ 594 bool rxtstamp; /* Enable TS */ 595 struct hwtstamp_config tstamp_config; 596 bool ptp_enable; 597 struct sched_table *sched_tbl; 598 u32 eth_flags; 599 600 /* viid and smt fields either returned by fw 601 * or decoded by parsing viid by driver. 602 */ 603 u8 vin; 604 u8 vivld; 605 u8 smt_idx; 606 u8 rx_cchan; 607 608 bool tc_block_shared; 609 }; 610 611 struct dentry; 612 struct work_struct; 613 614 enum { /* adapter flags */ 615 CXGB4_FULL_INIT_DONE = (1 << 0), 616 CXGB4_DEV_ENABLED = (1 << 1), 617 CXGB4_USING_MSI = (1 << 2), 618 CXGB4_USING_MSIX = (1 << 3), 619 CXGB4_FW_OK = (1 << 4), 620 CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 621 CXGB4_USING_SOFT_PARAMS = (1 << 6), 622 CXGB4_MASTER_PF = (1 << 7), 623 CXGB4_FW_OFLD_CONN = (1 << 9), 624 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 625 CXGB4_SHUTTING_DOWN = (1 << 11), 626 CXGB4_SGE_DBQ_TIMER = (1 << 12), 627 }; 628 629 enum { 630 ULP_CRYPTO_LOOKASIDE = 1 << 0, 631 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 632 }; 633 634 struct rx_sw_desc; 635 636 struct sge_fl { /* SGE free-buffer queue state */ 637 unsigned int avail; /* # of available Rx buffers */ 638 unsigned int pend_cred; /* new buffers since last FL DB ring */ 639 unsigned int cidx; /* consumer index */ 640 unsigned int pidx; /* producer index */ 641 unsigned long alloc_failed; /* # of times buffer allocation failed */ 642 unsigned long large_alloc_failed; 643 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 644 unsigned long low; /* # of times momentarily starving */ 645 unsigned long starving; 646 /* RO fields */ 647 unsigned int cntxt_id; /* SGE context id for the free list */ 648 unsigned int size; /* capacity of free list */ 649 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 650 __be64 *desc; /* address of HW Rx descriptor ring */ 651 dma_addr_t addr; /* bus address of HW ring start */ 652 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 653 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 654 }; 655 656 /* A packet gather list */ 657 struct pkt_gl { 658 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 659 struct page_frag frags[MAX_SKB_FRAGS]; 660 void *va; /* virtual address of first byte */ 661 unsigned int nfrags; /* # of fragments */ 662 unsigned int tot_len; /* total length of fragments */ 663 }; 664 665 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 666 const struct pkt_gl *gl); 667 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 668 /* LRO related declarations for ULD */ 669 struct t4_lro_mgr { 670 #define MAX_LRO_SESSIONS 64 671 u8 lro_session_cnt; /* # of sessions to aggregate */ 672 unsigned long lro_pkts; /* # of LRO super packets */ 673 unsigned long lro_merged; /* # of wire packets merged by LRO */ 674 struct sk_buff_head lroq; /* list of aggregated sessions */ 675 }; 676 677 struct sge_rspq { /* state for an SGE response queue */ 678 struct napi_struct napi; 679 const __be64 *cur_desc; /* current descriptor in queue */ 680 unsigned int cidx; /* consumer index */ 681 u8 gen; /* current generation bit */ 682 u8 intr_params; /* interrupt holdoff parameters */ 683 u8 next_intr_params; /* holdoff params for next interrupt */ 684 u8 adaptive_rx; 685 u8 pktcnt_idx; /* interrupt packet threshold */ 686 u8 uld; /* ULD handling this queue */ 687 u8 idx; /* queue index within its group */ 688 int offset; /* offset into current Rx buffer */ 689 u16 cntxt_id; /* SGE context id for the response q */ 690 u16 abs_id; /* absolute SGE id for the response q */ 691 __be64 *desc; /* address of HW response ring */ 692 dma_addr_t phys_addr; /* physical address of the ring */ 693 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 694 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 695 unsigned int iqe_len; /* entry size */ 696 unsigned int size; /* capacity of response queue */ 697 struct adapter *adap; 698 struct net_device *netdev; /* associated net device */ 699 rspq_handler_t handler; 700 rspq_flush_handler_t flush_handler; 701 struct t4_lro_mgr lro_mgr; 702 }; 703 704 struct sge_eth_stats { /* Ethernet queue statistics */ 705 unsigned long pkts; /* # of ethernet packets */ 706 unsigned long lro_pkts; /* # of LRO super packets */ 707 unsigned long lro_merged; /* # of wire packets merged by LRO */ 708 unsigned long rx_cso; /* # of Rx checksum offloads */ 709 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 710 unsigned long rx_drops; /* # of packets dropped due to no mem */ 711 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 712 }; 713 714 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 715 struct sge_rspq rspq; 716 struct sge_fl fl; 717 struct sge_eth_stats stats; 718 struct msix_info *msix; 719 } ____cacheline_aligned_in_smp; 720 721 struct sge_ofld_stats { /* offload queue statistics */ 722 unsigned long pkts; /* # of packets */ 723 unsigned long imm; /* # of immediate-data packets */ 724 unsigned long an; /* # of asynchronous notifications */ 725 unsigned long nomem; /* # of responses deferred due to no mem */ 726 }; 727 728 struct sge_ofld_rxq { /* SW offload Rx queue */ 729 struct sge_rspq rspq; 730 struct sge_fl fl; 731 struct sge_ofld_stats stats; 732 struct msix_info *msix; 733 } ____cacheline_aligned_in_smp; 734 735 struct tx_desc { 736 __be64 flit[8]; 737 }; 738 739 struct ulptx_sgl; 740 741 struct tx_sw_desc { 742 struct sk_buff *skb; /* SKB to free after getting completion */ 743 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 744 }; 745 746 struct sge_txq { 747 unsigned int in_use; /* # of in-use Tx descriptors */ 748 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 749 unsigned int size; /* # of descriptors */ 750 unsigned int cidx; /* SW consumer index */ 751 unsigned int pidx; /* producer index */ 752 unsigned long stops; /* # of times q has been stopped */ 753 unsigned long restarts; /* # of queue restarts */ 754 unsigned int cntxt_id; /* SGE context id for the Tx q */ 755 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 756 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 757 struct sge_qstat *stat; /* queue status entry */ 758 dma_addr_t phys_addr; /* physical address of the ring */ 759 spinlock_t db_lock; 760 int db_disabled; 761 unsigned short db_pidx; 762 unsigned short db_pidx_inc; 763 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 764 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 765 }; 766 767 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 768 struct sge_txq q; 769 struct netdev_queue *txq; /* associated netdev TX queue */ 770 #ifdef CONFIG_CHELSIO_T4_DCB 771 u8 dcb_prio; /* DCB Priority bound to queue */ 772 #endif 773 u8 dbqt; /* SGE Doorbell Queue Timer in use */ 774 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 775 unsigned long tso; /* # of TSO requests */ 776 unsigned long uso; /* # of USO requests */ 777 unsigned long tx_cso; /* # of Tx checksum offloads */ 778 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 779 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 780 } ____cacheline_aligned_in_smp; 781 782 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 783 struct sge_txq q; 784 struct adapter *adap; 785 struct sk_buff_head sendq; /* list of backpressured packets */ 786 struct tasklet_struct qresume_tsk; /* restarts the queue */ 787 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 788 u8 full; /* the Tx ring is full */ 789 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 790 } ____cacheline_aligned_in_smp; 791 792 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 793 struct sge_txq q; 794 struct adapter *adap; 795 struct sk_buff_head sendq; /* list of backpressured packets */ 796 struct tasklet_struct qresume_tsk; /* restarts the queue */ 797 u8 full; /* the Tx ring is full */ 798 } ____cacheline_aligned_in_smp; 799 800 struct sge_uld_rxq_info { 801 char name[IFNAMSIZ]; /* name of ULD driver */ 802 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 803 u16 *rspq_id; /* response queue id's of rxq */ 804 u16 nrxq; /* # of ingress uld queues */ 805 u16 nciq; /* # of completion queues */ 806 u8 uld; /* uld type */ 807 }; 808 809 struct sge_uld_txq_info { 810 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 811 atomic_t users; /* num users */ 812 u16 ntxq; /* # of egress uld queues */ 813 }; 814 815 enum sge_eosw_state { 816 CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 817 CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 818 CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 819 CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 820 CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 821 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 822 }; 823 824 struct sge_eosw_txq { 825 spinlock_t lock; /* Per queue lock to synchronize completions */ 826 enum sge_eosw_state state; /* Current ETHOFLD State */ 827 struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ 828 u32 ndesc; /* Number of descriptors */ 829 u32 pidx; /* Current Producer Index */ 830 u32 last_pidx; /* Last successfully transmitted Producer Index */ 831 u32 cidx; /* Current Consumer Index */ 832 u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 833 u32 flowc_idx; /* Descriptor containing a FLOWC request */ 834 u32 inuse; /* Number of packets held in ring */ 835 836 u32 cred; /* Current available credits */ 837 u32 ncompl; /* # of completions posted */ 838 u32 last_compl; /* # of credits consumed since last completion req */ 839 840 u32 eotid; /* Index into EOTID table in software */ 841 u32 hwtid; /* Hardware EOTID index */ 842 843 u32 hwqid; /* Underlying hardware queue index */ 844 struct net_device *netdev; /* Pointer to netdevice */ 845 struct tasklet_struct qresume_tsk; /* Restarts the queue */ 846 struct completion completion; /* completion for FLOWC rendezvous */ 847 }; 848 849 struct sge_eohw_txq { 850 spinlock_t lock; /* Per queue lock */ 851 struct sge_txq q; /* HW Txq */ 852 struct adapter *adap; /* Backpointer to adapter */ 853 unsigned long tso; /* # of TSO requests */ 854 unsigned long uso; /* # of USO requests */ 855 unsigned long tx_cso; /* # of Tx checksum offloads */ 856 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 857 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 858 }; 859 860 struct sge { 861 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 862 struct sge_eth_txq ptptxq; 863 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 864 865 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 866 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 867 struct sge_uld_rxq_info **uld_rxq_info; 868 struct sge_uld_txq_info **uld_txq_info; 869 870 struct sge_rspq intrq ____cacheline_aligned_in_smp; 871 spinlock_t intrq_lock; 872 873 struct sge_eohw_txq *eohw_txq; 874 struct sge_ofld_rxq *eohw_rxq; 875 876 u16 max_ethqsets; /* # of available Ethernet queue sets */ 877 u16 ethqsets; /* # of active Ethernet queue sets */ 878 u16 ethtxq_rover; /* Tx queue to clean up next */ 879 u16 ofldqsets; /* # of active ofld queue sets */ 880 u16 nqs_per_uld; /* # of Rx queues per ULD */ 881 u16 eoqsets; /* # of ETHOFLD queues */ 882 883 u16 timer_val[SGE_NTIMERS]; 884 u8 counter_val[SGE_NCOUNTERS]; 885 u16 dbqtimer_tick; 886 u16 dbqtimer_val[SGE_NDBQTIMERS]; 887 u32 fl_pg_order; /* large page allocation size */ 888 u32 stat_len; /* length of status page at ring end */ 889 u32 pktshift; /* padding between CPL & packet data */ 890 u32 fl_align; /* response queue message alignment */ 891 u32 fl_starve_thres; /* Free List starvation threshold */ 892 893 struct sge_idma_monitor_state idma_monitor; 894 unsigned int egr_start; 895 unsigned int egr_sz; 896 unsigned int ingr_start; 897 unsigned int ingr_sz; 898 void **egr_map; /* qid->queue egress queue map */ 899 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 900 unsigned long *starving_fl; 901 unsigned long *txq_maperr; 902 unsigned long *blocked_fl; 903 struct timer_list rx_timer; /* refills starving FLs */ 904 struct timer_list tx_timer; /* checks Tx queues */ 905 906 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 907 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 908 }; 909 910 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 911 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 912 913 struct l2t_data; 914 915 #ifdef CONFIG_PCI_IOV 916 917 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 918 * Configuration initialization for T5 only has SR-IOV functionality enabled 919 * on PF0-3 in order to simplify everything. 920 */ 921 #define NUM_OF_PF_WITH_SRIOV 4 922 923 #endif 924 925 struct doorbell_stats { 926 u32 db_drop; 927 u32 db_empty; 928 u32 db_full; 929 }; 930 931 struct hash_mac_addr { 932 struct list_head list; 933 u8 addr[ETH_ALEN]; 934 unsigned int iface_mac; 935 }; 936 937 struct msix_bmap { 938 unsigned long *msix_bmap; 939 unsigned int mapsize; 940 spinlock_t lock; /* lock for acquiring bitmap */ 941 }; 942 943 struct msix_info { 944 unsigned short vec; 945 char desc[IFNAMSIZ + 10]; 946 unsigned int idx; 947 cpumask_var_t aff_mask; 948 }; 949 950 struct vf_info { 951 unsigned char vf_mac_addr[ETH_ALEN]; 952 unsigned int tx_rate; 953 bool pf_set_mac; 954 u16 vlan; 955 int link_state; 956 }; 957 958 enum { 959 HMA_DMA_MAPPED_FLAG = 1 960 }; 961 962 struct hma_data { 963 unsigned char flags; 964 struct sg_table *sgt; 965 dma_addr_t *phy_addr; /* physical address of the page */ 966 }; 967 968 struct mbox_list { 969 struct list_head list; 970 }; 971 972 #if IS_ENABLED(CONFIG_THERMAL) 973 struct ch_thermal { 974 struct thermal_zone_device *tzdev; 975 int trip_temp; 976 int trip_type; 977 }; 978 #endif 979 980 struct mps_entries_ref { 981 struct list_head list; 982 u8 addr[ETH_ALEN]; 983 u8 mask[ETH_ALEN]; 984 u16 idx; 985 refcount_t refcnt; 986 }; 987 988 struct adapter { 989 void __iomem *regs; 990 void __iomem *bar2; 991 u32 t4_bar0; 992 struct pci_dev *pdev; 993 struct device *pdev_dev; 994 const char *name; 995 unsigned int mbox; 996 unsigned int pf; 997 unsigned int flags; 998 unsigned int adap_idx; 999 enum chip_type chip; 1000 u32 eth_flags; 1001 1002 int msg_enable; 1003 __be16 vxlan_port; 1004 u8 vxlan_port_cnt; 1005 __be16 geneve_port; 1006 u8 geneve_port_cnt; 1007 1008 struct adapter_params params; 1009 struct cxgb4_virt_res vres; 1010 unsigned int swintr; 1011 1012 /* MSI-X Info for NIC and OFLD queues */ 1013 struct msix_info *msix_info; 1014 struct msix_bmap msix_bmap; 1015 1016 struct doorbell_stats db_stats; 1017 struct sge sge; 1018 1019 struct net_device *port[MAX_NPORTS]; 1020 u8 chan_map[NCHAN]; /* channel -> port map */ 1021 1022 struct vf_info *vfinfo; 1023 u8 num_vfs; 1024 1025 u32 filter_mode; 1026 unsigned int l2t_start; 1027 unsigned int l2t_end; 1028 struct l2t_data *l2t; 1029 unsigned int clipt_start; 1030 unsigned int clipt_end; 1031 struct clip_tbl *clipt; 1032 unsigned int rawf_start; 1033 unsigned int rawf_cnt; 1034 struct smt_data *smt; 1035 struct cxgb4_uld_info *uld; 1036 void *uld_handle[CXGB4_ULD_MAX]; 1037 unsigned int num_uld; 1038 unsigned int num_ofld_uld; 1039 struct list_head list_node; 1040 struct list_head rcu_node; 1041 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 1042 struct list_head mps_ref; 1043 spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1044 1045 void *iscsi_ppm; 1046 1047 struct tid_info tids; 1048 void **tid_release_head; 1049 spinlock_t tid_release_lock; 1050 struct workqueue_struct *workq; 1051 struct work_struct tid_release_task; 1052 struct work_struct db_full_task; 1053 struct work_struct db_drop_task; 1054 struct work_struct fatal_err_notify_task; 1055 bool tid_release_task_busy; 1056 1057 /* lock for mailbox cmd list */ 1058 spinlock_t mbox_lock; 1059 struct mbox_list mlist; 1060 1061 /* support for mailbox command/reply logging */ 1062 #define T4_OS_LOG_MBOX_CMDS 256 1063 struct mbox_cmd_log *mbox_log; 1064 1065 struct mutex uld_mutex; 1066 1067 struct dentry *debugfs_root; 1068 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1069 bool trace_rss; /* 1 implies that different RSS flit per filter is 1070 * used per filter else if 0 default RSS flit is 1071 * used for all 4 filters. 1072 */ 1073 1074 struct ptp_clock *ptp_clock; 1075 struct ptp_clock_info ptp_clock_info; 1076 struct sk_buff *ptp_tx_skb; 1077 /* ptp lock */ 1078 spinlock_t ptp_lock; 1079 spinlock_t stats_lock; 1080 spinlock_t win0_lock ____cacheline_aligned_in_smp; 1081 1082 /* TC u32 offload */ 1083 struct cxgb4_tc_u32_table *tc_u32; 1084 struct chcr_stats_debug chcr_stats; 1085 1086 /* TC flower offload */ 1087 bool tc_flower_initialized; 1088 struct rhashtable flower_tbl; 1089 struct rhashtable_params flower_ht_params; 1090 struct timer_list flower_stats_timer; 1091 struct work_struct flower_stats_work; 1092 1093 /* Ethtool Dump */ 1094 struct ethtool_dump eth_dump; 1095 1096 /* HMA */ 1097 struct hma_data hma; 1098 1099 struct srq_data *srq; 1100 1101 /* Dump buffer for collecting logs in kdump kernel */ 1102 struct vmcoredd_data vmcoredd; 1103 #if IS_ENABLED(CONFIG_THERMAL) 1104 struct ch_thermal ch_thermal; 1105 #endif 1106 1107 /* TC MQPRIO offload */ 1108 struct cxgb4_tc_mqprio *tc_mqprio; 1109 1110 /* TC MATCHALL classifier offload */ 1111 struct cxgb4_tc_matchall *tc_matchall; 1112 }; 1113 1114 /* Support for "sched-class" command to allow a TX Scheduling Class to be 1115 * programmed with various parameters. 1116 */ 1117 struct ch_sched_params { 1118 s8 type; /* packet or flow */ 1119 union { 1120 struct { 1121 s8 level; /* scheduler hierarchy level */ 1122 s8 mode; /* per-class or per-flow */ 1123 s8 rateunit; /* bit or packet rate */ 1124 s8 ratemode; /* %port relative or kbps absolute */ 1125 s8 channel; /* scheduler channel [0..N] */ 1126 s8 class; /* scheduler class [0..N] */ 1127 s32 minrate; /* minimum rate */ 1128 s32 maxrate; /* maximum rate */ 1129 s16 weight; /* percent weight */ 1130 s16 pktsize; /* average packet size */ 1131 } params; 1132 } u; 1133 }; 1134 1135 enum { 1136 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 1137 }; 1138 1139 enum { 1140 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 1141 SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ 1142 }; 1143 1144 enum { 1145 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1146 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 1147 }; 1148 1149 enum { 1150 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1151 }; 1152 1153 enum { 1154 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1155 }; 1156 1157 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1158 * to be bound to a TX Scheduling Class. 1159 */ 1160 struct ch_sched_queue { 1161 s8 queue; /* queue index */ 1162 s8 class; /* class index */ 1163 }; 1164 1165 /* Support for "sched_flowc" command to allow one or more FLOWC 1166 * to be bound to a TX Scheduling Class. 1167 */ 1168 struct ch_sched_flowc { 1169 s32 tid; /* TID to bind */ 1170 s8 class; /* class index */ 1171 }; 1172 1173 /* Defined bit width of user definable filter tuples 1174 */ 1175 #define ETHTYPE_BITWIDTH 16 1176 #define FRAG_BITWIDTH 1 1177 #define MACIDX_BITWIDTH 9 1178 #define FCOE_BITWIDTH 1 1179 #define IPORT_BITWIDTH 3 1180 #define MATCHTYPE_BITWIDTH 3 1181 #define PROTO_BITWIDTH 8 1182 #define TOS_BITWIDTH 8 1183 #define PF_BITWIDTH 8 1184 #define VF_BITWIDTH 8 1185 #define IVLAN_BITWIDTH 16 1186 #define OVLAN_BITWIDTH 16 1187 #define ENCAP_VNI_BITWIDTH 24 1188 1189 /* Filter matching rules. These consist of a set of ingress packet field 1190 * (value, mask) tuples. The associated ingress packet field matches the 1191 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1192 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1193 * matches an ingress packet when all of the individual individual field 1194 * matching rules are true. 1195 * 1196 * Partial field masks are always valid, however, while it may be easy to 1197 * understand their meanings for some fields (e.g. IP address to match a 1198 * subnet), for others making sensible partial masks is less intuitive (e.g. 1199 * MPS match type) ... 1200 * 1201 * Most of the following data structures are modeled on T4 capabilities. 1202 * Drivers for earlier chips use the subsets which make sense for those chips. 1203 * We really need to come up with a hardware-independent mechanism to 1204 * represent hardware filter capabilities ... 1205 */ 1206 struct ch_filter_tuple { 1207 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1208 * register selects which of these fields will participate in the 1209 * filter match rules -- up to a maximum of 36 bits. Because 1210 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1211 * set of fields. 1212 */ 1213 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1214 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1215 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1216 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1217 uint32_t pfvf_vld:1; /* PF/VF valid */ 1218 uint32_t encap_vld:1; /* Encapsulation valid */ 1219 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1220 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1221 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1222 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1223 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1224 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1225 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1226 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1227 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1228 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1229 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1230 1231 /* Uncompressed header matching field rules. These are always 1232 * available for field rules. 1233 */ 1234 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1235 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1236 uint16_t lport; /* local port */ 1237 uint16_t fport; /* foreign port */ 1238 }; 1239 1240 /* A filter ioctl command. 1241 */ 1242 struct ch_filter_specification { 1243 /* Administrative fields for filter. 1244 */ 1245 uint32_t hitcnts:1; /* count filter hits in TCB */ 1246 uint32_t prio:1; /* filter has priority over active/server */ 1247 1248 /* Fundamental filter typing. This is the one element of filter 1249 * matching that doesn't exist as a (value, mask) tuple. 1250 */ 1251 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1252 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1253 1254 /* Packet dispatch information. Ingress packets which match the 1255 * filter rules will be dropped, passed to the host or switched back 1256 * out as egress packets. 1257 */ 1258 uint32_t action:2; /* drop, pass, switch */ 1259 1260 uint32_t rpttid:1; /* report TID in RSS hash field */ 1261 1262 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1263 uint32_t iq:10; /* ingress queue */ 1264 1265 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1266 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1267 /* 1 => TCB contains IQ ID */ 1268 1269 /* Switch proxy/rewrite fields. An ingress packet which matches a 1270 * filter with "switch" set will be looped back out as an egress 1271 * packet -- potentially with some Ethernet header rewriting. 1272 */ 1273 uint32_t eport:2; /* egress port to switch packet out */ 1274 uint32_t newdmac:1; /* rewrite destination MAC address */ 1275 uint32_t newsmac:1; /* rewrite source MAC address */ 1276 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1277 uint32_t nat_mode:3; /* specify NAT operation mode */ 1278 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1279 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1280 uint16_t vlan; /* VLAN Tag to insert */ 1281 1282 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1283 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1284 u16 nat_lport; /* local port to use after NAT'ing */ 1285 u16 nat_fport; /* foreign port to use after NAT'ing */ 1286 1287 u32 tc_prio; /* TC's filter priority index */ 1288 u64 tc_cookie; /* Unique cookie identifying TC rules */ 1289 1290 /* reservation for future additions */ 1291 u8 rsvd[12]; 1292 1293 /* Filter rule value/mask pairs. 1294 */ 1295 struct ch_filter_tuple val; 1296 struct ch_filter_tuple mask; 1297 }; 1298 1299 enum { 1300 FILTER_PASS = 0, /* default */ 1301 FILTER_DROP, 1302 FILTER_SWITCH 1303 }; 1304 1305 enum { 1306 VLAN_NOCHANGE = 0, /* default */ 1307 VLAN_REMOVE, 1308 VLAN_INSERT, 1309 VLAN_REWRITE 1310 }; 1311 1312 enum { 1313 NAT_MODE_NONE = 0, /* No NAT performed */ 1314 NAT_MODE_DIP, /* NAT on Dst IP */ 1315 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1316 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1317 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1318 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1319 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1320 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1321 }; 1322 1323 /* Host shadow copy of ingress filter entry. This is in host native format 1324 * and doesn't match the ordering or bit order, etc. of the hardware of the 1325 * firmware command. The use of bit-field structure elements is purely to 1326 * remind ourselves of the field size limitations and save memory in the case 1327 * where the filter table is large. 1328 */ 1329 struct filter_entry { 1330 /* Administrative fields for filter. */ 1331 u32 valid:1; /* filter allocated and valid */ 1332 u32 locked:1; /* filter is administratively locked */ 1333 1334 u32 pending:1; /* filter action is pending firmware reply */ 1335 struct filter_ctx *ctx; /* Caller's completion hook */ 1336 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1337 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1338 struct net_device *dev; /* Associated net device */ 1339 u32 tid; /* This will store the actual tid */ 1340 1341 /* The filter itself. Most of this is a straight copy of information 1342 * provided by the extended ioctl(). Some fields are translated to 1343 * internal forms -- for instance the Ingress Queue ID passed in from 1344 * the ioctl() is translated into the Absolute Ingress Queue ID. 1345 */ 1346 struct ch_filter_specification fs; 1347 }; 1348 1349 static inline int is_offload(const struct adapter *adap) 1350 { 1351 return adap->params.offload; 1352 } 1353 1354 static inline int is_hashfilter(const struct adapter *adap) 1355 { 1356 return adap->params.hash_filter; 1357 } 1358 1359 static inline int is_pci_uld(const struct adapter *adap) 1360 { 1361 return adap->params.crypto; 1362 } 1363 1364 static inline int is_uld(const struct adapter *adap) 1365 { 1366 return (adap->params.offload || adap->params.crypto); 1367 } 1368 1369 static inline int is_ethofld(const struct adapter *adap) 1370 { 1371 return adap->params.ethofld; 1372 } 1373 1374 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1375 { 1376 return readl(adap->regs + reg_addr); 1377 } 1378 1379 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1380 { 1381 writel(val, adap->regs + reg_addr); 1382 } 1383 1384 #ifndef readq 1385 static inline u64 readq(const volatile void __iomem *addr) 1386 { 1387 return readl(addr) + ((u64)readl(addr + 4) << 32); 1388 } 1389 1390 static inline void writeq(u64 val, volatile void __iomem *addr) 1391 { 1392 writel(val, addr); 1393 writel(val >> 32, addr + 4); 1394 } 1395 #endif 1396 1397 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1398 { 1399 return readq(adap->regs + reg_addr); 1400 } 1401 1402 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1403 { 1404 writeq(val, adap->regs + reg_addr); 1405 } 1406 1407 /** 1408 * t4_set_hw_addr - store a port's MAC address in SW 1409 * @adapter: the adapter 1410 * @port_idx: the port index 1411 * @hw_addr: the Ethernet address 1412 * 1413 * Store the Ethernet address of the given port in SW. Called by the common 1414 * code when it retrieves a port's Ethernet address from EEPROM. 1415 */ 1416 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1417 u8 hw_addr[]) 1418 { 1419 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1420 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1421 } 1422 1423 /** 1424 * netdev2pinfo - return the port_info structure associated with a net_device 1425 * @dev: the netdev 1426 * 1427 * Return the struct port_info associated with a net_device 1428 */ 1429 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1430 { 1431 return netdev_priv(dev); 1432 } 1433 1434 /** 1435 * adap2pinfo - return the port_info of a port 1436 * @adap: the adapter 1437 * @idx: the port index 1438 * 1439 * Return the port_info structure for the port of the given index. 1440 */ 1441 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1442 { 1443 return netdev_priv(adap->port[idx]); 1444 } 1445 1446 /** 1447 * netdev2adap - return the adapter structure associated with a net_device 1448 * @dev: the netdev 1449 * 1450 * Return the struct adapter associated with a net_device 1451 */ 1452 static inline struct adapter *netdev2adap(const struct net_device *dev) 1453 { 1454 return netdev2pinfo(dev)->adapter; 1455 } 1456 1457 /* Return a version number to identify the type of adapter. The scheme is: 1458 * - bits 0..9: chip version 1459 * - bits 10..15: chip revision 1460 * - bits 16..23: register dump version 1461 */ 1462 static inline unsigned int mk_adap_vers(struct adapter *ap) 1463 { 1464 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1465 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1466 } 1467 1468 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1469 static inline unsigned int qtimer_val(const struct adapter *adap, 1470 const struct sge_rspq *q) 1471 { 1472 unsigned int idx = q->intr_params >> 1; 1473 1474 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1475 } 1476 1477 /* driver version & name used for ethtool_drvinfo */ 1478 extern char cxgb4_driver_name[]; 1479 extern const char cxgb4_driver_version[]; 1480 1481 void t4_os_portmod_changed(struct adapter *adap, int port_id); 1482 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1483 1484 void t4_free_sge_resources(struct adapter *adap); 1485 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1486 irq_handler_t t4_intr_handler(struct adapter *adap); 1487 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1488 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1489 const struct pkt_gl *gl); 1490 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1491 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1492 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1493 struct net_device *dev, int intr_idx, 1494 struct sge_fl *fl, rspq_handler_t hnd, 1495 rspq_flush_handler_t flush_handler, int cong); 1496 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1497 struct net_device *dev, struct netdev_queue *netdevq, 1498 unsigned int iqid, u8 dbqt); 1499 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1500 struct net_device *dev, unsigned int iqid, 1501 unsigned int cmplqid); 1502 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1503 unsigned int cmplqid); 1504 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1505 struct net_device *dev, unsigned int iqid, 1506 unsigned int uld_type); 1507 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 1508 struct net_device *dev, u32 iqid); 1509 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1510 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1511 int t4_sge_init(struct adapter *adap); 1512 void t4_sge_start(struct adapter *adap); 1513 void t4_sge_stop(struct adapter *adap); 1514 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1515 int maxreclaim); 1516 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1517 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1518 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1519 extern int dbfifo_int_thresh; 1520 1521 #define for_each_port(adapter, iter) \ 1522 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1523 1524 static inline int is_bypass(struct adapter *adap) 1525 { 1526 return adap->params.bypass; 1527 } 1528 1529 static inline int is_bypass_device(int device) 1530 { 1531 /* this should be set based upon device capabilities */ 1532 switch (device) { 1533 case 0x440b: 1534 case 0x440c: 1535 return 1; 1536 default: 1537 return 0; 1538 } 1539 } 1540 1541 static inline int is_10gbt_device(int device) 1542 { 1543 /* this should be set based upon device capabilities */ 1544 switch (device) { 1545 case 0x4409: 1546 case 0x4486: 1547 return 1; 1548 1549 default: 1550 return 0; 1551 } 1552 } 1553 1554 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1555 { 1556 return adap->params.vpd.cclk / 1000; 1557 } 1558 1559 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1560 unsigned int us) 1561 { 1562 return (us * adap->params.vpd.cclk) / 1000; 1563 } 1564 1565 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1566 unsigned int ticks) 1567 { 1568 /* add Core Clock / 2 to round ticks to nearest uS */ 1569 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1570 adapter->params.vpd.cclk); 1571 } 1572 1573 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1574 unsigned int ticks) 1575 { 1576 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1577 } 1578 1579 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1580 u32 val); 1581 1582 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1583 int size, void *rpl, bool sleep_ok, int timeout); 1584 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1585 void *rpl, bool sleep_ok); 1586 1587 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1588 const void *cmd, int size, void *rpl, 1589 int timeout) 1590 { 1591 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1592 timeout); 1593 } 1594 1595 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1596 int size, void *rpl) 1597 { 1598 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1599 } 1600 1601 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1602 int size, void *rpl) 1603 { 1604 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1605 } 1606 1607 /** 1608 * hash_mac_addr - return the hash value of a MAC address 1609 * @addr: the 48-bit Ethernet MAC address 1610 * 1611 * Hashes a MAC address according to the hash function used by HW inexact 1612 * (hash) address matching. 1613 */ 1614 static inline int hash_mac_addr(const u8 *addr) 1615 { 1616 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1617 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1618 1619 a ^= b; 1620 a ^= (a >> 12); 1621 a ^= (a >> 6); 1622 return a & 0x3f; 1623 } 1624 1625 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1626 unsigned int cnt); 1627 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1628 unsigned int us, unsigned int cnt, 1629 unsigned int size, unsigned int iqe_size) 1630 { 1631 q->adap = adap; 1632 cxgb4_set_rspq_intr_params(q, us, cnt); 1633 q->iqe_len = iqe_size; 1634 q->size = size; 1635 } 1636 1637 /** 1638 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1639 * @fw_mod_type: the Firmware Mofule Type 1640 * 1641 * Return whether the Firmware Module Type represents a real Transceiver 1642 * Module/Cable Module Type which has been inserted. 1643 */ 1644 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1645 { 1646 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1647 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1648 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1649 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1650 } 1651 1652 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1653 unsigned int data_reg, const u32 *vals, 1654 unsigned int nregs, unsigned int start_idx); 1655 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1656 unsigned int data_reg, u32 *vals, unsigned int nregs, 1657 unsigned int start_idx); 1658 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1659 1660 struct fw_filter_wr; 1661 1662 void t4_intr_enable(struct adapter *adapter); 1663 void t4_intr_disable(struct adapter *adapter); 1664 int t4_slow_intr_handler(struct adapter *adapter); 1665 1666 int t4_wait_dev_ready(void __iomem *regs); 1667 1668 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 1669 struct link_config *lc); 1670 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 1671 unsigned int port, struct link_config *lc, 1672 u8 sleep_ok, int timeout); 1673 1674 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 1675 unsigned int port, struct link_config *lc) 1676 { 1677 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1678 true, FW_CMD_MAX_TIMEOUT); 1679 } 1680 1681 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 1682 unsigned int port, struct link_config *lc) 1683 { 1684 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1685 false, FW_CMD_MAX_TIMEOUT); 1686 } 1687 1688 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1689 1690 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1691 u32 t4_get_util_window(struct adapter *adap); 1692 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1693 1694 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1695 u32 *mem_base, u32 *mem_aperture); 1696 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1697 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1698 int dir); 1699 #define T4_MEMORY_WRITE 0 1700 #define T4_MEMORY_READ 1 1701 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1702 void *buf, int dir); 1703 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1704 u32 len, __be32 *buf) 1705 { 1706 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1707 } 1708 1709 unsigned int t4_get_regs_len(struct adapter *adapter); 1710 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1711 1712 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1713 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1714 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1715 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1716 int t4_get_pfres(struct adapter *adapter); 1717 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1718 unsigned int nwords, u32 *data, int byte_oriented); 1719 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1720 int t4_load_phy_fw(struct adapter *adap, 1721 int win, spinlock_t *lock, 1722 int (*phy_fw_version)(const u8 *, size_t), 1723 const u8 *phy_fw_data, size_t phy_fw_size); 1724 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1725 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1726 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1727 const u8 *fw_data, unsigned int size, int force); 1728 int t4_fl_pkt_align(struct adapter *adap); 1729 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1730 int t4_check_fw_version(struct adapter *adap); 1731 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1732 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1733 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1734 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1735 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1736 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1737 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1738 int t4_get_version_info(struct adapter *adapter); 1739 void t4_dump_version_info(struct adapter *adapter); 1740 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1741 const u8 *fw_data, unsigned int fw_size, 1742 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1743 int t4_prep_adapter(struct adapter *adapter); 1744 int t4_shutdown_adapter(struct adapter *adapter); 1745 1746 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1747 int t4_bar2_sge_qregs(struct adapter *adapter, 1748 unsigned int qid, 1749 enum t4_bar2_qtype qtype, 1750 int user, 1751 u64 *pbar2_qoffset, 1752 unsigned int *pbar2_qid); 1753 1754 unsigned int qtimer_val(const struct adapter *adap, 1755 const struct sge_rspq *q); 1756 1757 int t4_init_devlog_params(struct adapter *adapter); 1758 int t4_init_sge_params(struct adapter *adapter); 1759 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1760 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1761 int t4_init_rss_mode(struct adapter *adap, int mbox); 1762 int t4_init_portinfo(struct port_info *pi, int mbox, 1763 int port, int pf, int vf, u8 mac[]); 1764 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1765 void t4_fatal_err(struct adapter *adapter); 1766 unsigned int t4_chip_rss_size(struct adapter *adapter); 1767 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1768 int start, int n, const u16 *rspq, unsigned int nrspq); 1769 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1770 unsigned int flags); 1771 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1772 unsigned int flags, unsigned int defq); 1773 int t4_read_rss(struct adapter *adapter, u16 *entries); 1774 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1775 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1776 bool sleep_ok); 1777 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1778 u32 *valp, bool sleep_ok); 1779 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1780 u32 *vfl, u32 *vfh, bool sleep_ok); 1781 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1782 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1783 1784 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1785 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1786 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1787 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1788 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1789 size_t n); 1790 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1791 size_t n); 1792 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1793 unsigned int *valp); 1794 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1795 const unsigned int *valp); 1796 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1797 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1798 unsigned int *pif_req_wrptr, 1799 unsigned int *pif_rsp_wrptr); 1800 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1801 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1802 const char *t4_get_port_type_description(enum fw_port_type port_type); 1803 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1804 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1805 struct port_stats *stats, 1806 struct port_stats *offset); 1807 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1808 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1809 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1810 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1811 unsigned int mask, unsigned int val); 1812 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1813 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1814 bool sleep_ok); 1815 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1816 bool sleep_ok); 1817 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1818 bool sleep_ok); 1819 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1820 bool sleep_ok); 1821 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1822 struct tp_tcp_stats *v6, bool sleep_ok); 1823 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1824 struct tp_fcoe_stats *st, bool sleep_ok); 1825 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1826 const unsigned short *alpha, const unsigned short *beta); 1827 1828 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1829 1830 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1831 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1832 1833 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1834 const u8 *addr); 1835 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1836 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1837 1838 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1839 enum dev_master master, enum dev_state *state); 1840 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1841 int t4_early_init(struct adapter *adap, unsigned int mbox); 1842 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1843 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1844 unsigned int cache_line_size); 1845 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1846 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1847 unsigned int vf, unsigned int nparams, const u32 *params, 1848 u32 *val); 1849 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1850 unsigned int vf, unsigned int nparams, const u32 *params, 1851 u32 *val); 1852 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1853 unsigned int vf, unsigned int nparams, const u32 *params, 1854 u32 *val, int rw, bool sleep_ok); 1855 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1856 unsigned int pf, unsigned int vf, 1857 unsigned int nparams, const u32 *params, 1858 const u32 *val, int timeout); 1859 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1860 unsigned int vf, unsigned int nparams, const u32 *params, 1861 const u32 *val); 1862 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1863 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1864 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1865 unsigned int vi, unsigned int cmask, unsigned int pmask, 1866 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1867 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1868 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1869 unsigned int *rss_size, u8 *vivld, u8 *vin); 1870 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1871 unsigned int pf, unsigned int vf, 1872 unsigned int viid); 1873 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1874 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1875 bool sleep_ok); 1876 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1877 const u8 *addr, const u8 *mask, unsigned int idx, 1878 u8 lookup_type, u8 port_id, bool sleep_ok); 1879 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 1880 bool sleep_ok); 1881 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 1882 const u8 *addr, const u8 *mask, unsigned int vni, 1883 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 1884 bool sleep_ok); 1885 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1886 const u8 *addr, const u8 *mask, unsigned int idx, 1887 u8 lookup_type, u8 port_id, bool sleep_ok); 1888 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1889 unsigned int viid, bool free, unsigned int naddr, 1890 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1891 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1892 unsigned int viid, unsigned int naddr, 1893 const u8 **addr, bool sleep_ok); 1894 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1895 int idx, const u8 *addr, bool persist, u8 *smt_idx); 1896 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1897 bool ucast, u64 vec, bool sleep_ok); 1898 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1899 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1900 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1901 struct port_info *pi, 1902 bool rx_en, bool tx_en, bool dcb_en); 1903 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1904 bool rx_en, bool tx_en); 1905 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1906 unsigned int nblinks); 1907 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1908 unsigned int mmd, unsigned int reg, u16 *valp); 1909 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1910 unsigned int mmd, unsigned int reg, u16 val); 1911 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1912 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1913 unsigned int fl0id, unsigned int fl1id); 1914 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1915 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1916 unsigned int fl0id, unsigned int fl1id); 1917 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1918 unsigned int vf, unsigned int eqid); 1919 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1920 unsigned int vf, unsigned int eqid); 1921 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1922 unsigned int vf, unsigned int eqid); 1923 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1924 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 1925 u16 *dbqtimers); 1926 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1927 int t4_update_port_info(struct port_info *pi); 1928 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1929 unsigned int *speedp, unsigned int *mtup); 1930 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1931 void t4_db_full(struct adapter *adapter); 1932 void t4_db_dropped(struct adapter *adapter); 1933 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1934 int filter_index, int enable); 1935 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1936 int filter_index, int *enabled); 1937 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1938 u32 addr, u32 val); 1939 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1940 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1941 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1942 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1943 enum ctxt_type ctype, u32 *data); 1944 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1945 enum ctxt_type ctype, u32 *data); 1946 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1947 int rateunit, int ratemode, int channel, int class, 1948 int minrate, int maxrate, int weight, int pktsize); 1949 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1950 void t4_idma_monitor_init(struct adapter *adapter, 1951 struct sge_idma_monitor_state *idma); 1952 void t4_idma_monitor(struct adapter *adapter, 1953 struct sge_idma_monitor_state *idma, 1954 int hz, int ticks); 1955 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1956 unsigned int naddr, u8 *addr); 1957 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1958 u32 start_index, bool sleep_ok); 1959 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1960 u32 start_index, bool sleep_ok); 1961 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1962 u32 start_index, bool sleep_ok); 1963 1964 void t4_uld_mem_free(struct adapter *adap); 1965 int t4_uld_mem_alloc(struct adapter *adap); 1966 void t4_uld_clean_up(struct adapter *adap); 1967 void t4_register_netevent_notifier(void); 1968 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1969 unsigned int devid, unsigned int offset, 1970 unsigned int len, u8 *buf); 1971 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1972 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1973 unsigned int n, bool unmap); 1974 void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 1975 u32 ndesc); 1976 int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 1977 void cxgb4_ethofld_restart(unsigned long data); 1978 int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 1979 const struct pkt_gl *si); 1980 void free_txq(struct adapter *adap, struct sge_txq *q); 1981 void cxgb4_reclaim_completed_tx(struct adapter *adap, 1982 struct sge_txq *q, bool unmap); 1983 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1984 dma_addr_t *addr); 1985 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1986 void *pos); 1987 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1988 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1989 const dma_addr_t *addr); 1990 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 1991 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 1992 u16 vlan); 1993 int cxgb4_dcb_enabled(const struct net_device *dev); 1994 1995 int cxgb4_thermal_init(struct adapter *adap); 1996 int cxgb4_thermal_remove(struct adapter *adap); 1997 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 1998 cpumask_var_t *aff_mask, int idx); 1999 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 2000 2001 int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 2002 int *tcam_idx, const u8 *addr, 2003 bool persistent, u8 *smt_idx); 2004 2005 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 2006 bool free, unsigned int naddr, 2007 const u8 **addr, u16 *idx, 2008 u64 *hash, bool sleep_ok); 2009 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2010 unsigned int naddr, const u8 **addr, bool sleep_ok); 2011 int cxgb4_init_mps_ref_entries(struct adapter *adap); 2012 void cxgb4_free_mps_ref_entries(struct adapter *adap); 2013 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 2014 const u8 *addr, const u8 *mask, 2015 unsigned int vni, unsigned int vni_mask, 2016 u8 dip_hit, u8 lookup_type, bool sleep_ok); 2017 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 2018 int idx, bool sleep_ok); 2019 int cxgb4_free_raw_mac_filt(struct adapter *adap, 2020 unsigned int viid, 2021 const u8 *addr, 2022 const u8 *mask, 2023 unsigned int idx, 2024 u8 lookup_type, 2025 u8 port_id, 2026 bool sleep_ok); 2027 int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 2028 unsigned int viid, 2029 const u8 *addr, 2030 const u8 *mask, 2031 unsigned int idx, 2032 u8 lookup_type, 2033 u8 port_id, 2034 bool sleep_ok); 2035 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 2036 int *tcam_idx, const u8 *addr, 2037 bool persistent, u8 *smt_idx); 2038 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 2039 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2040 int cxgb_open(struct net_device *dev); 2041 int cxgb_close(struct net_device *dev); 2042 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 2043 void cxgb4_quiesce_rx(struct sge_rspq *q); 2044 #endif /* __CXGB4_H__ */ 2045