1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/rhashtable.h> 50 #include <linux/etherdevice.h> 51 #include <linux/net_tstamp.h> 52 #include <linux/ptp_clock_kernel.h> 53 #include <linux/ptp_classify.h> 54 #include <linux/crash_dump.h> 55 #include <linux/thermal.h> 56 #include <asm/io.h> 57 #include "t4_chip_type.h" 58 #include "cxgb4_uld.h" 59 #include "t4fw_api.h" 60 61 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 62 extern struct list_head adapter_list; 63 extern struct list_head uld_list; 64 extern struct mutex uld_mutex; 65 66 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 67 * This is the same as calc_tx_descs() for a TSO packet with 68 * nr_frags == MAX_SKB_FRAGS. 69 */ 70 #define ETHTXQ_STOP_THRES \ 71 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 72 73 #define FW_PARAM_DEV(param) \ 74 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 75 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 76 77 #define FW_PARAM_PFVF(param) \ 78 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 79 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 80 FW_PARAMS_PARAM_Y_V(0) | \ 81 FW_PARAMS_PARAM_Z_V(0)) 82 83 enum { 84 MAX_NPORTS = 4, /* max # of ports */ 85 SERNUM_LEN = 24, /* Serial # length */ 86 EC_LEN = 16, /* E/C length */ 87 ID_LEN = 16, /* ID length */ 88 PN_LEN = 16, /* Part Number length */ 89 MACADDR_LEN = 12, /* MAC Address length */ 90 }; 91 92 enum { 93 T4_REGMAP_SIZE = (160 * 1024), 94 T5_REGMAP_SIZE = (332 * 1024), 95 }; 96 97 enum { 98 MEM_EDC0, 99 MEM_EDC1, 100 MEM_MC, 101 MEM_MC0 = MEM_MC, 102 MEM_MC1, 103 MEM_HMA, 104 }; 105 106 enum { 107 MEMWIN0_APERTURE = 2048, 108 MEMWIN0_BASE = 0x1b800, 109 MEMWIN1_APERTURE = 32768, 110 MEMWIN1_BASE = 0x28000, 111 MEMWIN1_BASE_T5 = 0x52000, 112 MEMWIN2_APERTURE = 65536, 113 MEMWIN2_BASE = 0x30000, 114 MEMWIN2_APERTURE_T5 = 131072, 115 MEMWIN2_BASE_T5 = 0x60000, 116 }; 117 118 enum dev_master { 119 MASTER_CANT, 120 MASTER_MAY, 121 MASTER_MUST 122 }; 123 124 enum dev_state { 125 DEV_STATE_UNINIT, 126 DEV_STATE_INIT, 127 DEV_STATE_ERR 128 }; 129 130 enum cc_pause { 131 PAUSE_RX = 1 << 0, 132 PAUSE_TX = 1 << 1, 133 PAUSE_AUTONEG = 1 << 2 134 }; 135 136 enum cc_fec { 137 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 138 FEC_RS = 1 << 1, /* Reed-Solomon */ 139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 140 }; 141 142 enum { 143 CXGB4_ETHTOOL_FLASH_FW = 1, 144 CXGB4_ETHTOOL_FLASH_PHY = 2, 145 CXGB4_ETHTOOL_FLASH_BOOT = 3, 146 CXGB4_ETHTOOL_FLASH_BOOTCFG = 4 147 }; 148 149 struct cxgb4_bootcfg_data { 150 __le16 signature; 151 __u8 reserved[2]; 152 }; 153 154 struct cxgb4_pcir_data { 155 __le32 signature; /* Signature. The string "PCIR" */ 156 __le16 vendor_id; /* Vendor Identification */ 157 __le16 device_id; /* Device Identification */ 158 __u8 vital_product[2]; /* Pointer to Vital Product Data */ 159 __u8 length[2]; /* PCIR Data Structure Length */ 160 __u8 revision; /* PCIR Data Structure Revision */ 161 __u8 class_code[3]; /* Class Code */ 162 __u8 image_length[2]; /* Image Length. Multiple of 512B */ 163 __u8 code_revision[2]; /* Revision Level of Code/Data */ 164 __u8 code_type; 165 __u8 indicator; 166 __u8 reserved[2]; 167 }; 168 169 /* BIOS boot headers */ 170 struct cxgb4_pci_exp_rom_header { 171 __le16 signature; /* ROM Signature. Should be 0xaa55 */ 172 __u8 reserved[22]; /* Reserved per processor Architecture data */ 173 __le16 pcir_offset; /* Offset to PCI Data Structure */ 174 }; 175 176 /* Legacy PCI Expansion ROM Header */ 177 struct legacy_pci_rom_hdr { 178 __u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 179 __u8 size512; /* Current Image Size in units of 512 bytes */ 180 __u8 initentry_point[4]; 181 __u8 cksum; /* Checksum computed on the entire Image */ 182 __u8 reserved[16]; /* Reserved */ 183 __le16 pcir_offset; /* Offset to PCI Data Struture */ 184 }; 185 186 #define CXGB4_HDR_CODE1 0x00 187 #define CXGB4_HDR_CODE2 0x03 188 #define CXGB4_HDR_INDI 0x80 189 190 /* BOOT constants */ 191 enum { 192 BOOT_CFG_SIG = 0x4243, 193 BOOT_SIZE_INC = 512, 194 BOOT_SIGNATURE = 0xaa55, 195 BOOT_MIN_SIZE = sizeof(struct cxgb4_pci_exp_rom_header), 196 BOOT_MAX_SIZE = 1024 * BOOT_SIZE_INC, 197 PCIR_SIGNATURE = 0x52494350 198 }; 199 200 struct port_stats { 201 u64 tx_octets; /* total # of octets in good frames */ 202 u64 tx_frames; /* all good frames */ 203 u64 tx_bcast_frames; /* all broadcast frames */ 204 u64 tx_mcast_frames; /* all multicast frames */ 205 u64 tx_ucast_frames; /* all unicast frames */ 206 u64 tx_error_frames; /* all error frames */ 207 208 u64 tx_frames_64; /* # of Tx frames in a particular range */ 209 u64 tx_frames_65_127; 210 u64 tx_frames_128_255; 211 u64 tx_frames_256_511; 212 u64 tx_frames_512_1023; 213 u64 tx_frames_1024_1518; 214 u64 tx_frames_1519_max; 215 216 u64 tx_drop; /* # of dropped Tx frames */ 217 u64 tx_pause; /* # of transmitted pause frames */ 218 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 219 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 220 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 221 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 222 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 223 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 224 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 225 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 226 227 u64 rx_octets; /* total # of octets in good frames */ 228 u64 rx_frames; /* all good frames */ 229 u64 rx_bcast_frames; /* all broadcast frames */ 230 u64 rx_mcast_frames; /* all multicast frames */ 231 u64 rx_ucast_frames; /* all unicast frames */ 232 u64 rx_too_long; /* # of frames exceeding MTU */ 233 u64 rx_jabber; /* # of jabber frames */ 234 u64 rx_fcs_err; /* # of received frames with bad FCS */ 235 u64 rx_len_err; /* # of received frames with length error */ 236 u64 rx_symbol_err; /* symbol errors */ 237 u64 rx_runt; /* # of short frames */ 238 239 u64 rx_frames_64; /* # of Rx frames in a particular range */ 240 u64 rx_frames_65_127; 241 u64 rx_frames_128_255; 242 u64 rx_frames_256_511; 243 u64 rx_frames_512_1023; 244 u64 rx_frames_1024_1518; 245 u64 rx_frames_1519_max; 246 247 u64 rx_pause; /* # of received pause frames */ 248 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 249 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 250 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 251 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 252 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 253 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 254 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 255 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 256 257 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 258 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 259 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 260 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 261 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 262 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 263 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 264 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 265 }; 266 267 struct lb_port_stats { 268 u64 octets; 269 u64 frames; 270 u64 bcast_frames; 271 u64 mcast_frames; 272 u64 ucast_frames; 273 u64 error_frames; 274 275 u64 frames_64; 276 u64 frames_65_127; 277 u64 frames_128_255; 278 u64 frames_256_511; 279 u64 frames_512_1023; 280 u64 frames_1024_1518; 281 u64 frames_1519_max; 282 283 u64 drop; 284 285 u64 ovflow0; 286 u64 ovflow1; 287 u64 ovflow2; 288 u64 ovflow3; 289 u64 trunc0; 290 u64 trunc1; 291 u64 trunc2; 292 u64 trunc3; 293 }; 294 295 struct tp_tcp_stats { 296 u32 tcp_out_rsts; 297 u64 tcp_in_segs; 298 u64 tcp_out_segs; 299 u64 tcp_retrans_segs; 300 }; 301 302 struct tp_usm_stats { 303 u32 frames; 304 u32 drops; 305 u64 octets; 306 }; 307 308 struct tp_fcoe_stats { 309 u32 frames_ddp; 310 u32 frames_drop; 311 u64 octets_ddp; 312 }; 313 314 struct tp_err_stats { 315 u32 mac_in_errs[4]; 316 u32 hdr_in_errs[4]; 317 u32 tcp_in_errs[4]; 318 u32 tnl_cong_drops[4]; 319 u32 ofld_chan_drops[4]; 320 u32 tnl_tx_drops[4]; 321 u32 ofld_vlan_drops[4]; 322 u32 tcp6_in_errs[4]; 323 u32 ofld_no_neigh; 324 u32 ofld_cong_defer; 325 }; 326 327 struct tp_cpl_stats { 328 u32 req[4]; 329 u32 rsp[4]; 330 }; 331 332 struct tp_rdma_stats { 333 u32 rqe_dfr_pkt; 334 u32 rqe_dfr_mod; 335 }; 336 337 struct sge_params { 338 u32 hps; /* host page size for our PF/VF */ 339 u32 eq_qpp; /* egress queues/page for our PF/VF */ 340 u32 iq_qpp; /* egress queues/page for our PF/VF */ 341 }; 342 343 struct tp_params { 344 unsigned int tre; /* log2 of core clocks per TP tick */ 345 unsigned int la_mask; /* what events are recorded by TP LA */ 346 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 347 /* channel map */ 348 349 uint32_t dack_re; /* DACK timer resolution */ 350 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 351 352 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 353 u32 filter_mask; 354 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 355 356 /* cached TP_OUT_CONFIG compressed error vector 357 * and passing outer header info for encapsulated packets. 358 */ 359 int rx_pkt_encap; 360 361 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 362 * subset of the set of fields which may be present in the Compressed 363 * Filter Tuple portion of filters and TCP TCB connections. The 364 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 365 * Since a variable number of fields may or may not be present, their 366 * shifted field positions within the Compressed Filter Tuple may 367 * vary, or not even be present if the field isn't selected in 368 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 369 * places we store their offsets here, or a -1 if the field isn't 370 * present. 371 */ 372 int fcoe_shift; 373 int port_shift; 374 int vnic_shift; 375 int vlan_shift; 376 int tos_shift; 377 int protocol_shift; 378 int ethertype_shift; 379 int macmatch_shift; 380 int matchtype_shift; 381 int frag_shift; 382 383 u64 hash_filter_mask; 384 }; 385 386 struct vpd_params { 387 unsigned int cclk; 388 u8 ec[EC_LEN + 1]; 389 u8 sn[SERNUM_LEN + 1]; 390 u8 id[ID_LEN + 1]; 391 u8 pn[PN_LEN + 1]; 392 u8 na[MACADDR_LEN + 1]; 393 }; 394 395 /* Maximum resources provisioned for a PCI PF. 396 */ 397 struct pf_resources { 398 unsigned int nvi; /* N virtual interfaces */ 399 unsigned int neq; /* N egress Qs */ 400 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 401 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 402 unsigned int niq; /* N ingress Qs */ 403 unsigned int tc; /* PCI-E traffic class */ 404 unsigned int pmask; /* port access rights mask */ 405 unsigned int nexactf; /* N exact MPS filters */ 406 unsigned int r_caps; /* read capabilities */ 407 unsigned int wx_caps; /* write/execute capabilities */ 408 }; 409 410 struct pci_params { 411 unsigned int vpd_cap_addr; 412 unsigned char speed; 413 unsigned char width; 414 }; 415 416 struct devlog_params { 417 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 418 u32 start; /* start of log in firmware memory */ 419 u32 size; /* size of log */ 420 }; 421 422 /* Stores chip specific parameters */ 423 struct arch_specific_params { 424 u8 nchan; 425 u8 pm_stats_cnt; 426 u8 cng_ch_bits_log; /* congestion channel map bits width */ 427 u16 mps_rplc_size; 428 u16 vfcount; 429 u32 sge_fl_db; 430 u16 mps_tcam_size; 431 }; 432 433 struct adapter_params { 434 struct sge_params sge; 435 struct tp_params tp; 436 struct vpd_params vpd; 437 struct pf_resources pfres; 438 struct pci_params pci; 439 struct devlog_params devlog; 440 enum pcie_memwin drv_memwin; 441 442 unsigned int cim_la_size; 443 444 unsigned int sf_size; /* serial flash size in bytes */ 445 unsigned int sf_nsec; /* # of flash sectors */ 446 447 unsigned int fw_vers; /* firmware version */ 448 unsigned int bs_vers; /* bootstrap version */ 449 unsigned int tp_vers; /* TP microcode version */ 450 unsigned int er_vers; /* expansion ROM version */ 451 unsigned int scfg_vers; /* Serial Configuration version */ 452 unsigned int vpd_vers; /* VPD Version */ 453 u8 api_vers[7]; 454 455 unsigned short mtus[NMTUS]; 456 unsigned short a_wnd[NCCTRL_WIN]; 457 unsigned short b_wnd[NCCTRL_WIN]; 458 459 unsigned char nports; /* # of ethernet ports */ 460 unsigned char portvec; 461 enum chip_type chip; /* chip code */ 462 struct arch_specific_params arch; /* chip specific params */ 463 unsigned char offload; 464 unsigned char crypto; /* HW capability for crypto */ 465 unsigned char ethofld; /* QoS support */ 466 467 unsigned char bypass; 468 unsigned char hash_filter; 469 470 unsigned int ofldq_wr_cred; 471 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 472 473 unsigned int nsched_cls; /* number of traffic classes */ 474 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 475 unsigned int max_ird_adapter; /* Max read depth per adapter */ 476 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 477 u8 fw_caps_support; /* 32-bit Port Capabilities */ 478 bool filter2_wr_support; /* FW support for FILTER2_WR */ 479 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 480 481 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 482 * used by the Port 483 */ 484 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 485 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 486 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 487 }; 488 489 /* State needed to monitor the forward progress of SGE Ingress DMA activities 490 * and possible hangs. 491 */ 492 struct sge_idma_monitor_state { 493 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 494 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 495 unsigned int idma_state[2]; /* IDMA Hang detect state */ 496 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 497 unsigned int idma_warn[2]; /* time to warning in HZ */ 498 }; 499 500 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 501 * The access and execute times are signed in order to accommodate negative 502 * error returns. 503 */ 504 struct mbox_cmd { 505 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 506 u64 timestamp; /* OS-dependent timestamp */ 507 u32 seqno; /* sequence number */ 508 s16 access; /* time (ms) to access mailbox */ 509 s16 execute; /* time (ms) to execute */ 510 }; 511 512 struct mbox_cmd_log { 513 unsigned int size; /* number of entries in the log */ 514 unsigned int cursor; /* next position in the log to write */ 515 u32 seqno; /* next sequence number */ 516 /* variable length mailbox command log starts here */ 517 }; 518 519 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 520 * return a pointer to the specified entry. 521 */ 522 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 523 unsigned int entry_idx) 524 { 525 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 526 } 527 528 #define FW_VERSION(chip) ( \ 529 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 530 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 531 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 532 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 533 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 534 535 struct cxgb4_ethtool_lb_test { 536 struct completion completion; 537 int result; 538 int loopback; 539 }; 540 541 struct fw_info { 542 u8 chip; 543 char *fs_name; 544 char *fw_mod_name; 545 struct fw_hdr fw_hdr; 546 }; 547 548 struct trace_params { 549 u32 data[TRACE_LEN / 4]; 550 u32 mask[TRACE_LEN / 4]; 551 unsigned short snap_len; 552 unsigned short min_len; 553 unsigned char skip_ofst; 554 unsigned char skip_len; 555 unsigned char invert; 556 unsigned char port; 557 }; 558 559 struct cxgb4_fw_data { 560 __be32 signature; 561 __u8 reserved[4]; 562 }; 563 564 /* Firmware Port Capabilities types. */ 565 566 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 567 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 568 569 enum fw_caps { 570 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 571 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 572 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 573 }; 574 575 struct link_config { 576 fw_port_cap32_t pcaps; /* link capabilities */ 577 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 578 fw_port_cap32_t acaps; /* advertised capabilities */ 579 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 580 581 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 582 unsigned int speed; /* actual link speed (Mb/s) */ 583 584 enum cc_pause requested_fc; /* flow control user has requested */ 585 enum cc_pause fc; /* actual link flow control */ 586 enum cc_pause advertised_fc; /* actual advertised flow control */ 587 588 enum cc_fec requested_fec; /* Forward Error Correction: */ 589 enum cc_fec fec; /* requested and actual in use */ 590 591 unsigned char autoneg; /* autonegotiating? */ 592 593 unsigned char link_ok; /* link up? */ 594 unsigned char link_down_rc; /* link down reason */ 595 596 bool new_module; /* ->OS Transceiver Module inserted */ 597 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 598 }; 599 600 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 601 602 enum { 603 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 604 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 605 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 606 }; 607 608 enum { 609 MAX_TXQ_ENTRIES = 16384, 610 MAX_CTRL_TXQ_ENTRIES = 1024, 611 MAX_RSPQ_ENTRIES = 16384, 612 MAX_RX_BUFFERS = 16384, 613 MIN_TXQ_ENTRIES = 32, 614 MIN_CTRL_TXQ_ENTRIES = 32, 615 MIN_RSPQ_ENTRIES = 128, 616 MIN_FL_ENTRIES = 16 617 }; 618 619 enum { 620 MAX_TXQ_DESC_SIZE = 64, 621 MAX_RXQ_DESC_SIZE = 128, 622 MAX_FL_DESC_SIZE = 8, 623 MAX_CTRL_TXQ_DESC_SIZE = 64, 624 }; 625 626 enum { 627 INGQ_EXTRAS = 2, /* firmware event queue and */ 628 /* forwarded interrupts */ 629 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 630 }; 631 632 enum { 633 PRIV_FLAG_PORT_TX_VM_BIT, 634 }; 635 636 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 637 638 #define PRIV_FLAGS_ADAP 0 639 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 640 641 struct adapter; 642 struct sge_rspq; 643 644 #include "cxgb4_dcb.h" 645 646 #ifdef CONFIG_CHELSIO_T4_FCOE 647 #include "cxgb4_fcoe.h" 648 #endif /* CONFIG_CHELSIO_T4_FCOE */ 649 650 struct port_info { 651 struct adapter *adapter; 652 u16 viid; 653 int xact_addr_filt; /* index of exact MAC address filter */ 654 u16 rss_size; /* size of VI's RSS table slice */ 655 s8 mdio_addr; 656 enum fw_port_type port_type; 657 u8 mod_type; 658 u8 port_id; 659 u8 tx_chan; 660 u8 lport; /* associated offload logical port */ 661 u8 nqsets; /* # of qsets */ 662 u8 first_qset; /* index of first qset */ 663 u8 rss_mode; 664 struct link_config link_cfg; 665 u16 *rss; 666 struct port_stats stats_base; 667 #ifdef CONFIG_CHELSIO_T4_DCB 668 struct port_dcb_info dcb; /* Data Center Bridging support */ 669 #endif 670 #ifdef CONFIG_CHELSIO_T4_FCOE 671 struct cxgb_fcoe fcoe; 672 #endif /* CONFIG_CHELSIO_T4_FCOE */ 673 bool rxtstamp; /* Enable TS */ 674 struct hwtstamp_config tstamp_config; 675 bool ptp_enable; 676 struct sched_table *sched_tbl; 677 u32 eth_flags; 678 679 /* viid and smt fields either returned by fw 680 * or decoded by parsing viid by driver. 681 */ 682 u8 vin; 683 u8 vivld; 684 u8 smt_idx; 685 u8 rx_cchan; 686 687 bool tc_block_shared; 688 689 /* Mirror VI information */ 690 u16 viid_mirror; 691 u16 nmirrorqsets; 692 u32 vi_mirror_count; 693 struct mutex vi_mirror_mutex; /* Sync access to Mirror VI info */ 694 struct cxgb4_ethtool_lb_test ethtool_lb; 695 }; 696 697 struct dentry; 698 struct work_struct; 699 700 enum { /* adapter flags */ 701 CXGB4_FULL_INIT_DONE = (1 << 0), 702 CXGB4_DEV_ENABLED = (1 << 1), 703 CXGB4_USING_MSI = (1 << 2), 704 CXGB4_USING_MSIX = (1 << 3), 705 CXGB4_FW_OK = (1 << 4), 706 CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 707 CXGB4_USING_SOFT_PARAMS = (1 << 6), 708 CXGB4_MASTER_PF = (1 << 7), 709 CXGB4_FW_OFLD_CONN = (1 << 9), 710 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 711 CXGB4_SHUTTING_DOWN = (1 << 11), 712 CXGB4_SGE_DBQ_TIMER = (1 << 12), 713 }; 714 715 enum { 716 ULP_CRYPTO_LOOKASIDE = 1 << 0, 717 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 718 ULP_CRYPTO_KTLS_INLINE = 1 << 3, 719 }; 720 721 #define CXGB4_MIRROR_RXQ_DEFAULT_DESC_NUM 1024 722 #define CXGB4_MIRROR_RXQ_DEFAULT_DESC_SIZE 64 723 #define CXGB4_MIRROR_RXQ_DEFAULT_INTR_USEC 5 724 #define CXGB4_MIRROR_RXQ_DEFAULT_PKT_CNT 8 725 726 #define CXGB4_MIRROR_FLQ_DEFAULT_DESC_NUM 72 727 728 struct rx_sw_desc; 729 730 struct sge_fl { /* SGE free-buffer queue state */ 731 unsigned int avail; /* # of available Rx buffers */ 732 unsigned int pend_cred; /* new buffers since last FL DB ring */ 733 unsigned int cidx; /* consumer index */ 734 unsigned int pidx; /* producer index */ 735 unsigned long alloc_failed; /* # of times buffer allocation failed */ 736 unsigned long large_alloc_failed; 737 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 738 unsigned long low; /* # of times momentarily starving */ 739 unsigned long starving; 740 /* RO fields */ 741 unsigned int cntxt_id; /* SGE context id for the free list */ 742 unsigned int size; /* capacity of free list */ 743 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 744 __be64 *desc; /* address of HW Rx descriptor ring */ 745 dma_addr_t addr; /* bus address of HW ring start */ 746 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 747 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 748 }; 749 750 /* A packet gather list */ 751 struct pkt_gl { 752 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 753 struct page_frag frags[MAX_SKB_FRAGS]; 754 void *va; /* virtual address of first byte */ 755 unsigned int nfrags; /* # of fragments */ 756 unsigned int tot_len; /* total length of fragments */ 757 }; 758 759 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 760 const struct pkt_gl *gl); 761 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 762 /* LRO related declarations for ULD */ 763 struct t4_lro_mgr { 764 #define MAX_LRO_SESSIONS 64 765 u8 lro_session_cnt; /* # of sessions to aggregate */ 766 unsigned long lro_pkts; /* # of LRO super packets */ 767 unsigned long lro_merged; /* # of wire packets merged by LRO */ 768 struct sk_buff_head lroq; /* list of aggregated sessions */ 769 }; 770 771 struct sge_rspq { /* state for an SGE response queue */ 772 struct napi_struct napi; 773 const __be64 *cur_desc; /* current descriptor in queue */ 774 unsigned int cidx; /* consumer index */ 775 u8 gen; /* current generation bit */ 776 u8 intr_params; /* interrupt holdoff parameters */ 777 u8 next_intr_params; /* holdoff params for next interrupt */ 778 u8 adaptive_rx; 779 u8 pktcnt_idx; /* interrupt packet threshold */ 780 u8 uld; /* ULD handling this queue */ 781 u8 idx; /* queue index within its group */ 782 int offset; /* offset into current Rx buffer */ 783 u16 cntxt_id; /* SGE context id for the response q */ 784 u16 abs_id; /* absolute SGE id for the response q */ 785 __be64 *desc; /* address of HW response ring */ 786 dma_addr_t phys_addr; /* physical address of the ring */ 787 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 788 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 789 unsigned int iqe_len; /* entry size */ 790 unsigned int size; /* capacity of response queue */ 791 struct adapter *adap; 792 struct net_device *netdev; /* associated net device */ 793 rspq_handler_t handler; 794 rspq_flush_handler_t flush_handler; 795 struct t4_lro_mgr lro_mgr; 796 }; 797 798 struct sge_eth_stats { /* Ethernet queue statistics */ 799 unsigned long pkts; /* # of ethernet packets */ 800 unsigned long lro_pkts; /* # of LRO super packets */ 801 unsigned long lro_merged; /* # of wire packets merged by LRO */ 802 unsigned long rx_cso; /* # of Rx checksum offloads */ 803 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 804 unsigned long rx_drops; /* # of packets dropped due to no mem */ 805 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 806 }; 807 808 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 809 struct sge_rspq rspq; 810 struct sge_fl fl; 811 struct sge_eth_stats stats; 812 struct msix_info *msix; 813 } ____cacheline_aligned_in_smp; 814 815 struct sge_ofld_stats { /* offload queue statistics */ 816 unsigned long pkts; /* # of packets */ 817 unsigned long imm; /* # of immediate-data packets */ 818 unsigned long an; /* # of asynchronous notifications */ 819 unsigned long nomem; /* # of responses deferred due to no mem */ 820 }; 821 822 struct sge_ofld_rxq { /* SW offload Rx queue */ 823 struct sge_rspq rspq; 824 struct sge_fl fl; 825 struct sge_ofld_stats stats; 826 struct msix_info *msix; 827 } ____cacheline_aligned_in_smp; 828 829 struct tx_desc { 830 __be64 flit[8]; 831 }; 832 833 struct ulptx_sgl; 834 835 struct tx_sw_desc { 836 struct sk_buff *skb; /* SKB to free after getting completion */ 837 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 838 }; 839 840 struct sge_txq { 841 unsigned int in_use; /* # of in-use Tx descriptors */ 842 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 843 unsigned int size; /* # of descriptors */ 844 unsigned int cidx; /* SW consumer index */ 845 unsigned int pidx; /* producer index */ 846 unsigned long stops; /* # of times q has been stopped */ 847 unsigned long restarts; /* # of queue restarts */ 848 unsigned int cntxt_id; /* SGE context id for the Tx q */ 849 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 850 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 851 struct sge_qstat *stat; /* queue status entry */ 852 dma_addr_t phys_addr; /* physical address of the ring */ 853 spinlock_t db_lock; 854 int db_disabled; 855 unsigned short db_pidx; 856 unsigned short db_pidx_inc; 857 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 858 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 859 }; 860 861 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 862 struct sge_txq q; 863 struct netdev_queue *txq; /* associated netdev TX queue */ 864 #ifdef CONFIG_CHELSIO_T4_DCB 865 u8 dcb_prio; /* DCB Priority bound to queue */ 866 #endif 867 u8 dbqt; /* SGE Doorbell Queue Timer in use */ 868 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 869 unsigned long tso; /* # of TSO requests */ 870 unsigned long uso; /* # of USO requests */ 871 unsigned long tx_cso; /* # of Tx checksum offloads */ 872 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 873 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 874 } ____cacheline_aligned_in_smp; 875 876 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 877 struct sge_txq q; 878 struct adapter *adap; 879 struct sk_buff_head sendq; /* list of backpressured packets */ 880 struct tasklet_struct qresume_tsk; /* restarts the queue */ 881 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 882 u8 full; /* the Tx ring is full */ 883 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 884 } ____cacheline_aligned_in_smp; 885 886 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 887 struct sge_txq q; 888 struct adapter *adap; 889 struct sk_buff_head sendq; /* list of backpressured packets */ 890 struct tasklet_struct qresume_tsk; /* restarts the queue */ 891 u8 full; /* the Tx ring is full */ 892 } ____cacheline_aligned_in_smp; 893 894 struct sge_uld_rxq_info { 895 char name[IFNAMSIZ]; /* name of ULD driver */ 896 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 897 u16 *rspq_id; /* response queue id's of rxq */ 898 u16 nrxq; /* # of ingress uld queues */ 899 u16 nciq; /* # of completion queues */ 900 u8 uld; /* uld type */ 901 }; 902 903 struct sge_uld_txq_info { 904 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 905 atomic_t users; /* num users */ 906 u16 ntxq; /* # of egress uld queues */ 907 }; 908 909 /* struct to maintain ULD list to reallocate ULD resources on hotplug */ 910 struct cxgb4_uld_list { 911 struct cxgb4_uld_info uld_info; 912 struct list_head list_node; 913 enum cxgb4_uld uld_type; 914 }; 915 916 enum sge_eosw_state { 917 CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 918 CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 919 CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 920 CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 921 CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 922 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 923 }; 924 925 struct sge_eosw_txq { 926 spinlock_t lock; /* Per queue lock to synchronize completions */ 927 enum sge_eosw_state state; /* Current ETHOFLD State */ 928 struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ 929 u32 ndesc; /* Number of descriptors */ 930 u32 pidx; /* Current Producer Index */ 931 u32 last_pidx; /* Last successfully transmitted Producer Index */ 932 u32 cidx; /* Current Consumer Index */ 933 u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 934 u32 flowc_idx; /* Descriptor containing a FLOWC request */ 935 u32 inuse; /* Number of packets held in ring */ 936 937 u32 cred; /* Current available credits */ 938 u32 ncompl; /* # of completions posted */ 939 u32 last_compl; /* # of credits consumed since last completion req */ 940 941 u32 eotid; /* Index into EOTID table in software */ 942 u32 hwtid; /* Hardware EOTID index */ 943 944 u32 hwqid; /* Underlying hardware queue index */ 945 struct net_device *netdev; /* Pointer to netdevice */ 946 struct tasklet_struct qresume_tsk; /* Restarts the queue */ 947 struct completion completion; /* completion for FLOWC rendezvous */ 948 }; 949 950 struct sge_eohw_txq { 951 spinlock_t lock; /* Per queue lock */ 952 struct sge_txq q; /* HW Txq */ 953 struct adapter *adap; /* Backpointer to adapter */ 954 unsigned long tso; /* # of TSO requests */ 955 unsigned long uso; /* # of USO requests */ 956 unsigned long tx_cso; /* # of Tx checksum offloads */ 957 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 958 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 959 }; 960 961 struct sge { 962 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 963 struct sge_eth_txq ptptxq; 964 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 965 966 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 967 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 968 struct sge_uld_rxq_info **uld_rxq_info; 969 struct sge_uld_txq_info **uld_txq_info; 970 971 struct sge_rspq intrq ____cacheline_aligned_in_smp; 972 spinlock_t intrq_lock; 973 974 struct sge_eohw_txq *eohw_txq; 975 struct sge_ofld_rxq *eohw_rxq; 976 977 struct sge_eth_rxq *mirror_rxq[NCHAN]; 978 979 u16 max_ethqsets; /* # of available Ethernet queue sets */ 980 u16 ethqsets; /* # of active Ethernet queue sets */ 981 u16 ethtxq_rover; /* Tx queue to clean up next */ 982 u16 ofldqsets; /* # of active ofld queue sets */ 983 u16 nqs_per_uld; /* # of Rx queues per ULD */ 984 u16 eoqsets; /* # of ETHOFLD queues */ 985 u16 mirrorqsets; /* # of Mirror queues */ 986 987 u16 timer_val[SGE_NTIMERS]; 988 u8 counter_val[SGE_NCOUNTERS]; 989 u16 dbqtimer_tick; 990 u16 dbqtimer_val[SGE_NDBQTIMERS]; 991 u32 fl_pg_order; /* large page allocation size */ 992 u32 stat_len; /* length of status page at ring end */ 993 u32 pktshift; /* padding between CPL & packet data */ 994 u32 fl_align; /* response queue message alignment */ 995 u32 fl_starve_thres; /* Free List starvation threshold */ 996 997 struct sge_idma_monitor_state idma_monitor; 998 unsigned int egr_start; 999 unsigned int egr_sz; 1000 unsigned int ingr_start; 1001 unsigned int ingr_sz; 1002 void **egr_map; /* qid->queue egress queue map */ 1003 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 1004 unsigned long *starving_fl; 1005 unsigned long *txq_maperr; 1006 unsigned long *blocked_fl; 1007 struct timer_list rx_timer; /* refills starving FLs */ 1008 struct timer_list tx_timer; /* checks Tx queues */ 1009 1010 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 1011 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 1012 }; 1013 1014 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 1015 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 1016 1017 struct l2t_data; 1018 1019 #ifdef CONFIG_PCI_IOV 1020 1021 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 1022 * Configuration initialization for T5 only has SR-IOV functionality enabled 1023 * on PF0-3 in order to simplify everything. 1024 */ 1025 #define NUM_OF_PF_WITH_SRIOV 4 1026 1027 #endif 1028 1029 struct doorbell_stats { 1030 u32 db_drop; 1031 u32 db_empty; 1032 u32 db_full; 1033 }; 1034 1035 struct hash_mac_addr { 1036 struct list_head list; 1037 u8 addr[ETH_ALEN]; 1038 unsigned int iface_mac; 1039 }; 1040 1041 struct msix_bmap { 1042 unsigned long *msix_bmap; 1043 unsigned int mapsize; 1044 spinlock_t lock; /* lock for acquiring bitmap */ 1045 }; 1046 1047 struct msix_info { 1048 unsigned short vec; 1049 char desc[IFNAMSIZ + 10]; 1050 unsigned int idx; 1051 cpumask_var_t aff_mask; 1052 }; 1053 1054 struct vf_info { 1055 unsigned char vf_mac_addr[ETH_ALEN]; 1056 unsigned int tx_rate; 1057 bool pf_set_mac; 1058 u16 vlan; 1059 int link_state; 1060 }; 1061 1062 enum { 1063 HMA_DMA_MAPPED_FLAG = 1 1064 }; 1065 1066 struct hma_data { 1067 unsigned char flags; 1068 struct sg_table *sgt; 1069 dma_addr_t *phy_addr; /* physical address of the page */ 1070 }; 1071 1072 struct mbox_list { 1073 struct list_head list; 1074 }; 1075 1076 #if IS_ENABLED(CONFIG_THERMAL) 1077 struct ch_thermal { 1078 struct thermal_zone_device *tzdev; 1079 int trip_temp; 1080 int trip_type; 1081 }; 1082 #endif 1083 1084 struct mps_entries_ref { 1085 struct list_head list; 1086 u8 addr[ETH_ALEN]; 1087 u8 mask[ETH_ALEN]; 1088 u16 idx; 1089 refcount_t refcnt; 1090 }; 1091 1092 struct cxgb4_ethtool_filter_info { 1093 u32 *loc_array; /* Array holding the actual TIDs set to filters */ 1094 unsigned long *bmap; /* Bitmap for managing filters in use */ 1095 u32 in_use; /* # of filters in use */ 1096 }; 1097 1098 struct cxgb4_ethtool_filter { 1099 u32 nentries; /* Adapter wide number of supported filters */ 1100 struct cxgb4_ethtool_filter_info *port; /* Per port entry */ 1101 }; 1102 1103 struct adapter { 1104 void __iomem *regs; 1105 void __iomem *bar2; 1106 u32 t4_bar0; 1107 struct pci_dev *pdev; 1108 struct device *pdev_dev; 1109 const char *name; 1110 unsigned int mbox; 1111 unsigned int pf; 1112 unsigned int flags; 1113 unsigned int adap_idx; 1114 enum chip_type chip; 1115 u32 eth_flags; 1116 1117 int msg_enable; 1118 __be16 vxlan_port; 1119 __be16 geneve_port; 1120 1121 struct adapter_params params; 1122 struct cxgb4_virt_res vres; 1123 unsigned int swintr; 1124 1125 /* MSI-X Info for NIC and OFLD queues */ 1126 struct msix_info *msix_info; 1127 struct msix_bmap msix_bmap; 1128 1129 struct doorbell_stats db_stats; 1130 struct sge sge; 1131 1132 struct net_device *port[MAX_NPORTS]; 1133 u8 chan_map[NCHAN]; /* channel -> port map */ 1134 1135 struct vf_info *vfinfo; 1136 u8 num_vfs; 1137 1138 u32 filter_mode; 1139 unsigned int l2t_start; 1140 unsigned int l2t_end; 1141 struct l2t_data *l2t; 1142 unsigned int clipt_start; 1143 unsigned int clipt_end; 1144 struct clip_tbl *clipt; 1145 unsigned int rawf_start; 1146 unsigned int rawf_cnt; 1147 struct smt_data *smt; 1148 struct cxgb4_uld_info *uld; 1149 void *uld_handle[CXGB4_ULD_MAX]; 1150 unsigned int num_uld; 1151 unsigned int num_ofld_uld; 1152 struct list_head list_node; 1153 struct list_head rcu_node; 1154 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 1155 struct list_head mps_ref; 1156 spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1157 1158 void *iscsi_ppm; 1159 1160 struct tid_info tids; 1161 void **tid_release_head; 1162 spinlock_t tid_release_lock; 1163 struct workqueue_struct *workq; 1164 struct work_struct tid_release_task; 1165 struct work_struct db_full_task; 1166 struct work_struct db_drop_task; 1167 struct work_struct fatal_err_notify_task; 1168 bool tid_release_task_busy; 1169 1170 /* lock for mailbox cmd list */ 1171 spinlock_t mbox_lock; 1172 struct mbox_list mlist; 1173 1174 /* support for mailbox command/reply logging */ 1175 #define T4_OS_LOG_MBOX_CMDS 256 1176 struct mbox_cmd_log *mbox_log; 1177 1178 struct mutex uld_mutex; 1179 1180 struct dentry *debugfs_root; 1181 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1182 bool trace_rss; /* 1 implies that different RSS flit per filter is 1183 * used per filter else if 0 default RSS flit is 1184 * used for all 4 filters. 1185 */ 1186 1187 struct ptp_clock *ptp_clock; 1188 struct ptp_clock_info ptp_clock_info; 1189 struct sk_buff *ptp_tx_skb; 1190 /* ptp lock */ 1191 spinlock_t ptp_lock; 1192 spinlock_t stats_lock; 1193 spinlock_t win0_lock ____cacheline_aligned_in_smp; 1194 1195 /* TC u32 offload */ 1196 struct cxgb4_tc_u32_table *tc_u32; 1197 struct chcr_ktls chcr_ktls; 1198 struct chcr_stats_debug chcr_stats; 1199 1200 /* TC flower offload */ 1201 bool tc_flower_initialized; 1202 struct rhashtable flower_tbl; 1203 struct rhashtable_params flower_ht_params; 1204 struct timer_list flower_stats_timer; 1205 struct work_struct flower_stats_work; 1206 1207 /* Ethtool Dump */ 1208 struct ethtool_dump eth_dump; 1209 1210 /* HMA */ 1211 struct hma_data hma; 1212 1213 struct srq_data *srq; 1214 1215 /* Dump buffer for collecting logs in kdump kernel */ 1216 struct vmcoredd_data vmcoredd; 1217 #if IS_ENABLED(CONFIG_THERMAL) 1218 struct ch_thermal ch_thermal; 1219 #endif 1220 1221 /* TC MQPRIO offload */ 1222 struct cxgb4_tc_mqprio *tc_mqprio; 1223 1224 /* TC MATCHALL classifier offload */ 1225 struct cxgb4_tc_matchall *tc_matchall; 1226 1227 /* Ethtool n-tuple */ 1228 struct cxgb4_ethtool_filter *ethtool_filters; 1229 }; 1230 1231 /* Support for "sched-class" command to allow a TX Scheduling Class to be 1232 * programmed with various parameters. 1233 */ 1234 struct ch_sched_params { 1235 u8 type; /* packet or flow */ 1236 union { 1237 struct { 1238 u8 level; /* scheduler hierarchy level */ 1239 u8 mode; /* per-class or per-flow */ 1240 u8 rateunit; /* bit or packet rate */ 1241 u8 ratemode; /* %port relative or kbps absolute */ 1242 u8 channel; /* scheduler channel [0..N] */ 1243 u8 class; /* scheduler class [0..N] */ 1244 u32 minrate; /* minimum rate */ 1245 u32 maxrate; /* maximum rate */ 1246 u16 weight; /* percent weight */ 1247 u16 pktsize; /* average packet size */ 1248 u16 burstsize; /* burst buffer size */ 1249 } params; 1250 } u; 1251 }; 1252 1253 enum { 1254 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 1255 }; 1256 1257 enum { 1258 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 1259 SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ 1260 }; 1261 1262 enum { 1263 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1264 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 1265 }; 1266 1267 enum { 1268 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1269 }; 1270 1271 enum { 1272 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1273 }; 1274 1275 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1276 * to be bound to a TX Scheduling Class. 1277 */ 1278 struct ch_sched_queue { 1279 s8 queue; /* queue index */ 1280 s8 class; /* class index */ 1281 }; 1282 1283 /* Support for "sched_flowc" command to allow one or more FLOWC 1284 * to be bound to a TX Scheduling Class. 1285 */ 1286 struct ch_sched_flowc { 1287 s32 tid; /* TID to bind */ 1288 s8 class; /* class index */ 1289 }; 1290 1291 /* Defined bit width of user definable filter tuples 1292 */ 1293 #define ETHTYPE_BITWIDTH 16 1294 #define FRAG_BITWIDTH 1 1295 #define MACIDX_BITWIDTH 9 1296 #define FCOE_BITWIDTH 1 1297 #define IPORT_BITWIDTH 3 1298 #define MATCHTYPE_BITWIDTH 3 1299 #define PROTO_BITWIDTH 8 1300 #define TOS_BITWIDTH 8 1301 #define PF_BITWIDTH 8 1302 #define VF_BITWIDTH 8 1303 #define IVLAN_BITWIDTH 16 1304 #define OVLAN_BITWIDTH 16 1305 #define ENCAP_VNI_BITWIDTH 24 1306 1307 /* Filter matching rules. These consist of a set of ingress packet field 1308 * (value, mask) tuples. The associated ingress packet field matches the 1309 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1310 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1311 * matches an ingress packet when all of the individual individual field 1312 * matching rules are true. 1313 * 1314 * Partial field masks are always valid, however, while it may be easy to 1315 * understand their meanings for some fields (e.g. IP address to match a 1316 * subnet), for others making sensible partial masks is less intuitive (e.g. 1317 * MPS match type) ... 1318 * 1319 * Most of the following data structures are modeled on T4 capabilities. 1320 * Drivers for earlier chips use the subsets which make sense for those chips. 1321 * We really need to come up with a hardware-independent mechanism to 1322 * represent hardware filter capabilities ... 1323 */ 1324 struct ch_filter_tuple { 1325 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1326 * register selects which of these fields will participate in the 1327 * filter match rules -- up to a maximum of 36 bits. Because 1328 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1329 * set of fields. 1330 */ 1331 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1332 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1333 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1334 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1335 uint32_t pfvf_vld:1; /* PF/VF valid */ 1336 uint32_t encap_vld:1; /* Encapsulation valid */ 1337 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1338 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1339 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1340 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1341 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1342 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1343 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1344 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1345 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1346 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1347 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1348 1349 /* Uncompressed header matching field rules. These are always 1350 * available for field rules. 1351 */ 1352 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1353 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1354 uint16_t lport; /* local port */ 1355 uint16_t fport; /* foreign port */ 1356 }; 1357 1358 /* A filter ioctl command. 1359 */ 1360 struct ch_filter_specification { 1361 /* Administrative fields for filter. 1362 */ 1363 uint32_t hitcnts:1; /* count filter hits in TCB */ 1364 uint32_t prio:1; /* filter has priority over active/server */ 1365 1366 /* Fundamental filter typing. This is the one element of filter 1367 * matching that doesn't exist as a (value, mask) tuple. 1368 */ 1369 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1370 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1371 1372 /* Packet dispatch information. Ingress packets which match the 1373 * filter rules will be dropped, passed to the host or switched back 1374 * out as egress packets. 1375 */ 1376 uint32_t action:2; /* drop, pass, switch */ 1377 1378 uint32_t rpttid:1; /* report TID in RSS hash field */ 1379 1380 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1381 uint32_t iq:10; /* ingress queue */ 1382 1383 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1384 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1385 /* 1 => TCB contains IQ ID */ 1386 1387 /* Switch proxy/rewrite fields. An ingress packet which matches a 1388 * filter with "switch" set will be looped back out as an egress 1389 * packet -- potentially with some Ethernet header rewriting. 1390 */ 1391 uint32_t eport:2; /* egress port to switch packet out */ 1392 uint32_t newdmac:1; /* rewrite destination MAC address */ 1393 uint32_t newsmac:1; /* rewrite source MAC address */ 1394 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1395 uint32_t nat_mode:3; /* specify NAT operation mode */ 1396 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1397 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1398 uint16_t vlan; /* VLAN Tag to insert */ 1399 1400 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1401 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1402 u16 nat_lport; /* local port to use after NAT'ing */ 1403 u16 nat_fport; /* foreign port to use after NAT'ing */ 1404 1405 u32 tc_prio; /* TC's filter priority index */ 1406 u64 tc_cookie; /* Unique cookie identifying TC rules */ 1407 1408 /* reservation for future additions */ 1409 u8 rsvd[12]; 1410 1411 /* Filter rule value/mask pairs. 1412 */ 1413 struct ch_filter_tuple val; 1414 struct ch_filter_tuple mask; 1415 }; 1416 1417 enum { 1418 FILTER_PASS = 0, /* default */ 1419 FILTER_DROP, 1420 FILTER_SWITCH 1421 }; 1422 1423 enum { 1424 VLAN_NOCHANGE = 0, /* default */ 1425 VLAN_REMOVE, 1426 VLAN_INSERT, 1427 VLAN_REWRITE 1428 }; 1429 1430 enum { 1431 NAT_MODE_NONE = 0, /* No NAT performed */ 1432 NAT_MODE_DIP, /* NAT on Dst IP */ 1433 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1434 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1435 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1436 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1437 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1438 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1439 }; 1440 1441 #define CXGB4_FILTER_TYPE_MAX 2 1442 1443 /* Host shadow copy of ingress filter entry. This is in host native format 1444 * and doesn't match the ordering or bit order, etc. of the hardware of the 1445 * firmware command. The use of bit-field structure elements is purely to 1446 * remind ourselves of the field size limitations and save memory in the case 1447 * where the filter table is large. 1448 */ 1449 struct filter_entry { 1450 /* Administrative fields for filter. */ 1451 u32 valid:1; /* filter allocated and valid */ 1452 u32 locked:1; /* filter is administratively locked */ 1453 1454 u32 pending:1; /* filter action is pending firmware reply */ 1455 struct filter_ctx *ctx; /* Caller's completion hook */ 1456 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1457 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1458 struct net_device *dev; /* Associated net device */ 1459 u32 tid; /* This will store the actual tid */ 1460 1461 /* The filter itself. Most of this is a straight copy of information 1462 * provided by the extended ioctl(). Some fields are translated to 1463 * internal forms -- for instance the Ingress Queue ID passed in from 1464 * the ioctl() is translated into the Absolute Ingress Queue ID. 1465 */ 1466 struct ch_filter_specification fs; 1467 }; 1468 1469 static inline int is_offload(const struct adapter *adap) 1470 { 1471 return adap->params.offload; 1472 } 1473 1474 static inline int is_hashfilter(const struct adapter *adap) 1475 { 1476 return adap->params.hash_filter; 1477 } 1478 1479 static inline int is_pci_uld(const struct adapter *adap) 1480 { 1481 return adap->params.crypto; 1482 } 1483 1484 static inline int is_uld(const struct adapter *adap) 1485 { 1486 return (adap->params.offload || adap->params.crypto); 1487 } 1488 1489 static inline int is_ethofld(const struct adapter *adap) 1490 { 1491 return adap->params.ethofld; 1492 } 1493 1494 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1495 { 1496 return readl(adap->regs + reg_addr); 1497 } 1498 1499 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1500 { 1501 writel(val, adap->regs + reg_addr); 1502 } 1503 1504 #ifndef readq 1505 static inline u64 readq(const volatile void __iomem *addr) 1506 { 1507 return readl(addr) + ((u64)readl(addr + 4) << 32); 1508 } 1509 1510 static inline void writeq(u64 val, volatile void __iomem *addr) 1511 { 1512 writel(val, addr); 1513 writel(val >> 32, addr + 4); 1514 } 1515 #endif 1516 1517 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1518 { 1519 return readq(adap->regs + reg_addr); 1520 } 1521 1522 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1523 { 1524 writeq(val, adap->regs + reg_addr); 1525 } 1526 1527 /** 1528 * t4_set_hw_addr - store a port's MAC address in SW 1529 * @adapter: the adapter 1530 * @port_idx: the port index 1531 * @hw_addr: the Ethernet address 1532 * 1533 * Store the Ethernet address of the given port in SW. Called by the common 1534 * code when it retrieves a port's Ethernet address from EEPROM. 1535 */ 1536 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1537 u8 hw_addr[]) 1538 { 1539 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1540 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1541 } 1542 1543 /** 1544 * netdev2pinfo - return the port_info structure associated with a net_device 1545 * @dev: the netdev 1546 * 1547 * Return the struct port_info associated with a net_device 1548 */ 1549 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1550 { 1551 return netdev_priv(dev); 1552 } 1553 1554 /** 1555 * adap2pinfo - return the port_info of a port 1556 * @adap: the adapter 1557 * @idx: the port index 1558 * 1559 * Return the port_info structure for the port of the given index. 1560 */ 1561 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1562 { 1563 return netdev_priv(adap->port[idx]); 1564 } 1565 1566 /** 1567 * netdev2adap - return the adapter structure associated with a net_device 1568 * @dev: the netdev 1569 * 1570 * Return the struct adapter associated with a net_device 1571 */ 1572 static inline struct adapter *netdev2adap(const struct net_device *dev) 1573 { 1574 return netdev2pinfo(dev)->adapter; 1575 } 1576 1577 /* Return a version number to identify the type of adapter. The scheme is: 1578 * - bits 0..9: chip version 1579 * - bits 10..15: chip revision 1580 * - bits 16..23: register dump version 1581 */ 1582 static inline unsigned int mk_adap_vers(struct adapter *ap) 1583 { 1584 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1585 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1586 } 1587 1588 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1589 static inline unsigned int qtimer_val(const struct adapter *adap, 1590 const struct sge_rspq *q) 1591 { 1592 unsigned int idx = q->intr_params >> 1; 1593 1594 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1595 } 1596 1597 /* driver name used for ethtool_drvinfo */ 1598 extern char cxgb4_driver_name[]; 1599 1600 void t4_os_portmod_changed(struct adapter *adap, int port_id); 1601 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1602 1603 void t4_free_sge_resources(struct adapter *adap); 1604 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1605 irq_handler_t t4_intr_handler(struct adapter *adap); 1606 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1607 int cxgb4_selftest_lb_pkt(struct net_device *netdev); 1608 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1609 const struct pkt_gl *gl); 1610 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1611 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1612 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1613 struct net_device *dev, int intr_idx, 1614 struct sge_fl *fl, rspq_handler_t hnd, 1615 rspq_flush_handler_t flush_handler, int cong); 1616 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1617 struct net_device *dev, struct netdev_queue *netdevq, 1618 unsigned int iqid, u8 dbqt); 1619 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1620 struct net_device *dev, unsigned int iqid, 1621 unsigned int cmplqid); 1622 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1623 unsigned int cmplqid); 1624 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1625 struct net_device *dev, unsigned int iqid, 1626 unsigned int uld_type); 1627 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 1628 struct net_device *dev, u32 iqid); 1629 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1630 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1631 int t4_sge_init(struct adapter *adap); 1632 void t4_sge_start(struct adapter *adap); 1633 void t4_sge_stop(struct adapter *adap); 1634 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1635 int maxreclaim); 1636 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1637 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1638 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1639 extern int dbfifo_int_thresh; 1640 1641 #define for_each_port(adapter, iter) \ 1642 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1643 1644 static inline int is_bypass(struct adapter *adap) 1645 { 1646 return adap->params.bypass; 1647 } 1648 1649 static inline int is_bypass_device(int device) 1650 { 1651 /* this should be set based upon device capabilities */ 1652 switch (device) { 1653 case 0x440b: 1654 case 0x440c: 1655 return 1; 1656 default: 1657 return 0; 1658 } 1659 } 1660 1661 static inline int is_10gbt_device(int device) 1662 { 1663 /* this should be set based upon device capabilities */ 1664 switch (device) { 1665 case 0x4409: 1666 case 0x4486: 1667 return 1; 1668 1669 default: 1670 return 0; 1671 } 1672 } 1673 1674 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1675 { 1676 return adap->params.vpd.cclk / 1000; 1677 } 1678 1679 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1680 unsigned int us) 1681 { 1682 return (us * adap->params.vpd.cclk) / 1000; 1683 } 1684 1685 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1686 unsigned int ticks) 1687 { 1688 /* add Core Clock / 2 to round ticks to nearest uS */ 1689 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1690 adapter->params.vpd.cclk); 1691 } 1692 1693 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1694 unsigned int ticks) 1695 { 1696 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1697 } 1698 1699 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1700 u32 val); 1701 1702 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1703 int size, void *rpl, bool sleep_ok, int timeout); 1704 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1705 void *rpl, bool sleep_ok); 1706 1707 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1708 const void *cmd, int size, void *rpl, 1709 int timeout) 1710 { 1711 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1712 timeout); 1713 } 1714 1715 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1716 int size, void *rpl) 1717 { 1718 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1719 } 1720 1721 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1722 int size, void *rpl) 1723 { 1724 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1725 } 1726 1727 /** 1728 * hash_mac_addr - return the hash value of a MAC address 1729 * @addr: the 48-bit Ethernet MAC address 1730 * 1731 * Hashes a MAC address according to the hash function used by HW inexact 1732 * (hash) address matching. 1733 */ 1734 static inline int hash_mac_addr(const u8 *addr) 1735 { 1736 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1737 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1738 1739 a ^= b; 1740 a ^= (a >> 12); 1741 a ^= (a >> 6); 1742 return a & 0x3f; 1743 } 1744 1745 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1746 unsigned int cnt); 1747 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1748 unsigned int us, unsigned int cnt, 1749 unsigned int size, unsigned int iqe_size) 1750 { 1751 q->adap = adap; 1752 cxgb4_set_rspq_intr_params(q, us, cnt); 1753 q->iqe_len = iqe_size; 1754 q->size = size; 1755 } 1756 1757 /** 1758 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1759 * @fw_mod_type: the Firmware Mofule Type 1760 * 1761 * Return whether the Firmware Module Type represents a real Transceiver 1762 * Module/Cable Module Type which has been inserted. 1763 */ 1764 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1765 { 1766 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1767 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1768 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1769 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1770 } 1771 1772 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1773 unsigned int data_reg, const u32 *vals, 1774 unsigned int nregs, unsigned int start_idx); 1775 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1776 unsigned int data_reg, u32 *vals, unsigned int nregs, 1777 unsigned int start_idx); 1778 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1779 1780 struct fw_filter_wr; 1781 1782 void t4_intr_enable(struct adapter *adapter); 1783 void t4_intr_disable(struct adapter *adapter); 1784 int t4_slow_intr_handler(struct adapter *adapter); 1785 1786 int t4_wait_dev_ready(void __iomem *regs); 1787 1788 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 1789 struct link_config *lc); 1790 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 1791 unsigned int port, struct link_config *lc, 1792 u8 sleep_ok, int timeout); 1793 1794 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 1795 unsigned int port, struct link_config *lc) 1796 { 1797 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1798 true, FW_CMD_MAX_TIMEOUT); 1799 } 1800 1801 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 1802 unsigned int port, struct link_config *lc) 1803 { 1804 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1805 false, FW_CMD_MAX_TIMEOUT); 1806 } 1807 1808 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1809 1810 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1811 u32 t4_get_util_window(struct adapter *adap); 1812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1813 1814 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1815 u32 *mem_base, u32 *mem_aperture); 1816 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1817 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1818 int dir); 1819 #define T4_MEMORY_WRITE 0 1820 #define T4_MEMORY_READ 1 1821 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1822 void *buf, int dir); 1823 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1824 u32 len, __be32 *buf) 1825 { 1826 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1827 } 1828 1829 unsigned int t4_get_regs_len(struct adapter *adapter); 1830 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1831 1832 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1833 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1834 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1835 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1836 int t4_get_pfres(struct adapter *adapter); 1837 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1838 unsigned int nwords, u32 *data, int byte_oriented); 1839 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1840 int t4_load_phy_fw(struct adapter *adap, int win, 1841 int (*phy_fw_version)(const u8 *, size_t), 1842 const u8 *phy_fw_data, size_t phy_fw_size); 1843 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1844 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1845 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1846 const u8 *fw_data, unsigned int size, int force); 1847 int t4_fl_pkt_align(struct adapter *adap); 1848 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1849 int t4_check_fw_version(struct adapter *adap); 1850 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1851 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1852 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1853 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1854 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1855 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1856 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1857 int t4_get_version_info(struct adapter *adapter); 1858 void t4_dump_version_info(struct adapter *adapter); 1859 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1860 const u8 *fw_data, unsigned int fw_size, 1861 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1862 int t4_prep_adapter(struct adapter *adapter); 1863 int t4_shutdown_adapter(struct adapter *adapter); 1864 1865 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1866 int t4_bar2_sge_qregs(struct adapter *adapter, 1867 unsigned int qid, 1868 enum t4_bar2_qtype qtype, 1869 int user, 1870 u64 *pbar2_qoffset, 1871 unsigned int *pbar2_qid); 1872 1873 unsigned int qtimer_val(const struct adapter *adap, 1874 const struct sge_rspq *q); 1875 1876 int t4_init_devlog_params(struct adapter *adapter); 1877 int t4_init_sge_params(struct adapter *adapter); 1878 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1879 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1880 int t4_init_rss_mode(struct adapter *adap, int mbox); 1881 int t4_init_portinfo(struct port_info *pi, int mbox, 1882 int port, int pf, int vf, u8 mac[]); 1883 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1884 int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf, 1885 u16 *mirror_viid); 1886 void t4_fatal_err(struct adapter *adapter); 1887 unsigned int t4_chip_rss_size(struct adapter *adapter); 1888 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1889 int start, int n, const u16 *rspq, unsigned int nrspq); 1890 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1891 unsigned int flags); 1892 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1893 unsigned int flags, unsigned int defq); 1894 int t4_read_rss(struct adapter *adapter, u16 *entries); 1895 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1896 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1897 bool sleep_ok); 1898 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1899 u32 *valp, bool sleep_ok); 1900 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1901 u32 *vfl, u32 *vfh, bool sleep_ok); 1902 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1903 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1904 1905 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1906 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1907 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1908 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1909 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1910 size_t n); 1911 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1912 size_t n); 1913 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1914 unsigned int *valp); 1915 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1916 const unsigned int *valp); 1917 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1918 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1919 unsigned int *pif_req_wrptr, 1920 unsigned int *pif_rsp_wrptr); 1921 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1922 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1923 const char *t4_get_port_type_description(enum fw_port_type port_type); 1924 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1925 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1926 struct port_stats *stats, 1927 struct port_stats *offset); 1928 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1929 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1930 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1931 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1932 unsigned int mask, unsigned int val); 1933 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1934 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1935 bool sleep_ok); 1936 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1937 bool sleep_ok); 1938 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1939 bool sleep_ok); 1940 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1941 bool sleep_ok); 1942 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1943 struct tp_tcp_stats *v6, bool sleep_ok); 1944 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1945 struct tp_fcoe_stats *st, bool sleep_ok); 1946 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1947 const unsigned short *alpha, const unsigned short *beta); 1948 1949 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1950 1951 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1952 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1953 1954 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1955 const u8 *addr); 1956 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1957 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1958 1959 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1960 enum dev_master master, enum dev_state *state); 1961 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1962 int t4_early_init(struct adapter *adap, unsigned int mbox); 1963 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1964 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1965 unsigned int cache_line_size); 1966 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1967 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1968 unsigned int vf, unsigned int nparams, const u32 *params, 1969 u32 *val); 1970 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1971 unsigned int vf, unsigned int nparams, const u32 *params, 1972 u32 *val); 1973 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1974 unsigned int vf, unsigned int nparams, const u32 *params, 1975 u32 *val, int rw, bool sleep_ok); 1976 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1977 unsigned int pf, unsigned int vf, 1978 unsigned int nparams, const u32 *params, 1979 const u32 *val, int timeout); 1980 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1981 unsigned int vf, unsigned int nparams, const u32 *params, 1982 const u32 *val); 1983 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1984 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1985 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1986 unsigned int vi, unsigned int cmask, unsigned int pmask, 1987 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1988 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1989 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1990 unsigned int *rss_size, u8 *vivld, u8 *vin); 1991 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1992 unsigned int pf, unsigned int vf, 1993 unsigned int viid); 1994 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1995 unsigned int viid_mirror, int mtu, int promisc, int all_multi, 1996 int bcast, int vlanex, bool sleep_ok); 1997 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1998 const u8 *addr, const u8 *mask, unsigned int idx, 1999 u8 lookup_type, u8 port_id, bool sleep_ok); 2000 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 2001 bool sleep_ok); 2002 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 2003 const u8 *addr, const u8 *mask, unsigned int vni, 2004 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 2005 bool sleep_ok); 2006 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 2007 const u8 *addr, const u8 *mask, unsigned int idx, 2008 u8 lookup_type, u8 port_id, bool sleep_ok); 2009 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 2010 unsigned int viid, bool free, unsigned int naddr, 2011 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 2012 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 2013 unsigned int viid, unsigned int naddr, 2014 const u8 **addr, bool sleep_ok); 2015 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 2016 int idx, const u8 *addr, bool persist, u8 *smt_idx); 2017 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 2018 bool ucast, u64 vec, bool sleep_ok); 2019 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 2020 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 2021 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 2022 struct port_info *pi, 2023 bool rx_en, bool tx_en, bool dcb_en); 2024 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 2025 bool rx_en, bool tx_en); 2026 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 2027 unsigned int nblinks); 2028 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 2029 unsigned int mmd, unsigned int reg, u16 *valp); 2030 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 2031 unsigned int mmd, unsigned int reg, u16 val); 2032 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 2033 unsigned int vf, unsigned int iqtype, unsigned int iqid, 2034 unsigned int fl0id, unsigned int fl1id); 2035 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2036 unsigned int vf, unsigned int iqtype, unsigned int iqid, 2037 unsigned int fl0id, unsigned int fl1id); 2038 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2039 unsigned int vf, unsigned int eqid); 2040 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2041 unsigned int vf, unsigned int eqid); 2042 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2043 unsigned int vf, unsigned int eqid); 2044 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 2045 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 2046 u16 *dbqtimers); 2047 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 2048 int t4_update_port_info(struct port_info *pi); 2049 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 2050 unsigned int *speedp, unsigned int *mtup); 2051 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 2052 void t4_db_full(struct adapter *adapter); 2053 void t4_db_dropped(struct adapter *adapter); 2054 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 2055 int filter_index, int enable); 2056 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 2057 int filter_index, int *enabled); 2058 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 2059 u32 addr, u32 val); 2060 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 2061 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 2062 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 2063 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 2064 enum ctxt_type ctype, u32 *data); 2065 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 2066 enum ctxt_type ctype, u32 *data); 2067 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode, 2068 u8 rateunit, u8 ratemode, u8 channel, u8 class, 2069 u32 minrate, u32 maxrate, u16 weight, u16 pktsize, 2070 u16 burstsize); 2071 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 2072 void t4_idma_monitor_init(struct adapter *adapter, 2073 struct sge_idma_monitor_state *idma); 2074 void t4_idma_monitor(struct adapter *adapter, 2075 struct sge_idma_monitor_state *idma, 2076 int hz, int ticks); 2077 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 2078 unsigned int naddr, u8 *addr); 2079 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 2080 u32 start_index, bool sleep_ok); 2081 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 2082 u32 start_index, bool sleep_ok); 2083 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 2084 u32 start_index, bool sleep_ok); 2085 2086 void t4_uld_mem_free(struct adapter *adap); 2087 int t4_uld_mem_alloc(struct adapter *adap); 2088 void t4_uld_clean_up(struct adapter *adap); 2089 void t4_register_netevent_notifier(void); 2090 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 2091 unsigned int devid, unsigned int offset, 2092 unsigned int len, u8 *buf); 2093 int t4_load_boot(struct adapter *adap, u8 *boot_data, 2094 unsigned int boot_addr, unsigned int size); 2095 int t4_load_bootcfg(struct adapter *adap, 2096 const u8 *cfg_data, unsigned int size); 2097 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 2098 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 2099 unsigned int n, bool unmap); 2100 void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 2101 u32 ndesc); 2102 int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 2103 void cxgb4_ethofld_restart(unsigned long data); 2104 int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 2105 const struct pkt_gl *si); 2106 void free_txq(struct adapter *adap, struct sge_txq *q); 2107 void cxgb4_reclaim_completed_tx(struct adapter *adap, 2108 struct sge_txq *q, bool unmap); 2109 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 2110 dma_addr_t *addr); 2111 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 2112 void *pos); 2113 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 2114 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 2115 const dma_addr_t *addr); 2116 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 2117 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 2118 u16 vlan); 2119 int cxgb4_dcb_enabled(const struct net_device *dev); 2120 2121 int cxgb4_thermal_init(struct adapter *adap); 2122 int cxgb4_thermal_remove(struct adapter *adap); 2123 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 2124 cpumask_var_t *aff_mask, int idx); 2125 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 2126 2127 int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 2128 int *tcam_idx, const u8 *addr, 2129 bool persistent, u8 *smt_idx); 2130 2131 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 2132 bool free, unsigned int naddr, 2133 const u8 **addr, u16 *idx, 2134 u64 *hash, bool sleep_ok); 2135 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2136 unsigned int naddr, const u8 **addr, bool sleep_ok); 2137 int cxgb4_init_mps_ref_entries(struct adapter *adap); 2138 void cxgb4_free_mps_ref_entries(struct adapter *adap); 2139 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 2140 const u8 *addr, const u8 *mask, 2141 unsigned int vni, unsigned int vni_mask, 2142 u8 dip_hit, u8 lookup_type, bool sleep_ok); 2143 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 2144 int idx, bool sleep_ok); 2145 int cxgb4_free_raw_mac_filt(struct adapter *adap, 2146 unsigned int viid, 2147 const u8 *addr, 2148 const u8 *mask, 2149 unsigned int idx, 2150 u8 lookup_type, 2151 u8 port_id, 2152 bool sleep_ok); 2153 int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 2154 unsigned int viid, 2155 const u8 *addr, 2156 const u8 *mask, 2157 unsigned int idx, 2158 u8 lookup_type, 2159 u8 port_id, 2160 bool sleep_ok); 2161 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 2162 int *tcam_idx, const u8 *addr, 2163 bool persistent, u8 *smt_idx); 2164 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 2165 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2166 int cxgb_open(struct net_device *dev); 2167 int cxgb_close(struct net_device *dev); 2168 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 2169 void cxgb4_quiesce_rx(struct sge_rspq *q); 2170 int cxgb4_port_mirror_alloc(struct net_device *dev); 2171 void cxgb4_port_mirror_free(struct net_device *dev); 2172 #ifdef CONFIG_CHELSIO_TLS_DEVICE 2173 int cxgb4_set_ktls_feature(struct adapter *adap, bool enable); 2174 #endif 2175 #endif /* __CXGB4_H__ */ 2176