1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/rhashtable.h> 50 #include <linux/etherdevice.h> 51 #include <linux/net_tstamp.h> 52 #include <linux/ptp_clock_kernel.h> 53 #include <linux/ptp_classify.h> 54 #include <linux/crash_dump.h> 55 #include <linux/thermal.h> 56 #include <asm/io.h> 57 #include "t4_chip_type.h" 58 #include "cxgb4_uld.h" 59 #include "t4fw_api.h" 60 61 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 62 extern struct list_head adapter_list; 63 extern struct list_head uld_list; 64 extern struct mutex uld_mutex; 65 66 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 67 * This is the same as calc_tx_descs() for a TSO packet with 68 * nr_frags == MAX_SKB_FRAGS. 69 */ 70 #define ETHTXQ_STOP_THRES \ 71 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 72 73 #define FW_PARAM_DEV(param) \ 74 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 75 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 76 77 #define FW_PARAM_PFVF(param) \ 78 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 79 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 80 FW_PARAMS_PARAM_Y_V(0) | \ 81 FW_PARAMS_PARAM_Z_V(0)) 82 83 enum { 84 MAX_NPORTS = 4, /* max # of ports */ 85 SERNUM_LEN = 24, /* Serial # length */ 86 EC_LEN = 16, /* E/C length */ 87 ID_LEN = 16, /* ID length */ 88 PN_LEN = 16, /* Part Number length */ 89 MACADDR_LEN = 12, /* MAC Address length */ 90 }; 91 92 enum { 93 T4_REGMAP_SIZE = (160 * 1024), 94 T5_REGMAP_SIZE = (332 * 1024), 95 }; 96 97 enum { 98 MEM_EDC0, 99 MEM_EDC1, 100 MEM_MC, 101 MEM_MC0 = MEM_MC, 102 MEM_MC1, 103 MEM_HMA, 104 }; 105 106 enum { 107 MEMWIN0_APERTURE = 2048, 108 MEMWIN0_BASE = 0x1b800, 109 MEMWIN1_APERTURE = 32768, 110 MEMWIN1_BASE = 0x28000, 111 MEMWIN1_BASE_T5 = 0x52000, 112 MEMWIN2_APERTURE = 65536, 113 MEMWIN2_BASE = 0x30000, 114 MEMWIN2_APERTURE_T5 = 131072, 115 MEMWIN2_BASE_T5 = 0x60000, 116 }; 117 118 enum dev_master { 119 MASTER_CANT, 120 MASTER_MAY, 121 MASTER_MUST 122 }; 123 124 enum dev_state { 125 DEV_STATE_UNINIT, 126 DEV_STATE_INIT, 127 DEV_STATE_ERR 128 }; 129 130 enum cc_pause { 131 PAUSE_RX = 1 << 0, 132 PAUSE_TX = 1 << 1, 133 PAUSE_AUTONEG = 1 << 2 134 }; 135 136 enum cc_fec { 137 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 138 FEC_RS = 1 << 1, /* Reed-Solomon */ 139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 140 }; 141 142 enum { 143 CXGB4_ETHTOOL_FLASH_FW = 1, 144 CXGB4_ETHTOOL_FLASH_PHY = 2, 145 }; 146 147 struct port_stats { 148 u64 tx_octets; /* total # of octets in good frames */ 149 u64 tx_frames; /* all good frames */ 150 u64 tx_bcast_frames; /* all broadcast frames */ 151 u64 tx_mcast_frames; /* all multicast frames */ 152 u64 tx_ucast_frames; /* all unicast frames */ 153 u64 tx_error_frames; /* all error frames */ 154 155 u64 tx_frames_64; /* # of Tx frames in a particular range */ 156 u64 tx_frames_65_127; 157 u64 tx_frames_128_255; 158 u64 tx_frames_256_511; 159 u64 tx_frames_512_1023; 160 u64 tx_frames_1024_1518; 161 u64 tx_frames_1519_max; 162 163 u64 tx_drop; /* # of dropped Tx frames */ 164 u64 tx_pause; /* # of transmitted pause frames */ 165 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 166 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 167 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 168 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 169 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 170 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 171 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 172 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 173 174 u64 rx_octets; /* total # of octets in good frames */ 175 u64 rx_frames; /* all good frames */ 176 u64 rx_bcast_frames; /* all broadcast frames */ 177 u64 rx_mcast_frames; /* all multicast frames */ 178 u64 rx_ucast_frames; /* all unicast frames */ 179 u64 rx_too_long; /* # of frames exceeding MTU */ 180 u64 rx_jabber; /* # of jabber frames */ 181 u64 rx_fcs_err; /* # of received frames with bad FCS */ 182 u64 rx_len_err; /* # of received frames with length error */ 183 u64 rx_symbol_err; /* symbol errors */ 184 u64 rx_runt; /* # of short frames */ 185 186 u64 rx_frames_64; /* # of Rx frames in a particular range */ 187 u64 rx_frames_65_127; 188 u64 rx_frames_128_255; 189 u64 rx_frames_256_511; 190 u64 rx_frames_512_1023; 191 u64 rx_frames_1024_1518; 192 u64 rx_frames_1519_max; 193 194 u64 rx_pause; /* # of received pause frames */ 195 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 196 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 197 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 198 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 199 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 200 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 201 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 202 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 203 204 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 205 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 206 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 207 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 208 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 209 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 210 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 211 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 212 }; 213 214 struct lb_port_stats { 215 u64 octets; 216 u64 frames; 217 u64 bcast_frames; 218 u64 mcast_frames; 219 u64 ucast_frames; 220 u64 error_frames; 221 222 u64 frames_64; 223 u64 frames_65_127; 224 u64 frames_128_255; 225 u64 frames_256_511; 226 u64 frames_512_1023; 227 u64 frames_1024_1518; 228 u64 frames_1519_max; 229 230 u64 drop; 231 232 u64 ovflow0; 233 u64 ovflow1; 234 u64 ovflow2; 235 u64 ovflow3; 236 u64 trunc0; 237 u64 trunc1; 238 u64 trunc2; 239 u64 trunc3; 240 }; 241 242 struct tp_tcp_stats { 243 u32 tcp_out_rsts; 244 u64 tcp_in_segs; 245 u64 tcp_out_segs; 246 u64 tcp_retrans_segs; 247 }; 248 249 struct tp_usm_stats { 250 u32 frames; 251 u32 drops; 252 u64 octets; 253 }; 254 255 struct tp_fcoe_stats { 256 u32 frames_ddp; 257 u32 frames_drop; 258 u64 octets_ddp; 259 }; 260 261 struct tp_err_stats { 262 u32 mac_in_errs[4]; 263 u32 hdr_in_errs[4]; 264 u32 tcp_in_errs[4]; 265 u32 tnl_cong_drops[4]; 266 u32 ofld_chan_drops[4]; 267 u32 tnl_tx_drops[4]; 268 u32 ofld_vlan_drops[4]; 269 u32 tcp6_in_errs[4]; 270 u32 ofld_no_neigh; 271 u32 ofld_cong_defer; 272 }; 273 274 struct tp_cpl_stats { 275 u32 req[4]; 276 u32 rsp[4]; 277 }; 278 279 struct tp_rdma_stats { 280 u32 rqe_dfr_pkt; 281 u32 rqe_dfr_mod; 282 }; 283 284 struct sge_params { 285 u32 hps; /* host page size for our PF/VF */ 286 u32 eq_qpp; /* egress queues/page for our PF/VF */ 287 u32 iq_qpp; /* egress queues/page for our PF/VF */ 288 }; 289 290 struct tp_params { 291 unsigned int tre; /* log2 of core clocks per TP tick */ 292 unsigned int la_mask; /* what events are recorded by TP LA */ 293 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 294 /* channel map */ 295 296 uint32_t dack_re; /* DACK timer resolution */ 297 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 298 299 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 300 u32 filter_mask; 301 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 302 303 /* cached TP_OUT_CONFIG compressed error vector 304 * and passing outer header info for encapsulated packets. 305 */ 306 int rx_pkt_encap; 307 308 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 309 * subset of the set of fields which may be present in the Compressed 310 * Filter Tuple portion of filters and TCP TCB connections. The 311 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 312 * Since a variable number of fields may or may not be present, their 313 * shifted field positions within the Compressed Filter Tuple may 314 * vary, or not even be present if the field isn't selected in 315 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 316 * places we store their offsets here, or a -1 if the field isn't 317 * present. 318 */ 319 int fcoe_shift; 320 int port_shift; 321 int vnic_shift; 322 int vlan_shift; 323 int tos_shift; 324 int protocol_shift; 325 int ethertype_shift; 326 int macmatch_shift; 327 int matchtype_shift; 328 int frag_shift; 329 330 u64 hash_filter_mask; 331 }; 332 333 struct vpd_params { 334 unsigned int cclk; 335 u8 ec[EC_LEN + 1]; 336 u8 sn[SERNUM_LEN + 1]; 337 u8 id[ID_LEN + 1]; 338 u8 pn[PN_LEN + 1]; 339 u8 na[MACADDR_LEN + 1]; 340 }; 341 342 /* Maximum resources provisioned for a PCI PF. 343 */ 344 struct pf_resources { 345 unsigned int nvi; /* N virtual interfaces */ 346 unsigned int neq; /* N egress Qs */ 347 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 348 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 349 unsigned int niq; /* N ingress Qs */ 350 unsigned int tc; /* PCI-E traffic class */ 351 unsigned int pmask; /* port access rights mask */ 352 unsigned int nexactf; /* N exact MPS filters */ 353 unsigned int r_caps; /* read capabilities */ 354 unsigned int wx_caps; /* write/execute capabilities */ 355 }; 356 357 struct pci_params { 358 unsigned int vpd_cap_addr; 359 unsigned char speed; 360 unsigned char width; 361 }; 362 363 struct devlog_params { 364 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 365 u32 start; /* start of log in firmware memory */ 366 u32 size; /* size of log */ 367 }; 368 369 /* Stores chip specific parameters */ 370 struct arch_specific_params { 371 u8 nchan; 372 u8 pm_stats_cnt; 373 u8 cng_ch_bits_log; /* congestion channel map bits width */ 374 u16 mps_rplc_size; 375 u16 vfcount; 376 u32 sge_fl_db; 377 u16 mps_tcam_size; 378 }; 379 380 struct adapter_params { 381 struct sge_params sge; 382 struct tp_params tp; 383 struct vpd_params vpd; 384 struct pf_resources pfres; 385 struct pci_params pci; 386 struct devlog_params devlog; 387 enum pcie_memwin drv_memwin; 388 389 unsigned int cim_la_size; 390 391 unsigned int sf_size; /* serial flash size in bytes */ 392 unsigned int sf_nsec; /* # of flash sectors */ 393 394 unsigned int fw_vers; /* firmware version */ 395 unsigned int bs_vers; /* bootstrap version */ 396 unsigned int tp_vers; /* TP microcode version */ 397 unsigned int er_vers; /* expansion ROM version */ 398 unsigned int scfg_vers; /* Serial Configuration version */ 399 unsigned int vpd_vers; /* VPD Version */ 400 u8 api_vers[7]; 401 402 unsigned short mtus[NMTUS]; 403 unsigned short a_wnd[NCCTRL_WIN]; 404 unsigned short b_wnd[NCCTRL_WIN]; 405 406 unsigned char nports; /* # of ethernet ports */ 407 unsigned char portvec; 408 enum chip_type chip; /* chip code */ 409 struct arch_specific_params arch; /* chip specific params */ 410 unsigned char offload; 411 unsigned char crypto; /* HW capability for crypto */ 412 unsigned char ethofld; /* QoS support */ 413 414 unsigned char bypass; 415 unsigned char hash_filter; 416 417 unsigned int ofldq_wr_cred; 418 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 419 420 unsigned int nsched_cls; /* number of traffic classes */ 421 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 422 unsigned int max_ird_adapter; /* Max read depth per adapter */ 423 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 424 u8 fw_caps_support; /* 32-bit Port Capabilities */ 425 bool filter2_wr_support; /* FW support for FILTER2_WR */ 426 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 427 428 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 429 * used by the Port 430 */ 431 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 432 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 433 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 434 }; 435 436 /* State needed to monitor the forward progress of SGE Ingress DMA activities 437 * and possible hangs. 438 */ 439 struct sge_idma_monitor_state { 440 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 441 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 442 unsigned int idma_state[2]; /* IDMA Hang detect state */ 443 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 444 unsigned int idma_warn[2]; /* time to warning in HZ */ 445 }; 446 447 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 448 * The access and execute times are signed in order to accommodate negative 449 * error returns. 450 */ 451 struct mbox_cmd { 452 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 453 u64 timestamp; /* OS-dependent timestamp */ 454 u32 seqno; /* sequence number */ 455 s16 access; /* time (ms) to access mailbox */ 456 s16 execute; /* time (ms) to execute */ 457 }; 458 459 struct mbox_cmd_log { 460 unsigned int size; /* number of entries in the log */ 461 unsigned int cursor; /* next position in the log to write */ 462 u32 seqno; /* next sequence number */ 463 /* variable length mailbox command log starts here */ 464 }; 465 466 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 467 * return a pointer to the specified entry. 468 */ 469 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 470 unsigned int entry_idx) 471 { 472 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 473 } 474 475 #define FW_VERSION(chip) ( \ 476 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 477 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 478 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 479 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 480 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 481 482 struct fw_info { 483 u8 chip; 484 char *fs_name; 485 char *fw_mod_name; 486 struct fw_hdr fw_hdr; 487 }; 488 489 struct trace_params { 490 u32 data[TRACE_LEN / 4]; 491 u32 mask[TRACE_LEN / 4]; 492 unsigned short snap_len; 493 unsigned short min_len; 494 unsigned char skip_ofst; 495 unsigned char skip_len; 496 unsigned char invert; 497 unsigned char port; 498 }; 499 500 struct cxgb4_fw_data { 501 __be32 signature; 502 __u8 reserved[4]; 503 }; 504 505 /* Firmware Port Capabilities types. */ 506 507 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 508 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 509 510 enum fw_caps { 511 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 512 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 513 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 514 }; 515 516 struct link_config { 517 fw_port_cap32_t pcaps; /* link capabilities */ 518 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 519 fw_port_cap32_t acaps; /* advertised capabilities */ 520 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 521 522 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 523 unsigned int speed; /* actual link speed (Mb/s) */ 524 525 enum cc_pause requested_fc; /* flow control user has requested */ 526 enum cc_pause fc; /* actual link flow control */ 527 enum cc_pause advertised_fc; /* actual advertised flow control */ 528 529 enum cc_fec requested_fec; /* Forward Error Correction: */ 530 enum cc_fec fec; /* requested and actual in use */ 531 532 unsigned char autoneg; /* autonegotiating? */ 533 534 unsigned char link_ok; /* link up? */ 535 unsigned char link_down_rc; /* link down reason */ 536 537 bool new_module; /* ->OS Transceiver Module inserted */ 538 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 539 }; 540 541 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 542 543 enum { 544 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 545 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 546 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 547 }; 548 549 enum { 550 MAX_TXQ_ENTRIES = 16384, 551 MAX_CTRL_TXQ_ENTRIES = 1024, 552 MAX_RSPQ_ENTRIES = 16384, 553 MAX_RX_BUFFERS = 16384, 554 MIN_TXQ_ENTRIES = 32, 555 MIN_CTRL_TXQ_ENTRIES = 32, 556 MIN_RSPQ_ENTRIES = 128, 557 MIN_FL_ENTRIES = 16 558 }; 559 560 enum { 561 MAX_TXQ_DESC_SIZE = 64, 562 MAX_RXQ_DESC_SIZE = 128, 563 MAX_FL_DESC_SIZE = 8, 564 MAX_CTRL_TXQ_DESC_SIZE = 64, 565 }; 566 567 enum { 568 INGQ_EXTRAS = 2, /* firmware event queue and */ 569 /* forwarded interrupts */ 570 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 571 }; 572 573 enum { 574 PRIV_FLAG_PORT_TX_VM_BIT, 575 }; 576 577 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 578 579 #define PRIV_FLAGS_ADAP 0 580 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 581 582 struct adapter; 583 struct sge_rspq; 584 585 #include "cxgb4_dcb.h" 586 587 #ifdef CONFIG_CHELSIO_T4_FCOE 588 #include "cxgb4_fcoe.h" 589 #endif /* CONFIG_CHELSIO_T4_FCOE */ 590 591 struct port_info { 592 struct adapter *adapter; 593 u16 viid; 594 int xact_addr_filt; /* index of exact MAC address filter */ 595 u16 rss_size; /* size of VI's RSS table slice */ 596 s8 mdio_addr; 597 enum fw_port_type port_type; 598 u8 mod_type; 599 u8 port_id; 600 u8 tx_chan; 601 u8 lport; /* associated offload logical port */ 602 u8 nqsets; /* # of qsets */ 603 u8 first_qset; /* index of first qset */ 604 u8 rss_mode; 605 struct link_config link_cfg; 606 u16 *rss; 607 struct port_stats stats_base; 608 #ifdef CONFIG_CHELSIO_T4_DCB 609 struct port_dcb_info dcb; /* Data Center Bridging support */ 610 #endif 611 #ifdef CONFIG_CHELSIO_T4_FCOE 612 struct cxgb_fcoe fcoe; 613 #endif /* CONFIG_CHELSIO_T4_FCOE */ 614 bool rxtstamp; /* Enable TS */ 615 struct hwtstamp_config tstamp_config; 616 bool ptp_enable; 617 struct sched_table *sched_tbl; 618 u32 eth_flags; 619 620 /* viid and smt fields either returned by fw 621 * or decoded by parsing viid by driver. 622 */ 623 u8 vin; 624 u8 vivld; 625 u8 smt_idx; 626 u8 rx_cchan; 627 628 bool tc_block_shared; 629 }; 630 631 struct dentry; 632 struct work_struct; 633 634 enum { /* adapter flags */ 635 CXGB4_FULL_INIT_DONE = (1 << 0), 636 CXGB4_DEV_ENABLED = (1 << 1), 637 CXGB4_USING_MSI = (1 << 2), 638 CXGB4_USING_MSIX = (1 << 3), 639 CXGB4_FW_OK = (1 << 4), 640 CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 641 CXGB4_USING_SOFT_PARAMS = (1 << 6), 642 CXGB4_MASTER_PF = (1 << 7), 643 CXGB4_FW_OFLD_CONN = (1 << 9), 644 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 645 CXGB4_SHUTTING_DOWN = (1 << 11), 646 CXGB4_SGE_DBQ_TIMER = (1 << 12), 647 }; 648 649 enum { 650 ULP_CRYPTO_LOOKASIDE = 1 << 0, 651 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 652 ULP_CRYPTO_KTLS_INLINE = 1 << 3, 653 }; 654 655 struct rx_sw_desc; 656 657 struct sge_fl { /* SGE free-buffer queue state */ 658 unsigned int avail; /* # of available Rx buffers */ 659 unsigned int pend_cred; /* new buffers since last FL DB ring */ 660 unsigned int cidx; /* consumer index */ 661 unsigned int pidx; /* producer index */ 662 unsigned long alloc_failed; /* # of times buffer allocation failed */ 663 unsigned long large_alloc_failed; 664 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 665 unsigned long low; /* # of times momentarily starving */ 666 unsigned long starving; 667 /* RO fields */ 668 unsigned int cntxt_id; /* SGE context id for the free list */ 669 unsigned int size; /* capacity of free list */ 670 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 671 __be64 *desc; /* address of HW Rx descriptor ring */ 672 dma_addr_t addr; /* bus address of HW ring start */ 673 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 674 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 675 }; 676 677 /* A packet gather list */ 678 struct pkt_gl { 679 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 680 struct page_frag frags[MAX_SKB_FRAGS]; 681 void *va; /* virtual address of first byte */ 682 unsigned int nfrags; /* # of fragments */ 683 unsigned int tot_len; /* total length of fragments */ 684 }; 685 686 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 687 const struct pkt_gl *gl); 688 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 689 /* LRO related declarations for ULD */ 690 struct t4_lro_mgr { 691 #define MAX_LRO_SESSIONS 64 692 u8 lro_session_cnt; /* # of sessions to aggregate */ 693 unsigned long lro_pkts; /* # of LRO super packets */ 694 unsigned long lro_merged; /* # of wire packets merged by LRO */ 695 struct sk_buff_head lroq; /* list of aggregated sessions */ 696 }; 697 698 struct sge_rspq { /* state for an SGE response queue */ 699 struct napi_struct napi; 700 const __be64 *cur_desc; /* current descriptor in queue */ 701 unsigned int cidx; /* consumer index */ 702 u8 gen; /* current generation bit */ 703 u8 intr_params; /* interrupt holdoff parameters */ 704 u8 next_intr_params; /* holdoff params for next interrupt */ 705 u8 adaptive_rx; 706 u8 pktcnt_idx; /* interrupt packet threshold */ 707 u8 uld; /* ULD handling this queue */ 708 u8 idx; /* queue index within its group */ 709 int offset; /* offset into current Rx buffer */ 710 u16 cntxt_id; /* SGE context id for the response q */ 711 u16 abs_id; /* absolute SGE id for the response q */ 712 __be64 *desc; /* address of HW response ring */ 713 dma_addr_t phys_addr; /* physical address of the ring */ 714 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 715 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 716 unsigned int iqe_len; /* entry size */ 717 unsigned int size; /* capacity of response queue */ 718 struct adapter *adap; 719 struct net_device *netdev; /* associated net device */ 720 rspq_handler_t handler; 721 rspq_flush_handler_t flush_handler; 722 struct t4_lro_mgr lro_mgr; 723 }; 724 725 struct sge_eth_stats { /* Ethernet queue statistics */ 726 unsigned long pkts; /* # of ethernet packets */ 727 unsigned long lro_pkts; /* # of LRO super packets */ 728 unsigned long lro_merged; /* # of wire packets merged by LRO */ 729 unsigned long rx_cso; /* # of Rx checksum offloads */ 730 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 731 unsigned long rx_drops; /* # of packets dropped due to no mem */ 732 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 733 }; 734 735 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 736 struct sge_rspq rspq; 737 struct sge_fl fl; 738 struct sge_eth_stats stats; 739 struct msix_info *msix; 740 } ____cacheline_aligned_in_smp; 741 742 struct sge_ofld_stats { /* offload queue statistics */ 743 unsigned long pkts; /* # of packets */ 744 unsigned long imm; /* # of immediate-data packets */ 745 unsigned long an; /* # of asynchronous notifications */ 746 unsigned long nomem; /* # of responses deferred due to no mem */ 747 }; 748 749 struct sge_ofld_rxq { /* SW offload Rx queue */ 750 struct sge_rspq rspq; 751 struct sge_fl fl; 752 struct sge_ofld_stats stats; 753 struct msix_info *msix; 754 } ____cacheline_aligned_in_smp; 755 756 struct tx_desc { 757 __be64 flit[8]; 758 }; 759 760 struct ulptx_sgl; 761 762 struct tx_sw_desc { 763 struct sk_buff *skb; /* SKB to free after getting completion */ 764 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 765 }; 766 767 struct sge_txq { 768 unsigned int in_use; /* # of in-use Tx descriptors */ 769 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 770 unsigned int size; /* # of descriptors */ 771 unsigned int cidx; /* SW consumer index */ 772 unsigned int pidx; /* producer index */ 773 unsigned long stops; /* # of times q has been stopped */ 774 unsigned long restarts; /* # of queue restarts */ 775 unsigned int cntxt_id; /* SGE context id for the Tx q */ 776 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 777 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 778 struct sge_qstat *stat; /* queue status entry */ 779 dma_addr_t phys_addr; /* physical address of the ring */ 780 spinlock_t db_lock; 781 int db_disabled; 782 unsigned short db_pidx; 783 unsigned short db_pidx_inc; 784 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 785 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 786 }; 787 788 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 789 struct sge_txq q; 790 struct netdev_queue *txq; /* associated netdev TX queue */ 791 #ifdef CONFIG_CHELSIO_T4_DCB 792 u8 dcb_prio; /* DCB Priority bound to queue */ 793 #endif 794 u8 dbqt; /* SGE Doorbell Queue Timer in use */ 795 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 796 unsigned long tso; /* # of TSO requests */ 797 unsigned long uso; /* # of USO requests */ 798 unsigned long tx_cso; /* # of Tx checksum offloads */ 799 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 800 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 801 } ____cacheline_aligned_in_smp; 802 803 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 804 struct sge_txq q; 805 struct adapter *adap; 806 struct sk_buff_head sendq; /* list of backpressured packets */ 807 struct tasklet_struct qresume_tsk; /* restarts the queue */ 808 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 809 u8 full; /* the Tx ring is full */ 810 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 811 } ____cacheline_aligned_in_smp; 812 813 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 814 struct sge_txq q; 815 struct adapter *adap; 816 struct sk_buff_head sendq; /* list of backpressured packets */ 817 struct tasklet_struct qresume_tsk; /* restarts the queue */ 818 u8 full; /* the Tx ring is full */ 819 } ____cacheline_aligned_in_smp; 820 821 struct sge_uld_rxq_info { 822 char name[IFNAMSIZ]; /* name of ULD driver */ 823 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 824 u16 *rspq_id; /* response queue id's of rxq */ 825 u16 nrxq; /* # of ingress uld queues */ 826 u16 nciq; /* # of completion queues */ 827 u8 uld; /* uld type */ 828 }; 829 830 struct sge_uld_txq_info { 831 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 832 atomic_t users; /* num users */ 833 u16 ntxq; /* # of egress uld queues */ 834 }; 835 836 /* struct to maintain ULD list to reallocate ULD resources on hotplug */ 837 struct cxgb4_uld_list { 838 struct cxgb4_uld_info uld_info; 839 struct list_head list_node; 840 enum cxgb4_uld uld_type; 841 }; 842 843 enum sge_eosw_state { 844 CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 845 CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 846 CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 847 CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 848 CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 849 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 850 }; 851 852 struct sge_eosw_txq { 853 spinlock_t lock; /* Per queue lock to synchronize completions */ 854 enum sge_eosw_state state; /* Current ETHOFLD State */ 855 struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ 856 u32 ndesc; /* Number of descriptors */ 857 u32 pidx; /* Current Producer Index */ 858 u32 last_pidx; /* Last successfully transmitted Producer Index */ 859 u32 cidx; /* Current Consumer Index */ 860 u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 861 u32 flowc_idx; /* Descriptor containing a FLOWC request */ 862 u32 inuse; /* Number of packets held in ring */ 863 864 u32 cred; /* Current available credits */ 865 u32 ncompl; /* # of completions posted */ 866 u32 last_compl; /* # of credits consumed since last completion req */ 867 868 u32 eotid; /* Index into EOTID table in software */ 869 u32 hwtid; /* Hardware EOTID index */ 870 871 u32 hwqid; /* Underlying hardware queue index */ 872 struct net_device *netdev; /* Pointer to netdevice */ 873 struct tasklet_struct qresume_tsk; /* Restarts the queue */ 874 struct completion completion; /* completion for FLOWC rendezvous */ 875 }; 876 877 struct sge_eohw_txq { 878 spinlock_t lock; /* Per queue lock */ 879 struct sge_txq q; /* HW Txq */ 880 struct adapter *adap; /* Backpointer to adapter */ 881 unsigned long tso; /* # of TSO requests */ 882 unsigned long uso; /* # of USO requests */ 883 unsigned long tx_cso; /* # of Tx checksum offloads */ 884 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 885 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 886 }; 887 888 struct sge { 889 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 890 struct sge_eth_txq ptptxq; 891 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 892 893 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 894 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 895 struct sge_uld_rxq_info **uld_rxq_info; 896 struct sge_uld_txq_info **uld_txq_info; 897 898 struct sge_rspq intrq ____cacheline_aligned_in_smp; 899 spinlock_t intrq_lock; 900 901 struct sge_eohw_txq *eohw_txq; 902 struct sge_ofld_rxq *eohw_rxq; 903 904 u16 max_ethqsets; /* # of available Ethernet queue sets */ 905 u16 ethqsets; /* # of active Ethernet queue sets */ 906 u16 ethtxq_rover; /* Tx queue to clean up next */ 907 u16 ofldqsets; /* # of active ofld queue sets */ 908 u16 nqs_per_uld; /* # of Rx queues per ULD */ 909 u16 eoqsets; /* # of ETHOFLD queues */ 910 911 u16 timer_val[SGE_NTIMERS]; 912 u8 counter_val[SGE_NCOUNTERS]; 913 u16 dbqtimer_tick; 914 u16 dbqtimer_val[SGE_NDBQTIMERS]; 915 u32 fl_pg_order; /* large page allocation size */ 916 u32 stat_len; /* length of status page at ring end */ 917 u32 pktshift; /* padding between CPL & packet data */ 918 u32 fl_align; /* response queue message alignment */ 919 u32 fl_starve_thres; /* Free List starvation threshold */ 920 921 struct sge_idma_monitor_state idma_monitor; 922 unsigned int egr_start; 923 unsigned int egr_sz; 924 unsigned int ingr_start; 925 unsigned int ingr_sz; 926 void **egr_map; /* qid->queue egress queue map */ 927 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 928 unsigned long *starving_fl; 929 unsigned long *txq_maperr; 930 unsigned long *blocked_fl; 931 struct timer_list rx_timer; /* refills starving FLs */ 932 struct timer_list tx_timer; /* checks Tx queues */ 933 934 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 935 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 936 }; 937 938 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 939 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 940 941 struct l2t_data; 942 943 #ifdef CONFIG_PCI_IOV 944 945 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 946 * Configuration initialization for T5 only has SR-IOV functionality enabled 947 * on PF0-3 in order to simplify everything. 948 */ 949 #define NUM_OF_PF_WITH_SRIOV 4 950 951 #endif 952 953 struct doorbell_stats { 954 u32 db_drop; 955 u32 db_empty; 956 u32 db_full; 957 }; 958 959 struct hash_mac_addr { 960 struct list_head list; 961 u8 addr[ETH_ALEN]; 962 unsigned int iface_mac; 963 }; 964 965 struct msix_bmap { 966 unsigned long *msix_bmap; 967 unsigned int mapsize; 968 spinlock_t lock; /* lock for acquiring bitmap */ 969 }; 970 971 struct msix_info { 972 unsigned short vec; 973 char desc[IFNAMSIZ + 10]; 974 unsigned int idx; 975 cpumask_var_t aff_mask; 976 }; 977 978 struct vf_info { 979 unsigned char vf_mac_addr[ETH_ALEN]; 980 unsigned int tx_rate; 981 bool pf_set_mac; 982 u16 vlan; 983 int link_state; 984 }; 985 986 enum { 987 HMA_DMA_MAPPED_FLAG = 1 988 }; 989 990 struct hma_data { 991 unsigned char flags; 992 struct sg_table *sgt; 993 dma_addr_t *phy_addr; /* physical address of the page */ 994 }; 995 996 struct mbox_list { 997 struct list_head list; 998 }; 999 1000 #if IS_ENABLED(CONFIG_THERMAL) 1001 struct ch_thermal { 1002 struct thermal_zone_device *tzdev; 1003 int trip_temp; 1004 int trip_type; 1005 }; 1006 #endif 1007 1008 struct mps_entries_ref { 1009 struct list_head list; 1010 u8 addr[ETH_ALEN]; 1011 u8 mask[ETH_ALEN]; 1012 u16 idx; 1013 refcount_t refcnt; 1014 }; 1015 1016 struct adapter { 1017 void __iomem *regs; 1018 void __iomem *bar2; 1019 u32 t4_bar0; 1020 struct pci_dev *pdev; 1021 struct device *pdev_dev; 1022 const char *name; 1023 unsigned int mbox; 1024 unsigned int pf; 1025 unsigned int flags; 1026 unsigned int adap_idx; 1027 enum chip_type chip; 1028 u32 eth_flags; 1029 1030 int msg_enable; 1031 __be16 vxlan_port; 1032 u8 vxlan_port_cnt; 1033 __be16 geneve_port; 1034 u8 geneve_port_cnt; 1035 1036 struct adapter_params params; 1037 struct cxgb4_virt_res vres; 1038 unsigned int swintr; 1039 1040 /* MSI-X Info for NIC and OFLD queues */ 1041 struct msix_info *msix_info; 1042 struct msix_bmap msix_bmap; 1043 1044 struct doorbell_stats db_stats; 1045 struct sge sge; 1046 1047 struct net_device *port[MAX_NPORTS]; 1048 u8 chan_map[NCHAN]; /* channel -> port map */ 1049 1050 struct vf_info *vfinfo; 1051 u8 num_vfs; 1052 1053 u32 filter_mode; 1054 unsigned int l2t_start; 1055 unsigned int l2t_end; 1056 struct l2t_data *l2t; 1057 unsigned int clipt_start; 1058 unsigned int clipt_end; 1059 struct clip_tbl *clipt; 1060 unsigned int rawf_start; 1061 unsigned int rawf_cnt; 1062 struct smt_data *smt; 1063 struct cxgb4_uld_info *uld; 1064 void *uld_handle[CXGB4_ULD_MAX]; 1065 unsigned int num_uld; 1066 unsigned int num_ofld_uld; 1067 struct list_head list_node; 1068 struct list_head rcu_node; 1069 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 1070 struct list_head mps_ref; 1071 spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1072 1073 void *iscsi_ppm; 1074 1075 struct tid_info tids; 1076 void **tid_release_head; 1077 spinlock_t tid_release_lock; 1078 struct workqueue_struct *workq; 1079 struct work_struct tid_release_task; 1080 struct work_struct db_full_task; 1081 struct work_struct db_drop_task; 1082 struct work_struct fatal_err_notify_task; 1083 bool tid_release_task_busy; 1084 1085 /* lock for mailbox cmd list */ 1086 spinlock_t mbox_lock; 1087 struct mbox_list mlist; 1088 1089 /* support for mailbox command/reply logging */ 1090 #define T4_OS_LOG_MBOX_CMDS 256 1091 struct mbox_cmd_log *mbox_log; 1092 1093 struct mutex uld_mutex; 1094 1095 struct dentry *debugfs_root; 1096 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1097 bool trace_rss; /* 1 implies that different RSS flit per filter is 1098 * used per filter else if 0 default RSS flit is 1099 * used for all 4 filters. 1100 */ 1101 1102 struct ptp_clock *ptp_clock; 1103 struct ptp_clock_info ptp_clock_info; 1104 struct sk_buff *ptp_tx_skb; 1105 /* ptp lock */ 1106 spinlock_t ptp_lock; 1107 spinlock_t stats_lock; 1108 spinlock_t win0_lock ____cacheline_aligned_in_smp; 1109 1110 /* TC u32 offload */ 1111 struct cxgb4_tc_u32_table *tc_u32; 1112 struct chcr_ktls chcr_ktls; 1113 struct chcr_stats_debug chcr_stats; 1114 1115 /* TC flower offload */ 1116 bool tc_flower_initialized; 1117 struct rhashtable flower_tbl; 1118 struct rhashtable_params flower_ht_params; 1119 struct timer_list flower_stats_timer; 1120 struct work_struct flower_stats_work; 1121 1122 /* Ethtool Dump */ 1123 struct ethtool_dump eth_dump; 1124 1125 /* HMA */ 1126 struct hma_data hma; 1127 1128 struct srq_data *srq; 1129 1130 /* Dump buffer for collecting logs in kdump kernel */ 1131 struct vmcoredd_data vmcoredd; 1132 #if IS_ENABLED(CONFIG_THERMAL) 1133 struct ch_thermal ch_thermal; 1134 #endif 1135 1136 /* TC MQPRIO offload */ 1137 struct cxgb4_tc_mqprio *tc_mqprio; 1138 1139 /* TC MATCHALL classifier offload */ 1140 struct cxgb4_tc_matchall *tc_matchall; 1141 }; 1142 1143 /* Support for "sched-class" command to allow a TX Scheduling Class to be 1144 * programmed with various parameters. 1145 */ 1146 struct ch_sched_params { 1147 u8 type; /* packet or flow */ 1148 union { 1149 struct { 1150 u8 level; /* scheduler hierarchy level */ 1151 u8 mode; /* per-class or per-flow */ 1152 u8 rateunit; /* bit or packet rate */ 1153 u8 ratemode; /* %port relative or kbps absolute */ 1154 u8 channel; /* scheduler channel [0..N] */ 1155 u8 class; /* scheduler class [0..N] */ 1156 u32 minrate; /* minimum rate */ 1157 u32 maxrate; /* maximum rate */ 1158 u16 weight; /* percent weight */ 1159 u16 pktsize; /* average packet size */ 1160 u16 burstsize; /* burst buffer size */ 1161 } params; 1162 } u; 1163 }; 1164 1165 enum { 1166 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 1167 }; 1168 1169 enum { 1170 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 1171 SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ 1172 }; 1173 1174 enum { 1175 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1176 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 1177 }; 1178 1179 enum { 1180 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1181 }; 1182 1183 enum { 1184 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1185 }; 1186 1187 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1188 * to be bound to a TX Scheduling Class. 1189 */ 1190 struct ch_sched_queue { 1191 s8 queue; /* queue index */ 1192 s8 class; /* class index */ 1193 }; 1194 1195 /* Support for "sched_flowc" command to allow one or more FLOWC 1196 * to be bound to a TX Scheduling Class. 1197 */ 1198 struct ch_sched_flowc { 1199 s32 tid; /* TID to bind */ 1200 s8 class; /* class index */ 1201 }; 1202 1203 /* Defined bit width of user definable filter tuples 1204 */ 1205 #define ETHTYPE_BITWIDTH 16 1206 #define FRAG_BITWIDTH 1 1207 #define MACIDX_BITWIDTH 9 1208 #define FCOE_BITWIDTH 1 1209 #define IPORT_BITWIDTH 3 1210 #define MATCHTYPE_BITWIDTH 3 1211 #define PROTO_BITWIDTH 8 1212 #define TOS_BITWIDTH 8 1213 #define PF_BITWIDTH 8 1214 #define VF_BITWIDTH 8 1215 #define IVLAN_BITWIDTH 16 1216 #define OVLAN_BITWIDTH 16 1217 #define ENCAP_VNI_BITWIDTH 24 1218 1219 /* Filter matching rules. These consist of a set of ingress packet field 1220 * (value, mask) tuples. The associated ingress packet field matches the 1221 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1222 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1223 * matches an ingress packet when all of the individual individual field 1224 * matching rules are true. 1225 * 1226 * Partial field masks are always valid, however, while it may be easy to 1227 * understand their meanings for some fields (e.g. IP address to match a 1228 * subnet), for others making sensible partial masks is less intuitive (e.g. 1229 * MPS match type) ... 1230 * 1231 * Most of the following data structures are modeled on T4 capabilities. 1232 * Drivers for earlier chips use the subsets which make sense for those chips. 1233 * We really need to come up with a hardware-independent mechanism to 1234 * represent hardware filter capabilities ... 1235 */ 1236 struct ch_filter_tuple { 1237 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1238 * register selects which of these fields will participate in the 1239 * filter match rules -- up to a maximum of 36 bits. Because 1240 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1241 * set of fields. 1242 */ 1243 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1244 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1245 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1246 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1247 uint32_t pfvf_vld:1; /* PF/VF valid */ 1248 uint32_t encap_vld:1; /* Encapsulation valid */ 1249 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1250 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1251 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1252 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1253 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1254 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1255 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1256 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1257 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1258 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1259 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1260 1261 /* Uncompressed header matching field rules. These are always 1262 * available for field rules. 1263 */ 1264 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1265 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1266 uint16_t lport; /* local port */ 1267 uint16_t fport; /* foreign port */ 1268 }; 1269 1270 /* A filter ioctl command. 1271 */ 1272 struct ch_filter_specification { 1273 /* Administrative fields for filter. 1274 */ 1275 uint32_t hitcnts:1; /* count filter hits in TCB */ 1276 uint32_t prio:1; /* filter has priority over active/server */ 1277 1278 /* Fundamental filter typing. This is the one element of filter 1279 * matching that doesn't exist as a (value, mask) tuple. 1280 */ 1281 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1282 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1283 1284 /* Packet dispatch information. Ingress packets which match the 1285 * filter rules will be dropped, passed to the host or switched back 1286 * out as egress packets. 1287 */ 1288 uint32_t action:2; /* drop, pass, switch */ 1289 1290 uint32_t rpttid:1; /* report TID in RSS hash field */ 1291 1292 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1293 uint32_t iq:10; /* ingress queue */ 1294 1295 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1296 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1297 /* 1 => TCB contains IQ ID */ 1298 1299 /* Switch proxy/rewrite fields. An ingress packet which matches a 1300 * filter with "switch" set will be looped back out as an egress 1301 * packet -- potentially with some Ethernet header rewriting. 1302 */ 1303 uint32_t eport:2; /* egress port to switch packet out */ 1304 uint32_t newdmac:1; /* rewrite destination MAC address */ 1305 uint32_t newsmac:1; /* rewrite source MAC address */ 1306 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1307 uint32_t nat_mode:3; /* specify NAT operation mode */ 1308 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1309 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1310 uint16_t vlan; /* VLAN Tag to insert */ 1311 1312 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1313 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1314 u16 nat_lport; /* local port to use after NAT'ing */ 1315 u16 nat_fport; /* foreign port to use after NAT'ing */ 1316 1317 u32 tc_prio; /* TC's filter priority index */ 1318 u64 tc_cookie; /* Unique cookie identifying TC rules */ 1319 1320 /* reservation for future additions */ 1321 u8 rsvd[12]; 1322 1323 /* Filter rule value/mask pairs. 1324 */ 1325 struct ch_filter_tuple val; 1326 struct ch_filter_tuple mask; 1327 }; 1328 1329 enum { 1330 FILTER_PASS = 0, /* default */ 1331 FILTER_DROP, 1332 FILTER_SWITCH 1333 }; 1334 1335 enum { 1336 VLAN_NOCHANGE = 0, /* default */ 1337 VLAN_REMOVE, 1338 VLAN_INSERT, 1339 VLAN_REWRITE 1340 }; 1341 1342 enum { 1343 NAT_MODE_NONE = 0, /* No NAT performed */ 1344 NAT_MODE_DIP, /* NAT on Dst IP */ 1345 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1346 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1347 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1348 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1349 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1350 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1351 }; 1352 1353 /* Host shadow copy of ingress filter entry. This is in host native format 1354 * and doesn't match the ordering or bit order, etc. of the hardware of the 1355 * firmware command. The use of bit-field structure elements is purely to 1356 * remind ourselves of the field size limitations and save memory in the case 1357 * where the filter table is large. 1358 */ 1359 struct filter_entry { 1360 /* Administrative fields for filter. */ 1361 u32 valid:1; /* filter allocated and valid */ 1362 u32 locked:1; /* filter is administratively locked */ 1363 1364 u32 pending:1; /* filter action is pending firmware reply */ 1365 struct filter_ctx *ctx; /* Caller's completion hook */ 1366 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1367 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1368 struct net_device *dev; /* Associated net device */ 1369 u32 tid; /* This will store the actual tid */ 1370 1371 /* The filter itself. Most of this is a straight copy of information 1372 * provided by the extended ioctl(). Some fields are translated to 1373 * internal forms -- for instance the Ingress Queue ID passed in from 1374 * the ioctl() is translated into the Absolute Ingress Queue ID. 1375 */ 1376 struct ch_filter_specification fs; 1377 }; 1378 1379 static inline int is_offload(const struct adapter *adap) 1380 { 1381 return adap->params.offload; 1382 } 1383 1384 static inline int is_hashfilter(const struct adapter *adap) 1385 { 1386 return adap->params.hash_filter; 1387 } 1388 1389 static inline int is_pci_uld(const struct adapter *adap) 1390 { 1391 return adap->params.crypto; 1392 } 1393 1394 static inline int is_uld(const struct adapter *adap) 1395 { 1396 return (adap->params.offload || adap->params.crypto); 1397 } 1398 1399 static inline int is_ethofld(const struct adapter *adap) 1400 { 1401 return adap->params.ethofld; 1402 } 1403 1404 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1405 { 1406 return readl(adap->regs + reg_addr); 1407 } 1408 1409 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1410 { 1411 writel(val, adap->regs + reg_addr); 1412 } 1413 1414 #ifndef readq 1415 static inline u64 readq(const volatile void __iomem *addr) 1416 { 1417 return readl(addr) + ((u64)readl(addr + 4) << 32); 1418 } 1419 1420 static inline void writeq(u64 val, volatile void __iomem *addr) 1421 { 1422 writel(val, addr); 1423 writel(val >> 32, addr + 4); 1424 } 1425 #endif 1426 1427 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1428 { 1429 return readq(adap->regs + reg_addr); 1430 } 1431 1432 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1433 { 1434 writeq(val, adap->regs + reg_addr); 1435 } 1436 1437 /** 1438 * t4_set_hw_addr - store a port's MAC address in SW 1439 * @adapter: the adapter 1440 * @port_idx: the port index 1441 * @hw_addr: the Ethernet address 1442 * 1443 * Store the Ethernet address of the given port in SW. Called by the common 1444 * code when it retrieves a port's Ethernet address from EEPROM. 1445 */ 1446 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1447 u8 hw_addr[]) 1448 { 1449 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1450 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1451 } 1452 1453 /** 1454 * netdev2pinfo - return the port_info structure associated with a net_device 1455 * @dev: the netdev 1456 * 1457 * Return the struct port_info associated with a net_device 1458 */ 1459 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1460 { 1461 return netdev_priv(dev); 1462 } 1463 1464 /** 1465 * adap2pinfo - return the port_info of a port 1466 * @adap: the adapter 1467 * @idx: the port index 1468 * 1469 * Return the port_info structure for the port of the given index. 1470 */ 1471 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1472 { 1473 return netdev_priv(adap->port[idx]); 1474 } 1475 1476 /** 1477 * netdev2adap - return the adapter structure associated with a net_device 1478 * @dev: the netdev 1479 * 1480 * Return the struct adapter associated with a net_device 1481 */ 1482 static inline struct adapter *netdev2adap(const struct net_device *dev) 1483 { 1484 return netdev2pinfo(dev)->adapter; 1485 } 1486 1487 /* Return a version number to identify the type of adapter. The scheme is: 1488 * - bits 0..9: chip version 1489 * - bits 10..15: chip revision 1490 * - bits 16..23: register dump version 1491 */ 1492 static inline unsigned int mk_adap_vers(struct adapter *ap) 1493 { 1494 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1495 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1496 } 1497 1498 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1499 static inline unsigned int qtimer_val(const struct adapter *adap, 1500 const struct sge_rspq *q) 1501 { 1502 unsigned int idx = q->intr_params >> 1; 1503 1504 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1505 } 1506 1507 /* driver name used for ethtool_drvinfo */ 1508 extern char cxgb4_driver_name[]; 1509 1510 void t4_os_portmod_changed(struct adapter *adap, int port_id); 1511 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1512 1513 void t4_free_sge_resources(struct adapter *adap); 1514 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1515 irq_handler_t t4_intr_handler(struct adapter *adap); 1516 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1517 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1518 const struct pkt_gl *gl); 1519 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1520 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1521 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1522 struct net_device *dev, int intr_idx, 1523 struct sge_fl *fl, rspq_handler_t hnd, 1524 rspq_flush_handler_t flush_handler, int cong); 1525 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1526 struct net_device *dev, struct netdev_queue *netdevq, 1527 unsigned int iqid, u8 dbqt); 1528 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1529 struct net_device *dev, unsigned int iqid, 1530 unsigned int cmplqid); 1531 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1532 unsigned int cmplqid); 1533 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1534 struct net_device *dev, unsigned int iqid, 1535 unsigned int uld_type); 1536 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 1537 struct net_device *dev, u32 iqid); 1538 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1539 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1540 int t4_sge_init(struct adapter *adap); 1541 void t4_sge_start(struct adapter *adap); 1542 void t4_sge_stop(struct adapter *adap); 1543 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1544 int maxreclaim); 1545 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1546 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1547 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1548 extern int dbfifo_int_thresh; 1549 1550 #define for_each_port(adapter, iter) \ 1551 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1552 1553 static inline int is_bypass(struct adapter *adap) 1554 { 1555 return adap->params.bypass; 1556 } 1557 1558 static inline int is_bypass_device(int device) 1559 { 1560 /* this should be set based upon device capabilities */ 1561 switch (device) { 1562 case 0x440b: 1563 case 0x440c: 1564 return 1; 1565 default: 1566 return 0; 1567 } 1568 } 1569 1570 static inline int is_10gbt_device(int device) 1571 { 1572 /* this should be set based upon device capabilities */ 1573 switch (device) { 1574 case 0x4409: 1575 case 0x4486: 1576 return 1; 1577 1578 default: 1579 return 0; 1580 } 1581 } 1582 1583 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1584 { 1585 return adap->params.vpd.cclk / 1000; 1586 } 1587 1588 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1589 unsigned int us) 1590 { 1591 return (us * adap->params.vpd.cclk) / 1000; 1592 } 1593 1594 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1595 unsigned int ticks) 1596 { 1597 /* add Core Clock / 2 to round ticks to nearest uS */ 1598 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1599 adapter->params.vpd.cclk); 1600 } 1601 1602 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1603 unsigned int ticks) 1604 { 1605 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1606 } 1607 1608 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1609 u32 val); 1610 1611 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1612 int size, void *rpl, bool sleep_ok, int timeout); 1613 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1614 void *rpl, bool sleep_ok); 1615 1616 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1617 const void *cmd, int size, void *rpl, 1618 int timeout) 1619 { 1620 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1621 timeout); 1622 } 1623 1624 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1625 int size, void *rpl) 1626 { 1627 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1628 } 1629 1630 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1631 int size, void *rpl) 1632 { 1633 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1634 } 1635 1636 /** 1637 * hash_mac_addr - return the hash value of a MAC address 1638 * @addr: the 48-bit Ethernet MAC address 1639 * 1640 * Hashes a MAC address according to the hash function used by HW inexact 1641 * (hash) address matching. 1642 */ 1643 static inline int hash_mac_addr(const u8 *addr) 1644 { 1645 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1646 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1647 1648 a ^= b; 1649 a ^= (a >> 12); 1650 a ^= (a >> 6); 1651 return a & 0x3f; 1652 } 1653 1654 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1655 unsigned int cnt); 1656 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1657 unsigned int us, unsigned int cnt, 1658 unsigned int size, unsigned int iqe_size) 1659 { 1660 q->adap = adap; 1661 cxgb4_set_rspq_intr_params(q, us, cnt); 1662 q->iqe_len = iqe_size; 1663 q->size = size; 1664 } 1665 1666 /** 1667 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1668 * @fw_mod_type: the Firmware Mofule Type 1669 * 1670 * Return whether the Firmware Module Type represents a real Transceiver 1671 * Module/Cable Module Type which has been inserted. 1672 */ 1673 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1674 { 1675 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1676 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1677 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1678 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1679 } 1680 1681 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1682 unsigned int data_reg, const u32 *vals, 1683 unsigned int nregs, unsigned int start_idx); 1684 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1685 unsigned int data_reg, u32 *vals, unsigned int nregs, 1686 unsigned int start_idx); 1687 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1688 1689 struct fw_filter_wr; 1690 1691 void t4_intr_enable(struct adapter *adapter); 1692 void t4_intr_disable(struct adapter *adapter); 1693 int t4_slow_intr_handler(struct adapter *adapter); 1694 1695 int t4_wait_dev_ready(void __iomem *regs); 1696 1697 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 1698 struct link_config *lc); 1699 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 1700 unsigned int port, struct link_config *lc, 1701 u8 sleep_ok, int timeout); 1702 1703 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 1704 unsigned int port, struct link_config *lc) 1705 { 1706 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1707 true, FW_CMD_MAX_TIMEOUT); 1708 } 1709 1710 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 1711 unsigned int port, struct link_config *lc) 1712 { 1713 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1714 false, FW_CMD_MAX_TIMEOUT); 1715 } 1716 1717 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1718 1719 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1720 u32 t4_get_util_window(struct adapter *adap); 1721 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1722 1723 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1724 u32 *mem_base, u32 *mem_aperture); 1725 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1726 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1727 int dir); 1728 #define T4_MEMORY_WRITE 0 1729 #define T4_MEMORY_READ 1 1730 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1731 void *buf, int dir); 1732 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1733 u32 len, __be32 *buf) 1734 { 1735 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1736 } 1737 1738 unsigned int t4_get_regs_len(struct adapter *adapter); 1739 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1740 1741 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1742 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1743 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1744 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1745 int t4_get_pfres(struct adapter *adapter); 1746 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1747 unsigned int nwords, u32 *data, int byte_oriented); 1748 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1749 int t4_load_phy_fw(struct adapter *adap, 1750 int win, spinlock_t *lock, 1751 int (*phy_fw_version)(const u8 *, size_t), 1752 const u8 *phy_fw_data, size_t phy_fw_size); 1753 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1754 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1755 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1756 const u8 *fw_data, unsigned int size, int force); 1757 int t4_fl_pkt_align(struct adapter *adap); 1758 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1759 int t4_check_fw_version(struct adapter *adap); 1760 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1761 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1762 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1763 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1764 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1765 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1766 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1767 int t4_get_version_info(struct adapter *adapter); 1768 void t4_dump_version_info(struct adapter *adapter); 1769 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1770 const u8 *fw_data, unsigned int fw_size, 1771 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1772 int t4_prep_adapter(struct adapter *adapter); 1773 int t4_shutdown_adapter(struct adapter *adapter); 1774 1775 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1776 int t4_bar2_sge_qregs(struct adapter *adapter, 1777 unsigned int qid, 1778 enum t4_bar2_qtype qtype, 1779 int user, 1780 u64 *pbar2_qoffset, 1781 unsigned int *pbar2_qid); 1782 1783 unsigned int qtimer_val(const struct adapter *adap, 1784 const struct sge_rspq *q); 1785 1786 int t4_init_devlog_params(struct adapter *adapter); 1787 int t4_init_sge_params(struct adapter *adapter); 1788 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1789 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1790 int t4_init_rss_mode(struct adapter *adap, int mbox); 1791 int t4_init_portinfo(struct port_info *pi, int mbox, 1792 int port, int pf, int vf, u8 mac[]); 1793 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1794 void t4_fatal_err(struct adapter *adapter); 1795 unsigned int t4_chip_rss_size(struct adapter *adapter); 1796 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1797 int start, int n, const u16 *rspq, unsigned int nrspq); 1798 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1799 unsigned int flags); 1800 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1801 unsigned int flags, unsigned int defq); 1802 int t4_read_rss(struct adapter *adapter, u16 *entries); 1803 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1804 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1805 bool sleep_ok); 1806 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1807 u32 *valp, bool sleep_ok); 1808 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1809 u32 *vfl, u32 *vfh, bool sleep_ok); 1810 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1811 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1812 1813 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1814 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1815 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1816 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1817 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1818 size_t n); 1819 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1820 size_t n); 1821 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1822 unsigned int *valp); 1823 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1824 const unsigned int *valp); 1825 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1826 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1827 unsigned int *pif_req_wrptr, 1828 unsigned int *pif_rsp_wrptr); 1829 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1830 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1831 const char *t4_get_port_type_description(enum fw_port_type port_type); 1832 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1833 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1834 struct port_stats *stats, 1835 struct port_stats *offset); 1836 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1837 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1838 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1839 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1840 unsigned int mask, unsigned int val); 1841 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1842 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1843 bool sleep_ok); 1844 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1845 bool sleep_ok); 1846 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1847 bool sleep_ok); 1848 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1849 bool sleep_ok); 1850 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1851 struct tp_tcp_stats *v6, bool sleep_ok); 1852 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1853 struct tp_fcoe_stats *st, bool sleep_ok); 1854 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1855 const unsigned short *alpha, const unsigned short *beta); 1856 1857 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1858 1859 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1860 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1861 1862 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1863 const u8 *addr); 1864 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1865 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1866 1867 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1868 enum dev_master master, enum dev_state *state); 1869 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1870 int t4_early_init(struct adapter *adap, unsigned int mbox); 1871 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1872 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1873 unsigned int cache_line_size); 1874 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1875 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1876 unsigned int vf, unsigned int nparams, const u32 *params, 1877 u32 *val); 1878 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1879 unsigned int vf, unsigned int nparams, const u32 *params, 1880 u32 *val); 1881 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1882 unsigned int vf, unsigned int nparams, const u32 *params, 1883 u32 *val, int rw, bool sleep_ok); 1884 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1885 unsigned int pf, unsigned int vf, 1886 unsigned int nparams, const u32 *params, 1887 const u32 *val, int timeout); 1888 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1889 unsigned int vf, unsigned int nparams, const u32 *params, 1890 const u32 *val); 1891 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1892 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1893 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1894 unsigned int vi, unsigned int cmask, unsigned int pmask, 1895 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1896 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1897 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1898 unsigned int *rss_size, u8 *vivld, u8 *vin); 1899 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1900 unsigned int pf, unsigned int vf, 1901 unsigned int viid); 1902 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1903 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1904 bool sleep_ok); 1905 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1906 const u8 *addr, const u8 *mask, unsigned int idx, 1907 u8 lookup_type, u8 port_id, bool sleep_ok); 1908 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 1909 bool sleep_ok); 1910 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 1911 const u8 *addr, const u8 *mask, unsigned int vni, 1912 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 1913 bool sleep_ok); 1914 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1915 const u8 *addr, const u8 *mask, unsigned int idx, 1916 u8 lookup_type, u8 port_id, bool sleep_ok); 1917 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1918 unsigned int viid, bool free, unsigned int naddr, 1919 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1920 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1921 unsigned int viid, unsigned int naddr, 1922 const u8 **addr, bool sleep_ok); 1923 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1924 int idx, const u8 *addr, bool persist, u8 *smt_idx); 1925 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1926 bool ucast, u64 vec, bool sleep_ok); 1927 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1928 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1929 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1930 struct port_info *pi, 1931 bool rx_en, bool tx_en, bool dcb_en); 1932 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1933 bool rx_en, bool tx_en); 1934 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1935 unsigned int nblinks); 1936 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1937 unsigned int mmd, unsigned int reg, u16 *valp); 1938 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1939 unsigned int mmd, unsigned int reg, u16 val); 1940 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1941 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1942 unsigned int fl0id, unsigned int fl1id); 1943 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1944 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1945 unsigned int fl0id, unsigned int fl1id); 1946 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1947 unsigned int vf, unsigned int eqid); 1948 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1949 unsigned int vf, unsigned int eqid); 1950 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1951 unsigned int vf, unsigned int eqid); 1952 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1953 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 1954 u16 *dbqtimers); 1955 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1956 int t4_update_port_info(struct port_info *pi); 1957 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1958 unsigned int *speedp, unsigned int *mtup); 1959 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1960 void t4_db_full(struct adapter *adapter); 1961 void t4_db_dropped(struct adapter *adapter); 1962 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1963 int filter_index, int enable); 1964 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1965 int filter_index, int *enabled); 1966 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1967 u32 addr, u32 val); 1968 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1969 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1970 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1971 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1972 enum ctxt_type ctype, u32 *data); 1973 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1974 enum ctxt_type ctype, u32 *data); 1975 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode, 1976 u8 rateunit, u8 ratemode, u8 channel, u8 class, 1977 u32 minrate, u32 maxrate, u16 weight, u16 pktsize, 1978 u16 burstsize); 1979 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1980 void t4_idma_monitor_init(struct adapter *adapter, 1981 struct sge_idma_monitor_state *idma); 1982 void t4_idma_monitor(struct adapter *adapter, 1983 struct sge_idma_monitor_state *idma, 1984 int hz, int ticks); 1985 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1986 unsigned int naddr, u8 *addr); 1987 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1988 u32 start_index, bool sleep_ok); 1989 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1990 u32 start_index, bool sleep_ok); 1991 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1992 u32 start_index, bool sleep_ok); 1993 1994 void t4_uld_mem_free(struct adapter *adap); 1995 int t4_uld_mem_alloc(struct adapter *adap); 1996 void t4_uld_clean_up(struct adapter *adap); 1997 void t4_register_netevent_notifier(void); 1998 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1999 unsigned int devid, unsigned int offset, 2000 unsigned int len, u8 *buf); 2001 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 2002 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 2003 unsigned int n, bool unmap); 2004 void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 2005 u32 ndesc); 2006 int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 2007 void cxgb4_ethofld_restart(unsigned long data); 2008 int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 2009 const struct pkt_gl *si); 2010 void free_txq(struct adapter *adap, struct sge_txq *q); 2011 void cxgb4_reclaim_completed_tx(struct adapter *adap, 2012 struct sge_txq *q, bool unmap); 2013 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 2014 dma_addr_t *addr); 2015 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 2016 void *pos); 2017 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 2018 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 2019 const dma_addr_t *addr); 2020 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 2021 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 2022 u16 vlan); 2023 int cxgb4_dcb_enabled(const struct net_device *dev); 2024 2025 int cxgb4_thermal_init(struct adapter *adap); 2026 int cxgb4_thermal_remove(struct adapter *adap); 2027 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 2028 cpumask_var_t *aff_mask, int idx); 2029 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 2030 2031 int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 2032 int *tcam_idx, const u8 *addr, 2033 bool persistent, u8 *smt_idx); 2034 2035 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 2036 bool free, unsigned int naddr, 2037 const u8 **addr, u16 *idx, 2038 u64 *hash, bool sleep_ok); 2039 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2040 unsigned int naddr, const u8 **addr, bool sleep_ok); 2041 int cxgb4_init_mps_ref_entries(struct adapter *adap); 2042 void cxgb4_free_mps_ref_entries(struct adapter *adap); 2043 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 2044 const u8 *addr, const u8 *mask, 2045 unsigned int vni, unsigned int vni_mask, 2046 u8 dip_hit, u8 lookup_type, bool sleep_ok); 2047 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 2048 int idx, bool sleep_ok); 2049 int cxgb4_free_raw_mac_filt(struct adapter *adap, 2050 unsigned int viid, 2051 const u8 *addr, 2052 const u8 *mask, 2053 unsigned int idx, 2054 u8 lookup_type, 2055 u8 port_id, 2056 bool sleep_ok); 2057 int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 2058 unsigned int viid, 2059 const u8 *addr, 2060 const u8 *mask, 2061 unsigned int idx, 2062 u8 lookup_type, 2063 u8 port_id, 2064 bool sleep_ok); 2065 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 2066 int *tcam_idx, const u8 *addr, 2067 bool persistent, u8 *smt_idx); 2068 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 2069 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2070 int cxgb_open(struct net_device *dev); 2071 int cxgb_close(struct net_device *dev); 2072 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 2073 void cxgb4_quiesce_rx(struct sge_rspq *q); 2074 #ifdef CONFIG_CHELSIO_TLS_DEVICE 2075 int cxgb4_set_ktls_feature(struct adapter *adap, bool enable); 2076 #endif 2077 #endif /* __CXGB4_H__ */ 2078