1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <asm/io.h> 52 #include "t4_chip_type.h" 53 #include "cxgb4_uld.h" 54 55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 56 extern struct list_head adapter_list; 57 extern struct mutex uld_mutex; 58 59 enum { 60 MAX_NPORTS = 4, /* max # of ports */ 61 SERNUM_LEN = 24, /* Serial # length */ 62 EC_LEN = 16, /* E/C length */ 63 ID_LEN = 16, /* ID length */ 64 PN_LEN = 16, /* Part Number length */ 65 MACADDR_LEN = 12, /* MAC Address length */ 66 }; 67 68 enum { 69 T4_REGMAP_SIZE = (160 * 1024), 70 T5_REGMAP_SIZE = (332 * 1024), 71 }; 72 73 enum { 74 MEM_EDC0, 75 MEM_EDC1, 76 MEM_MC, 77 MEM_MC0 = MEM_MC, 78 MEM_MC1 79 }; 80 81 enum { 82 MEMWIN0_APERTURE = 2048, 83 MEMWIN0_BASE = 0x1b800, 84 MEMWIN1_APERTURE = 32768, 85 MEMWIN1_BASE = 0x28000, 86 MEMWIN1_BASE_T5 = 0x52000, 87 MEMWIN2_APERTURE = 65536, 88 MEMWIN2_BASE = 0x30000, 89 MEMWIN2_APERTURE_T5 = 131072, 90 MEMWIN2_BASE_T5 = 0x60000, 91 }; 92 93 enum dev_master { 94 MASTER_CANT, 95 MASTER_MAY, 96 MASTER_MUST 97 }; 98 99 enum dev_state { 100 DEV_STATE_UNINIT, 101 DEV_STATE_INIT, 102 DEV_STATE_ERR 103 }; 104 105 enum { 106 PAUSE_RX = 1 << 0, 107 PAUSE_TX = 1 << 1, 108 PAUSE_AUTONEG = 1 << 2 109 }; 110 111 struct port_stats { 112 u64 tx_octets; /* total # of octets in good frames */ 113 u64 tx_frames; /* all good frames */ 114 u64 tx_bcast_frames; /* all broadcast frames */ 115 u64 tx_mcast_frames; /* all multicast frames */ 116 u64 tx_ucast_frames; /* all unicast frames */ 117 u64 tx_error_frames; /* all error frames */ 118 119 u64 tx_frames_64; /* # of Tx frames in a particular range */ 120 u64 tx_frames_65_127; 121 u64 tx_frames_128_255; 122 u64 tx_frames_256_511; 123 u64 tx_frames_512_1023; 124 u64 tx_frames_1024_1518; 125 u64 tx_frames_1519_max; 126 127 u64 tx_drop; /* # of dropped Tx frames */ 128 u64 tx_pause; /* # of transmitted pause frames */ 129 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 130 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 131 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 132 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 133 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 134 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 135 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 136 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 137 138 u64 rx_octets; /* total # of octets in good frames */ 139 u64 rx_frames; /* all good frames */ 140 u64 rx_bcast_frames; /* all broadcast frames */ 141 u64 rx_mcast_frames; /* all multicast frames */ 142 u64 rx_ucast_frames; /* all unicast frames */ 143 u64 rx_too_long; /* # of frames exceeding MTU */ 144 u64 rx_jabber; /* # of jabber frames */ 145 u64 rx_fcs_err; /* # of received frames with bad FCS */ 146 u64 rx_len_err; /* # of received frames with length error */ 147 u64 rx_symbol_err; /* symbol errors */ 148 u64 rx_runt; /* # of short frames */ 149 150 u64 rx_frames_64; /* # of Rx frames in a particular range */ 151 u64 rx_frames_65_127; 152 u64 rx_frames_128_255; 153 u64 rx_frames_256_511; 154 u64 rx_frames_512_1023; 155 u64 rx_frames_1024_1518; 156 u64 rx_frames_1519_max; 157 158 u64 rx_pause; /* # of received pause frames */ 159 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 160 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 161 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 162 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 163 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 164 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 165 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 166 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 167 168 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 169 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 170 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 171 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 172 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 173 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 174 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 175 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 176 }; 177 178 struct lb_port_stats { 179 u64 octets; 180 u64 frames; 181 u64 bcast_frames; 182 u64 mcast_frames; 183 u64 ucast_frames; 184 u64 error_frames; 185 186 u64 frames_64; 187 u64 frames_65_127; 188 u64 frames_128_255; 189 u64 frames_256_511; 190 u64 frames_512_1023; 191 u64 frames_1024_1518; 192 u64 frames_1519_max; 193 194 u64 drop; 195 196 u64 ovflow0; 197 u64 ovflow1; 198 u64 ovflow2; 199 u64 ovflow3; 200 u64 trunc0; 201 u64 trunc1; 202 u64 trunc2; 203 u64 trunc3; 204 }; 205 206 struct tp_tcp_stats { 207 u32 tcp_out_rsts; 208 u64 tcp_in_segs; 209 u64 tcp_out_segs; 210 u64 tcp_retrans_segs; 211 }; 212 213 struct tp_usm_stats { 214 u32 frames; 215 u32 drops; 216 u64 octets; 217 }; 218 219 struct tp_fcoe_stats { 220 u32 frames_ddp; 221 u32 frames_drop; 222 u64 octets_ddp; 223 }; 224 225 struct tp_err_stats { 226 u32 mac_in_errs[4]; 227 u32 hdr_in_errs[4]; 228 u32 tcp_in_errs[4]; 229 u32 tnl_cong_drops[4]; 230 u32 ofld_chan_drops[4]; 231 u32 tnl_tx_drops[4]; 232 u32 ofld_vlan_drops[4]; 233 u32 tcp6_in_errs[4]; 234 u32 ofld_no_neigh; 235 u32 ofld_cong_defer; 236 }; 237 238 struct tp_cpl_stats { 239 u32 req[4]; 240 u32 rsp[4]; 241 }; 242 243 struct tp_rdma_stats { 244 u32 rqe_dfr_pkt; 245 u32 rqe_dfr_mod; 246 }; 247 248 struct sge_params { 249 u32 hps; /* host page size for our PF/VF */ 250 u32 eq_qpp; /* egress queues/page for our PF/VF */ 251 u32 iq_qpp; /* egress queues/page for our PF/VF */ 252 }; 253 254 struct tp_params { 255 unsigned int tre; /* log2 of core clocks per TP tick */ 256 unsigned int la_mask; /* what events are recorded by TP LA */ 257 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 258 /* channel map */ 259 260 uint32_t dack_re; /* DACK timer resolution */ 261 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 262 263 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 264 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 265 266 /* cached TP_OUT_CONFIG compressed error vector 267 * and passing outer header info for encapsulated packets. 268 */ 269 int rx_pkt_encap; 270 271 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 272 * subset of the set of fields which may be present in the Compressed 273 * Filter Tuple portion of filters and TCP TCB connections. The 274 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 275 * Since a variable number of fields may or may not be present, their 276 * shifted field positions within the Compressed Filter Tuple may 277 * vary, or not even be present if the field isn't selected in 278 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 279 * places we store their offsets here, or a -1 if the field isn't 280 * present. 281 */ 282 int vlan_shift; 283 int vnic_shift; 284 int port_shift; 285 int protocol_shift; 286 }; 287 288 struct vpd_params { 289 unsigned int cclk; 290 u8 ec[EC_LEN + 1]; 291 u8 sn[SERNUM_LEN + 1]; 292 u8 id[ID_LEN + 1]; 293 u8 pn[PN_LEN + 1]; 294 u8 na[MACADDR_LEN + 1]; 295 }; 296 297 struct pci_params { 298 unsigned char speed; 299 unsigned char width; 300 }; 301 302 struct devlog_params { 303 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 304 u32 start; /* start of log in firmware memory */ 305 u32 size; /* size of log */ 306 }; 307 308 /* Stores chip specific parameters */ 309 struct arch_specific_params { 310 u8 nchan; 311 u8 pm_stats_cnt; 312 u8 cng_ch_bits_log; /* congestion channel map bits width */ 313 u16 mps_rplc_size; 314 u16 vfcount; 315 u32 sge_fl_db; 316 u16 mps_tcam_size; 317 }; 318 319 struct adapter_params { 320 struct sge_params sge; 321 struct tp_params tp; 322 struct vpd_params vpd; 323 struct pci_params pci; 324 struct devlog_params devlog; 325 enum pcie_memwin drv_memwin; 326 327 unsigned int cim_la_size; 328 329 unsigned int sf_size; /* serial flash size in bytes */ 330 unsigned int sf_nsec; /* # of flash sectors */ 331 unsigned int sf_fw_start; /* start of FW image in flash */ 332 333 unsigned int fw_vers; 334 unsigned int bs_vers; /* bootstrap version */ 335 unsigned int tp_vers; 336 unsigned int er_vers; /* expansion ROM version */ 337 u8 api_vers[7]; 338 339 unsigned short mtus[NMTUS]; 340 unsigned short a_wnd[NCCTRL_WIN]; 341 unsigned short b_wnd[NCCTRL_WIN]; 342 343 unsigned char nports; /* # of ethernet ports */ 344 unsigned char portvec; 345 enum chip_type chip; /* chip code */ 346 struct arch_specific_params arch; /* chip specific params */ 347 unsigned char offload; 348 unsigned char crypto; /* HW capability for crypto */ 349 350 unsigned char bypass; 351 352 unsigned int ofldq_wr_cred; 353 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 354 355 unsigned int nsched_cls; /* number of traffic classes */ 356 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 357 unsigned int max_ird_adapter; /* Max read depth per adapter */ 358 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 359 }; 360 361 /* State needed to monitor the forward progress of SGE Ingress DMA activities 362 * and possible hangs. 363 */ 364 struct sge_idma_monitor_state { 365 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 366 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 367 unsigned int idma_state[2]; /* IDMA Hang detect state */ 368 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 369 unsigned int idma_warn[2]; /* time to warning in HZ */ 370 }; 371 372 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 373 * The access and execute times are signed in order to accommodate negative 374 * error returns. 375 */ 376 struct mbox_cmd { 377 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 378 u64 timestamp; /* OS-dependent timestamp */ 379 u32 seqno; /* sequence number */ 380 s16 access; /* time (ms) to access mailbox */ 381 s16 execute; /* time (ms) to execute */ 382 }; 383 384 struct mbox_cmd_log { 385 unsigned int size; /* number of entries in the log */ 386 unsigned int cursor; /* next position in the log to write */ 387 u32 seqno; /* next sequence number */ 388 /* variable length mailbox command log starts here */ 389 }; 390 391 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 392 * return a pointer to the specified entry. 393 */ 394 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 395 unsigned int entry_idx) 396 { 397 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 398 } 399 400 #include "t4fw_api.h" 401 402 #define FW_VERSION(chip) ( \ 403 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 404 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 405 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 406 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 407 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 408 409 struct fw_info { 410 u8 chip; 411 char *fs_name; 412 char *fw_mod_name; 413 struct fw_hdr fw_hdr; 414 }; 415 416 struct trace_params { 417 u32 data[TRACE_LEN / 4]; 418 u32 mask[TRACE_LEN / 4]; 419 unsigned short snap_len; 420 unsigned short min_len; 421 unsigned char skip_ofst; 422 unsigned char skip_len; 423 unsigned char invert; 424 unsigned char port; 425 }; 426 427 struct link_config { 428 unsigned short supported; /* link capabilities */ 429 unsigned short advertising; /* advertised capabilities */ 430 unsigned short lp_advertising; /* peer advertised capabilities */ 431 unsigned int requested_speed; /* speed user has requested */ 432 unsigned int speed; /* actual link speed */ 433 unsigned char requested_fc; /* flow control user has requested */ 434 unsigned char fc; /* actual link flow control */ 435 unsigned char autoneg; /* autonegotiating? */ 436 unsigned char link_ok; /* link up? */ 437 unsigned char link_down_rc; /* link down reason */ 438 }; 439 440 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 441 442 enum { 443 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 444 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 445 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 446 }; 447 448 enum { 449 MAX_TXQ_ENTRIES = 16384, 450 MAX_CTRL_TXQ_ENTRIES = 1024, 451 MAX_RSPQ_ENTRIES = 16384, 452 MAX_RX_BUFFERS = 16384, 453 MIN_TXQ_ENTRIES = 32, 454 MIN_CTRL_TXQ_ENTRIES = 32, 455 MIN_RSPQ_ENTRIES = 128, 456 MIN_FL_ENTRIES = 16 457 }; 458 459 enum { 460 INGQ_EXTRAS = 2, /* firmware event queue and */ 461 /* forwarded interrupts */ 462 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 463 }; 464 465 struct adapter; 466 struct sge_rspq; 467 468 #include "cxgb4_dcb.h" 469 470 #ifdef CONFIG_CHELSIO_T4_FCOE 471 #include "cxgb4_fcoe.h" 472 #endif /* CONFIG_CHELSIO_T4_FCOE */ 473 474 struct port_info { 475 struct adapter *adapter; 476 u16 viid; 477 s16 xact_addr_filt; /* index of exact MAC address filter */ 478 u16 rss_size; /* size of VI's RSS table slice */ 479 s8 mdio_addr; 480 enum fw_port_type port_type; 481 u8 mod_type; 482 u8 port_id; 483 u8 tx_chan; 484 u8 lport; /* associated offload logical port */ 485 u8 nqsets; /* # of qsets */ 486 u8 first_qset; /* index of first qset */ 487 u8 rss_mode; 488 struct link_config link_cfg; 489 u16 *rss; 490 struct port_stats stats_base; 491 #ifdef CONFIG_CHELSIO_T4_DCB 492 struct port_dcb_info dcb; /* Data Center Bridging support */ 493 #endif 494 #ifdef CONFIG_CHELSIO_T4_FCOE 495 struct cxgb_fcoe fcoe; 496 #endif /* CONFIG_CHELSIO_T4_FCOE */ 497 bool rxtstamp; /* Enable TS */ 498 struct hwtstamp_config tstamp_config; 499 struct sched_table *sched_tbl; 500 }; 501 502 struct dentry; 503 struct work_struct; 504 505 enum { /* adapter flags */ 506 FULL_INIT_DONE = (1 << 0), 507 DEV_ENABLED = (1 << 1), 508 USING_MSI = (1 << 2), 509 USING_MSIX = (1 << 3), 510 FW_OK = (1 << 4), 511 RSS_TNLALLLOOKUP = (1 << 5), 512 USING_SOFT_PARAMS = (1 << 6), 513 MASTER_PF = (1 << 7), 514 FW_OFLD_CONN = (1 << 9), 515 }; 516 517 enum { 518 ULP_CRYPTO_LOOKASIDE = 1 << 0, 519 }; 520 521 struct rx_sw_desc; 522 523 struct sge_fl { /* SGE free-buffer queue state */ 524 unsigned int avail; /* # of available Rx buffers */ 525 unsigned int pend_cred; /* new buffers since last FL DB ring */ 526 unsigned int cidx; /* consumer index */ 527 unsigned int pidx; /* producer index */ 528 unsigned long alloc_failed; /* # of times buffer allocation failed */ 529 unsigned long large_alloc_failed; 530 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 531 unsigned long low; /* # of times momentarily starving */ 532 unsigned long starving; 533 /* RO fields */ 534 unsigned int cntxt_id; /* SGE context id for the free list */ 535 unsigned int size; /* capacity of free list */ 536 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 537 __be64 *desc; /* address of HW Rx descriptor ring */ 538 dma_addr_t addr; /* bus address of HW ring start */ 539 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 540 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 541 }; 542 543 /* A packet gather list */ 544 struct pkt_gl { 545 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 546 struct page_frag frags[MAX_SKB_FRAGS]; 547 void *va; /* virtual address of first byte */ 548 unsigned int nfrags; /* # of fragments */ 549 unsigned int tot_len; /* total length of fragments */ 550 }; 551 552 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 553 const struct pkt_gl *gl); 554 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 555 /* LRO related declarations for ULD */ 556 struct t4_lro_mgr { 557 #define MAX_LRO_SESSIONS 64 558 u8 lro_session_cnt; /* # of sessions to aggregate */ 559 unsigned long lro_pkts; /* # of LRO super packets */ 560 unsigned long lro_merged; /* # of wire packets merged by LRO */ 561 struct sk_buff_head lroq; /* list of aggregated sessions */ 562 }; 563 564 struct sge_rspq { /* state for an SGE response queue */ 565 struct napi_struct napi; 566 const __be64 *cur_desc; /* current descriptor in queue */ 567 unsigned int cidx; /* consumer index */ 568 u8 gen; /* current generation bit */ 569 u8 intr_params; /* interrupt holdoff parameters */ 570 u8 next_intr_params; /* holdoff params for next interrupt */ 571 u8 adaptive_rx; 572 u8 pktcnt_idx; /* interrupt packet threshold */ 573 u8 uld; /* ULD handling this queue */ 574 u8 idx; /* queue index within its group */ 575 int offset; /* offset into current Rx buffer */ 576 u16 cntxt_id; /* SGE context id for the response q */ 577 u16 abs_id; /* absolute SGE id for the response q */ 578 __be64 *desc; /* address of HW response ring */ 579 dma_addr_t phys_addr; /* physical address of the ring */ 580 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 581 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 582 unsigned int iqe_len; /* entry size */ 583 unsigned int size; /* capacity of response queue */ 584 struct adapter *adap; 585 struct net_device *netdev; /* associated net device */ 586 rspq_handler_t handler; 587 rspq_flush_handler_t flush_handler; 588 struct t4_lro_mgr lro_mgr; 589 }; 590 591 struct sge_eth_stats { /* Ethernet queue statistics */ 592 unsigned long pkts; /* # of ethernet packets */ 593 unsigned long lro_pkts; /* # of LRO super packets */ 594 unsigned long lro_merged; /* # of wire packets merged by LRO */ 595 unsigned long rx_cso; /* # of Rx checksum offloads */ 596 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 597 unsigned long rx_drops; /* # of packets dropped due to no mem */ 598 }; 599 600 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 601 struct sge_rspq rspq; 602 struct sge_fl fl; 603 struct sge_eth_stats stats; 604 } ____cacheline_aligned_in_smp; 605 606 struct sge_ofld_stats { /* offload queue statistics */ 607 unsigned long pkts; /* # of packets */ 608 unsigned long imm; /* # of immediate-data packets */ 609 unsigned long an; /* # of asynchronous notifications */ 610 unsigned long nomem; /* # of responses deferred due to no mem */ 611 }; 612 613 struct sge_ofld_rxq { /* SW offload Rx queue */ 614 struct sge_rspq rspq; 615 struct sge_fl fl; 616 struct sge_ofld_stats stats; 617 } ____cacheline_aligned_in_smp; 618 619 struct tx_desc { 620 __be64 flit[8]; 621 }; 622 623 struct tx_sw_desc; 624 625 struct sge_txq { 626 unsigned int in_use; /* # of in-use Tx descriptors */ 627 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 628 unsigned int size; /* # of descriptors */ 629 unsigned int cidx; /* SW consumer index */ 630 unsigned int pidx; /* producer index */ 631 unsigned long stops; /* # of times q has been stopped */ 632 unsigned long restarts; /* # of queue restarts */ 633 unsigned int cntxt_id; /* SGE context id for the Tx q */ 634 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 635 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 636 struct sge_qstat *stat; /* queue status entry */ 637 dma_addr_t phys_addr; /* physical address of the ring */ 638 spinlock_t db_lock; 639 int db_disabled; 640 unsigned short db_pidx; 641 unsigned short db_pidx_inc; 642 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 643 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 644 }; 645 646 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 647 struct sge_txq q; 648 struct netdev_queue *txq; /* associated netdev TX queue */ 649 #ifdef CONFIG_CHELSIO_T4_DCB 650 u8 dcb_prio; /* DCB Priority bound to queue */ 651 #endif 652 unsigned long tso; /* # of TSO requests */ 653 unsigned long tx_cso; /* # of Tx checksum offloads */ 654 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 655 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 656 } ____cacheline_aligned_in_smp; 657 658 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 659 struct sge_txq q; 660 struct adapter *adap; 661 struct sk_buff_head sendq; /* list of backpressured packets */ 662 struct tasklet_struct qresume_tsk; /* restarts the queue */ 663 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 664 u8 full; /* the Tx ring is full */ 665 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 666 } ____cacheline_aligned_in_smp; 667 668 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 669 struct sge_txq q; 670 struct adapter *adap; 671 struct sk_buff_head sendq; /* list of backpressured packets */ 672 struct tasklet_struct qresume_tsk; /* restarts the queue */ 673 u8 full; /* the Tx ring is full */ 674 } ____cacheline_aligned_in_smp; 675 676 struct sge_uld_rxq_info { 677 char name[IFNAMSIZ]; /* name of ULD driver */ 678 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 679 u16 *msix_tbl; /* msix_tbl for uld */ 680 u16 *rspq_id; /* response queue id's of rxq */ 681 u16 nrxq; /* # of ingress uld queues */ 682 u16 nciq; /* # of completion queues */ 683 u8 uld; /* uld type */ 684 }; 685 686 struct sge_uld_txq_info { 687 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 688 atomic_t users; /* num users */ 689 u16 ntxq; /* # of egress uld queues */ 690 }; 691 692 struct sge { 693 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 694 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 695 696 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 697 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 698 struct sge_uld_rxq_info **uld_rxq_info; 699 struct sge_uld_txq_info **uld_txq_info; 700 701 struct sge_rspq intrq ____cacheline_aligned_in_smp; 702 spinlock_t intrq_lock; 703 704 u16 max_ethqsets; /* # of available Ethernet queue sets */ 705 u16 ethqsets; /* # of active Ethernet queue sets */ 706 u16 ethtxq_rover; /* Tx queue to clean up next */ 707 u16 ofldqsets; /* # of active ofld queue sets */ 708 u16 nqs_per_uld; /* # of Rx queues per ULD */ 709 u16 timer_val[SGE_NTIMERS]; 710 u8 counter_val[SGE_NCOUNTERS]; 711 u32 fl_pg_order; /* large page allocation size */ 712 u32 stat_len; /* length of status page at ring end */ 713 u32 pktshift; /* padding between CPL & packet data */ 714 u32 fl_align; /* response queue message alignment */ 715 u32 fl_starve_thres; /* Free List starvation threshold */ 716 717 struct sge_idma_monitor_state idma_monitor; 718 unsigned int egr_start; 719 unsigned int egr_sz; 720 unsigned int ingr_start; 721 unsigned int ingr_sz; 722 void **egr_map; /* qid->queue egress queue map */ 723 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 724 unsigned long *starving_fl; 725 unsigned long *txq_maperr; 726 unsigned long *blocked_fl; 727 struct timer_list rx_timer; /* refills starving FLs */ 728 struct timer_list tx_timer; /* checks Tx queues */ 729 }; 730 731 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 732 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 733 734 struct l2t_data; 735 736 #ifdef CONFIG_PCI_IOV 737 738 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 739 * Configuration initialization for T5 only has SR-IOV functionality enabled 740 * on PF0-3 in order to simplify everything. 741 */ 742 #define NUM_OF_PF_WITH_SRIOV 4 743 744 #endif 745 746 struct doorbell_stats { 747 u32 db_drop; 748 u32 db_empty; 749 u32 db_full; 750 }; 751 752 struct hash_mac_addr { 753 struct list_head list; 754 u8 addr[ETH_ALEN]; 755 }; 756 757 struct uld_msix_bmap { 758 unsigned long *msix_bmap; 759 unsigned int mapsize; 760 spinlock_t lock; /* lock for acquiring bitmap */ 761 }; 762 763 struct uld_msix_info { 764 unsigned short vec; 765 char desc[IFNAMSIZ + 10]; 766 unsigned int idx; 767 }; 768 769 struct vf_info { 770 unsigned char vf_mac_addr[ETH_ALEN]; 771 bool pf_set_mac; 772 }; 773 774 struct mbox_list { 775 struct list_head list; 776 }; 777 778 struct adapter { 779 void __iomem *regs; 780 void __iomem *bar2; 781 u32 t4_bar0; 782 struct pci_dev *pdev; 783 struct device *pdev_dev; 784 const char *name; 785 unsigned int mbox; 786 unsigned int pf; 787 unsigned int flags; 788 unsigned int adap_idx; 789 enum chip_type chip; 790 791 int msg_enable; 792 793 struct adapter_params params; 794 struct cxgb4_virt_res vres; 795 unsigned int swintr; 796 797 struct { 798 unsigned short vec; 799 char desc[IFNAMSIZ + 10]; 800 } msix_info[MAX_INGQ + 1]; 801 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 802 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 803 int msi_idx; 804 805 struct doorbell_stats db_stats; 806 struct sge sge; 807 808 struct net_device *port[MAX_NPORTS]; 809 u8 chan_map[NCHAN]; /* channel -> port map */ 810 811 struct vf_info *vfinfo; 812 u8 num_vfs; 813 814 u32 filter_mode; 815 unsigned int l2t_start; 816 unsigned int l2t_end; 817 struct l2t_data *l2t; 818 unsigned int clipt_start; 819 unsigned int clipt_end; 820 struct clip_tbl *clipt; 821 struct cxgb4_uld_info *uld; 822 void *uld_handle[CXGB4_ULD_MAX]; 823 unsigned int num_uld; 824 unsigned int num_ofld_uld; 825 struct list_head list_node; 826 struct list_head rcu_node; 827 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 828 829 void *iscsi_ppm; 830 831 struct tid_info tids; 832 void **tid_release_head; 833 spinlock_t tid_release_lock; 834 struct workqueue_struct *workq; 835 struct work_struct tid_release_task; 836 struct work_struct db_full_task; 837 struct work_struct db_drop_task; 838 bool tid_release_task_busy; 839 840 /* lock for mailbox cmd list */ 841 spinlock_t mbox_lock; 842 struct mbox_list mlist; 843 844 /* support for mailbox command/reply logging */ 845 #define T4_OS_LOG_MBOX_CMDS 256 846 struct mbox_cmd_log *mbox_log; 847 848 struct mutex uld_mutex; 849 850 struct dentry *debugfs_root; 851 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 852 bool trace_rss; /* 1 implies that different RSS flit per filter is 853 * used per filter else if 0 default RSS flit is 854 * used for all 4 filters. 855 */ 856 857 spinlock_t stats_lock; 858 spinlock_t win0_lock ____cacheline_aligned_in_smp; 859 860 /* TC u32 offload */ 861 struct cxgb4_tc_u32_table *tc_u32; 862 }; 863 864 /* Support for "sched-class" command to allow a TX Scheduling Class to be 865 * programmed with various parameters. 866 */ 867 struct ch_sched_params { 868 s8 type; /* packet or flow */ 869 union { 870 struct { 871 s8 level; /* scheduler hierarchy level */ 872 s8 mode; /* per-class or per-flow */ 873 s8 rateunit; /* bit or packet rate */ 874 s8 ratemode; /* %port relative or kbps absolute */ 875 s8 channel; /* scheduler channel [0..N] */ 876 s8 class; /* scheduler class [0..N] */ 877 s32 minrate; /* minimum rate */ 878 s32 maxrate; /* maximum rate */ 879 s16 weight; /* percent weight */ 880 s16 pktsize; /* average packet size */ 881 } params; 882 } u; 883 }; 884 885 enum { 886 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 887 }; 888 889 enum { 890 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 891 }; 892 893 enum { 894 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 895 }; 896 897 enum { 898 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 899 }; 900 901 enum { 902 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 903 }; 904 905 /* Support for "sched_queue" command to allow one or more NIC TX Queues 906 * to be bound to a TX Scheduling Class. 907 */ 908 struct ch_sched_queue { 909 s8 queue; /* queue index */ 910 s8 class; /* class index */ 911 }; 912 913 /* Defined bit width of user definable filter tuples 914 */ 915 #define ETHTYPE_BITWIDTH 16 916 #define FRAG_BITWIDTH 1 917 #define MACIDX_BITWIDTH 9 918 #define FCOE_BITWIDTH 1 919 #define IPORT_BITWIDTH 3 920 #define MATCHTYPE_BITWIDTH 3 921 #define PROTO_BITWIDTH 8 922 #define TOS_BITWIDTH 8 923 #define PF_BITWIDTH 8 924 #define VF_BITWIDTH 8 925 #define IVLAN_BITWIDTH 16 926 #define OVLAN_BITWIDTH 16 927 928 /* Filter matching rules. These consist of a set of ingress packet field 929 * (value, mask) tuples. The associated ingress packet field matches the 930 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 931 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 932 * matches an ingress packet when all of the individual individual field 933 * matching rules are true. 934 * 935 * Partial field masks are always valid, however, while it may be easy to 936 * understand their meanings for some fields (e.g. IP address to match a 937 * subnet), for others making sensible partial masks is less intuitive (e.g. 938 * MPS match type) ... 939 * 940 * Most of the following data structures are modeled on T4 capabilities. 941 * Drivers for earlier chips use the subsets which make sense for those chips. 942 * We really need to come up with a hardware-independent mechanism to 943 * represent hardware filter capabilities ... 944 */ 945 struct ch_filter_tuple { 946 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 947 * register selects which of these fields will participate in the 948 * filter match rules -- up to a maximum of 36 bits. Because 949 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 950 * set of fields. 951 */ 952 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 953 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 954 uint32_t ivlan_vld:1; /* inner VLAN valid */ 955 uint32_t ovlan_vld:1; /* outer VLAN valid */ 956 uint32_t pfvf_vld:1; /* PF/VF valid */ 957 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 958 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 959 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 960 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 961 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 962 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 963 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 964 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 965 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 966 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 967 968 /* Uncompressed header matching field rules. These are always 969 * available for field rules. 970 */ 971 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 972 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 973 uint16_t lport; /* local port */ 974 uint16_t fport; /* foreign port */ 975 }; 976 977 /* A filter ioctl command. 978 */ 979 struct ch_filter_specification { 980 /* Administrative fields for filter. 981 */ 982 uint32_t hitcnts:1; /* count filter hits in TCB */ 983 uint32_t prio:1; /* filter has priority over active/server */ 984 985 /* Fundamental filter typing. This is the one element of filter 986 * matching that doesn't exist as a (value, mask) tuple. 987 */ 988 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 989 990 /* Packet dispatch information. Ingress packets which match the 991 * filter rules will be dropped, passed to the host or switched back 992 * out as egress packets. 993 */ 994 uint32_t action:2; /* drop, pass, switch */ 995 996 uint32_t rpttid:1; /* report TID in RSS hash field */ 997 998 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 999 uint32_t iq:10; /* ingress queue */ 1000 1001 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1002 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1003 /* 1 => TCB contains IQ ID */ 1004 1005 /* Switch proxy/rewrite fields. An ingress packet which matches a 1006 * filter with "switch" set will be looped back out as an egress 1007 * packet -- potentially with some Ethernet header rewriting. 1008 */ 1009 uint32_t eport:2; /* egress port to switch packet out */ 1010 uint32_t newdmac:1; /* rewrite destination MAC address */ 1011 uint32_t newsmac:1; /* rewrite source MAC address */ 1012 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1013 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1014 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1015 uint16_t vlan; /* VLAN Tag to insert */ 1016 1017 /* Filter rule value/mask pairs. 1018 */ 1019 struct ch_filter_tuple val; 1020 struct ch_filter_tuple mask; 1021 }; 1022 1023 enum { 1024 FILTER_PASS = 0, /* default */ 1025 FILTER_DROP, 1026 FILTER_SWITCH 1027 }; 1028 1029 enum { 1030 VLAN_NOCHANGE = 0, /* default */ 1031 VLAN_REMOVE, 1032 VLAN_INSERT, 1033 VLAN_REWRITE 1034 }; 1035 1036 /* Host shadow copy of ingress filter entry. This is in host native format 1037 * and doesn't match the ordering or bit order, etc. of the hardware of the 1038 * firmware command. The use of bit-field structure elements is purely to 1039 * remind ourselves of the field size limitations and save memory in the case 1040 * where the filter table is large. 1041 */ 1042 struct filter_entry { 1043 /* Administrative fields for filter. */ 1044 u32 valid:1; /* filter allocated and valid */ 1045 u32 locked:1; /* filter is administratively locked */ 1046 1047 u32 pending:1; /* filter action is pending firmware reply */ 1048 u32 smtidx:8; /* Source MAC Table index for smac */ 1049 struct filter_ctx *ctx; /* Caller's completion hook */ 1050 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1051 struct net_device *dev; /* Associated net device */ 1052 u32 tid; /* This will store the actual tid */ 1053 1054 /* The filter itself. Most of this is a straight copy of information 1055 * provided by the extended ioctl(). Some fields are translated to 1056 * internal forms -- for instance the Ingress Queue ID passed in from 1057 * the ioctl() is translated into the Absolute Ingress Queue ID. 1058 */ 1059 struct ch_filter_specification fs; 1060 }; 1061 1062 static inline int is_offload(const struct adapter *adap) 1063 { 1064 return adap->params.offload; 1065 } 1066 1067 static inline int is_pci_uld(const struct adapter *adap) 1068 { 1069 return adap->params.crypto; 1070 } 1071 1072 static inline int is_uld(const struct adapter *adap) 1073 { 1074 return (adap->params.offload || adap->params.crypto); 1075 } 1076 1077 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1078 { 1079 return readl(adap->regs + reg_addr); 1080 } 1081 1082 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1083 { 1084 writel(val, adap->regs + reg_addr); 1085 } 1086 1087 #ifndef readq 1088 static inline u64 readq(const volatile void __iomem *addr) 1089 { 1090 return readl(addr) + ((u64)readl(addr + 4) << 32); 1091 } 1092 1093 static inline void writeq(u64 val, volatile void __iomem *addr) 1094 { 1095 writel(val, addr); 1096 writel(val >> 32, addr + 4); 1097 } 1098 #endif 1099 1100 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1101 { 1102 return readq(adap->regs + reg_addr); 1103 } 1104 1105 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1106 { 1107 writeq(val, adap->regs + reg_addr); 1108 } 1109 1110 /** 1111 * t4_set_hw_addr - store a port's MAC address in SW 1112 * @adapter: the adapter 1113 * @port_idx: the port index 1114 * @hw_addr: the Ethernet address 1115 * 1116 * Store the Ethernet address of the given port in SW. Called by the common 1117 * code when it retrieves a port's Ethernet address from EEPROM. 1118 */ 1119 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1120 u8 hw_addr[]) 1121 { 1122 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1123 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1124 } 1125 1126 /** 1127 * netdev2pinfo - return the port_info structure associated with a net_device 1128 * @dev: the netdev 1129 * 1130 * Return the struct port_info associated with a net_device 1131 */ 1132 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1133 { 1134 return netdev_priv(dev); 1135 } 1136 1137 /** 1138 * adap2pinfo - return the port_info of a port 1139 * @adap: the adapter 1140 * @idx: the port index 1141 * 1142 * Return the port_info structure for the port of the given index. 1143 */ 1144 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1145 { 1146 return netdev_priv(adap->port[idx]); 1147 } 1148 1149 /** 1150 * netdev2adap - return the adapter structure associated with a net_device 1151 * @dev: the netdev 1152 * 1153 * Return the struct adapter associated with a net_device 1154 */ 1155 static inline struct adapter *netdev2adap(const struct net_device *dev) 1156 { 1157 return netdev2pinfo(dev)->adapter; 1158 } 1159 1160 /* Return a version number to identify the type of adapter. The scheme is: 1161 * - bits 0..9: chip version 1162 * - bits 10..15: chip revision 1163 * - bits 16..23: register dump version 1164 */ 1165 static inline unsigned int mk_adap_vers(struct adapter *ap) 1166 { 1167 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1168 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1169 } 1170 1171 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1172 static inline unsigned int qtimer_val(const struct adapter *adap, 1173 const struct sge_rspq *q) 1174 { 1175 unsigned int idx = q->intr_params >> 1; 1176 1177 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1178 } 1179 1180 /* driver version & name used for ethtool_drvinfo */ 1181 extern char cxgb4_driver_name[]; 1182 extern const char cxgb4_driver_version[]; 1183 1184 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1185 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1186 1187 void *t4_alloc_mem(size_t size); 1188 1189 void t4_free_sge_resources(struct adapter *adap); 1190 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1191 irq_handler_t t4_intr_handler(struct adapter *adap); 1192 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1193 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1194 const struct pkt_gl *gl); 1195 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1196 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1197 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1198 struct net_device *dev, int intr_idx, 1199 struct sge_fl *fl, rspq_handler_t hnd, 1200 rspq_flush_handler_t flush_handler, int cong); 1201 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1202 struct net_device *dev, struct netdev_queue *netdevq, 1203 unsigned int iqid); 1204 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1205 struct net_device *dev, unsigned int iqid, 1206 unsigned int cmplqid); 1207 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1208 unsigned int cmplqid); 1209 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1210 struct net_device *dev, unsigned int iqid, 1211 unsigned int uld_type); 1212 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1213 int t4_sge_init(struct adapter *adap); 1214 void t4_sge_start(struct adapter *adap); 1215 void t4_sge_stop(struct adapter *adap); 1216 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1217 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1218 extern int dbfifo_int_thresh; 1219 1220 #define for_each_port(adapter, iter) \ 1221 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1222 1223 static inline int is_bypass(struct adapter *adap) 1224 { 1225 return adap->params.bypass; 1226 } 1227 1228 static inline int is_bypass_device(int device) 1229 { 1230 /* this should be set based upon device capabilities */ 1231 switch (device) { 1232 case 0x440b: 1233 case 0x440c: 1234 return 1; 1235 default: 1236 return 0; 1237 } 1238 } 1239 1240 static inline int is_10gbt_device(int device) 1241 { 1242 /* this should be set based upon device capabilities */ 1243 switch (device) { 1244 case 0x4409: 1245 case 0x4486: 1246 return 1; 1247 1248 default: 1249 return 0; 1250 } 1251 } 1252 1253 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1254 { 1255 return adap->params.vpd.cclk / 1000; 1256 } 1257 1258 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1259 unsigned int us) 1260 { 1261 return (us * adap->params.vpd.cclk) / 1000; 1262 } 1263 1264 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1265 unsigned int ticks) 1266 { 1267 /* add Core Clock / 2 to round ticks to nearest uS */ 1268 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1269 adapter->params.vpd.cclk); 1270 } 1271 1272 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1273 u32 val); 1274 1275 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1276 int size, void *rpl, bool sleep_ok, int timeout); 1277 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1278 void *rpl, bool sleep_ok); 1279 1280 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1281 const void *cmd, int size, void *rpl, 1282 int timeout) 1283 { 1284 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1285 timeout); 1286 } 1287 1288 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1289 int size, void *rpl) 1290 { 1291 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1292 } 1293 1294 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1295 int size, void *rpl) 1296 { 1297 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1298 } 1299 1300 /** 1301 * hash_mac_addr - return the hash value of a MAC address 1302 * @addr: the 48-bit Ethernet MAC address 1303 * 1304 * Hashes a MAC address according to the hash function used by HW inexact 1305 * (hash) address matching. 1306 */ 1307 static inline int hash_mac_addr(const u8 *addr) 1308 { 1309 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1310 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1311 1312 a ^= b; 1313 a ^= (a >> 12); 1314 a ^= (a >> 6); 1315 return a & 0x3f; 1316 } 1317 1318 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1319 unsigned int cnt); 1320 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1321 unsigned int us, unsigned int cnt, 1322 unsigned int size, unsigned int iqe_size) 1323 { 1324 q->adap = adap; 1325 cxgb4_set_rspq_intr_params(q, us, cnt); 1326 q->iqe_len = iqe_size; 1327 q->size = size; 1328 } 1329 1330 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1331 unsigned int data_reg, const u32 *vals, 1332 unsigned int nregs, unsigned int start_idx); 1333 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1334 unsigned int data_reg, u32 *vals, unsigned int nregs, 1335 unsigned int start_idx); 1336 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1337 1338 struct fw_filter_wr; 1339 1340 void t4_intr_enable(struct adapter *adapter); 1341 void t4_intr_disable(struct adapter *adapter); 1342 int t4_slow_intr_handler(struct adapter *adapter); 1343 1344 int t4_wait_dev_ready(void __iomem *regs); 1345 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1346 struct link_config *lc); 1347 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1348 1349 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1350 u32 t4_get_util_window(struct adapter *adap); 1351 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1352 1353 #define T4_MEMORY_WRITE 0 1354 #define T4_MEMORY_READ 1 1355 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1356 void *buf, int dir); 1357 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1358 u32 len, __be32 *buf) 1359 { 1360 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1361 } 1362 1363 unsigned int t4_get_regs_len(struct adapter *adapter); 1364 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1365 1366 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1367 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1368 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1369 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1370 unsigned int nwords, u32 *data, int byte_oriented); 1371 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1372 int t4_load_phy_fw(struct adapter *adap, 1373 int win, spinlock_t *lock, 1374 int (*phy_fw_version)(const u8 *, size_t), 1375 const u8 *phy_fw_data, size_t phy_fw_size); 1376 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1377 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1378 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1379 const u8 *fw_data, unsigned int size, int force); 1380 int t4_fl_pkt_align(struct adapter *adap); 1381 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1382 int t4_check_fw_version(struct adapter *adap); 1383 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1384 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1385 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1386 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1387 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1388 const u8 *fw_data, unsigned int fw_size, 1389 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1390 int t4_prep_adapter(struct adapter *adapter); 1391 int t4_shutdown_adapter(struct adapter *adapter); 1392 1393 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1394 int t4_bar2_sge_qregs(struct adapter *adapter, 1395 unsigned int qid, 1396 enum t4_bar2_qtype qtype, 1397 int user, 1398 u64 *pbar2_qoffset, 1399 unsigned int *pbar2_qid); 1400 1401 unsigned int qtimer_val(const struct adapter *adap, 1402 const struct sge_rspq *q); 1403 1404 int t4_init_devlog_params(struct adapter *adapter); 1405 int t4_init_sge_params(struct adapter *adapter); 1406 int t4_init_tp_params(struct adapter *adap); 1407 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1408 int t4_init_rss_mode(struct adapter *adap, int mbox); 1409 int t4_init_portinfo(struct port_info *pi, int mbox, 1410 int port, int pf, int vf, u8 mac[]); 1411 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1412 void t4_fatal_err(struct adapter *adapter); 1413 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1414 int start, int n, const u16 *rspq, unsigned int nrspq); 1415 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1416 unsigned int flags); 1417 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1418 unsigned int flags, unsigned int defq); 1419 int t4_read_rss(struct adapter *adapter, u16 *entries); 1420 void t4_read_rss_key(struct adapter *adapter, u32 *key); 1421 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1422 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1423 u32 *valp); 1424 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1425 u32 *vfl, u32 *vfh); 1426 u32 t4_read_rss_pf_map(struct adapter *adapter); 1427 u32 t4_read_rss_pf_mask(struct adapter *adapter); 1428 1429 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1430 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1431 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1432 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1433 size_t n); 1434 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1435 size_t n); 1436 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1437 unsigned int *valp); 1438 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1439 const unsigned int *valp); 1440 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1441 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1442 unsigned int *pif_req_wrptr, 1443 unsigned int *pif_rsp_wrptr); 1444 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1445 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1446 const char *t4_get_port_type_description(enum fw_port_type port_type); 1447 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1448 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1449 struct port_stats *stats, 1450 struct port_stats *offset); 1451 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1452 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1453 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1454 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1455 unsigned int mask, unsigned int val); 1456 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1457 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1458 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1459 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1460 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1461 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1462 struct tp_tcp_stats *v6); 1463 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1464 struct tp_fcoe_stats *st); 1465 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1466 const unsigned short *alpha, const unsigned short *beta); 1467 1468 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1469 1470 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1471 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1472 1473 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1474 const u8 *addr); 1475 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1476 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1477 1478 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1479 enum dev_master master, enum dev_state *state); 1480 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1481 int t4_early_init(struct adapter *adap, unsigned int mbox); 1482 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1483 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1484 unsigned int cache_line_size); 1485 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1486 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1487 unsigned int vf, unsigned int nparams, const u32 *params, 1488 u32 *val); 1489 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1490 unsigned int vf, unsigned int nparams, const u32 *params, 1491 u32 *val, int rw); 1492 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1493 unsigned int pf, unsigned int vf, 1494 unsigned int nparams, const u32 *params, 1495 const u32 *val, int timeout); 1496 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1497 unsigned int vf, unsigned int nparams, const u32 *params, 1498 const u32 *val); 1499 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1500 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1501 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1502 unsigned int vi, unsigned int cmask, unsigned int pmask, 1503 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1504 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1505 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1506 unsigned int *rss_size); 1507 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1508 unsigned int pf, unsigned int vf, 1509 unsigned int viid); 1510 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1511 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1512 bool sleep_ok); 1513 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1514 unsigned int viid, bool free, unsigned int naddr, 1515 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1516 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1517 unsigned int viid, unsigned int naddr, 1518 const u8 **addr, bool sleep_ok); 1519 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1520 int idx, const u8 *addr, bool persist, bool add_smt); 1521 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1522 bool ucast, u64 vec, bool sleep_ok); 1523 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1524 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1525 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1526 bool rx_en, bool tx_en); 1527 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1528 unsigned int nblinks); 1529 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1530 unsigned int mmd, unsigned int reg, u16 *valp); 1531 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1532 unsigned int mmd, unsigned int reg, u16 val); 1533 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1534 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1535 unsigned int fl0id, unsigned int fl1id); 1536 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1537 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1538 unsigned int fl0id, unsigned int fl1id); 1539 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1540 unsigned int vf, unsigned int eqid); 1541 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1542 unsigned int vf, unsigned int eqid); 1543 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1544 unsigned int vf, unsigned int eqid); 1545 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1546 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1547 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1548 void t4_db_full(struct adapter *adapter); 1549 void t4_db_dropped(struct adapter *adapter); 1550 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1551 int filter_index, int enable); 1552 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1553 int filter_index, int *enabled); 1554 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1555 u32 addr, u32 val); 1556 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1557 int rateunit, int ratemode, int channel, int class, 1558 int minrate, int maxrate, int weight, int pktsize); 1559 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1560 void t4_free_mem(void *addr); 1561 void t4_idma_monitor_init(struct adapter *adapter, 1562 struct sge_idma_monitor_state *idma); 1563 void t4_idma_monitor(struct adapter *adapter, 1564 struct sge_idma_monitor_state *idma, 1565 int hz, int ticks); 1566 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1567 unsigned int naddr, u8 *addr); 1568 void t4_uld_mem_free(struct adapter *adap); 1569 int t4_uld_mem_alloc(struct adapter *adap); 1570 void t4_uld_clean_up(struct adapter *adap); 1571 void t4_register_netevent_notifier(void); 1572 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1573 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1574 unsigned int n, bool unmap); 1575 void free_txq(struct adapter *adap, struct sge_txq *q); 1576 #endif /* __CXGB4_H__ */ 1577