1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <asm/io.h> 52 #include "t4_chip_type.h" 53 #include "cxgb4_uld.h" 54 55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 56 57 enum { 58 MAX_NPORTS = 4, /* max # of ports */ 59 SERNUM_LEN = 24, /* Serial # length */ 60 EC_LEN = 16, /* E/C length */ 61 ID_LEN = 16, /* ID length */ 62 PN_LEN = 16, /* Part Number length */ 63 MACADDR_LEN = 12, /* MAC Address length */ 64 }; 65 66 enum { 67 T4_REGMAP_SIZE = (160 * 1024), 68 T5_REGMAP_SIZE = (332 * 1024), 69 }; 70 71 enum { 72 MEM_EDC0, 73 MEM_EDC1, 74 MEM_MC, 75 MEM_MC0 = MEM_MC, 76 MEM_MC1 77 }; 78 79 enum { 80 MEMWIN0_APERTURE = 2048, 81 MEMWIN0_BASE = 0x1b800, 82 MEMWIN1_APERTURE = 32768, 83 MEMWIN1_BASE = 0x28000, 84 MEMWIN1_BASE_T5 = 0x52000, 85 MEMWIN2_APERTURE = 65536, 86 MEMWIN2_BASE = 0x30000, 87 MEMWIN2_APERTURE_T5 = 131072, 88 MEMWIN2_BASE_T5 = 0x60000, 89 }; 90 91 enum dev_master { 92 MASTER_CANT, 93 MASTER_MAY, 94 MASTER_MUST 95 }; 96 97 enum dev_state { 98 DEV_STATE_UNINIT, 99 DEV_STATE_INIT, 100 DEV_STATE_ERR 101 }; 102 103 enum { 104 PAUSE_RX = 1 << 0, 105 PAUSE_TX = 1 << 1, 106 PAUSE_AUTONEG = 1 << 2 107 }; 108 109 struct port_stats { 110 u64 tx_octets; /* total # of octets in good frames */ 111 u64 tx_frames; /* all good frames */ 112 u64 tx_bcast_frames; /* all broadcast frames */ 113 u64 tx_mcast_frames; /* all multicast frames */ 114 u64 tx_ucast_frames; /* all unicast frames */ 115 u64 tx_error_frames; /* all error frames */ 116 117 u64 tx_frames_64; /* # of Tx frames in a particular range */ 118 u64 tx_frames_65_127; 119 u64 tx_frames_128_255; 120 u64 tx_frames_256_511; 121 u64 tx_frames_512_1023; 122 u64 tx_frames_1024_1518; 123 u64 tx_frames_1519_max; 124 125 u64 tx_drop; /* # of dropped Tx frames */ 126 u64 tx_pause; /* # of transmitted pause frames */ 127 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 128 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 129 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 130 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 131 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 132 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 133 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 134 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 135 136 u64 rx_octets; /* total # of octets in good frames */ 137 u64 rx_frames; /* all good frames */ 138 u64 rx_bcast_frames; /* all broadcast frames */ 139 u64 rx_mcast_frames; /* all multicast frames */ 140 u64 rx_ucast_frames; /* all unicast frames */ 141 u64 rx_too_long; /* # of frames exceeding MTU */ 142 u64 rx_jabber; /* # of jabber frames */ 143 u64 rx_fcs_err; /* # of received frames with bad FCS */ 144 u64 rx_len_err; /* # of received frames with length error */ 145 u64 rx_symbol_err; /* symbol errors */ 146 u64 rx_runt; /* # of short frames */ 147 148 u64 rx_frames_64; /* # of Rx frames in a particular range */ 149 u64 rx_frames_65_127; 150 u64 rx_frames_128_255; 151 u64 rx_frames_256_511; 152 u64 rx_frames_512_1023; 153 u64 rx_frames_1024_1518; 154 u64 rx_frames_1519_max; 155 156 u64 rx_pause; /* # of received pause frames */ 157 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 158 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 159 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 160 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 161 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 162 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 163 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 164 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 165 166 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 167 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 168 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 169 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 170 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 171 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 172 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 173 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 174 }; 175 176 struct lb_port_stats { 177 u64 octets; 178 u64 frames; 179 u64 bcast_frames; 180 u64 mcast_frames; 181 u64 ucast_frames; 182 u64 error_frames; 183 184 u64 frames_64; 185 u64 frames_65_127; 186 u64 frames_128_255; 187 u64 frames_256_511; 188 u64 frames_512_1023; 189 u64 frames_1024_1518; 190 u64 frames_1519_max; 191 192 u64 drop; 193 194 u64 ovflow0; 195 u64 ovflow1; 196 u64 ovflow2; 197 u64 ovflow3; 198 u64 trunc0; 199 u64 trunc1; 200 u64 trunc2; 201 u64 trunc3; 202 }; 203 204 struct tp_tcp_stats { 205 u32 tcp_out_rsts; 206 u64 tcp_in_segs; 207 u64 tcp_out_segs; 208 u64 tcp_retrans_segs; 209 }; 210 211 struct tp_usm_stats { 212 u32 frames; 213 u32 drops; 214 u64 octets; 215 }; 216 217 struct tp_fcoe_stats { 218 u32 frames_ddp; 219 u32 frames_drop; 220 u64 octets_ddp; 221 }; 222 223 struct tp_err_stats { 224 u32 mac_in_errs[4]; 225 u32 hdr_in_errs[4]; 226 u32 tcp_in_errs[4]; 227 u32 tnl_cong_drops[4]; 228 u32 ofld_chan_drops[4]; 229 u32 tnl_tx_drops[4]; 230 u32 ofld_vlan_drops[4]; 231 u32 tcp6_in_errs[4]; 232 u32 ofld_no_neigh; 233 u32 ofld_cong_defer; 234 }; 235 236 struct tp_cpl_stats { 237 u32 req[4]; 238 u32 rsp[4]; 239 }; 240 241 struct tp_rdma_stats { 242 u32 rqe_dfr_pkt; 243 u32 rqe_dfr_mod; 244 }; 245 246 struct sge_params { 247 u32 hps; /* host page size for our PF/VF */ 248 u32 eq_qpp; /* egress queues/page for our PF/VF */ 249 u32 iq_qpp; /* egress queues/page for our PF/VF */ 250 }; 251 252 struct tp_params { 253 unsigned int tre; /* log2 of core clocks per TP tick */ 254 unsigned int la_mask; /* what events are recorded by TP LA */ 255 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 256 /* channel map */ 257 258 uint32_t dack_re; /* DACK timer resolution */ 259 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 260 261 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 262 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 263 264 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 265 * subset of the set of fields which may be present in the Compressed 266 * Filter Tuple portion of filters and TCP TCB connections. The 267 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 268 * Since a variable number of fields may or may not be present, their 269 * shifted field positions within the Compressed Filter Tuple may 270 * vary, or not even be present if the field isn't selected in 271 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 272 * places we store their offsets here, or a -1 if the field isn't 273 * present. 274 */ 275 int vlan_shift; 276 int vnic_shift; 277 int port_shift; 278 int protocol_shift; 279 }; 280 281 struct vpd_params { 282 unsigned int cclk; 283 u8 ec[EC_LEN + 1]; 284 u8 sn[SERNUM_LEN + 1]; 285 u8 id[ID_LEN + 1]; 286 u8 pn[PN_LEN + 1]; 287 u8 na[MACADDR_LEN + 1]; 288 }; 289 290 struct pci_params { 291 unsigned char speed; 292 unsigned char width; 293 }; 294 295 struct devlog_params { 296 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 297 u32 start; /* start of log in firmware memory */ 298 u32 size; /* size of log */ 299 }; 300 301 /* Stores chip specific parameters */ 302 struct arch_specific_params { 303 u8 nchan; 304 u8 pm_stats_cnt; 305 u8 cng_ch_bits_log; /* congestion channel map bits width */ 306 u16 mps_rplc_size; 307 u16 vfcount; 308 u32 sge_fl_db; 309 u16 mps_tcam_size; 310 }; 311 312 struct adapter_params { 313 struct sge_params sge; 314 struct tp_params tp; 315 struct vpd_params vpd; 316 struct pci_params pci; 317 struct devlog_params devlog; 318 enum pcie_memwin drv_memwin; 319 320 unsigned int cim_la_size; 321 322 unsigned int sf_size; /* serial flash size in bytes */ 323 unsigned int sf_nsec; /* # of flash sectors */ 324 unsigned int sf_fw_start; /* start of FW image in flash */ 325 326 unsigned int fw_vers; 327 unsigned int tp_vers; 328 u8 api_vers[7]; 329 330 unsigned short mtus[NMTUS]; 331 unsigned short a_wnd[NCCTRL_WIN]; 332 unsigned short b_wnd[NCCTRL_WIN]; 333 334 unsigned char nports; /* # of ethernet ports */ 335 unsigned char portvec; 336 enum chip_type chip; /* chip code */ 337 struct arch_specific_params arch; /* chip specific params */ 338 unsigned char offload; 339 340 unsigned char bypass; 341 342 unsigned int ofldq_wr_cred; 343 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 344 345 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 346 unsigned int max_ird_adapter; /* Max read depth per adapter */ 347 }; 348 349 /* State needed to monitor the forward progress of SGE Ingress DMA activities 350 * and possible hangs. 351 */ 352 struct sge_idma_monitor_state { 353 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 354 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 355 unsigned int idma_state[2]; /* IDMA Hang detect state */ 356 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 357 unsigned int idma_warn[2]; /* time to warning in HZ */ 358 }; 359 360 #include "t4fw_api.h" 361 362 #define FW_VERSION(chip) ( \ 363 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 364 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 365 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 366 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 367 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 368 369 struct fw_info { 370 u8 chip; 371 char *fs_name; 372 char *fw_mod_name; 373 struct fw_hdr fw_hdr; 374 }; 375 376 377 struct trace_params { 378 u32 data[TRACE_LEN / 4]; 379 u32 mask[TRACE_LEN / 4]; 380 unsigned short snap_len; 381 unsigned short min_len; 382 unsigned char skip_ofst; 383 unsigned char skip_len; 384 unsigned char invert; 385 unsigned char port; 386 }; 387 388 struct link_config { 389 unsigned short supported; /* link capabilities */ 390 unsigned short advertising; /* advertised capabilities */ 391 unsigned short requested_speed; /* speed user has requested */ 392 unsigned short speed; /* actual link speed */ 393 unsigned char requested_fc; /* flow control user has requested */ 394 unsigned char fc; /* actual link flow control */ 395 unsigned char autoneg; /* autonegotiating? */ 396 unsigned char link_ok; /* link up? */ 397 }; 398 399 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 400 401 enum { 402 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 403 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 404 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 405 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 406 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ 407 408 /* # of streaming iSCSIT Rx queues */ 409 MAX_ISCSIT_QUEUES = MAX_OFLD_QSETS, 410 }; 411 412 enum { 413 MAX_TXQ_ENTRIES = 16384, 414 MAX_CTRL_TXQ_ENTRIES = 1024, 415 MAX_RSPQ_ENTRIES = 16384, 416 MAX_RX_BUFFERS = 16384, 417 MIN_TXQ_ENTRIES = 32, 418 MIN_CTRL_TXQ_ENTRIES = 32, 419 MIN_RSPQ_ENTRIES = 128, 420 MIN_FL_ENTRIES = 16 421 }; 422 423 enum { 424 INGQ_EXTRAS = 2, /* firmware event queue and */ 425 /* forwarded interrupts */ 426 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES + 427 MAX_RDMA_CIQS + MAX_ISCSIT_QUEUES + INGQ_EXTRAS, 428 }; 429 430 struct adapter; 431 struct sge_rspq; 432 433 #include "cxgb4_dcb.h" 434 435 #ifdef CONFIG_CHELSIO_T4_FCOE 436 #include "cxgb4_fcoe.h" 437 #endif /* CONFIG_CHELSIO_T4_FCOE */ 438 439 struct port_info { 440 struct adapter *adapter; 441 u16 viid; 442 s16 xact_addr_filt; /* index of exact MAC address filter */ 443 u16 rss_size; /* size of VI's RSS table slice */ 444 s8 mdio_addr; 445 enum fw_port_type port_type; 446 u8 mod_type; 447 u8 port_id; 448 u8 tx_chan; 449 u8 lport; /* associated offload logical port */ 450 u8 nqsets; /* # of qsets */ 451 u8 first_qset; /* index of first qset */ 452 u8 rss_mode; 453 struct link_config link_cfg; 454 u16 *rss; 455 struct port_stats stats_base; 456 #ifdef CONFIG_CHELSIO_T4_DCB 457 struct port_dcb_info dcb; /* Data Center Bridging support */ 458 #endif 459 #ifdef CONFIG_CHELSIO_T4_FCOE 460 struct cxgb_fcoe fcoe; 461 #endif /* CONFIG_CHELSIO_T4_FCOE */ 462 bool rxtstamp; /* Enable TS */ 463 struct hwtstamp_config tstamp_config; 464 }; 465 466 struct dentry; 467 struct work_struct; 468 469 enum { /* adapter flags */ 470 FULL_INIT_DONE = (1 << 0), 471 DEV_ENABLED = (1 << 1), 472 USING_MSI = (1 << 2), 473 USING_MSIX = (1 << 3), 474 FW_OK = (1 << 4), 475 RSS_TNLALLLOOKUP = (1 << 5), 476 USING_SOFT_PARAMS = (1 << 6), 477 MASTER_PF = (1 << 7), 478 FW_OFLD_CONN = (1 << 9), 479 }; 480 481 struct rx_sw_desc; 482 483 struct sge_fl { /* SGE free-buffer queue state */ 484 unsigned int avail; /* # of available Rx buffers */ 485 unsigned int pend_cred; /* new buffers since last FL DB ring */ 486 unsigned int cidx; /* consumer index */ 487 unsigned int pidx; /* producer index */ 488 unsigned long alloc_failed; /* # of times buffer allocation failed */ 489 unsigned long large_alloc_failed; 490 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 491 unsigned long low; /* # of times momentarily starving */ 492 unsigned long starving; 493 /* RO fields */ 494 unsigned int cntxt_id; /* SGE context id for the free list */ 495 unsigned int size; /* capacity of free list */ 496 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 497 __be64 *desc; /* address of HW Rx descriptor ring */ 498 dma_addr_t addr; /* bus address of HW ring start */ 499 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 500 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 501 }; 502 503 /* A packet gather list */ 504 struct pkt_gl { 505 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 506 struct page_frag frags[MAX_SKB_FRAGS]; 507 void *va; /* virtual address of first byte */ 508 unsigned int nfrags; /* # of fragments */ 509 unsigned int tot_len; /* total length of fragments */ 510 }; 511 512 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 513 const struct pkt_gl *gl); 514 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 515 /* LRO related declarations for ULD */ 516 struct t4_lro_mgr { 517 #define MAX_LRO_SESSIONS 64 518 u8 lro_session_cnt; /* # of sessions to aggregate */ 519 unsigned long lro_pkts; /* # of LRO super packets */ 520 unsigned long lro_merged; /* # of wire packets merged by LRO */ 521 struct sk_buff_head lroq; /* list of aggregated sessions */ 522 }; 523 524 struct sge_rspq { /* state for an SGE response queue */ 525 struct napi_struct napi; 526 const __be64 *cur_desc; /* current descriptor in queue */ 527 unsigned int cidx; /* consumer index */ 528 u8 gen; /* current generation bit */ 529 u8 intr_params; /* interrupt holdoff parameters */ 530 u8 next_intr_params; /* holdoff params for next interrupt */ 531 u8 adaptive_rx; 532 u8 pktcnt_idx; /* interrupt packet threshold */ 533 u8 uld; /* ULD handling this queue */ 534 u8 idx; /* queue index within its group */ 535 int offset; /* offset into current Rx buffer */ 536 u16 cntxt_id; /* SGE context id for the response q */ 537 u16 abs_id; /* absolute SGE id for the response q */ 538 __be64 *desc; /* address of HW response ring */ 539 dma_addr_t phys_addr; /* physical address of the ring */ 540 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 541 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 542 unsigned int iqe_len; /* entry size */ 543 unsigned int size; /* capacity of response queue */ 544 struct adapter *adap; 545 struct net_device *netdev; /* associated net device */ 546 rspq_handler_t handler; 547 rspq_flush_handler_t flush_handler; 548 struct t4_lro_mgr lro_mgr; 549 #ifdef CONFIG_NET_RX_BUSY_POLL 550 #define CXGB_POLL_STATE_IDLE 0 551 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 552 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 553 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 554 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 555 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 556 CXGB_POLL_STATE_POLL_YIELD) 557 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 558 CXGB_POLL_STATE_POLL) 559 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 560 CXGB_POLL_STATE_POLL_YIELD) 561 unsigned int bpoll_state; 562 spinlock_t bpoll_lock; /* lock for busy poll */ 563 #endif /* CONFIG_NET_RX_BUSY_POLL */ 564 565 }; 566 567 struct sge_eth_stats { /* Ethernet queue statistics */ 568 unsigned long pkts; /* # of ethernet packets */ 569 unsigned long lro_pkts; /* # of LRO super packets */ 570 unsigned long lro_merged; /* # of wire packets merged by LRO */ 571 unsigned long rx_cso; /* # of Rx checksum offloads */ 572 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 573 unsigned long rx_drops; /* # of packets dropped due to no mem */ 574 }; 575 576 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 577 struct sge_rspq rspq; 578 struct sge_fl fl; 579 struct sge_eth_stats stats; 580 } ____cacheline_aligned_in_smp; 581 582 struct sge_ofld_stats { /* offload queue statistics */ 583 unsigned long pkts; /* # of packets */ 584 unsigned long imm; /* # of immediate-data packets */ 585 unsigned long an; /* # of asynchronous notifications */ 586 unsigned long nomem; /* # of responses deferred due to no mem */ 587 }; 588 589 struct sge_ofld_rxq { /* SW offload Rx queue */ 590 struct sge_rspq rspq; 591 struct sge_fl fl; 592 struct sge_ofld_stats stats; 593 } ____cacheline_aligned_in_smp; 594 595 struct tx_desc { 596 __be64 flit[8]; 597 }; 598 599 struct tx_sw_desc; 600 601 struct sge_txq { 602 unsigned int in_use; /* # of in-use Tx descriptors */ 603 unsigned int size; /* # of descriptors */ 604 unsigned int cidx; /* SW consumer index */ 605 unsigned int pidx; /* producer index */ 606 unsigned long stops; /* # of times q has been stopped */ 607 unsigned long restarts; /* # of queue restarts */ 608 unsigned int cntxt_id; /* SGE context id for the Tx q */ 609 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 610 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 611 struct sge_qstat *stat; /* queue status entry */ 612 dma_addr_t phys_addr; /* physical address of the ring */ 613 spinlock_t db_lock; 614 int db_disabled; 615 unsigned short db_pidx; 616 unsigned short db_pidx_inc; 617 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 618 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 619 }; 620 621 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 622 struct sge_txq q; 623 struct netdev_queue *txq; /* associated netdev TX queue */ 624 #ifdef CONFIG_CHELSIO_T4_DCB 625 u8 dcb_prio; /* DCB Priority bound to queue */ 626 #endif 627 unsigned long tso; /* # of TSO requests */ 628 unsigned long tx_cso; /* # of Tx checksum offloads */ 629 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 630 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 631 } ____cacheline_aligned_in_smp; 632 633 struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 634 struct sge_txq q; 635 struct adapter *adap; 636 struct sk_buff_head sendq; /* list of backpressured packets */ 637 struct tasklet_struct qresume_tsk; /* restarts the queue */ 638 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 639 u8 full; /* the Tx ring is full */ 640 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 641 } ____cacheline_aligned_in_smp; 642 643 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 644 struct sge_txq q; 645 struct adapter *adap; 646 struct sk_buff_head sendq; /* list of backpressured packets */ 647 struct tasklet_struct qresume_tsk; /* restarts the queue */ 648 u8 full; /* the Tx ring is full */ 649 } ____cacheline_aligned_in_smp; 650 651 struct sge { 652 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 653 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 654 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 655 656 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 657 struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS]; 658 struct sge_ofld_rxq iscsitrxq[MAX_ISCSIT_QUEUES]; 659 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 660 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 661 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 662 663 struct sge_rspq intrq ____cacheline_aligned_in_smp; 664 spinlock_t intrq_lock; 665 666 u16 max_ethqsets; /* # of available Ethernet queue sets */ 667 u16 ethqsets; /* # of active Ethernet queue sets */ 668 u16 ethtxq_rover; /* Tx queue to clean up next */ 669 u16 iscsiqsets; /* # of active iSCSI queue sets */ 670 u16 niscsitq; /* # of available iSCST Rx queues */ 671 u16 rdmaqs; /* # of available RDMA Rx queues */ 672 u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 673 u16 iscsi_rxq[MAX_OFLD_QSETS]; 674 u16 iscsit_rxq[MAX_ISCSIT_QUEUES]; 675 u16 rdma_rxq[MAX_RDMA_QUEUES]; 676 u16 rdma_ciq[MAX_RDMA_CIQS]; 677 u16 timer_val[SGE_NTIMERS]; 678 u8 counter_val[SGE_NCOUNTERS]; 679 u32 fl_pg_order; /* large page allocation size */ 680 u32 stat_len; /* length of status page at ring end */ 681 u32 pktshift; /* padding between CPL & packet data */ 682 u32 fl_align; /* response queue message alignment */ 683 u32 fl_starve_thres; /* Free List starvation threshold */ 684 685 struct sge_idma_monitor_state idma_monitor; 686 unsigned int egr_start; 687 unsigned int egr_sz; 688 unsigned int ingr_start; 689 unsigned int ingr_sz; 690 void **egr_map; /* qid->queue egress queue map */ 691 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 692 unsigned long *starving_fl; 693 unsigned long *txq_maperr; 694 unsigned long *blocked_fl; 695 struct timer_list rx_timer; /* refills starving FLs */ 696 struct timer_list tx_timer; /* checks Tx queues */ 697 }; 698 699 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 700 #define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++) 701 #define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++) 702 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 703 #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 704 705 struct l2t_data; 706 707 #ifdef CONFIG_PCI_IOV 708 709 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 710 * Configuration initialization for T5 only has SR-IOV functionality enabled 711 * on PF0-3 in order to simplify everything. 712 */ 713 #define NUM_OF_PF_WITH_SRIOV 4 714 715 #endif 716 717 struct doorbell_stats { 718 u32 db_drop; 719 u32 db_empty; 720 u32 db_full; 721 }; 722 723 struct hash_mac_addr { 724 struct list_head list; 725 u8 addr[ETH_ALEN]; 726 }; 727 728 struct adapter { 729 void __iomem *regs; 730 void __iomem *bar2; 731 u32 t4_bar0; 732 struct pci_dev *pdev; 733 struct device *pdev_dev; 734 unsigned int mbox; 735 unsigned int pf; 736 unsigned int flags; 737 enum chip_type chip; 738 739 int msg_enable; 740 741 struct adapter_params params; 742 struct cxgb4_virt_res vres; 743 unsigned int swintr; 744 745 struct { 746 unsigned short vec; 747 char desc[IFNAMSIZ + 10]; 748 } msix_info[MAX_INGQ + 1]; 749 750 struct doorbell_stats db_stats; 751 struct sge sge; 752 753 struct net_device *port[MAX_NPORTS]; 754 u8 chan_map[NCHAN]; /* channel -> port map */ 755 756 u32 filter_mode; 757 unsigned int l2t_start; 758 unsigned int l2t_end; 759 struct l2t_data *l2t; 760 unsigned int clipt_start; 761 unsigned int clipt_end; 762 struct clip_tbl *clipt; 763 void *uld_handle[CXGB4_ULD_MAX]; 764 struct list_head list_node; 765 struct list_head rcu_node; 766 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 767 768 void *iscsi_ppm; 769 770 struct tid_info tids; 771 void **tid_release_head; 772 spinlock_t tid_release_lock; 773 struct workqueue_struct *workq; 774 struct work_struct tid_release_task; 775 struct work_struct db_full_task; 776 struct work_struct db_drop_task; 777 bool tid_release_task_busy; 778 779 struct dentry *debugfs_root; 780 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 781 bool trace_rss; /* 1 implies that different RSS flit per filter is 782 * used per filter else if 0 default RSS flit is 783 * used for all 4 filters. 784 */ 785 786 spinlock_t stats_lock; 787 spinlock_t win0_lock ____cacheline_aligned_in_smp; 788 }; 789 790 /* Defined bit width of user definable filter tuples 791 */ 792 #define ETHTYPE_BITWIDTH 16 793 #define FRAG_BITWIDTH 1 794 #define MACIDX_BITWIDTH 9 795 #define FCOE_BITWIDTH 1 796 #define IPORT_BITWIDTH 3 797 #define MATCHTYPE_BITWIDTH 3 798 #define PROTO_BITWIDTH 8 799 #define TOS_BITWIDTH 8 800 #define PF_BITWIDTH 8 801 #define VF_BITWIDTH 8 802 #define IVLAN_BITWIDTH 16 803 #define OVLAN_BITWIDTH 16 804 805 /* Filter matching rules. These consist of a set of ingress packet field 806 * (value, mask) tuples. The associated ingress packet field matches the 807 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 808 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 809 * matches an ingress packet when all of the individual individual field 810 * matching rules are true. 811 * 812 * Partial field masks are always valid, however, while it may be easy to 813 * understand their meanings for some fields (e.g. IP address to match a 814 * subnet), for others making sensible partial masks is less intuitive (e.g. 815 * MPS match type) ... 816 * 817 * Most of the following data structures are modeled on T4 capabilities. 818 * Drivers for earlier chips use the subsets which make sense for those chips. 819 * We really need to come up with a hardware-independent mechanism to 820 * represent hardware filter capabilities ... 821 */ 822 struct ch_filter_tuple { 823 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 824 * register selects which of these fields will participate in the 825 * filter match rules -- up to a maximum of 36 bits. Because 826 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 827 * set of fields. 828 */ 829 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 830 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 831 uint32_t ivlan_vld:1; /* inner VLAN valid */ 832 uint32_t ovlan_vld:1; /* outer VLAN valid */ 833 uint32_t pfvf_vld:1; /* PF/VF valid */ 834 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 835 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 836 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 837 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 838 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 839 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 840 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 841 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 842 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 843 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 844 845 /* Uncompressed header matching field rules. These are always 846 * available for field rules. 847 */ 848 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 849 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 850 uint16_t lport; /* local port */ 851 uint16_t fport; /* foreign port */ 852 }; 853 854 /* A filter ioctl command. 855 */ 856 struct ch_filter_specification { 857 /* Administrative fields for filter. 858 */ 859 uint32_t hitcnts:1; /* count filter hits in TCB */ 860 uint32_t prio:1; /* filter has priority over active/server */ 861 862 /* Fundamental filter typing. This is the one element of filter 863 * matching that doesn't exist as a (value, mask) tuple. 864 */ 865 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 866 867 /* Packet dispatch information. Ingress packets which match the 868 * filter rules will be dropped, passed to the host or switched back 869 * out as egress packets. 870 */ 871 uint32_t action:2; /* drop, pass, switch */ 872 873 uint32_t rpttid:1; /* report TID in RSS hash field */ 874 875 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 876 uint32_t iq:10; /* ingress queue */ 877 878 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 879 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 880 /* 1 => TCB contains IQ ID */ 881 882 /* Switch proxy/rewrite fields. An ingress packet which matches a 883 * filter with "switch" set will be looped back out as an egress 884 * packet -- potentially with some Ethernet header rewriting. 885 */ 886 uint32_t eport:2; /* egress port to switch packet out */ 887 uint32_t newdmac:1; /* rewrite destination MAC address */ 888 uint32_t newsmac:1; /* rewrite source MAC address */ 889 uint32_t newvlan:2; /* rewrite VLAN Tag */ 890 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 891 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 892 uint16_t vlan; /* VLAN Tag to insert */ 893 894 /* Filter rule value/mask pairs. 895 */ 896 struct ch_filter_tuple val; 897 struct ch_filter_tuple mask; 898 }; 899 900 enum { 901 FILTER_PASS = 0, /* default */ 902 FILTER_DROP, 903 FILTER_SWITCH 904 }; 905 906 enum { 907 VLAN_NOCHANGE = 0, /* default */ 908 VLAN_REMOVE, 909 VLAN_INSERT, 910 VLAN_REWRITE 911 }; 912 913 static inline int is_offload(const struct adapter *adap) 914 { 915 return adap->params.offload; 916 } 917 918 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 919 { 920 return readl(adap->regs + reg_addr); 921 } 922 923 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 924 { 925 writel(val, adap->regs + reg_addr); 926 } 927 928 #ifndef readq 929 static inline u64 readq(const volatile void __iomem *addr) 930 { 931 return readl(addr) + ((u64)readl(addr + 4) << 32); 932 } 933 934 static inline void writeq(u64 val, volatile void __iomem *addr) 935 { 936 writel(val, addr); 937 writel(val >> 32, addr + 4); 938 } 939 #endif 940 941 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 942 { 943 return readq(adap->regs + reg_addr); 944 } 945 946 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 947 { 948 writeq(val, adap->regs + reg_addr); 949 } 950 951 /** 952 * t4_set_hw_addr - store a port's MAC address in SW 953 * @adapter: the adapter 954 * @port_idx: the port index 955 * @hw_addr: the Ethernet address 956 * 957 * Store the Ethernet address of the given port in SW. Called by the common 958 * code when it retrieves a port's Ethernet address from EEPROM. 959 */ 960 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 961 u8 hw_addr[]) 962 { 963 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 964 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 965 } 966 967 /** 968 * netdev2pinfo - return the port_info structure associated with a net_device 969 * @dev: the netdev 970 * 971 * Return the struct port_info associated with a net_device 972 */ 973 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 974 { 975 return netdev_priv(dev); 976 } 977 978 /** 979 * adap2pinfo - return the port_info of a port 980 * @adap: the adapter 981 * @idx: the port index 982 * 983 * Return the port_info structure for the port of the given index. 984 */ 985 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 986 { 987 return netdev_priv(adap->port[idx]); 988 } 989 990 /** 991 * netdev2adap - return the adapter structure associated with a net_device 992 * @dev: the netdev 993 * 994 * Return the struct adapter associated with a net_device 995 */ 996 static inline struct adapter *netdev2adap(const struct net_device *dev) 997 { 998 return netdev2pinfo(dev)->adapter; 999 } 1000 1001 #ifdef CONFIG_NET_RX_BUSY_POLL 1002 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 1003 { 1004 spin_lock_init(&q->bpoll_lock); 1005 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1006 } 1007 1008 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 1009 { 1010 bool rc = true; 1011 1012 spin_lock(&q->bpoll_lock); 1013 if (q->bpoll_state & CXGB_POLL_LOCKED) { 1014 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 1015 rc = false; 1016 } else { 1017 q->bpoll_state = CXGB_POLL_STATE_NAPI; 1018 } 1019 spin_unlock(&q->bpoll_lock); 1020 return rc; 1021 } 1022 1023 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 1024 { 1025 bool rc = false; 1026 1027 spin_lock(&q->bpoll_lock); 1028 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 1029 rc = true; 1030 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1031 spin_unlock(&q->bpoll_lock); 1032 return rc; 1033 } 1034 1035 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 1036 { 1037 bool rc = true; 1038 1039 spin_lock_bh(&q->bpoll_lock); 1040 if (q->bpoll_state & CXGB_POLL_LOCKED) { 1041 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 1042 rc = false; 1043 } else { 1044 q->bpoll_state |= CXGB_POLL_STATE_POLL; 1045 } 1046 spin_unlock_bh(&q->bpoll_lock); 1047 return rc; 1048 } 1049 1050 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 1051 { 1052 bool rc = false; 1053 1054 spin_lock_bh(&q->bpoll_lock); 1055 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 1056 rc = true; 1057 q->bpoll_state = CXGB_POLL_STATE_IDLE; 1058 spin_unlock_bh(&q->bpoll_lock); 1059 return rc; 1060 } 1061 1062 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 1063 { 1064 return q->bpoll_state & CXGB_POLL_USER_PEND; 1065 } 1066 #else 1067 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 1068 { 1069 } 1070 1071 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 1072 { 1073 return true; 1074 } 1075 1076 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 1077 { 1078 return false; 1079 } 1080 1081 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 1082 { 1083 return false; 1084 } 1085 1086 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 1087 { 1088 return false; 1089 } 1090 1091 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 1092 { 1093 return false; 1094 } 1095 #endif /* CONFIG_NET_RX_BUSY_POLL */ 1096 1097 /* Return a version number to identify the type of adapter. The scheme is: 1098 * - bits 0..9: chip version 1099 * - bits 10..15: chip revision 1100 * - bits 16..23: register dump version 1101 */ 1102 static inline unsigned int mk_adap_vers(struct adapter *ap) 1103 { 1104 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1105 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1106 } 1107 1108 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1109 static inline unsigned int qtimer_val(const struct adapter *adap, 1110 const struct sge_rspq *q) 1111 { 1112 unsigned int idx = q->intr_params >> 1; 1113 1114 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1115 } 1116 1117 /* driver version & name used for ethtool_drvinfo */ 1118 extern char cxgb4_driver_name[]; 1119 extern const char cxgb4_driver_version[]; 1120 1121 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1122 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1123 1124 void *t4_alloc_mem(size_t size); 1125 1126 void t4_free_sge_resources(struct adapter *adap); 1127 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1128 irq_handler_t t4_intr_handler(struct adapter *adap); 1129 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1130 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1131 const struct pkt_gl *gl); 1132 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1133 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1134 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1135 struct net_device *dev, int intr_idx, 1136 struct sge_fl *fl, rspq_handler_t hnd, 1137 rspq_flush_handler_t flush_handler, int cong); 1138 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1139 struct net_device *dev, struct netdev_queue *netdevq, 1140 unsigned int iqid); 1141 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1142 struct net_device *dev, unsigned int iqid, 1143 unsigned int cmplqid); 1144 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1145 struct net_device *dev, unsigned int iqid); 1146 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1147 int t4_sge_init(struct adapter *adap); 1148 void t4_sge_start(struct adapter *adap); 1149 void t4_sge_stop(struct adapter *adap); 1150 int cxgb_busy_poll(struct napi_struct *napi); 1151 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1152 unsigned int cnt); 1153 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1154 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1155 extern int dbfifo_int_thresh; 1156 1157 #define for_each_port(adapter, iter) \ 1158 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1159 1160 static inline int is_bypass(struct adapter *adap) 1161 { 1162 return adap->params.bypass; 1163 } 1164 1165 static inline int is_bypass_device(int device) 1166 { 1167 /* this should be set based upon device capabilities */ 1168 switch (device) { 1169 case 0x440b: 1170 case 0x440c: 1171 return 1; 1172 default: 1173 return 0; 1174 } 1175 } 1176 1177 static inline int is_10gbt_device(int device) 1178 { 1179 /* this should be set based upon device capabilities */ 1180 switch (device) { 1181 case 0x4409: 1182 case 0x4486: 1183 return 1; 1184 1185 default: 1186 return 0; 1187 } 1188 } 1189 1190 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1191 { 1192 return adap->params.vpd.cclk / 1000; 1193 } 1194 1195 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1196 unsigned int us) 1197 { 1198 return (us * adap->params.vpd.cclk) / 1000; 1199 } 1200 1201 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1202 unsigned int ticks) 1203 { 1204 /* add Core Clock / 2 to round ticks to nearest uS */ 1205 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1206 adapter->params.vpd.cclk); 1207 } 1208 1209 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1210 u32 val); 1211 1212 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1213 int size, void *rpl, bool sleep_ok, int timeout); 1214 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1215 void *rpl, bool sleep_ok); 1216 1217 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1218 const void *cmd, int size, void *rpl, 1219 int timeout) 1220 { 1221 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1222 timeout); 1223 } 1224 1225 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1226 int size, void *rpl) 1227 { 1228 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1229 } 1230 1231 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1232 int size, void *rpl) 1233 { 1234 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1235 } 1236 1237 /** 1238 * hash_mac_addr - return the hash value of a MAC address 1239 * @addr: the 48-bit Ethernet MAC address 1240 * 1241 * Hashes a MAC address according to the hash function used by HW inexact 1242 * (hash) address matching. 1243 */ 1244 static inline int hash_mac_addr(const u8 *addr) 1245 { 1246 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1247 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1248 1249 a ^= b; 1250 a ^= (a >> 12); 1251 a ^= (a >> 6); 1252 return a & 0x3f; 1253 } 1254 1255 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1256 unsigned int data_reg, const u32 *vals, 1257 unsigned int nregs, unsigned int start_idx); 1258 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1259 unsigned int data_reg, u32 *vals, unsigned int nregs, 1260 unsigned int start_idx); 1261 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1262 1263 struct fw_filter_wr; 1264 1265 void t4_intr_enable(struct adapter *adapter); 1266 void t4_intr_disable(struct adapter *adapter); 1267 int t4_slow_intr_handler(struct adapter *adapter); 1268 1269 int t4_wait_dev_ready(void __iomem *regs); 1270 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1271 struct link_config *lc); 1272 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1273 1274 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1275 u32 t4_get_util_window(struct adapter *adap); 1276 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1277 1278 #define T4_MEMORY_WRITE 0 1279 #define T4_MEMORY_READ 1 1280 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1281 void *buf, int dir); 1282 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1283 u32 len, __be32 *buf) 1284 { 1285 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1286 } 1287 1288 unsigned int t4_get_regs_len(struct adapter *adapter); 1289 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1290 1291 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1292 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1293 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1294 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1295 unsigned int nwords, u32 *data, int byte_oriented); 1296 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1297 int t4_load_phy_fw(struct adapter *adap, 1298 int win, spinlock_t *lock, 1299 int (*phy_fw_version)(const u8 *, size_t), 1300 const u8 *phy_fw_data, size_t phy_fw_size); 1301 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1302 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1303 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1304 const u8 *fw_data, unsigned int size, int force); 1305 int t4_fl_pkt_align(struct adapter *adap); 1306 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1307 int t4_check_fw_version(struct adapter *adap); 1308 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1309 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1310 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1311 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1312 const u8 *fw_data, unsigned int fw_size, 1313 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1314 int t4_prep_adapter(struct adapter *adapter); 1315 1316 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1317 int t4_bar2_sge_qregs(struct adapter *adapter, 1318 unsigned int qid, 1319 enum t4_bar2_qtype qtype, 1320 int user, 1321 u64 *pbar2_qoffset, 1322 unsigned int *pbar2_qid); 1323 1324 unsigned int qtimer_val(const struct adapter *adap, 1325 const struct sge_rspq *q); 1326 1327 int t4_init_devlog_params(struct adapter *adapter); 1328 int t4_init_sge_params(struct adapter *adapter); 1329 int t4_init_tp_params(struct adapter *adap); 1330 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1331 int t4_init_rss_mode(struct adapter *adap, int mbox); 1332 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1333 void t4_fatal_err(struct adapter *adapter); 1334 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1335 int start, int n, const u16 *rspq, unsigned int nrspq); 1336 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1337 unsigned int flags); 1338 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1339 unsigned int flags, unsigned int defq); 1340 int t4_read_rss(struct adapter *adapter, u16 *entries); 1341 void t4_read_rss_key(struct adapter *adapter, u32 *key); 1342 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1343 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1344 u32 *valp); 1345 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1346 u32 *vfl, u32 *vfh); 1347 u32 t4_read_rss_pf_map(struct adapter *adapter); 1348 u32 t4_read_rss_pf_mask(struct adapter *adapter); 1349 1350 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1351 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1352 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1353 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1354 size_t n); 1355 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1356 size_t n); 1357 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1358 unsigned int *valp); 1359 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1360 const unsigned int *valp); 1361 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1362 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1363 unsigned int *pif_req_wrptr, 1364 unsigned int *pif_rsp_wrptr); 1365 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1366 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1367 const char *t4_get_port_type_description(enum fw_port_type port_type); 1368 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1369 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1370 struct port_stats *stats, 1371 struct port_stats *offset); 1372 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1373 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1374 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1375 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1376 unsigned int mask, unsigned int val); 1377 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1378 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1379 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1380 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1381 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1382 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1383 struct tp_tcp_stats *v6); 1384 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1385 struct tp_fcoe_stats *st); 1386 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1387 const unsigned short *alpha, const unsigned short *beta); 1388 1389 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1390 1391 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1392 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1393 1394 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1395 const u8 *addr); 1396 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1397 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1398 1399 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1400 enum dev_master master, enum dev_state *state); 1401 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1402 int t4_early_init(struct adapter *adap, unsigned int mbox); 1403 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1404 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1405 unsigned int cache_line_size); 1406 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1407 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1408 unsigned int vf, unsigned int nparams, const u32 *params, 1409 u32 *val); 1410 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1411 unsigned int vf, unsigned int nparams, const u32 *params, 1412 u32 *val, int rw); 1413 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1414 unsigned int pf, unsigned int vf, 1415 unsigned int nparams, const u32 *params, 1416 const u32 *val, int timeout); 1417 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1418 unsigned int vf, unsigned int nparams, const u32 *params, 1419 const u32 *val); 1420 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1421 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1422 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1423 unsigned int vi, unsigned int cmask, unsigned int pmask, 1424 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1425 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1426 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1427 unsigned int *rss_size); 1428 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1429 unsigned int pf, unsigned int vf, 1430 unsigned int viid); 1431 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1432 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1433 bool sleep_ok); 1434 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1435 unsigned int viid, bool free, unsigned int naddr, 1436 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1437 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1438 unsigned int viid, unsigned int naddr, 1439 const u8 **addr, bool sleep_ok); 1440 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1441 int idx, const u8 *addr, bool persist, bool add_smt); 1442 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1443 bool ucast, u64 vec, bool sleep_ok); 1444 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1445 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1446 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1447 bool rx_en, bool tx_en); 1448 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1449 unsigned int nblinks); 1450 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1451 unsigned int mmd, unsigned int reg, u16 *valp); 1452 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1453 unsigned int mmd, unsigned int reg, u16 val); 1454 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1455 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1456 unsigned int fl0id, unsigned int fl1id); 1457 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1458 unsigned int vf, unsigned int eqid); 1459 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1460 unsigned int vf, unsigned int eqid); 1461 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1462 unsigned int vf, unsigned int eqid); 1463 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1464 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1465 void t4_db_full(struct adapter *adapter); 1466 void t4_db_dropped(struct adapter *adapter); 1467 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1468 int filter_index, int enable); 1469 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1470 int filter_index, int *enabled); 1471 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1472 u32 addr, u32 val); 1473 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1474 void t4_free_mem(void *addr); 1475 void t4_idma_monitor_init(struct adapter *adapter, 1476 struct sge_idma_monitor_state *idma); 1477 void t4_idma_monitor(struct adapter *adapter, 1478 struct sge_idma_monitor_state *idma, 1479 int hz, int ticks); 1480 #endif /* __CXGB4_H__ */ 1481