1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include <linux/bitops.h> 39 #include <linux/cache.h> 40 #include <linux/interrupt.h> 41 #include <linux/list.h> 42 #include <linux/netdevice.h> 43 #include <linux/pci.h> 44 #include <linux/spinlock.h> 45 #include <linux/timer.h> 46 #include <asm/io.h> 47 #include "cxgb4_uld.h" 48 #include "t4_hw.h" 49 50 #define FW_VERSION_MAJOR 1 51 #define FW_VERSION_MINOR 1 52 #define FW_VERSION_MICRO 0 53 54 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 55 56 enum { 57 MAX_NPORTS = 4, /* max # of ports */ 58 SERNUM_LEN = 24, /* Serial # length */ 59 EC_LEN = 16, /* E/C length */ 60 ID_LEN = 16, /* ID length */ 61 }; 62 63 enum { 64 MEM_EDC0, 65 MEM_EDC1, 66 MEM_MC 67 }; 68 69 enum { 70 MEMWIN0_APERTURE = 65536, 71 MEMWIN0_BASE = 0x30000, 72 MEMWIN1_APERTURE = 32768, 73 MEMWIN1_BASE = 0x28000, 74 MEMWIN2_APERTURE = 2048, 75 MEMWIN2_BASE = 0x1b800, 76 }; 77 78 enum dev_master { 79 MASTER_CANT, 80 MASTER_MAY, 81 MASTER_MUST 82 }; 83 84 enum dev_state { 85 DEV_STATE_UNINIT, 86 DEV_STATE_INIT, 87 DEV_STATE_ERR 88 }; 89 90 enum { 91 PAUSE_RX = 1 << 0, 92 PAUSE_TX = 1 << 1, 93 PAUSE_AUTONEG = 1 << 2 94 }; 95 96 struct port_stats { 97 u64 tx_octets; /* total # of octets in good frames */ 98 u64 tx_frames; /* all good frames */ 99 u64 tx_bcast_frames; /* all broadcast frames */ 100 u64 tx_mcast_frames; /* all multicast frames */ 101 u64 tx_ucast_frames; /* all unicast frames */ 102 u64 tx_error_frames; /* all error frames */ 103 104 u64 tx_frames_64; /* # of Tx frames in a particular range */ 105 u64 tx_frames_65_127; 106 u64 tx_frames_128_255; 107 u64 tx_frames_256_511; 108 u64 tx_frames_512_1023; 109 u64 tx_frames_1024_1518; 110 u64 tx_frames_1519_max; 111 112 u64 tx_drop; /* # of dropped Tx frames */ 113 u64 tx_pause; /* # of transmitted pause frames */ 114 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 115 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 116 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 117 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 118 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 119 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 120 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 121 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 122 123 u64 rx_octets; /* total # of octets in good frames */ 124 u64 rx_frames; /* all good frames */ 125 u64 rx_bcast_frames; /* all broadcast frames */ 126 u64 rx_mcast_frames; /* all multicast frames */ 127 u64 rx_ucast_frames; /* all unicast frames */ 128 u64 rx_too_long; /* # of frames exceeding MTU */ 129 u64 rx_jabber; /* # of jabber frames */ 130 u64 rx_fcs_err; /* # of received frames with bad FCS */ 131 u64 rx_len_err; /* # of received frames with length error */ 132 u64 rx_symbol_err; /* symbol errors */ 133 u64 rx_runt; /* # of short frames */ 134 135 u64 rx_frames_64; /* # of Rx frames in a particular range */ 136 u64 rx_frames_65_127; 137 u64 rx_frames_128_255; 138 u64 rx_frames_256_511; 139 u64 rx_frames_512_1023; 140 u64 rx_frames_1024_1518; 141 u64 rx_frames_1519_max; 142 143 u64 rx_pause; /* # of received pause frames */ 144 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 145 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 146 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 147 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 148 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 149 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 150 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 151 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 152 153 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 154 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 155 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 156 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 157 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 158 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 159 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 160 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 161 }; 162 163 struct lb_port_stats { 164 u64 octets; 165 u64 frames; 166 u64 bcast_frames; 167 u64 mcast_frames; 168 u64 ucast_frames; 169 u64 error_frames; 170 171 u64 frames_64; 172 u64 frames_65_127; 173 u64 frames_128_255; 174 u64 frames_256_511; 175 u64 frames_512_1023; 176 u64 frames_1024_1518; 177 u64 frames_1519_max; 178 179 u64 drop; 180 181 u64 ovflow0; 182 u64 ovflow1; 183 u64 ovflow2; 184 u64 ovflow3; 185 u64 trunc0; 186 u64 trunc1; 187 u64 trunc2; 188 u64 trunc3; 189 }; 190 191 struct tp_tcp_stats { 192 u32 tcpOutRsts; 193 u64 tcpInSegs; 194 u64 tcpOutSegs; 195 u64 tcpRetransSegs; 196 }; 197 198 struct tp_err_stats { 199 u32 macInErrs[4]; 200 u32 hdrInErrs[4]; 201 u32 tcpInErrs[4]; 202 u32 tnlCongDrops[4]; 203 u32 ofldChanDrops[4]; 204 u32 tnlTxDrops[4]; 205 u32 ofldVlanDrops[4]; 206 u32 tcp6InErrs[4]; 207 u32 ofldNoNeigh; 208 u32 ofldCongDefer; 209 }; 210 211 struct tp_params { 212 unsigned int ntxchan; /* # of Tx channels */ 213 unsigned int tre; /* log2 of core clocks per TP tick */ 214 }; 215 216 struct vpd_params { 217 unsigned int cclk; 218 u8 ec[EC_LEN + 1]; 219 u8 sn[SERNUM_LEN + 1]; 220 u8 id[ID_LEN + 1]; 221 }; 222 223 struct pci_params { 224 unsigned char speed; 225 unsigned char width; 226 }; 227 228 struct adapter_params { 229 struct tp_params tp; 230 struct vpd_params vpd; 231 struct pci_params pci; 232 233 unsigned int sf_size; /* serial flash size in bytes */ 234 unsigned int sf_nsec; /* # of flash sectors */ 235 unsigned int sf_fw_start; /* start of FW image in flash */ 236 237 unsigned int fw_vers; 238 unsigned int tp_vers; 239 u8 api_vers[7]; 240 241 unsigned short mtus[NMTUS]; 242 unsigned short a_wnd[NCCTRL_WIN]; 243 unsigned short b_wnd[NCCTRL_WIN]; 244 245 unsigned char nports; /* # of ethernet ports */ 246 unsigned char portvec; 247 unsigned char rev; /* chip revision */ 248 unsigned char offload; 249 250 unsigned int ofldq_wr_cred; 251 }; 252 253 struct trace_params { 254 u32 data[TRACE_LEN / 4]; 255 u32 mask[TRACE_LEN / 4]; 256 unsigned short snap_len; 257 unsigned short min_len; 258 unsigned char skip_ofst; 259 unsigned char skip_len; 260 unsigned char invert; 261 unsigned char port; 262 }; 263 264 struct link_config { 265 unsigned short supported; /* link capabilities */ 266 unsigned short advertising; /* advertised capabilities */ 267 unsigned short requested_speed; /* speed user has requested */ 268 unsigned short speed; /* actual link speed */ 269 unsigned char requested_fc; /* flow control user has requested */ 270 unsigned char fc; /* actual link flow control */ 271 unsigned char autoneg; /* autonegotiating? */ 272 unsigned char link_ok; /* link up? */ 273 }; 274 275 #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16) 276 277 enum { 278 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 279 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 280 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 281 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 282 }; 283 284 enum { 285 MAX_EGRQ = 128, /* max # of egress queues, including FLs */ 286 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */ 287 }; 288 289 struct adapter; 290 struct sge_rspq; 291 292 struct port_info { 293 struct adapter *adapter; 294 u16 viid; 295 s16 xact_addr_filt; /* index of exact MAC address filter */ 296 u16 rss_size; /* size of VI's RSS table slice */ 297 s8 mdio_addr; 298 u8 port_type; 299 u8 mod_type; 300 u8 port_id; 301 u8 tx_chan; 302 u8 lport; /* associated offload logical port */ 303 u8 nqsets; /* # of qsets */ 304 u8 first_qset; /* index of first qset */ 305 u8 rss_mode; 306 struct link_config link_cfg; 307 u16 *rss; 308 }; 309 310 struct dentry; 311 struct work_struct; 312 313 enum { /* adapter flags */ 314 FULL_INIT_DONE = (1 << 0), 315 USING_MSI = (1 << 1), 316 USING_MSIX = (1 << 2), 317 FW_OK = (1 << 4), 318 }; 319 320 struct rx_sw_desc; 321 322 struct sge_fl { /* SGE free-buffer queue state */ 323 unsigned int avail; /* # of available Rx buffers */ 324 unsigned int pend_cred; /* new buffers since last FL DB ring */ 325 unsigned int cidx; /* consumer index */ 326 unsigned int pidx; /* producer index */ 327 unsigned long alloc_failed; /* # of times buffer allocation failed */ 328 unsigned long large_alloc_failed; 329 unsigned long starving; 330 /* RO fields */ 331 unsigned int cntxt_id; /* SGE context id for the free list */ 332 unsigned int size; /* capacity of free list */ 333 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 334 __be64 *desc; /* address of HW Rx descriptor ring */ 335 dma_addr_t addr; /* bus address of HW ring start */ 336 }; 337 338 /* A packet gather list */ 339 struct pkt_gl { 340 struct page_frag frags[MAX_SKB_FRAGS]; 341 void *va; /* virtual address of first byte */ 342 unsigned int nfrags; /* # of fragments */ 343 unsigned int tot_len; /* total length of fragments */ 344 }; 345 346 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 347 const struct pkt_gl *gl); 348 349 struct sge_rspq { /* state for an SGE response queue */ 350 struct napi_struct napi; 351 const __be64 *cur_desc; /* current descriptor in queue */ 352 unsigned int cidx; /* consumer index */ 353 u8 gen; /* current generation bit */ 354 u8 intr_params; /* interrupt holdoff parameters */ 355 u8 next_intr_params; /* holdoff params for next interrupt */ 356 u8 pktcnt_idx; /* interrupt packet threshold */ 357 u8 uld; /* ULD handling this queue */ 358 u8 idx; /* queue index within its group */ 359 int offset; /* offset into current Rx buffer */ 360 u16 cntxt_id; /* SGE context id for the response q */ 361 u16 abs_id; /* absolute SGE id for the response q */ 362 __be64 *desc; /* address of HW response ring */ 363 dma_addr_t phys_addr; /* physical address of the ring */ 364 unsigned int iqe_len; /* entry size */ 365 unsigned int size; /* capacity of response queue */ 366 struct adapter *adap; 367 struct net_device *netdev; /* associated net device */ 368 rspq_handler_t handler; 369 }; 370 371 struct sge_eth_stats { /* Ethernet queue statistics */ 372 unsigned long pkts; /* # of ethernet packets */ 373 unsigned long lro_pkts; /* # of LRO super packets */ 374 unsigned long lro_merged; /* # of wire packets merged by LRO */ 375 unsigned long rx_cso; /* # of Rx checksum offloads */ 376 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 377 unsigned long rx_drops; /* # of packets dropped due to no mem */ 378 }; 379 380 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 381 struct sge_rspq rspq; 382 struct sge_fl fl; 383 struct sge_eth_stats stats; 384 } ____cacheline_aligned_in_smp; 385 386 struct sge_ofld_stats { /* offload queue statistics */ 387 unsigned long pkts; /* # of packets */ 388 unsigned long imm; /* # of immediate-data packets */ 389 unsigned long an; /* # of asynchronous notifications */ 390 unsigned long nomem; /* # of responses deferred due to no mem */ 391 }; 392 393 struct sge_ofld_rxq { /* SW offload Rx queue */ 394 struct sge_rspq rspq; 395 struct sge_fl fl; 396 struct sge_ofld_stats stats; 397 } ____cacheline_aligned_in_smp; 398 399 struct tx_desc { 400 __be64 flit[8]; 401 }; 402 403 struct tx_sw_desc; 404 405 struct sge_txq { 406 unsigned int in_use; /* # of in-use Tx descriptors */ 407 unsigned int size; /* # of descriptors */ 408 unsigned int cidx; /* SW consumer index */ 409 unsigned int pidx; /* producer index */ 410 unsigned long stops; /* # of times q has been stopped */ 411 unsigned long restarts; /* # of queue restarts */ 412 unsigned int cntxt_id; /* SGE context id for the Tx q */ 413 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 414 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 415 struct sge_qstat *stat; /* queue status entry */ 416 dma_addr_t phys_addr; /* physical address of the ring */ 417 spinlock_t db_lock; 418 int db_disabled; 419 unsigned short db_pidx; 420 }; 421 422 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 423 struct sge_txq q; 424 struct netdev_queue *txq; /* associated netdev TX queue */ 425 unsigned long tso; /* # of TSO requests */ 426 unsigned long tx_cso; /* # of Tx checksum offloads */ 427 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 428 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 429 } ____cacheline_aligned_in_smp; 430 431 struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 432 struct sge_txq q; 433 struct adapter *adap; 434 struct sk_buff_head sendq; /* list of backpressured packets */ 435 struct tasklet_struct qresume_tsk; /* restarts the queue */ 436 u8 full; /* the Tx ring is full */ 437 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 438 } ____cacheline_aligned_in_smp; 439 440 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 441 struct sge_txq q; 442 struct adapter *adap; 443 struct sk_buff_head sendq; /* list of backpressured packets */ 444 struct tasklet_struct qresume_tsk; /* restarts the queue */ 445 u8 full; /* the Tx ring is full */ 446 } ____cacheline_aligned_in_smp; 447 448 struct sge { 449 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 450 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 451 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 452 453 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 454 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 455 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 456 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 457 458 struct sge_rspq intrq ____cacheline_aligned_in_smp; 459 spinlock_t intrq_lock; 460 461 u16 max_ethqsets; /* # of available Ethernet queue sets */ 462 u16 ethqsets; /* # of active Ethernet queue sets */ 463 u16 ethtxq_rover; /* Tx queue to clean up next */ 464 u16 ofldqsets; /* # of active offload queue sets */ 465 u16 rdmaqs; /* # of available RDMA Rx queues */ 466 u16 ofld_rxq[MAX_OFLD_QSETS]; 467 u16 rdma_rxq[NCHAN]; 468 u16 timer_val[SGE_NTIMERS]; 469 u8 counter_val[SGE_NCOUNTERS]; 470 unsigned int starve_thres; 471 u8 idma_state[2]; 472 unsigned int egr_start; 473 unsigned int ingr_start; 474 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */ 475 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */ 476 DECLARE_BITMAP(starving_fl, MAX_EGRQ); 477 DECLARE_BITMAP(txq_maperr, MAX_EGRQ); 478 struct timer_list rx_timer; /* refills starving FLs */ 479 struct timer_list tx_timer; /* checks Tx queues */ 480 }; 481 482 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 483 #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 484 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 485 486 struct l2t_data; 487 488 struct adapter { 489 void __iomem *regs; 490 struct pci_dev *pdev; 491 struct device *pdev_dev; 492 unsigned int mbox; 493 unsigned int fn; 494 unsigned int flags; 495 496 int msg_enable; 497 498 struct adapter_params params; 499 struct cxgb4_virt_res vres; 500 unsigned int swintr; 501 502 unsigned int wol; 503 504 struct { 505 unsigned short vec; 506 char desc[IFNAMSIZ + 10]; 507 } msix_info[MAX_INGQ + 1]; 508 509 struct sge sge; 510 511 struct net_device *port[MAX_NPORTS]; 512 u8 chan_map[NCHAN]; /* channel -> port map */ 513 514 struct l2t_data *l2t; 515 void *uld_handle[CXGB4_ULD_MAX]; 516 struct list_head list_node; 517 518 struct tid_info tids; 519 void **tid_release_head; 520 spinlock_t tid_release_lock; 521 struct work_struct tid_release_task; 522 struct work_struct db_full_task; 523 struct work_struct db_drop_task; 524 bool tid_release_task_busy; 525 526 struct dentry *debugfs_root; 527 528 spinlock_t stats_lock; 529 }; 530 531 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 532 { 533 return readl(adap->regs + reg_addr); 534 } 535 536 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 537 { 538 writel(val, adap->regs + reg_addr); 539 } 540 541 #ifndef readq 542 static inline u64 readq(const volatile void __iomem *addr) 543 { 544 return readl(addr) + ((u64)readl(addr + 4) << 32); 545 } 546 547 static inline void writeq(u64 val, volatile void __iomem *addr) 548 { 549 writel(val, addr); 550 writel(val >> 32, addr + 4); 551 } 552 #endif 553 554 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 555 { 556 return readq(adap->regs + reg_addr); 557 } 558 559 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 560 { 561 writeq(val, adap->regs + reg_addr); 562 } 563 564 /** 565 * netdev2pinfo - return the port_info structure associated with a net_device 566 * @dev: the netdev 567 * 568 * Return the struct port_info associated with a net_device 569 */ 570 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 571 { 572 return netdev_priv(dev); 573 } 574 575 /** 576 * adap2pinfo - return the port_info of a port 577 * @adap: the adapter 578 * @idx: the port index 579 * 580 * Return the port_info structure for the port of the given index. 581 */ 582 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 583 { 584 return netdev_priv(adap->port[idx]); 585 } 586 587 /** 588 * netdev2adap - return the adapter structure associated with a net_device 589 * @dev: the netdev 590 * 591 * Return the struct adapter associated with a net_device 592 */ 593 static inline struct adapter *netdev2adap(const struct net_device *dev) 594 { 595 return netdev2pinfo(dev)->adapter; 596 } 597 598 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 599 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 600 601 void *t4_alloc_mem(size_t size); 602 603 void t4_free_sge_resources(struct adapter *adap); 604 irq_handler_t t4_intr_handler(struct adapter *adap); 605 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 606 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 607 const struct pkt_gl *gl); 608 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 609 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 610 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 611 struct net_device *dev, int intr_idx, 612 struct sge_fl *fl, rspq_handler_t hnd); 613 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 614 struct net_device *dev, struct netdev_queue *netdevq, 615 unsigned int iqid); 616 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 617 struct net_device *dev, unsigned int iqid, 618 unsigned int cmplqid); 619 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 620 struct net_device *dev, unsigned int iqid); 621 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 622 void t4_sge_init(struct adapter *adap); 623 void t4_sge_start(struct adapter *adap); 624 void t4_sge_stop(struct adapter *adap); 625 extern int dbfifo_int_thresh; 626 627 #define for_each_port(adapter, iter) \ 628 for (iter = 0; iter < (adapter)->params.nports; ++iter) 629 630 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 631 { 632 return adap->params.vpd.cclk / 1000; 633 } 634 635 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 636 unsigned int us) 637 { 638 return (us * adap->params.vpd.cclk) / 1000; 639 } 640 641 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 642 u32 val); 643 644 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 645 void *rpl, bool sleep_ok); 646 647 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 648 int size, void *rpl) 649 { 650 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 651 } 652 653 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 654 int size, void *rpl) 655 { 656 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 657 } 658 659 void t4_intr_enable(struct adapter *adapter); 660 void t4_intr_disable(struct adapter *adapter); 661 int t4_slow_intr_handler(struct adapter *adapter); 662 663 int t4_wait_dev_ready(struct adapter *adap); 664 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 665 struct link_config *lc); 666 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 667 int t4_seeprom_wp(struct adapter *adapter, bool enable); 668 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 669 int t4_check_fw_version(struct adapter *adapter); 670 int t4_prep_adapter(struct adapter *adapter); 671 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 672 void t4_fatal_err(struct adapter *adapter); 673 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 674 int start, int n, const u16 *rspq, unsigned int nrspq); 675 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 676 unsigned int flags); 677 int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity); 678 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 679 u64 *parity); 680 681 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 682 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 683 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 684 struct tp_tcp_stats *v6); 685 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 686 const unsigned short *alpha, const unsigned short *beta); 687 688 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 689 const u8 *addr); 690 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 691 u64 mask0, u64 mask1, unsigned int crc, bool enable); 692 693 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 694 enum dev_master master, enum dev_state *state); 695 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 696 int t4_early_init(struct adapter *adap, unsigned int mbox); 697 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 698 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 699 unsigned int vf, unsigned int nparams, const u32 *params, 700 u32 *val); 701 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 702 unsigned int vf, unsigned int nparams, const u32 *params, 703 const u32 *val); 704 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 705 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 706 unsigned int rxqi, unsigned int rxq, unsigned int tc, 707 unsigned int vi, unsigned int cmask, unsigned int pmask, 708 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 709 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 710 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 711 unsigned int *rss_size); 712 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 713 int mtu, int promisc, int all_multi, int bcast, int vlanex, 714 bool sleep_ok); 715 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 716 unsigned int viid, bool free, unsigned int naddr, 717 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 718 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 719 int idx, const u8 *addr, bool persist, bool add_smt); 720 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 721 bool ucast, u64 vec, bool sleep_ok); 722 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 723 bool rx_en, bool tx_en); 724 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 725 unsigned int nblinks); 726 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 727 unsigned int mmd, unsigned int reg, u16 *valp); 728 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 729 unsigned int mmd, unsigned int reg, u16 val); 730 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 731 unsigned int vf, unsigned int iqtype, unsigned int iqid, 732 unsigned int fl0id, unsigned int fl1id); 733 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 734 unsigned int vf, unsigned int eqid); 735 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 736 unsigned int vf, unsigned int eqid); 737 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 738 unsigned int vf, unsigned int eqid); 739 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 740 void t4_db_full(struct adapter *adapter); 741 void t4_db_dropped(struct adapter *adapter); 742 int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len); 743 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 744 u32 addr, u32 val); 745 #endif /* __CXGB4_H__ */ 746