1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/rhashtable.h> 50 #include <linux/etherdevice.h> 51 #include <linux/net_tstamp.h> 52 #include <linux/ptp_clock_kernel.h> 53 #include <linux/ptp_classify.h> 54 #include <linux/crash_dump.h> 55 #include <linux/thermal.h> 56 #include <asm/io.h> 57 #include "t4_chip_type.h" 58 #include "cxgb4_uld.h" 59 #include "t4fw_api.h" 60 61 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 62 extern struct list_head adapter_list; 63 extern struct list_head uld_list; 64 extern struct mutex uld_mutex; 65 66 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 67 * This is the same as calc_tx_descs() for a TSO packet with 68 * nr_frags == MAX_SKB_FRAGS. 69 */ 70 #define ETHTXQ_STOP_THRES \ 71 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 72 73 #define FW_PARAM_DEV(param) \ 74 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 75 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 76 77 #define FW_PARAM_PFVF(param) \ 78 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 79 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 80 FW_PARAMS_PARAM_Y_V(0) | \ 81 FW_PARAMS_PARAM_Z_V(0)) 82 83 enum { 84 MAX_NPORTS = 4, /* max # of ports */ 85 SERNUM_LEN = 24, /* Serial # length */ 86 EC_LEN = 16, /* E/C length */ 87 ID_LEN = 16, /* ID length */ 88 PN_LEN = 16, /* Part Number length */ 89 MACADDR_LEN = 12, /* MAC Address length */ 90 }; 91 92 enum { 93 T4_REGMAP_SIZE = (160 * 1024), 94 T5_REGMAP_SIZE = (332 * 1024), 95 }; 96 97 enum { 98 MEM_EDC0, 99 MEM_EDC1, 100 MEM_MC, 101 MEM_MC0 = MEM_MC, 102 MEM_MC1, 103 MEM_HMA, 104 }; 105 106 enum { 107 MEMWIN0_APERTURE = 2048, 108 MEMWIN0_BASE = 0x1b800, 109 MEMWIN1_APERTURE = 32768, 110 MEMWIN1_BASE = 0x28000, 111 MEMWIN1_BASE_T5 = 0x52000, 112 MEMWIN2_APERTURE = 65536, 113 MEMWIN2_BASE = 0x30000, 114 MEMWIN2_APERTURE_T5 = 131072, 115 MEMWIN2_BASE_T5 = 0x60000, 116 }; 117 118 enum dev_master { 119 MASTER_CANT, 120 MASTER_MAY, 121 MASTER_MUST 122 }; 123 124 enum dev_state { 125 DEV_STATE_UNINIT, 126 DEV_STATE_INIT, 127 DEV_STATE_ERR 128 }; 129 130 enum cc_pause { 131 PAUSE_RX = 1 << 0, 132 PAUSE_TX = 1 << 1, 133 PAUSE_AUTONEG = 1 << 2 134 }; 135 136 enum cc_fec { 137 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 138 FEC_RS = 1 << 1, /* Reed-Solomon */ 139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 140 }; 141 142 struct port_stats { 143 u64 tx_octets; /* total # of octets in good frames */ 144 u64 tx_frames; /* all good frames */ 145 u64 tx_bcast_frames; /* all broadcast frames */ 146 u64 tx_mcast_frames; /* all multicast frames */ 147 u64 tx_ucast_frames; /* all unicast frames */ 148 u64 tx_error_frames; /* all error frames */ 149 150 u64 tx_frames_64; /* # of Tx frames in a particular range */ 151 u64 tx_frames_65_127; 152 u64 tx_frames_128_255; 153 u64 tx_frames_256_511; 154 u64 tx_frames_512_1023; 155 u64 tx_frames_1024_1518; 156 u64 tx_frames_1519_max; 157 158 u64 tx_drop; /* # of dropped Tx frames */ 159 u64 tx_pause; /* # of transmitted pause frames */ 160 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 161 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 162 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 163 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 164 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 165 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 166 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 167 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 168 169 u64 rx_octets; /* total # of octets in good frames */ 170 u64 rx_frames; /* all good frames */ 171 u64 rx_bcast_frames; /* all broadcast frames */ 172 u64 rx_mcast_frames; /* all multicast frames */ 173 u64 rx_ucast_frames; /* all unicast frames */ 174 u64 rx_too_long; /* # of frames exceeding MTU */ 175 u64 rx_jabber; /* # of jabber frames */ 176 u64 rx_fcs_err; /* # of received frames with bad FCS */ 177 u64 rx_len_err; /* # of received frames with length error */ 178 u64 rx_symbol_err; /* symbol errors */ 179 u64 rx_runt; /* # of short frames */ 180 181 u64 rx_frames_64; /* # of Rx frames in a particular range */ 182 u64 rx_frames_65_127; 183 u64 rx_frames_128_255; 184 u64 rx_frames_256_511; 185 u64 rx_frames_512_1023; 186 u64 rx_frames_1024_1518; 187 u64 rx_frames_1519_max; 188 189 u64 rx_pause; /* # of received pause frames */ 190 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 191 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 192 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 193 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 194 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 195 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 196 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 197 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 198 199 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 200 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 201 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 202 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 203 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 204 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 205 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 206 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 207 }; 208 209 struct lb_port_stats { 210 u64 octets; 211 u64 frames; 212 u64 bcast_frames; 213 u64 mcast_frames; 214 u64 ucast_frames; 215 u64 error_frames; 216 217 u64 frames_64; 218 u64 frames_65_127; 219 u64 frames_128_255; 220 u64 frames_256_511; 221 u64 frames_512_1023; 222 u64 frames_1024_1518; 223 u64 frames_1519_max; 224 225 u64 drop; 226 227 u64 ovflow0; 228 u64 ovflow1; 229 u64 ovflow2; 230 u64 ovflow3; 231 u64 trunc0; 232 u64 trunc1; 233 u64 trunc2; 234 u64 trunc3; 235 }; 236 237 struct tp_tcp_stats { 238 u32 tcp_out_rsts; 239 u64 tcp_in_segs; 240 u64 tcp_out_segs; 241 u64 tcp_retrans_segs; 242 }; 243 244 struct tp_usm_stats { 245 u32 frames; 246 u32 drops; 247 u64 octets; 248 }; 249 250 struct tp_fcoe_stats { 251 u32 frames_ddp; 252 u32 frames_drop; 253 u64 octets_ddp; 254 }; 255 256 struct tp_err_stats { 257 u32 mac_in_errs[4]; 258 u32 hdr_in_errs[4]; 259 u32 tcp_in_errs[4]; 260 u32 tnl_cong_drops[4]; 261 u32 ofld_chan_drops[4]; 262 u32 tnl_tx_drops[4]; 263 u32 ofld_vlan_drops[4]; 264 u32 tcp6_in_errs[4]; 265 u32 ofld_no_neigh; 266 u32 ofld_cong_defer; 267 }; 268 269 struct tp_cpl_stats { 270 u32 req[4]; 271 u32 rsp[4]; 272 }; 273 274 struct tp_rdma_stats { 275 u32 rqe_dfr_pkt; 276 u32 rqe_dfr_mod; 277 }; 278 279 struct sge_params { 280 u32 hps; /* host page size for our PF/VF */ 281 u32 eq_qpp; /* egress queues/page for our PF/VF */ 282 u32 iq_qpp; /* egress queues/page for our PF/VF */ 283 }; 284 285 struct tp_params { 286 unsigned int tre; /* log2 of core clocks per TP tick */ 287 unsigned int la_mask; /* what events are recorded by TP LA */ 288 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 289 /* channel map */ 290 291 uint32_t dack_re; /* DACK timer resolution */ 292 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 293 294 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 295 u32 filter_mask; 296 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 297 298 /* cached TP_OUT_CONFIG compressed error vector 299 * and passing outer header info for encapsulated packets. 300 */ 301 int rx_pkt_encap; 302 303 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 304 * subset of the set of fields which may be present in the Compressed 305 * Filter Tuple portion of filters and TCP TCB connections. The 306 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 307 * Since a variable number of fields may or may not be present, their 308 * shifted field positions within the Compressed Filter Tuple may 309 * vary, or not even be present if the field isn't selected in 310 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 311 * places we store their offsets here, or a -1 if the field isn't 312 * present. 313 */ 314 int fcoe_shift; 315 int port_shift; 316 int vnic_shift; 317 int vlan_shift; 318 int tos_shift; 319 int protocol_shift; 320 int ethertype_shift; 321 int macmatch_shift; 322 int matchtype_shift; 323 int frag_shift; 324 325 u64 hash_filter_mask; 326 }; 327 328 struct vpd_params { 329 unsigned int cclk; 330 u8 ec[EC_LEN + 1]; 331 u8 sn[SERNUM_LEN + 1]; 332 u8 id[ID_LEN + 1]; 333 u8 pn[PN_LEN + 1]; 334 u8 na[MACADDR_LEN + 1]; 335 }; 336 337 /* Maximum resources provisioned for a PCI PF. 338 */ 339 struct pf_resources { 340 unsigned int nvi; /* N virtual interfaces */ 341 unsigned int neq; /* N egress Qs */ 342 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 343 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 344 unsigned int niq; /* N ingress Qs */ 345 unsigned int tc; /* PCI-E traffic class */ 346 unsigned int pmask; /* port access rights mask */ 347 unsigned int nexactf; /* N exact MPS filters */ 348 unsigned int r_caps; /* read capabilities */ 349 unsigned int wx_caps; /* write/execute capabilities */ 350 }; 351 352 struct pci_params { 353 unsigned int vpd_cap_addr; 354 unsigned char speed; 355 unsigned char width; 356 }; 357 358 struct devlog_params { 359 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 360 u32 start; /* start of log in firmware memory */ 361 u32 size; /* size of log */ 362 }; 363 364 /* Stores chip specific parameters */ 365 struct arch_specific_params { 366 u8 nchan; 367 u8 pm_stats_cnt; 368 u8 cng_ch_bits_log; /* congestion channel map bits width */ 369 u16 mps_rplc_size; 370 u16 vfcount; 371 u32 sge_fl_db; 372 u16 mps_tcam_size; 373 }; 374 375 struct adapter_params { 376 struct sge_params sge; 377 struct tp_params tp; 378 struct vpd_params vpd; 379 struct pf_resources pfres; 380 struct pci_params pci; 381 struct devlog_params devlog; 382 enum pcie_memwin drv_memwin; 383 384 unsigned int cim_la_size; 385 386 unsigned int sf_size; /* serial flash size in bytes */ 387 unsigned int sf_nsec; /* # of flash sectors */ 388 389 unsigned int fw_vers; /* firmware version */ 390 unsigned int bs_vers; /* bootstrap version */ 391 unsigned int tp_vers; /* TP microcode version */ 392 unsigned int er_vers; /* expansion ROM version */ 393 unsigned int scfg_vers; /* Serial Configuration version */ 394 unsigned int vpd_vers; /* VPD Version */ 395 u8 api_vers[7]; 396 397 unsigned short mtus[NMTUS]; 398 unsigned short a_wnd[NCCTRL_WIN]; 399 unsigned short b_wnd[NCCTRL_WIN]; 400 401 unsigned char nports; /* # of ethernet ports */ 402 unsigned char portvec; 403 enum chip_type chip; /* chip code */ 404 struct arch_specific_params arch; /* chip specific params */ 405 unsigned char offload; 406 unsigned char crypto; /* HW capability for crypto */ 407 unsigned char ethofld; /* QoS support */ 408 409 unsigned char bypass; 410 unsigned char hash_filter; 411 412 unsigned int ofldq_wr_cred; 413 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 414 415 unsigned int nsched_cls; /* number of traffic classes */ 416 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 417 unsigned int max_ird_adapter; /* Max read depth per adapter */ 418 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 419 u8 fw_caps_support; /* 32-bit Port Capabilities */ 420 bool filter2_wr_support; /* FW support for FILTER2_WR */ 421 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 422 423 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 424 * used by the Port 425 */ 426 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 427 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 428 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 429 }; 430 431 /* State needed to monitor the forward progress of SGE Ingress DMA activities 432 * and possible hangs. 433 */ 434 struct sge_idma_monitor_state { 435 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 436 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 437 unsigned int idma_state[2]; /* IDMA Hang detect state */ 438 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 439 unsigned int idma_warn[2]; /* time to warning in HZ */ 440 }; 441 442 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 443 * The access and execute times are signed in order to accommodate negative 444 * error returns. 445 */ 446 struct mbox_cmd { 447 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 448 u64 timestamp; /* OS-dependent timestamp */ 449 u32 seqno; /* sequence number */ 450 s16 access; /* time (ms) to access mailbox */ 451 s16 execute; /* time (ms) to execute */ 452 }; 453 454 struct mbox_cmd_log { 455 unsigned int size; /* number of entries in the log */ 456 unsigned int cursor; /* next position in the log to write */ 457 u32 seqno; /* next sequence number */ 458 /* variable length mailbox command log starts here */ 459 }; 460 461 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 462 * return a pointer to the specified entry. 463 */ 464 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 465 unsigned int entry_idx) 466 { 467 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 468 } 469 470 #define FW_VERSION(chip) ( \ 471 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 472 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 473 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 474 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 475 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 476 477 struct fw_info { 478 u8 chip; 479 char *fs_name; 480 char *fw_mod_name; 481 struct fw_hdr fw_hdr; 482 }; 483 484 struct trace_params { 485 u32 data[TRACE_LEN / 4]; 486 u32 mask[TRACE_LEN / 4]; 487 unsigned short snap_len; 488 unsigned short min_len; 489 unsigned char skip_ofst; 490 unsigned char skip_len; 491 unsigned char invert; 492 unsigned char port; 493 }; 494 495 /* Firmware Port Capabilities types. */ 496 497 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 498 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 499 500 enum fw_caps { 501 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 502 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 503 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 504 }; 505 506 struct link_config { 507 fw_port_cap32_t pcaps; /* link capabilities */ 508 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 509 fw_port_cap32_t acaps; /* advertised capabilities */ 510 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 511 512 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 513 unsigned int speed; /* actual link speed (Mb/s) */ 514 515 enum cc_pause requested_fc; /* flow control user has requested */ 516 enum cc_pause fc; /* actual link flow control */ 517 enum cc_pause advertised_fc; /* actual advertised flow control */ 518 519 enum cc_fec requested_fec; /* Forward Error Correction: */ 520 enum cc_fec fec; /* requested and actual in use */ 521 522 unsigned char autoneg; /* autonegotiating? */ 523 524 unsigned char link_ok; /* link up? */ 525 unsigned char link_down_rc; /* link down reason */ 526 527 bool new_module; /* ->OS Transceiver Module inserted */ 528 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 529 }; 530 531 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 532 533 enum { 534 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 535 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 536 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 537 }; 538 539 enum { 540 MAX_TXQ_ENTRIES = 16384, 541 MAX_CTRL_TXQ_ENTRIES = 1024, 542 MAX_RSPQ_ENTRIES = 16384, 543 MAX_RX_BUFFERS = 16384, 544 MIN_TXQ_ENTRIES = 32, 545 MIN_CTRL_TXQ_ENTRIES = 32, 546 MIN_RSPQ_ENTRIES = 128, 547 MIN_FL_ENTRIES = 16 548 }; 549 550 enum { 551 MAX_TXQ_DESC_SIZE = 64, 552 MAX_RXQ_DESC_SIZE = 128, 553 MAX_FL_DESC_SIZE = 8, 554 MAX_CTRL_TXQ_DESC_SIZE = 64, 555 }; 556 557 enum { 558 INGQ_EXTRAS = 2, /* firmware event queue and */ 559 /* forwarded interrupts */ 560 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 561 }; 562 563 enum { 564 PRIV_FLAG_PORT_TX_VM_BIT, 565 }; 566 567 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 568 569 #define PRIV_FLAGS_ADAP 0 570 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 571 572 struct adapter; 573 struct sge_rspq; 574 575 #include "cxgb4_dcb.h" 576 577 #ifdef CONFIG_CHELSIO_T4_FCOE 578 #include "cxgb4_fcoe.h" 579 #endif /* CONFIG_CHELSIO_T4_FCOE */ 580 581 struct port_info { 582 struct adapter *adapter; 583 u16 viid; 584 int xact_addr_filt; /* index of exact MAC address filter */ 585 u16 rss_size; /* size of VI's RSS table slice */ 586 s8 mdio_addr; 587 enum fw_port_type port_type; 588 u8 mod_type; 589 u8 port_id; 590 u8 tx_chan; 591 u8 lport; /* associated offload logical port */ 592 u8 nqsets; /* # of qsets */ 593 u8 first_qset; /* index of first qset */ 594 u8 rss_mode; 595 struct link_config link_cfg; 596 u16 *rss; 597 struct port_stats stats_base; 598 #ifdef CONFIG_CHELSIO_T4_DCB 599 struct port_dcb_info dcb; /* Data Center Bridging support */ 600 #endif 601 #ifdef CONFIG_CHELSIO_T4_FCOE 602 struct cxgb_fcoe fcoe; 603 #endif /* CONFIG_CHELSIO_T4_FCOE */ 604 bool rxtstamp; /* Enable TS */ 605 struct hwtstamp_config tstamp_config; 606 bool ptp_enable; 607 struct sched_table *sched_tbl; 608 u32 eth_flags; 609 610 /* viid and smt fields either returned by fw 611 * or decoded by parsing viid by driver. 612 */ 613 u8 vin; 614 u8 vivld; 615 u8 smt_idx; 616 u8 rx_cchan; 617 618 bool tc_block_shared; 619 }; 620 621 struct dentry; 622 struct work_struct; 623 624 enum { /* adapter flags */ 625 CXGB4_FULL_INIT_DONE = (1 << 0), 626 CXGB4_DEV_ENABLED = (1 << 1), 627 CXGB4_USING_MSI = (1 << 2), 628 CXGB4_USING_MSIX = (1 << 3), 629 CXGB4_FW_OK = (1 << 4), 630 CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 631 CXGB4_USING_SOFT_PARAMS = (1 << 6), 632 CXGB4_MASTER_PF = (1 << 7), 633 CXGB4_FW_OFLD_CONN = (1 << 9), 634 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 635 CXGB4_SHUTTING_DOWN = (1 << 11), 636 CXGB4_SGE_DBQ_TIMER = (1 << 12), 637 }; 638 639 enum { 640 ULP_CRYPTO_LOOKASIDE = 1 << 0, 641 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 642 ULP_CRYPTO_KTLS_INLINE = 1 << 3, 643 }; 644 645 struct rx_sw_desc; 646 647 struct sge_fl { /* SGE free-buffer queue state */ 648 unsigned int avail; /* # of available Rx buffers */ 649 unsigned int pend_cred; /* new buffers since last FL DB ring */ 650 unsigned int cidx; /* consumer index */ 651 unsigned int pidx; /* producer index */ 652 unsigned long alloc_failed; /* # of times buffer allocation failed */ 653 unsigned long large_alloc_failed; 654 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 655 unsigned long low; /* # of times momentarily starving */ 656 unsigned long starving; 657 /* RO fields */ 658 unsigned int cntxt_id; /* SGE context id for the free list */ 659 unsigned int size; /* capacity of free list */ 660 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 661 __be64 *desc; /* address of HW Rx descriptor ring */ 662 dma_addr_t addr; /* bus address of HW ring start */ 663 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 664 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 665 }; 666 667 /* A packet gather list */ 668 struct pkt_gl { 669 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 670 struct page_frag frags[MAX_SKB_FRAGS]; 671 void *va; /* virtual address of first byte */ 672 unsigned int nfrags; /* # of fragments */ 673 unsigned int tot_len; /* total length of fragments */ 674 }; 675 676 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 677 const struct pkt_gl *gl); 678 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 679 /* LRO related declarations for ULD */ 680 struct t4_lro_mgr { 681 #define MAX_LRO_SESSIONS 64 682 u8 lro_session_cnt; /* # of sessions to aggregate */ 683 unsigned long lro_pkts; /* # of LRO super packets */ 684 unsigned long lro_merged; /* # of wire packets merged by LRO */ 685 struct sk_buff_head lroq; /* list of aggregated sessions */ 686 }; 687 688 struct sge_rspq { /* state for an SGE response queue */ 689 struct napi_struct napi; 690 const __be64 *cur_desc; /* current descriptor in queue */ 691 unsigned int cidx; /* consumer index */ 692 u8 gen; /* current generation bit */ 693 u8 intr_params; /* interrupt holdoff parameters */ 694 u8 next_intr_params; /* holdoff params for next interrupt */ 695 u8 adaptive_rx; 696 u8 pktcnt_idx; /* interrupt packet threshold */ 697 u8 uld; /* ULD handling this queue */ 698 u8 idx; /* queue index within its group */ 699 int offset; /* offset into current Rx buffer */ 700 u16 cntxt_id; /* SGE context id for the response q */ 701 u16 abs_id; /* absolute SGE id for the response q */ 702 __be64 *desc; /* address of HW response ring */ 703 dma_addr_t phys_addr; /* physical address of the ring */ 704 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 705 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 706 unsigned int iqe_len; /* entry size */ 707 unsigned int size; /* capacity of response queue */ 708 struct adapter *adap; 709 struct net_device *netdev; /* associated net device */ 710 rspq_handler_t handler; 711 rspq_flush_handler_t flush_handler; 712 struct t4_lro_mgr lro_mgr; 713 }; 714 715 struct sge_eth_stats { /* Ethernet queue statistics */ 716 unsigned long pkts; /* # of ethernet packets */ 717 unsigned long lro_pkts; /* # of LRO super packets */ 718 unsigned long lro_merged; /* # of wire packets merged by LRO */ 719 unsigned long rx_cso; /* # of Rx checksum offloads */ 720 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 721 unsigned long rx_drops; /* # of packets dropped due to no mem */ 722 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 723 }; 724 725 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 726 struct sge_rspq rspq; 727 struct sge_fl fl; 728 struct sge_eth_stats stats; 729 struct msix_info *msix; 730 } ____cacheline_aligned_in_smp; 731 732 struct sge_ofld_stats { /* offload queue statistics */ 733 unsigned long pkts; /* # of packets */ 734 unsigned long imm; /* # of immediate-data packets */ 735 unsigned long an; /* # of asynchronous notifications */ 736 unsigned long nomem; /* # of responses deferred due to no mem */ 737 }; 738 739 struct sge_ofld_rxq { /* SW offload Rx queue */ 740 struct sge_rspq rspq; 741 struct sge_fl fl; 742 struct sge_ofld_stats stats; 743 struct msix_info *msix; 744 } ____cacheline_aligned_in_smp; 745 746 struct tx_desc { 747 __be64 flit[8]; 748 }; 749 750 struct ulptx_sgl; 751 752 struct tx_sw_desc { 753 struct sk_buff *skb; /* SKB to free after getting completion */ 754 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 755 }; 756 757 struct sge_txq { 758 unsigned int in_use; /* # of in-use Tx descriptors */ 759 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 760 unsigned int size; /* # of descriptors */ 761 unsigned int cidx; /* SW consumer index */ 762 unsigned int pidx; /* producer index */ 763 unsigned long stops; /* # of times q has been stopped */ 764 unsigned long restarts; /* # of queue restarts */ 765 unsigned int cntxt_id; /* SGE context id for the Tx q */ 766 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 767 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 768 struct sge_qstat *stat; /* queue status entry */ 769 dma_addr_t phys_addr; /* physical address of the ring */ 770 spinlock_t db_lock; 771 int db_disabled; 772 unsigned short db_pidx; 773 unsigned short db_pidx_inc; 774 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 775 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 776 }; 777 778 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 779 struct sge_txq q; 780 struct netdev_queue *txq; /* associated netdev TX queue */ 781 #ifdef CONFIG_CHELSIO_T4_DCB 782 u8 dcb_prio; /* DCB Priority bound to queue */ 783 #endif 784 u8 dbqt; /* SGE Doorbell Queue Timer in use */ 785 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 786 unsigned long tso; /* # of TSO requests */ 787 unsigned long uso; /* # of USO requests */ 788 unsigned long tx_cso; /* # of Tx checksum offloads */ 789 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 790 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 791 } ____cacheline_aligned_in_smp; 792 793 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 794 struct sge_txq q; 795 struct adapter *adap; 796 struct sk_buff_head sendq; /* list of backpressured packets */ 797 struct tasklet_struct qresume_tsk; /* restarts the queue */ 798 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 799 u8 full; /* the Tx ring is full */ 800 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 801 } ____cacheline_aligned_in_smp; 802 803 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 804 struct sge_txq q; 805 struct adapter *adap; 806 struct sk_buff_head sendq; /* list of backpressured packets */ 807 struct tasklet_struct qresume_tsk; /* restarts the queue */ 808 u8 full; /* the Tx ring is full */ 809 } ____cacheline_aligned_in_smp; 810 811 struct sge_uld_rxq_info { 812 char name[IFNAMSIZ]; /* name of ULD driver */ 813 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 814 u16 *rspq_id; /* response queue id's of rxq */ 815 u16 nrxq; /* # of ingress uld queues */ 816 u16 nciq; /* # of completion queues */ 817 u8 uld; /* uld type */ 818 }; 819 820 struct sge_uld_txq_info { 821 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 822 atomic_t users; /* num users */ 823 u16 ntxq; /* # of egress uld queues */ 824 }; 825 826 /* struct to maintain ULD list to reallocate ULD resources on hotplug */ 827 struct cxgb4_uld_list { 828 struct cxgb4_uld_info uld_info; 829 struct list_head list_node; 830 enum cxgb4_uld uld_type; 831 }; 832 833 enum sge_eosw_state { 834 CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 835 CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 836 CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 837 CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 838 CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 839 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 840 }; 841 842 struct sge_eosw_txq { 843 spinlock_t lock; /* Per queue lock to synchronize completions */ 844 enum sge_eosw_state state; /* Current ETHOFLD State */ 845 struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ 846 u32 ndesc; /* Number of descriptors */ 847 u32 pidx; /* Current Producer Index */ 848 u32 last_pidx; /* Last successfully transmitted Producer Index */ 849 u32 cidx; /* Current Consumer Index */ 850 u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 851 u32 flowc_idx; /* Descriptor containing a FLOWC request */ 852 u32 inuse; /* Number of packets held in ring */ 853 854 u32 cred; /* Current available credits */ 855 u32 ncompl; /* # of completions posted */ 856 u32 last_compl; /* # of credits consumed since last completion req */ 857 858 u32 eotid; /* Index into EOTID table in software */ 859 u32 hwtid; /* Hardware EOTID index */ 860 861 u32 hwqid; /* Underlying hardware queue index */ 862 struct net_device *netdev; /* Pointer to netdevice */ 863 struct tasklet_struct qresume_tsk; /* Restarts the queue */ 864 struct completion completion; /* completion for FLOWC rendezvous */ 865 }; 866 867 struct sge_eohw_txq { 868 spinlock_t lock; /* Per queue lock */ 869 struct sge_txq q; /* HW Txq */ 870 struct adapter *adap; /* Backpointer to adapter */ 871 unsigned long tso; /* # of TSO requests */ 872 unsigned long uso; /* # of USO requests */ 873 unsigned long tx_cso; /* # of Tx checksum offloads */ 874 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 875 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 876 }; 877 878 struct sge { 879 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 880 struct sge_eth_txq ptptxq; 881 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 882 883 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 884 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 885 struct sge_uld_rxq_info **uld_rxq_info; 886 struct sge_uld_txq_info **uld_txq_info; 887 888 struct sge_rspq intrq ____cacheline_aligned_in_smp; 889 spinlock_t intrq_lock; 890 891 struct sge_eohw_txq *eohw_txq; 892 struct sge_ofld_rxq *eohw_rxq; 893 894 u16 max_ethqsets; /* # of available Ethernet queue sets */ 895 u16 ethqsets; /* # of active Ethernet queue sets */ 896 u16 ethtxq_rover; /* Tx queue to clean up next */ 897 u16 ofldqsets; /* # of active ofld queue sets */ 898 u16 nqs_per_uld; /* # of Rx queues per ULD */ 899 u16 eoqsets; /* # of ETHOFLD queues */ 900 901 u16 timer_val[SGE_NTIMERS]; 902 u8 counter_val[SGE_NCOUNTERS]; 903 u16 dbqtimer_tick; 904 u16 dbqtimer_val[SGE_NDBQTIMERS]; 905 u32 fl_pg_order; /* large page allocation size */ 906 u32 stat_len; /* length of status page at ring end */ 907 u32 pktshift; /* padding between CPL & packet data */ 908 u32 fl_align; /* response queue message alignment */ 909 u32 fl_starve_thres; /* Free List starvation threshold */ 910 911 struct sge_idma_monitor_state idma_monitor; 912 unsigned int egr_start; 913 unsigned int egr_sz; 914 unsigned int ingr_start; 915 unsigned int ingr_sz; 916 void **egr_map; /* qid->queue egress queue map */ 917 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 918 unsigned long *starving_fl; 919 unsigned long *txq_maperr; 920 unsigned long *blocked_fl; 921 struct timer_list rx_timer; /* refills starving FLs */ 922 struct timer_list tx_timer; /* checks Tx queues */ 923 924 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 925 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 926 }; 927 928 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 929 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 930 931 struct l2t_data; 932 933 #ifdef CONFIG_PCI_IOV 934 935 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 936 * Configuration initialization for T5 only has SR-IOV functionality enabled 937 * on PF0-3 in order to simplify everything. 938 */ 939 #define NUM_OF_PF_WITH_SRIOV 4 940 941 #endif 942 943 struct doorbell_stats { 944 u32 db_drop; 945 u32 db_empty; 946 u32 db_full; 947 }; 948 949 struct hash_mac_addr { 950 struct list_head list; 951 u8 addr[ETH_ALEN]; 952 unsigned int iface_mac; 953 }; 954 955 struct msix_bmap { 956 unsigned long *msix_bmap; 957 unsigned int mapsize; 958 spinlock_t lock; /* lock for acquiring bitmap */ 959 }; 960 961 struct msix_info { 962 unsigned short vec; 963 char desc[IFNAMSIZ + 10]; 964 unsigned int idx; 965 cpumask_var_t aff_mask; 966 }; 967 968 struct vf_info { 969 unsigned char vf_mac_addr[ETH_ALEN]; 970 unsigned int tx_rate; 971 bool pf_set_mac; 972 u16 vlan; 973 int link_state; 974 }; 975 976 enum { 977 HMA_DMA_MAPPED_FLAG = 1 978 }; 979 980 struct hma_data { 981 unsigned char flags; 982 struct sg_table *sgt; 983 dma_addr_t *phy_addr; /* physical address of the page */ 984 }; 985 986 struct mbox_list { 987 struct list_head list; 988 }; 989 990 #if IS_ENABLED(CONFIG_THERMAL) 991 struct ch_thermal { 992 struct thermal_zone_device *tzdev; 993 int trip_temp; 994 int trip_type; 995 }; 996 #endif 997 998 struct mps_entries_ref { 999 struct list_head list; 1000 u8 addr[ETH_ALEN]; 1001 u8 mask[ETH_ALEN]; 1002 u16 idx; 1003 refcount_t refcnt; 1004 }; 1005 1006 struct adapter { 1007 void __iomem *regs; 1008 void __iomem *bar2; 1009 u32 t4_bar0; 1010 struct pci_dev *pdev; 1011 struct device *pdev_dev; 1012 const char *name; 1013 unsigned int mbox; 1014 unsigned int pf; 1015 unsigned int flags; 1016 unsigned int adap_idx; 1017 enum chip_type chip; 1018 u32 eth_flags; 1019 1020 int msg_enable; 1021 __be16 vxlan_port; 1022 u8 vxlan_port_cnt; 1023 __be16 geneve_port; 1024 u8 geneve_port_cnt; 1025 1026 struct adapter_params params; 1027 struct cxgb4_virt_res vres; 1028 unsigned int swintr; 1029 1030 /* MSI-X Info for NIC and OFLD queues */ 1031 struct msix_info *msix_info; 1032 struct msix_bmap msix_bmap; 1033 1034 struct doorbell_stats db_stats; 1035 struct sge sge; 1036 1037 struct net_device *port[MAX_NPORTS]; 1038 u8 chan_map[NCHAN]; /* channel -> port map */ 1039 1040 struct vf_info *vfinfo; 1041 u8 num_vfs; 1042 1043 u32 filter_mode; 1044 unsigned int l2t_start; 1045 unsigned int l2t_end; 1046 struct l2t_data *l2t; 1047 unsigned int clipt_start; 1048 unsigned int clipt_end; 1049 struct clip_tbl *clipt; 1050 unsigned int rawf_start; 1051 unsigned int rawf_cnt; 1052 struct smt_data *smt; 1053 struct cxgb4_uld_info *uld; 1054 void *uld_handle[CXGB4_ULD_MAX]; 1055 unsigned int num_uld; 1056 unsigned int num_ofld_uld; 1057 struct list_head list_node; 1058 struct list_head rcu_node; 1059 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 1060 struct list_head mps_ref; 1061 spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1062 1063 void *iscsi_ppm; 1064 1065 struct tid_info tids; 1066 void **tid_release_head; 1067 spinlock_t tid_release_lock; 1068 struct workqueue_struct *workq; 1069 struct work_struct tid_release_task; 1070 struct work_struct db_full_task; 1071 struct work_struct db_drop_task; 1072 struct work_struct fatal_err_notify_task; 1073 bool tid_release_task_busy; 1074 1075 /* lock for mailbox cmd list */ 1076 spinlock_t mbox_lock; 1077 struct mbox_list mlist; 1078 1079 /* support for mailbox command/reply logging */ 1080 #define T4_OS_LOG_MBOX_CMDS 256 1081 struct mbox_cmd_log *mbox_log; 1082 1083 struct mutex uld_mutex; 1084 1085 struct dentry *debugfs_root; 1086 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1087 bool trace_rss; /* 1 implies that different RSS flit per filter is 1088 * used per filter else if 0 default RSS flit is 1089 * used for all 4 filters. 1090 */ 1091 1092 struct ptp_clock *ptp_clock; 1093 struct ptp_clock_info ptp_clock_info; 1094 struct sk_buff *ptp_tx_skb; 1095 /* ptp lock */ 1096 spinlock_t ptp_lock; 1097 spinlock_t stats_lock; 1098 spinlock_t win0_lock ____cacheline_aligned_in_smp; 1099 1100 /* TC u32 offload */ 1101 struct cxgb4_tc_u32_table *tc_u32; 1102 struct chcr_ktls chcr_ktls; 1103 struct chcr_stats_debug chcr_stats; 1104 1105 /* TC flower offload */ 1106 bool tc_flower_initialized; 1107 struct rhashtable flower_tbl; 1108 struct rhashtable_params flower_ht_params; 1109 struct timer_list flower_stats_timer; 1110 struct work_struct flower_stats_work; 1111 1112 /* Ethtool Dump */ 1113 struct ethtool_dump eth_dump; 1114 1115 /* HMA */ 1116 struct hma_data hma; 1117 1118 struct srq_data *srq; 1119 1120 /* Dump buffer for collecting logs in kdump kernel */ 1121 struct vmcoredd_data vmcoredd; 1122 #if IS_ENABLED(CONFIG_THERMAL) 1123 struct ch_thermal ch_thermal; 1124 #endif 1125 1126 /* TC MQPRIO offload */ 1127 struct cxgb4_tc_mqprio *tc_mqprio; 1128 1129 /* TC MATCHALL classifier offload */ 1130 struct cxgb4_tc_matchall *tc_matchall; 1131 }; 1132 1133 /* Support for "sched-class" command to allow a TX Scheduling Class to be 1134 * programmed with various parameters. 1135 */ 1136 struct ch_sched_params { 1137 u8 type; /* packet or flow */ 1138 union { 1139 struct { 1140 u8 level; /* scheduler hierarchy level */ 1141 u8 mode; /* per-class or per-flow */ 1142 u8 rateunit; /* bit or packet rate */ 1143 u8 ratemode; /* %port relative or kbps absolute */ 1144 u8 channel; /* scheduler channel [0..N] */ 1145 u8 class; /* scheduler class [0..N] */ 1146 u32 minrate; /* minimum rate */ 1147 u32 maxrate; /* maximum rate */ 1148 u16 weight; /* percent weight */ 1149 u16 pktsize; /* average packet size */ 1150 u16 burstsize; /* burst buffer size */ 1151 } params; 1152 } u; 1153 }; 1154 1155 enum { 1156 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 1157 }; 1158 1159 enum { 1160 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 1161 SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ 1162 }; 1163 1164 enum { 1165 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1166 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 1167 }; 1168 1169 enum { 1170 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1171 }; 1172 1173 enum { 1174 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1175 }; 1176 1177 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1178 * to be bound to a TX Scheduling Class. 1179 */ 1180 struct ch_sched_queue { 1181 s8 queue; /* queue index */ 1182 s8 class; /* class index */ 1183 }; 1184 1185 /* Support for "sched_flowc" command to allow one or more FLOWC 1186 * to be bound to a TX Scheduling Class. 1187 */ 1188 struct ch_sched_flowc { 1189 s32 tid; /* TID to bind */ 1190 s8 class; /* class index */ 1191 }; 1192 1193 /* Defined bit width of user definable filter tuples 1194 */ 1195 #define ETHTYPE_BITWIDTH 16 1196 #define FRAG_BITWIDTH 1 1197 #define MACIDX_BITWIDTH 9 1198 #define FCOE_BITWIDTH 1 1199 #define IPORT_BITWIDTH 3 1200 #define MATCHTYPE_BITWIDTH 3 1201 #define PROTO_BITWIDTH 8 1202 #define TOS_BITWIDTH 8 1203 #define PF_BITWIDTH 8 1204 #define VF_BITWIDTH 8 1205 #define IVLAN_BITWIDTH 16 1206 #define OVLAN_BITWIDTH 16 1207 #define ENCAP_VNI_BITWIDTH 24 1208 1209 /* Filter matching rules. These consist of a set of ingress packet field 1210 * (value, mask) tuples. The associated ingress packet field matches the 1211 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1212 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1213 * matches an ingress packet when all of the individual individual field 1214 * matching rules are true. 1215 * 1216 * Partial field masks are always valid, however, while it may be easy to 1217 * understand their meanings for some fields (e.g. IP address to match a 1218 * subnet), for others making sensible partial masks is less intuitive (e.g. 1219 * MPS match type) ... 1220 * 1221 * Most of the following data structures are modeled on T4 capabilities. 1222 * Drivers for earlier chips use the subsets which make sense for those chips. 1223 * We really need to come up with a hardware-independent mechanism to 1224 * represent hardware filter capabilities ... 1225 */ 1226 struct ch_filter_tuple { 1227 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1228 * register selects which of these fields will participate in the 1229 * filter match rules -- up to a maximum of 36 bits. Because 1230 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1231 * set of fields. 1232 */ 1233 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1234 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1235 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1236 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1237 uint32_t pfvf_vld:1; /* PF/VF valid */ 1238 uint32_t encap_vld:1; /* Encapsulation valid */ 1239 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1240 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1241 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1242 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1243 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1244 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1245 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1246 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1247 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1248 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1249 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1250 1251 /* Uncompressed header matching field rules. These are always 1252 * available for field rules. 1253 */ 1254 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1255 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1256 uint16_t lport; /* local port */ 1257 uint16_t fport; /* foreign port */ 1258 }; 1259 1260 /* A filter ioctl command. 1261 */ 1262 struct ch_filter_specification { 1263 /* Administrative fields for filter. 1264 */ 1265 uint32_t hitcnts:1; /* count filter hits in TCB */ 1266 uint32_t prio:1; /* filter has priority over active/server */ 1267 1268 /* Fundamental filter typing. This is the one element of filter 1269 * matching that doesn't exist as a (value, mask) tuple. 1270 */ 1271 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1272 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1273 1274 /* Packet dispatch information. Ingress packets which match the 1275 * filter rules will be dropped, passed to the host or switched back 1276 * out as egress packets. 1277 */ 1278 uint32_t action:2; /* drop, pass, switch */ 1279 1280 uint32_t rpttid:1; /* report TID in RSS hash field */ 1281 1282 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1283 uint32_t iq:10; /* ingress queue */ 1284 1285 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1286 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1287 /* 1 => TCB contains IQ ID */ 1288 1289 /* Switch proxy/rewrite fields. An ingress packet which matches a 1290 * filter with "switch" set will be looped back out as an egress 1291 * packet -- potentially with some Ethernet header rewriting. 1292 */ 1293 uint32_t eport:2; /* egress port to switch packet out */ 1294 uint32_t newdmac:1; /* rewrite destination MAC address */ 1295 uint32_t newsmac:1; /* rewrite source MAC address */ 1296 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1297 uint32_t nat_mode:3; /* specify NAT operation mode */ 1298 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1299 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1300 uint16_t vlan; /* VLAN Tag to insert */ 1301 1302 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1303 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1304 u16 nat_lport; /* local port to use after NAT'ing */ 1305 u16 nat_fport; /* foreign port to use after NAT'ing */ 1306 1307 u32 tc_prio; /* TC's filter priority index */ 1308 u64 tc_cookie; /* Unique cookie identifying TC rules */ 1309 1310 /* reservation for future additions */ 1311 u8 rsvd[12]; 1312 1313 /* Filter rule value/mask pairs. 1314 */ 1315 struct ch_filter_tuple val; 1316 struct ch_filter_tuple mask; 1317 }; 1318 1319 enum { 1320 FILTER_PASS = 0, /* default */ 1321 FILTER_DROP, 1322 FILTER_SWITCH 1323 }; 1324 1325 enum { 1326 VLAN_NOCHANGE = 0, /* default */ 1327 VLAN_REMOVE, 1328 VLAN_INSERT, 1329 VLAN_REWRITE 1330 }; 1331 1332 enum { 1333 NAT_MODE_NONE = 0, /* No NAT performed */ 1334 NAT_MODE_DIP, /* NAT on Dst IP */ 1335 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1336 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1337 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1338 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1339 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1340 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1341 }; 1342 1343 /* Host shadow copy of ingress filter entry. This is in host native format 1344 * and doesn't match the ordering or bit order, etc. of the hardware of the 1345 * firmware command. The use of bit-field structure elements is purely to 1346 * remind ourselves of the field size limitations and save memory in the case 1347 * where the filter table is large. 1348 */ 1349 struct filter_entry { 1350 /* Administrative fields for filter. */ 1351 u32 valid:1; /* filter allocated and valid */ 1352 u32 locked:1; /* filter is administratively locked */ 1353 1354 u32 pending:1; /* filter action is pending firmware reply */ 1355 struct filter_ctx *ctx; /* Caller's completion hook */ 1356 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1357 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1358 struct net_device *dev; /* Associated net device */ 1359 u32 tid; /* This will store the actual tid */ 1360 1361 /* The filter itself. Most of this is a straight copy of information 1362 * provided by the extended ioctl(). Some fields are translated to 1363 * internal forms -- for instance the Ingress Queue ID passed in from 1364 * the ioctl() is translated into the Absolute Ingress Queue ID. 1365 */ 1366 struct ch_filter_specification fs; 1367 }; 1368 1369 static inline int is_offload(const struct adapter *adap) 1370 { 1371 return adap->params.offload; 1372 } 1373 1374 static inline int is_hashfilter(const struct adapter *adap) 1375 { 1376 return adap->params.hash_filter; 1377 } 1378 1379 static inline int is_pci_uld(const struct adapter *adap) 1380 { 1381 return adap->params.crypto; 1382 } 1383 1384 static inline int is_uld(const struct adapter *adap) 1385 { 1386 return (adap->params.offload || adap->params.crypto); 1387 } 1388 1389 static inline int is_ethofld(const struct adapter *adap) 1390 { 1391 return adap->params.ethofld; 1392 } 1393 1394 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1395 { 1396 return readl(adap->regs + reg_addr); 1397 } 1398 1399 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1400 { 1401 writel(val, adap->regs + reg_addr); 1402 } 1403 1404 #ifndef readq 1405 static inline u64 readq(const volatile void __iomem *addr) 1406 { 1407 return readl(addr) + ((u64)readl(addr + 4) << 32); 1408 } 1409 1410 static inline void writeq(u64 val, volatile void __iomem *addr) 1411 { 1412 writel(val, addr); 1413 writel(val >> 32, addr + 4); 1414 } 1415 #endif 1416 1417 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1418 { 1419 return readq(adap->regs + reg_addr); 1420 } 1421 1422 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1423 { 1424 writeq(val, adap->regs + reg_addr); 1425 } 1426 1427 /** 1428 * t4_set_hw_addr - store a port's MAC address in SW 1429 * @adapter: the adapter 1430 * @port_idx: the port index 1431 * @hw_addr: the Ethernet address 1432 * 1433 * Store the Ethernet address of the given port in SW. Called by the common 1434 * code when it retrieves a port's Ethernet address from EEPROM. 1435 */ 1436 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1437 u8 hw_addr[]) 1438 { 1439 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1440 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1441 } 1442 1443 /** 1444 * netdev2pinfo - return the port_info structure associated with a net_device 1445 * @dev: the netdev 1446 * 1447 * Return the struct port_info associated with a net_device 1448 */ 1449 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1450 { 1451 return netdev_priv(dev); 1452 } 1453 1454 /** 1455 * adap2pinfo - return the port_info of a port 1456 * @adap: the adapter 1457 * @idx: the port index 1458 * 1459 * Return the port_info structure for the port of the given index. 1460 */ 1461 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1462 { 1463 return netdev_priv(adap->port[idx]); 1464 } 1465 1466 /** 1467 * netdev2adap - return the adapter structure associated with a net_device 1468 * @dev: the netdev 1469 * 1470 * Return the struct adapter associated with a net_device 1471 */ 1472 static inline struct adapter *netdev2adap(const struct net_device *dev) 1473 { 1474 return netdev2pinfo(dev)->adapter; 1475 } 1476 1477 /* Return a version number to identify the type of adapter. The scheme is: 1478 * - bits 0..9: chip version 1479 * - bits 10..15: chip revision 1480 * - bits 16..23: register dump version 1481 */ 1482 static inline unsigned int mk_adap_vers(struct adapter *ap) 1483 { 1484 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1485 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1486 } 1487 1488 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1489 static inline unsigned int qtimer_val(const struct adapter *adap, 1490 const struct sge_rspq *q) 1491 { 1492 unsigned int idx = q->intr_params >> 1; 1493 1494 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1495 } 1496 1497 /* driver name used for ethtool_drvinfo */ 1498 extern char cxgb4_driver_name[]; 1499 1500 void t4_os_portmod_changed(struct adapter *adap, int port_id); 1501 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1502 1503 void t4_free_sge_resources(struct adapter *adap); 1504 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1505 irq_handler_t t4_intr_handler(struct adapter *adap); 1506 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1507 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1508 const struct pkt_gl *gl); 1509 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1510 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1511 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1512 struct net_device *dev, int intr_idx, 1513 struct sge_fl *fl, rspq_handler_t hnd, 1514 rspq_flush_handler_t flush_handler, int cong); 1515 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1516 struct net_device *dev, struct netdev_queue *netdevq, 1517 unsigned int iqid, u8 dbqt); 1518 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1519 struct net_device *dev, unsigned int iqid, 1520 unsigned int cmplqid); 1521 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1522 unsigned int cmplqid); 1523 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1524 struct net_device *dev, unsigned int iqid, 1525 unsigned int uld_type); 1526 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 1527 struct net_device *dev, u32 iqid); 1528 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1529 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1530 int t4_sge_init(struct adapter *adap); 1531 void t4_sge_start(struct adapter *adap); 1532 void t4_sge_stop(struct adapter *adap); 1533 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1534 int maxreclaim); 1535 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1536 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1537 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1538 extern int dbfifo_int_thresh; 1539 1540 #define for_each_port(adapter, iter) \ 1541 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1542 1543 static inline int is_bypass(struct adapter *adap) 1544 { 1545 return adap->params.bypass; 1546 } 1547 1548 static inline int is_bypass_device(int device) 1549 { 1550 /* this should be set based upon device capabilities */ 1551 switch (device) { 1552 case 0x440b: 1553 case 0x440c: 1554 return 1; 1555 default: 1556 return 0; 1557 } 1558 } 1559 1560 static inline int is_10gbt_device(int device) 1561 { 1562 /* this should be set based upon device capabilities */ 1563 switch (device) { 1564 case 0x4409: 1565 case 0x4486: 1566 return 1; 1567 1568 default: 1569 return 0; 1570 } 1571 } 1572 1573 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1574 { 1575 return adap->params.vpd.cclk / 1000; 1576 } 1577 1578 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1579 unsigned int us) 1580 { 1581 return (us * adap->params.vpd.cclk) / 1000; 1582 } 1583 1584 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1585 unsigned int ticks) 1586 { 1587 /* add Core Clock / 2 to round ticks to nearest uS */ 1588 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1589 adapter->params.vpd.cclk); 1590 } 1591 1592 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1593 unsigned int ticks) 1594 { 1595 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1596 } 1597 1598 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1599 u32 val); 1600 1601 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1602 int size, void *rpl, bool sleep_ok, int timeout); 1603 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1604 void *rpl, bool sleep_ok); 1605 1606 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1607 const void *cmd, int size, void *rpl, 1608 int timeout) 1609 { 1610 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1611 timeout); 1612 } 1613 1614 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1615 int size, void *rpl) 1616 { 1617 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1618 } 1619 1620 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1621 int size, void *rpl) 1622 { 1623 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1624 } 1625 1626 /** 1627 * hash_mac_addr - return the hash value of a MAC address 1628 * @addr: the 48-bit Ethernet MAC address 1629 * 1630 * Hashes a MAC address according to the hash function used by HW inexact 1631 * (hash) address matching. 1632 */ 1633 static inline int hash_mac_addr(const u8 *addr) 1634 { 1635 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1636 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1637 1638 a ^= b; 1639 a ^= (a >> 12); 1640 a ^= (a >> 6); 1641 return a & 0x3f; 1642 } 1643 1644 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1645 unsigned int cnt); 1646 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1647 unsigned int us, unsigned int cnt, 1648 unsigned int size, unsigned int iqe_size) 1649 { 1650 q->adap = adap; 1651 cxgb4_set_rspq_intr_params(q, us, cnt); 1652 q->iqe_len = iqe_size; 1653 q->size = size; 1654 } 1655 1656 /** 1657 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1658 * @fw_mod_type: the Firmware Mofule Type 1659 * 1660 * Return whether the Firmware Module Type represents a real Transceiver 1661 * Module/Cable Module Type which has been inserted. 1662 */ 1663 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1664 { 1665 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1666 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1667 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1668 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1669 } 1670 1671 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1672 unsigned int data_reg, const u32 *vals, 1673 unsigned int nregs, unsigned int start_idx); 1674 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1675 unsigned int data_reg, u32 *vals, unsigned int nregs, 1676 unsigned int start_idx); 1677 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1678 1679 struct fw_filter_wr; 1680 1681 void t4_intr_enable(struct adapter *adapter); 1682 void t4_intr_disable(struct adapter *adapter); 1683 int t4_slow_intr_handler(struct adapter *adapter); 1684 1685 int t4_wait_dev_ready(void __iomem *regs); 1686 1687 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 1688 struct link_config *lc); 1689 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 1690 unsigned int port, struct link_config *lc, 1691 u8 sleep_ok, int timeout); 1692 1693 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 1694 unsigned int port, struct link_config *lc) 1695 { 1696 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1697 true, FW_CMD_MAX_TIMEOUT); 1698 } 1699 1700 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 1701 unsigned int port, struct link_config *lc) 1702 { 1703 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1704 false, FW_CMD_MAX_TIMEOUT); 1705 } 1706 1707 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1708 1709 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1710 u32 t4_get_util_window(struct adapter *adap); 1711 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1712 1713 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1714 u32 *mem_base, u32 *mem_aperture); 1715 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1716 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1717 int dir); 1718 #define T4_MEMORY_WRITE 0 1719 #define T4_MEMORY_READ 1 1720 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1721 void *buf, int dir); 1722 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1723 u32 len, __be32 *buf) 1724 { 1725 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1726 } 1727 1728 unsigned int t4_get_regs_len(struct adapter *adapter); 1729 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1730 1731 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1732 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1733 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1734 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1735 int t4_get_pfres(struct adapter *adapter); 1736 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1737 unsigned int nwords, u32 *data, int byte_oriented); 1738 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1739 int t4_load_phy_fw(struct adapter *adap, 1740 int win, spinlock_t *lock, 1741 int (*phy_fw_version)(const u8 *, size_t), 1742 const u8 *phy_fw_data, size_t phy_fw_size); 1743 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1744 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1745 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1746 const u8 *fw_data, unsigned int size, int force); 1747 int t4_fl_pkt_align(struct adapter *adap); 1748 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1749 int t4_check_fw_version(struct adapter *adap); 1750 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1751 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1752 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1753 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1754 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1755 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1756 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1757 int t4_get_version_info(struct adapter *adapter); 1758 void t4_dump_version_info(struct adapter *adapter); 1759 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1760 const u8 *fw_data, unsigned int fw_size, 1761 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1762 int t4_prep_adapter(struct adapter *adapter); 1763 int t4_shutdown_adapter(struct adapter *adapter); 1764 1765 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1766 int t4_bar2_sge_qregs(struct adapter *adapter, 1767 unsigned int qid, 1768 enum t4_bar2_qtype qtype, 1769 int user, 1770 u64 *pbar2_qoffset, 1771 unsigned int *pbar2_qid); 1772 1773 unsigned int qtimer_val(const struct adapter *adap, 1774 const struct sge_rspq *q); 1775 1776 int t4_init_devlog_params(struct adapter *adapter); 1777 int t4_init_sge_params(struct adapter *adapter); 1778 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1779 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1780 int t4_init_rss_mode(struct adapter *adap, int mbox); 1781 int t4_init_portinfo(struct port_info *pi, int mbox, 1782 int port, int pf, int vf, u8 mac[]); 1783 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1784 void t4_fatal_err(struct adapter *adapter); 1785 unsigned int t4_chip_rss_size(struct adapter *adapter); 1786 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1787 int start, int n, const u16 *rspq, unsigned int nrspq); 1788 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1789 unsigned int flags); 1790 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1791 unsigned int flags, unsigned int defq); 1792 int t4_read_rss(struct adapter *adapter, u16 *entries); 1793 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1794 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1795 bool sleep_ok); 1796 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1797 u32 *valp, bool sleep_ok); 1798 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1799 u32 *vfl, u32 *vfh, bool sleep_ok); 1800 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1801 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1802 1803 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1804 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1805 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1806 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1807 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1808 size_t n); 1809 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1810 size_t n); 1811 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1812 unsigned int *valp); 1813 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1814 const unsigned int *valp); 1815 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1816 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1817 unsigned int *pif_req_wrptr, 1818 unsigned int *pif_rsp_wrptr); 1819 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1820 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1821 const char *t4_get_port_type_description(enum fw_port_type port_type); 1822 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1823 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1824 struct port_stats *stats, 1825 struct port_stats *offset); 1826 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1827 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1828 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1829 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1830 unsigned int mask, unsigned int val); 1831 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1832 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1833 bool sleep_ok); 1834 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1835 bool sleep_ok); 1836 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1837 bool sleep_ok); 1838 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1839 bool sleep_ok); 1840 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1841 struct tp_tcp_stats *v6, bool sleep_ok); 1842 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1843 struct tp_fcoe_stats *st, bool sleep_ok); 1844 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1845 const unsigned short *alpha, const unsigned short *beta); 1846 1847 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1848 1849 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1850 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1851 1852 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1853 const u8 *addr); 1854 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1855 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1856 1857 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1858 enum dev_master master, enum dev_state *state); 1859 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1860 int t4_early_init(struct adapter *adap, unsigned int mbox); 1861 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1862 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1863 unsigned int cache_line_size); 1864 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1865 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1866 unsigned int vf, unsigned int nparams, const u32 *params, 1867 u32 *val); 1868 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1869 unsigned int vf, unsigned int nparams, const u32 *params, 1870 u32 *val); 1871 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1872 unsigned int vf, unsigned int nparams, const u32 *params, 1873 u32 *val, int rw, bool sleep_ok); 1874 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1875 unsigned int pf, unsigned int vf, 1876 unsigned int nparams, const u32 *params, 1877 const u32 *val, int timeout); 1878 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1879 unsigned int vf, unsigned int nparams, const u32 *params, 1880 const u32 *val); 1881 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1882 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1883 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1884 unsigned int vi, unsigned int cmask, unsigned int pmask, 1885 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1886 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1887 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1888 unsigned int *rss_size, u8 *vivld, u8 *vin); 1889 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1890 unsigned int pf, unsigned int vf, 1891 unsigned int viid); 1892 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1893 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1894 bool sleep_ok); 1895 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1896 const u8 *addr, const u8 *mask, unsigned int idx, 1897 u8 lookup_type, u8 port_id, bool sleep_ok); 1898 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 1899 bool sleep_ok); 1900 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 1901 const u8 *addr, const u8 *mask, unsigned int vni, 1902 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 1903 bool sleep_ok); 1904 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1905 const u8 *addr, const u8 *mask, unsigned int idx, 1906 u8 lookup_type, u8 port_id, bool sleep_ok); 1907 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1908 unsigned int viid, bool free, unsigned int naddr, 1909 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1910 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1911 unsigned int viid, unsigned int naddr, 1912 const u8 **addr, bool sleep_ok); 1913 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1914 int idx, const u8 *addr, bool persist, u8 *smt_idx); 1915 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1916 bool ucast, u64 vec, bool sleep_ok); 1917 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1918 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1919 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1920 struct port_info *pi, 1921 bool rx_en, bool tx_en, bool dcb_en); 1922 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1923 bool rx_en, bool tx_en); 1924 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1925 unsigned int nblinks); 1926 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1927 unsigned int mmd, unsigned int reg, u16 *valp); 1928 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1929 unsigned int mmd, unsigned int reg, u16 val); 1930 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1931 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1932 unsigned int fl0id, unsigned int fl1id); 1933 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1934 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1935 unsigned int fl0id, unsigned int fl1id); 1936 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1937 unsigned int vf, unsigned int eqid); 1938 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1939 unsigned int vf, unsigned int eqid); 1940 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1941 unsigned int vf, unsigned int eqid); 1942 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1943 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 1944 u16 *dbqtimers); 1945 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1946 int t4_update_port_info(struct port_info *pi); 1947 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1948 unsigned int *speedp, unsigned int *mtup); 1949 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1950 void t4_db_full(struct adapter *adapter); 1951 void t4_db_dropped(struct adapter *adapter); 1952 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1953 int filter_index, int enable); 1954 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1955 int filter_index, int *enabled); 1956 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1957 u32 addr, u32 val); 1958 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1959 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1960 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1961 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1962 enum ctxt_type ctype, u32 *data); 1963 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1964 enum ctxt_type ctype, u32 *data); 1965 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode, 1966 u8 rateunit, u8 ratemode, u8 channel, u8 class, 1967 u32 minrate, u32 maxrate, u16 weight, u16 pktsize, 1968 u16 burstsize); 1969 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1970 void t4_idma_monitor_init(struct adapter *adapter, 1971 struct sge_idma_monitor_state *idma); 1972 void t4_idma_monitor(struct adapter *adapter, 1973 struct sge_idma_monitor_state *idma, 1974 int hz, int ticks); 1975 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1976 unsigned int naddr, u8 *addr); 1977 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1978 u32 start_index, bool sleep_ok); 1979 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1980 u32 start_index, bool sleep_ok); 1981 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1982 u32 start_index, bool sleep_ok); 1983 1984 void t4_uld_mem_free(struct adapter *adap); 1985 int t4_uld_mem_alloc(struct adapter *adap); 1986 void t4_uld_clean_up(struct adapter *adap); 1987 void t4_register_netevent_notifier(void); 1988 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1989 unsigned int devid, unsigned int offset, 1990 unsigned int len, u8 *buf); 1991 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1992 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1993 unsigned int n, bool unmap); 1994 void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 1995 u32 ndesc); 1996 int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 1997 void cxgb4_ethofld_restart(unsigned long data); 1998 int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 1999 const struct pkt_gl *si); 2000 void free_txq(struct adapter *adap, struct sge_txq *q); 2001 void cxgb4_reclaim_completed_tx(struct adapter *adap, 2002 struct sge_txq *q, bool unmap); 2003 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 2004 dma_addr_t *addr); 2005 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 2006 void *pos); 2007 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 2008 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 2009 const dma_addr_t *addr); 2010 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 2011 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 2012 u16 vlan); 2013 int cxgb4_dcb_enabled(const struct net_device *dev); 2014 2015 int cxgb4_thermal_init(struct adapter *adap); 2016 int cxgb4_thermal_remove(struct adapter *adap); 2017 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 2018 cpumask_var_t *aff_mask, int idx); 2019 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 2020 2021 int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 2022 int *tcam_idx, const u8 *addr, 2023 bool persistent, u8 *smt_idx); 2024 2025 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 2026 bool free, unsigned int naddr, 2027 const u8 **addr, u16 *idx, 2028 u64 *hash, bool sleep_ok); 2029 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2030 unsigned int naddr, const u8 **addr, bool sleep_ok); 2031 int cxgb4_init_mps_ref_entries(struct adapter *adap); 2032 void cxgb4_free_mps_ref_entries(struct adapter *adap); 2033 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 2034 const u8 *addr, const u8 *mask, 2035 unsigned int vni, unsigned int vni_mask, 2036 u8 dip_hit, u8 lookup_type, bool sleep_ok); 2037 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 2038 int idx, bool sleep_ok); 2039 int cxgb4_free_raw_mac_filt(struct adapter *adap, 2040 unsigned int viid, 2041 const u8 *addr, 2042 const u8 *mask, 2043 unsigned int idx, 2044 u8 lookup_type, 2045 u8 port_id, 2046 bool sleep_ok); 2047 int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 2048 unsigned int viid, 2049 const u8 *addr, 2050 const u8 *mask, 2051 unsigned int idx, 2052 u8 lookup_type, 2053 u8 port_id, 2054 bool sleep_ok); 2055 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 2056 int *tcam_idx, const u8 *addr, 2057 bool persistent, u8 *smt_idx); 2058 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 2059 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2060 int cxgb_open(struct net_device *dev); 2061 int cxgb_close(struct net_device *dev); 2062 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 2063 void cxgb4_quiesce_rx(struct sge_rspq *q); 2064 #ifdef CONFIG_CHELSIO_TLS_DEVICE 2065 int cxgb4_set_ktls_feature(struct adapter *adap, bool enable); 2066 #endif 2067 #endif /* __CXGB4_H__ */ 2068