1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/etherdevice.h> 50 #include <linux/net_tstamp.h> 51 #include <asm/io.h> 52 #include "t4_chip_type.h" 53 #include "cxgb4_uld.h" 54 55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 56 extern struct list_head adapter_list; 57 extern struct mutex uld_mutex; 58 59 enum { 60 MAX_NPORTS = 4, /* max # of ports */ 61 SERNUM_LEN = 24, /* Serial # length */ 62 EC_LEN = 16, /* E/C length */ 63 ID_LEN = 16, /* ID length */ 64 PN_LEN = 16, /* Part Number length */ 65 MACADDR_LEN = 12, /* MAC Address length */ 66 }; 67 68 enum { 69 T4_REGMAP_SIZE = (160 * 1024), 70 T5_REGMAP_SIZE = (332 * 1024), 71 }; 72 73 enum { 74 MEM_EDC0, 75 MEM_EDC1, 76 MEM_MC, 77 MEM_MC0 = MEM_MC, 78 MEM_MC1 79 }; 80 81 enum { 82 MEMWIN0_APERTURE = 2048, 83 MEMWIN0_BASE = 0x1b800, 84 MEMWIN1_APERTURE = 32768, 85 MEMWIN1_BASE = 0x28000, 86 MEMWIN1_BASE_T5 = 0x52000, 87 MEMWIN2_APERTURE = 65536, 88 MEMWIN2_BASE = 0x30000, 89 MEMWIN2_APERTURE_T5 = 131072, 90 MEMWIN2_BASE_T5 = 0x60000, 91 }; 92 93 enum dev_master { 94 MASTER_CANT, 95 MASTER_MAY, 96 MASTER_MUST 97 }; 98 99 enum dev_state { 100 DEV_STATE_UNINIT, 101 DEV_STATE_INIT, 102 DEV_STATE_ERR 103 }; 104 105 enum { 106 PAUSE_RX = 1 << 0, 107 PAUSE_TX = 1 << 1, 108 PAUSE_AUTONEG = 1 << 2 109 }; 110 111 enum { 112 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 113 FEC_RS = 1 << 1, /* Reed-Solomon */ 114 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 115 }; 116 117 struct port_stats { 118 u64 tx_octets; /* total # of octets in good frames */ 119 u64 tx_frames; /* all good frames */ 120 u64 tx_bcast_frames; /* all broadcast frames */ 121 u64 tx_mcast_frames; /* all multicast frames */ 122 u64 tx_ucast_frames; /* all unicast frames */ 123 u64 tx_error_frames; /* all error frames */ 124 125 u64 tx_frames_64; /* # of Tx frames in a particular range */ 126 u64 tx_frames_65_127; 127 u64 tx_frames_128_255; 128 u64 tx_frames_256_511; 129 u64 tx_frames_512_1023; 130 u64 tx_frames_1024_1518; 131 u64 tx_frames_1519_max; 132 133 u64 tx_drop; /* # of dropped Tx frames */ 134 u64 tx_pause; /* # of transmitted pause frames */ 135 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 136 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 137 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 138 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 139 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 140 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 141 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 142 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 143 144 u64 rx_octets; /* total # of octets in good frames */ 145 u64 rx_frames; /* all good frames */ 146 u64 rx_bcast_frames; /* all broadcast frames */ 147 u64 rx_mcast_frames; /* all multicast frames */ 148 u64 rx_ucast_frames; /* all unicast frames */ 149 u64 rx_too_long; /* # of frames exceeding MTU */ 150 u64 rx_jabber; /* # of jabber frames */ 151 u64 rx_fcs_err; /* # of received frames with bad FCS */ 152 u64 rx_len_err; /* # of received frames with length error */ 153 u64 rx_symbol_err; /* symbol errors */ 154 u64 rx_runt; /* # of short frames */ 155 156 u64 rx_frames_64; /* # of Rx frames in a particular range */ 157 u64 rx_frames_65_127; 158 u64 rx_frames_128_255; 159 u64 rx_frames_256_511; 160 u64 rx_frames_512_1023; 161 u64 rx_frames_1024_1518; 162 u64 rx_frames_1519_max; 163 164 u64 rx_pause; /* # of received pause frames */ 165 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 166 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 167 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 168 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 169 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 170 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 171 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 172 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 173 174 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 175 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 176 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 177 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 178 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 179 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 180 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 181 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 182 }; 183 184 struct lb_port_stats { 185 u64 octets; 186 u64 frames; 187 u64 bcast_frames; 188 u64 mcast_frames; 189 u64 ucast_frames; 190 u64 error_frames; 191 192 u64 frames_64; 193 u64 frames_65_127; 194 u64 frames_128_255; 195 u64 frames_256_511; 196 u64 frames_512_1023; 197 u64 frames_1024_1518; 198 u64 frames_1519_max; 199 200 u64 drop; 201 202 u64 ovflow0; 203 u64 ovflow1; 204 u64 ovflow2; 205 u64 ovflow3; 206 u64 trunc0; 207 u64 trunc1; 208 u64 trunc2; 209 u64 trunc3; 210 }; 211 212 struct tp_tcp_stats { 213 u32 tcp_out_rsts; 214 u64 tcp_in_segs; 215 u64 tcp_out_segs; 216 u64 tcp_retrans_segs; 217 }; 218 219 struct tp_usm_stats { 220 u32 frames; 221 u32 drops; 222 u64 octets; 223 }; 224 225 struct tp_fcoe_stats { 226 u32 frames_ddp; 227 u32 frames_drop; 228 u64 octets_ddp; 229 }; 230 231 struct tp_err_stats { 232 u32 mac_in_errs[4]; 233 u32 hdr_in_errs[4]; 234 u32 tcp_in_errs[4]; 235 u32 tnl_cong_drops[4]; 236 u32 ofld_chan_drops[4]; 237 u32 tnl_tx_drops[4]; 238 u32 ofld_vlan_drops[4]; 239 u32 tcp6_in_errs[4]; 240 u32 ofld_no_neigh; 241 u32 ofld_cong_defer; 242 }; 243 244 struct tp_cpl_stats { 245 u32 req[4]; 246 u32 rsp[4]; 247 }; 248 249 struct tp_rdma_stats { 250 u32 rqe_dfr_pkt; 251 u32 rqe_dfr_mod; 252 }; 253 254 struct sge_params { 255 u32 hps; /* host page size for our PF/VF */ 256 u32 eq_qpp; /* egress queues/page for our PF/VF */ 257 u32 iq_qpp; /* egress queues/page for our PF/VF */ 258 }; 259 260 struct tp_params { 261 unsigned int tre; /* log2 of core clocks per TP tick */ 262 unsigned int la_mask; /* what events are recorded by TP LA */ 263 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 264 /* channel map */ 265 266 uint32_t dack_re; /* DACK timer resolution */ 267 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 268 269 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 270 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 271 272 /* cached TP_OUT_CONFIG compressed error vector 273 * and passing outer header info for encapsulated packets. 274 */ 275 int rx_pkt_encap; 276 277 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 278 * subset of the set of fields which may be present in the Compressed 279 * Filter Tuple portion of filters and TCP TCB connections. The 280 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 281 * Since a variable number of fields may or may not be present, their 282 * shifted field positions within the Compressed Filter Tuple may 283 * vary, or not even be present if the field isn't selected in 284 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 285 * places we store their offsets here, or a -1 if the field isn't 286 * present. 287 */ 288 int vlan_shift; 289 int vnic_shift; 290 int port_shift; 291 int protocol_shift; 292 }; 293 294 struct vpd_params { 295 unsigned int cclk; 296 u8 ec[EC_LEN + 1]; 297 u8 sn[SERNUM_LEN + 1]; 298 u8 id[ID_LEN + 1]; 299 u8 pn[PN_LEN + 1]; 300 u8 na[MACADDR_LEN + 1]; 301 }; 302 303 struct pci_params { 304 unsigned char speed; 305 unsigned char width; 306 }; 307 308 struct devlog_params { 309 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 310 u32 start; /* start of log in firmware memory */ 311 u32 size; /* size of log */ 312 }; 313 314 /* Stores chip specific parameters */ 315 struct arch_specific_params { 316 u8 nchan; 317 u8 pm_stats_cnt; 318 u8 cng_ch_bits_log; /* congestion channel map bits width */ 319 u16 mps_rplc_size; 320 u16 vfcount; 321 u32 sge_fl_db; 322 u16 mps_tcam_size; 323 }; 324 325 struct adapter_params { 326 struct sge_params sge; 327 struct tp_params tp; 328 struct vpd_params vpd; 329 struct pci_params pci; 330 struct devlog_params devlog; 331 enum pcie_memwin drv_memwin; 332 333 unsigned int cim_la_size; 334 335 unsigned int sf_size; /* serial flash size in bytes */ 336 unsigned int sf_nsec; /* # of flash sectors */ 337 unsigned int sf_fw_start; /* start of FW image in flash */ 338 339 unsigned int fw_vers; 340 unsigned int bs_vers; /* bootstrap version */ 341 unsigned int tp_vers; 342 unsigned int er_vers; /* expansion ROM version */ 343 u8 api_vers[7]; 344 345 unsigned short mtus[NMTUS]; 346 unsigned short a_wnd[NCCTRL_WIN]; 347 unsigned short b_wnd[NCCTRL_WIN]; 348 349 unsigned char nports; /* # of ethernet ports */ 350 unsigned char portvec; 351 enum chip_type chip; /* chip code */ 352 struct arch_specific_params arch; /* chip specific params */ 353 unsigned char offload; 354 unsigned char crypto; /* HW capability for crypto */ 355 356 unsigned char bypass; 357 358 unsigned int ofldq_wr_cred; 359 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 360 361 unsigned int nsched_cls; /* number of traffic classes */ 362 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 363 unsigned int max_ird_adapter; /* Max read depth per adapter */ 364 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 365 }; 366 367 /* State needed to monitor the forward progress of SGE Ingress DMA activities 368 * and possible hangs. 369 */ 370 struct sge_idma_monitor_state { 371 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 372 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 373 unsigned int idma_state[2]; /* IDMA Hang detect state */ 374 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 375 unsigned int idma_warn[2]; /* time to warning in HZ */ 376 }; 377 378 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 379 * The access and execute times are signed in order to accommodate negative 380 * error returns. 381 */ 382 struct mbox_cmd { 383 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 384 u64 timestamp; /* OS-dependent timestamp */ 385 u32 seqno; /* sequence number */ 386 s16 access; /* time (ms) to access mailbox */ 387 s16 execute; /* time (ms) to execute */ 388 }; 389 390 struct mbox_cmd_log { 391 unsigned int size; /* number of entries in the log */ 392 unsigned int cursor; /* next position in the log to write */ 393 u32 seqno; /* next sequence number */ 394 /* variable length mailbox command log starts here */ 395 }; 396 397 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 398 * return a pointer to the specified entry. 399 */ 400 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 401 unsigned int entry_idx) 402 { 403 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 404 } 405 406 #include "t4fw_api.h" 407 408 #define FW_VERSION(chip) ( \ 409 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 410 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 411 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 412 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 413 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 414 415 struct fw_info { 416 u8 chip; 417 char *fs_name; 418 char *fw_mod_name; 419 struct fw_hdr fw_hdr; 420 }; 421 422 struct trace_params { 423 u32 data[TRACE_LEN / 4]; 424 u32 mask[TRACE_LEN / 4]; 425 unsigned short snap_len; 426 unsigned short min_len; 427 unsigned char skip_ofst; 428 unsigned char skip_len; 429 unsigned char invert; 430 unsigned char port; 431 }; 432 433 struct link_config { 434 unsigned short supported; /* link capabilities */ 435 unsigned short advertising; /* advertised capabilities */ 436 unsigned short lp_advertising; /* peer advertised capabilities */ 437 unsigned int requested_speed; /* speed user has requested */ 438 unsigned int speed; /* actual link speed */ 439 unsigned char requested_fc; /* flow control user has requested */ 440 unsigned char fc; /* actual link flow control */ 441 unsigned char auto_fec; /* Forward Error Correction: */ 442 unsigned char requested_fec; /* "automatic" (IEEE 802.3), */ 443 unsigned char fec; /* requested, and actual in use */ 444 unsigned char autoneg; /* autonegotiating? */ 445 unsigned char link_ok; /* link up? */ 446 unsigned char link_down_rc; /* link down reason */ 447 }; 448 449 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 450 451 enum { 452 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 453 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 454 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 455 }; 456 457 enum { 458 MAX_TXQ_ENTRIES = 16384, 459 MAX_CTRL_TXQ_ENTRIES = 1024, 460 MAX_RSPQ_ENTRIES = 16384, 461 MAX_RX_BUFFERS = 16384, 462 MIN_TXQ_ENTRIES = 32, 463 MIN_CTRL_TXQ_ENTRIES = 32, 464 MIN_RSPQ_ENTRIES = 128, 465 MIN_FL_ENTRIES = 16 466 }; 467 468 enum { 469 INGQ_EXTRAS = 2, /* firmware event queue and */ 470 /* forwarded interrupts */ 471 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 472 }; 473 474 struct adapter; 475 struct sge_rspq; 476 477 #include "cxgb4_dcb.h" 478 479 #ifdef CONFIG_CHELSIO_T4_FCOE 480 #include "cxgb4_fcoe.h" 481 #endif /* CONFIG_CHELSIO_T4_FCOE */ 482 483 struct port_info { 484 struct adapter *adapter; 485 u16 viid; 486 s16 xact_addr_filt; /* index of exact MAC address filter */ 487 u16 rss_size; /* size of VI's RSS table slice */ 488 s8 mdio_addr; 489 enum fw_port_type port_type; 490 u8 mod_type; 491 u8 port_id; 492 u8 tx_chan; 493 u8 lport; /* associated offload logical port */ 494 u8 nqsets; /* # of qsets */ 495 u8 first_qset; /* index of first qset */ 496 u8 rss_mode; 497 struct link_config link_cfg; 498 u16 *rss; 499 struct port_stats stats_base; 500 #ifdef CONFIG_CHELSIO_T4_DCB 501 struct port_dcb_info dcb; /* Data Center Bridging support */ 502 #endif 503 #ifdef CONFIG_CHELSIO_T4_FCOE 504 struct cxgb_fcoe fcoe; 505 #endif /* CONFIG_CHELSIO_T4_FCOE */ 506 bool rxtstamp; /* Enable TS */ 507 struct hwtstamp_config tstamp_config; 508 struct sched_table *sched_tbl; 509 }; 510 511 struct dentry; 512 struct work_struct; 513 514 enum { /* adapter flags */ 515 FULL_INIT_DONE = (1 << 0), 516 DEV_ENABLED = (1 << 1), 517 USING_MSI = (1 << 2), 518 USING_MSIX = (1 << 3), 519 FW_OK = (1 << 4), 520 RSS_TNLALLLOOKUP = (1 << 5), 521 USING_SOFT_PARAMS = (1 << 6), 522 MASTER_PF = (1 << 7), 523 FW_OFLD_CONN = (1 << 9), 524 }; 525 526 enum { 527 ULP_CRYPTO_LOOKASIDE = 1 << 0, 528 }; 529 530 struct rx_sw_desc; 531 532 struct sge_fl { /* SGE free-buffer queue state */ 533 unsigned int avail; /* # of available Rx buffers */ 534 unsigned int pend_cred; /* new buffers since last FL DB ring */ 535 unsigned int cidx; /* consumer index */ 536 unsigned int pidx; /* producer index */ 537 unsigned long alloc_failed; /* # of times buffer allocation failed */ 538 unsigned long large_alloc_failed; 539 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 540 unsigned long low; /* # of times momentarily starving */ 541 unsigned long starving; 542 /* RO fields */ 543 unsigned int cntxt_id; /* SGE context id for the free list */ 544 unsigned int size; /* capacity of free list */ 545 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 546 __be64 *desc; /* address of HW Rx descriptor ring */ 547 dma_addr_t addr; /* bus address of HW ring start */ 548 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 549 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 550 }; 551 552 /* A packet gather list */ 553 struct pkt_gl { 554 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 555 struct page_frag frags[MAX_SKB_FRAGS]; 556 void *va; /* virtual address of first byte */ 557 unsigned int nfrags; /* # of fragments */ 558 unsigned int tot_len; /* total length of fragments */ 559 }; 560 561 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 562 const struct pkt_gl *gl); 563 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 564 /* LRO related declarations for ULD */ 565 struct t4_lro_mgr { 566 #define MAX_LRO_SESSIONS 64 567 u8 lro_session_cnt; /* # of sessions to aggregate */ 568 unsigned long lro_pkts; /* # of LRO super packets */ 569 unsigned long lro_merged; /* # of wire packets merged by LRO */ 570 struct sk_buff_head lroq; /* list of aggregated sessions */ 571 }; 572 573 struct sge_rspq { /* state for an SGE response queue */ 574 struct napi_struct napi; 575 const __be64 *cur_desc; /* current descriptor in queue */ 576 unsigned int cidx; /* consumer index */ 577 u8 gen; /* current generation bit */ 578 u8 intr_params; /* interrupt holdoff parameters */ 579 u8 next_intr_params; /* holdoff params for next interrupt */ 580 u8 adaptive_rx; 581 u8 pktcnt_idx; /* interrupt packet threshold */ 582 u8 uld; /* ULD handling this queue */ 583 u8 idx; /* queue index within its group */ 584 int offset; /* offset into current Rx buffer */ 585 u16 cntxt_id; /* SGE context id for the response q */ 586 u16 abs_id; /* absolute SGE id for the response q */ 587 __be64 *desc; /* address of HW response ring */ 588 dma_addr_t phys_addr; /* physical address of the ring */ 589 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 590 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 591 unsigned int iqe_len; /* entry size */ 592 unsigned int size; /* capacity of response queue */ 593 struct adapter *adap; 594 struct net_device *netdev; /* associated net device */ 595 rspq_handler_t handler; 596 rspq_flush_handler_t flush_handler; 597 struct t4_lro_mgr lro_mgr; 598 }; 599 600 struct sge_eth_stats { /* Ethernet queue statistics */ 601 unsigned long pkts; /* # of ethernet packets */ 602 unsigned long lro_pkts; /* # of LRO super packets */ 603 unsigned long lro_merged; /* # of wire packets merged by LRO */ 604 unsigned long rx_cso; /* # of Rx checksum offloads */ 605 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 606 unsigned long rx_drops; /* # of packets dropped due to no mem */ 607 }; 608 609 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 610 struct sge_rspq rspq; 611 struct sge_fl fl; 612 struct sge_eth_stats stats; 613 } ____cacheline_aligned_in_smp; 614 615 struct sge_ofld_stats { /* offload queue statistics */ 616 unsigned long pkts; /* # of packets */ 617 unsigned long imm; /* # of immediate-data packets */ 618 unsigned long an; /* # of asynchronous notifications */ 619 unsigned long nomem; /* # of responses deferred due to no mem */ 620 }; 621 622 struct sge_ofld_rxq { /* SW offload Rx queue */ 623 struct sge_rspq rspq; 624 struct sge_fl fl; 625 struct sge_ofld_stats stats; 626 } ____cacheline_aligned_in_smp; 627 628 struct tx_desc { 629 __be64 flit[8]; 630 }; 631 632 struct tx_sw_desc; 633 634 struct sge_txq { 635 unsigned int in_use; /* # of in-use Tx descriptors */ 636 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 637 unsigned int size; /* # of descriptors */ 638 unsigned int cidx; /* SW consumer index */ 639 unsigned int pidx; /* producer index */ 640 unsigned long stops; /* # of times q has been stopped */ 641 unsigned long restarts; /* # of queue restarts */ 642 unsigned int cntxt_id; /* SGE context id for the Tx q */ 643 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 644 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 645 struct sge_qstat *stat; /* queue status entry */ 646 dma_addr_t phys_addr; /* physical address of the ring */ 647 spinlock_t db_lock; 648 int db_disabled; 649 unsigned short db_pidx; 650 unsigned short db_pidx_inc; 651 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 652 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 653 }; 654 655 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 656 struct sge_txq q; 657 struct netdev_queue *txq; /* associated netdev TX queue */ 658 #ifdef CONFIG_CHELSIO_T4_DCB 659 u8 dcb_prio; /* DCB Priority bound to queue */ 660 #endif 661 unsigned long tso; /* # of TSO requests */ 662 unsigned long tx_cso; /* # of Tx checksum offloads */ 663 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 664 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 665 } ____cacheline_aligned_in_smp; 666 667 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 668 struct sge_txq q; 669 struct adapter *adap; 670 struct sk_buff_head sendq; /* list of backpressured packets */ 671 struct tasklet_struct qresume_tsk; /* restarts the queue */ 672 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 673 u8 full; /* the Tx ring is full */ 674 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 675 } ____cacheline_aligned_in_smp; 676 677 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 678 struct sge_txq q; 679 struct adapter *adap; 680 struct sk_buff_head sendq; /* list of backpressured packets */ 681 struct tasklet_struct qresume_tsk; /* restarts the queue */ 682 u8 full; /* the Tx ring is full */ 683 } ____cacheline_aligned_in_smp; 684 685 struct sge_uld_rxq_info { 686 char name[IFNAMSIZ]; /* name of ULD driver */ 687 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 688 u16 *msix_tbl; /* msix_tbl for uld */ 689 u16 *rspq_id; /* response queue id's of rxq */ 690 u16 nrxq; /* # of ingress uld queues */ 691 u16 nciq; /* # of completion queues */ 692 u8 uld; /* uld type */ 693 }; 694 695 struct sge_uld_txq_info { 696 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 697 atomic_t users; /* num users */ 698 u16 ntxq; /* # of egress uld queues */ 699 }; 700 701 struct sge { 702 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 703 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 704 705 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 706 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 707 struct sge_uld_rxq_info **uld_rxq_info; 708 struct sge_uld_txq_info **uld_txq_info; 709 710 struct sge_rspq intrq ____cacheline_aligned_in_smp; 711 spinlock_t intrq_lock; 712 713 u16 max_ethqsets; /* # of available Ethernet queue sets */ 714 u16 ethqsets; /* # of active Ethernet queue sets */ 715 u16 ethtxq_rover; /* Tx queue to clean up next */ 716 u16 ofldqsets; /* # of active ofld queue sets */ 717 u16 nqs_per_uld; /* # of Rx queues per ULD */ 718 u16 timer_val[SGE_NTIMERS]; 719 u8 counter_val[SGE_NCOUNTERS]; 720 u32 fl_pg_order; /* large page allocation size */ 721 u32 stat_len; /* length of status page at ring end */ 722 u32 pktshift; /* padding between CPL & packet data */ 723 u32 fl_align; /* response queue message alignment */ 724 u32 fl_starve_thres; /* Free List starvation threshold */ 725 726 struct sge_idma_monitor_state idma_monitor; 727 unsigned int egr_start; 728 unsigned int egr_sz; 729 unsigned int ingr_start; 730 unsigned int ingr_sz; 731 void **egr_map; /* qid->queue egress queue map */ 732 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 733 unsigned long *starving_fl; 734 unsigned long *txq_maperr; 735 unsigned long *blocked_fl; 736 struct timer_list rx_timer; /* refills starving FLs */ 737 struct timer_list tx_timer; /* checks Tx queues */ 738 }; 739 740 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 741 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 742 743 struct l2t_data; 744 745 #ifdef CONFIG_PCI_IOV 746 747 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 748 * Configuration initialization for T5 only has SR-IOV functionality enabled 749 * on PF0-3 in order to simplify everything. 750 */ 751 #define NUM_OF_PF_WITH_SRIOV 4 752 753 #endif 754 755 struct doorbell_stats { 756 u32 db_drop; 757 u32 db_empty; 758 u32 db_full; 759 }; 760 761 struct hash_mac_addr { 762 struct list_head list; 763 u8 addr[ETH_ALEN]; 764 }; 765 766 struct uld_msix_bmap { 767 unsigned long *msix_bmap; 768 unsigned int mapsize; 769 spinlock_t lock; /* lock for acquiring bitmap */ 770 }; 771 772 struct uld_msix_info { 773 unsigned short vec; 774 char desc[IFNAMSIZ + 10]; 775 unsigned int idx; 776 }; 777 778 struct vf_info { 779 unsigned char vf_mac_addr[ETH_ALEN]; 780 bool pf_set_mac; 781 }; 782 783 struct mbox_list { 784 struct list_head list; 785 }; 786 787 struct adapter { 788 void __iomem *regs; 789 void __iomem *bar2; 790 u32 t4_bar0; 791 struct pci_dev *pdev; 792 struct device *pdev_dev; 793 const char *name; 794 unsigned int mbox; 795 unsigned int pf; 796 unsigned int flags; 797 unsigned int adap_idx; 798 enum chip_type chip; 799 800 int msg_enable; 801 802 struct adapter_params params; 803 struct cxgb4_virt_res vres; 804 unsigned int swintr; 805 806 struct { 807 unsigned short vec; 808 char desc[IFNAMSIZ + 10]; 809 } msix_info[MAX_INGQ + 1]; 810 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 811 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 812 int msi_idx; 813 814 struct doorbell_stats db_stats; 815 struct sge sge; 816 817 struct net_device *port[MAX_NPORTS]; 818 u8 chan_map[NCHAN]; /* channel -> port map */ 819 820 struct vf_info *vfinfo; 821 u8 num_vfs; 822 823 u32 filter_mode; 824 unsigned int l2t_start; 825 unsigned int l2t_end; 826 struct l2t_data *l2t; 827 unsigned int clipt_start; 828 unsigned int clipt_end; 829 struct clip_tbl *clipt; 830 struct cxgb4_uld_info *uld; 831 void *uld_handle[CXGB4_ULD_MAX]; 832 unsigned int num_uld; 833 unsigned int num_ofld_uld; 834 struct list_head list_node; 835 struct list_head rcu_node; 836 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 837 838 void *iscsi_ppm; 839 840 struct tid_info tids; 841 void **tid_release_head; 842 spinlock_t tid_release_lock; 843 struct workqueue_struct *workq; 844 struct work_struct tid_release_task; 845 struct work_struct db_full_task; 846 struct work_struct db_drop_task; 847 bool tid_release_task_busy; 848 849 /* lock for mailbox cmd list */ 850 spinlock_t mbox_lock; 851 struct mbox_list mlist; 852 853 /* support for mailbox command/reply logging */ 854 #define T4_OS_LOG_MBOX_CMDS 256 855 struct mbox_cmd_log *mbox_log; 856 857 struct mutex uld_mutex; 858 859 struct dentry *debugfs_root; 860 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 861 bool trace_rss; /* 1 implies that different RSS flit per filter is 862 * used per filter else if 0 default RSS flit is 863 * used for all 4 filters. 864 */ 865 866 spinlock_t stats_lock; 867 spinlock_t win0_lock ____cacheline_aligned_in_smp; 868 869 /* TC u32 offload */ 870 struct cxgb4_tc_u32_table *tc_u32; 871 }; 872 873 /* Support for "sched-class" command to allow a TX Scheduling Class to be 874 * programmed with various parameters. 875 */ 876 struct ch_sched_params { 877 s8 type; /* packet or flow */ 878 union { 879 struct { 880 s8 level; /* scheduler hierarchy level */ 881 s8 mode; /* per-class or per-flow */ 882 s8 rateunit; /* bit or packet rate */ 883 s8 ratemode; /* %port relative or kbps absolute */ 884 s8 channel; /* scheduler channel [0..N] */ 885 s8 class; /* scheduler class [0..N] */ 886 s32 minrate; /* minimum rate */ 887 s32 maxrate; /* maximum rate */ 888 s16 weight; /* percent weight */ 889 s16 pktsize; /* average packet size */ 890 } params; 891 } u; 892 }; 893 894 enum { 895 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 896 }; 897 898 enum { 899 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 900 }; 901 902 enum { 903 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 904 }; 905 906 enum { 907 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 908 }; 909 910 enum { 911 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 912 }; 913 914 /* Support for "sched_queue" command to allow one or more NIC TX Queues 915 * to be bound to a TX Scheduling Class. 916 */ 917 struct ch_sched_queue { 918 s8 queue; /* queue index */ 919 s8 class; /* class index */ 920 }; 921 922 /* Defined bit width of user definable filter tuples 923 */ 924 #define ETHTYPE_BITWIDTH 16 925 #define FRAG_BITWIDTH 1 926 #define MACIDX_BITWIDTH 9 927 #define FCOE_BITWIDTH 1 928 #define IPORT_BITWIDTH 3 929 #define MATCHTYPE_BITWIDTH 3 930 #define PROTO_BITWIDTH 8 931 #define TOS_BITWIDTH 8 932 #define PF_BITWIDTH 8 933 #define VF_BITWIDTH 8 934 #define IVLAN_BITWIDTH 16 935 #define OVLAN_BITWIDTH 16 936 937 /* Filter matching rules. These consist of a set of ingress packet field 938 * (value, mask) tuples. The associated ingress packet field matches the 939 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 940 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 941 * matches an ingress packet when all of the individual individual field 942 * matching rules are true. 943 * 944 * Partial field masks are always valid, however, while it may be easy to 945 * understand their meanings for some fields (e.g. IP address to match a 946 * subnet), for others making sensible partial masks is less intuitive (e.g. 947 * MPS match type) ... 948 * 949 * Most of the following data structures are modeled on T4 capabilities. 950 * Drivers for earlier chips use the subsets which make sense for those chips. 951 * We really need to come up with a hardware-independent mechanism to 952 * represent hardware filter capabilities ... 953 */ 954 struct ch_filter_tuple { 955 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 956 * register selects which of these fields will participate in the 957 * filter match rules -- up to a maximum of 36 bits. Because 958 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 959 * set of fields. 960 */ 961 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 962 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 963 uint32_t ivlan_vld:1; /* inner VLAN valid */ 964 uint32_t ovlan_vld:1; /* outer VLAN valid */ 965 uint32_t pfvf_vld:1; /* PF/VF valid */ 966 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 967 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 968 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 969 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 970 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 971 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 972 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 973 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 974 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 975 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 976 977 /* Uncompressed header matching field rules. These are always 978 * available for field rules. 979 */ 980 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 981 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 982 uint16_t lport; /* local port */ 983 uint16_t fport; /* foreign port */ 984 }; 985 986 /* A filter ioctl command. 987 */ 988 struct ch_filter_specification { 989 /* Administrative fields for filter. 990 */ 991 uint32_t hitcnts:1; /* count filter hits in TCB */ 992 uint32_t prio:1; /* filter has priority over active/server */ 993 994 /* Fundamental filter typing. This is the one element of filter 995 * matching that doesn't exist as a (value, mask) tuple. 996 */ 997 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 998 999 /* Packet dispatch information. Ingress packets which match the 1000 * filter rules will be dropped, passed to the host or switched back 1001 * out as egress packets. 1002 */ 1003 uint32_t action:2; /* drop, pass, switch */ 1004 1005 uint32_t rpttid:1; /* report TID in RSS hash field */ 1006 1007 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1008 uint32_t iq:10; /* ingress queue */ 1009 1010 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1011 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1012 /* 1 => TCB contains IQ ID */ 1013 1014 /* Switch proxy/rewrite fields. An ingress packet which matches a 1015 * filter with "switch" set will be looped back out as an egress 1016 * packet -- potentially with some Ethernet header rewriting. 1017 */ 1018 uint32_t eport:2; /* egress port to switch packet out */ 1019 uint32_t newdmac:1; /* rewrite destination MAC address */ 1020 uint32_t newsmac:1; /* rewrite source MAC address */ 1021 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1022 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1023 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1024 uint16_t vlan; /* VLAN Tag to insert */ 1025 1026 /* Filter rule value/mask pairs. 1027 */ 1028 struct ch_filter_tuple val; 1029 struct ch_filter_tuple mask; 1030 }; 1031 1032 enum { 1033 FILTER_PASS = 0, /* default */ 1034 FILTER_DROP, 1035 FILTER_SWITCH 1036 }; 1037 1038 enum { 1039 VLAN_NOCHANGE = 0, /* default */ 1040 VLAN_REMOVE, 1041 VLAN_INSERT, 1042 VLAN_REWRITE 1043 }; 1044 1045 /* Host shadow copy of ingress filter entry. This is in host native format 1046 * and doesn't match the ordering or bit order, etc. of the hardware of the 1047 * firmware command. The use of bit-field structure elements is purely to 1048 * remind ourselves of the field size limitations and save memory in the case 1049 * where the filter table is large. 1050 */ 1051 struct filter_entry { 1052 /* Administrative fields for filter. */ 1053 u32 valid:1; /* filter allocated and valid */ 1054 u32 locked:1; /* filter is administratively locked */ 1055 1056 u32 pending:1; /* filter action is pending firmware reply */ 1057 u32 smtidx:8; /* Source MAC Table index for smac */ 1058 struct filter_ctx *ctx; /* Caller's completion hook */ 1059 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1060 struct net_device *dev; /* Associated net device */ 1061 u32 tid; /* This will store the actual tid */ 1062 1063 /* The filter itself. Most of this is a straight copy of information 1064 * provided by the extended ioctl(). Some fields are translated to 1065 * internal forms -- for instance the Ingress Queue ID passed in from 1066 * the ioctl() is translated into the Absolute Ingress Queue ID. 1067 */ 1068 struct ch_filter_specification fs; 1069 }; 1070 1071 static inline int is_offload(const struct adapter *adap) 1072 { 1073 return adap->params.offload; 1074 } 1075 1076 static inline int is_pci_uld(const struct adapter *adap) 1077 { 1078 return adap->params.crypto; 1079 } 1080 1081 static inline int is_uld(const struct adapter *adap) 1082 { 1083 return (adap->params.offload || adap->params.crypto); 1084 } 1085 1086 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1087 { 1088 return readl(adap->regs + reg_addr); 1089 } 1090 1091 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1092 { 1093 writel(val, adap->regs + reg_addr); 1094 } 1095 1096 #ifndef readq 1097 static inline u64 readq(const volatile void __iomem *addr) 1098 { 1099 return readl(addr) + ((u64)readl(addr + 4) << 32); 1100 } 1101 1102 static inline void writeq(u64 val, volatile void __iomem *addr) 1103 { 1104 writel(val, addr); 1105 writel(val >> 32, addr + 4); 1106 } 1107 #endif 1108 1109 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1110 { 1111 return readq(adap->regs + reg_addr); 1112 } 1113 1114 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1115 { 1116 writeq(val, adap->regs + reg_addr); 1117 } 1118 1119 /** 1120 * t4_set_hw_addr - store a port's MAC address in SW 1121 * @adapter: the adapter 1122 * @port_idx: the port index 1123 * @hw_addr: the Ethernet address 1124 * 1125 * Store the Ethernet address of the given port in SW. Called by the common 1126 * code when it retrieves a port's Ethernet address from EEPROM. 1127 */ 1128 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1129 u8 hw_addr[]) 1130 { 1131 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1132 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1133 } 1134 1135 /** 1136 * netdev2pinfo - return the port_info structure associated with a net_device 1137 * @dev: the netdev 1138 * 1139 * Return the struct port_info associated with a net_device 1140 */ 1141 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1142 { 1143 return netdev_priv(dev); 1144 } 1145 1146 /** 1147 * adap2pinfo - return the port_info of a port 1148 * @adap: the adapter 1149 * @idx: the port index 1150 * 1151 * Return the port_info structure for the port of the given index. 1152 */ 1153 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1154 { 1155 return netdev_priv(adap->port[idx]); 1156 } 1157 1158 /** 1159 * netdev2adap - return the adapter structure associated with a net_device 1160 * @dev: the netdev 1161 * 1162 * Return the struct adapter associated with a net_device 1163 */ 1164 static inline struct adapter *netdev2adap(const struct net_device *dev) 1165 { 1166 return netdev2pinfo(dev)->adapter; 1167 } 1168 1169 /* Return a version number to identify the type of adapter. The scheme is: 1170 * - bits 0..9: chip version 1171 * - bits 10..15: chip revision 1172 * - bits 16..23: register dump version 1173 */ 1174 static inline unsigned int mk_adap_vers(struct adapter *ap) 1175 { 1176 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1177 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1178 } 1179 1180 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1181 static inline unsigned int qtimer_val(const struct adapter *adap, 1182 const struct sge_rspq *q) 1183 { 1184 unsigned int idx = q->intr_params >> 1; 1185 1186 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1187 } 1188 1189 /* driver version & name used for ethtool_drvinfo */ 1190 extern char cxgb4_driver_name[]; 1191 extern const char cxgb4_driver_version[]; 1192 1193 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1194 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1195 1196 void t4_free_sge_resources(struct adapter *adap); 1197 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1198 irq_handler_t t4_intr_handler(struct adapter *adap); 1199 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1200 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1201 const struct pkt_gl *gl); 1202 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1203 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1204 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1205 struct net_device *dev, int intr_idx, 1206 struct sge_fl *fl, rspq_handler_t hnd, 1207 rspq_flush_handler_t flush_handler, int cong); 1208 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1209 struct net_device *dev, struct netdev_queue *netdevq, 1210 unsigned int iqid); 1211 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1212 struct net_device *dev, unsigned int iqid, 1213 unsigned int cmplqid); 1214 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1215 unsigned int cmplqid); 1216 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1217 struct net_device *dev, unsigned int iqid, 1218 unsigned int uld_type); 1219 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1220 int t4_sge_init(struct adapter *adap); 1221 void t4_sge_start(struct adapter *adap); 1222 void t4_sge_stop(struct adapter *adap); 1223 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1224 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1225 extern int dbfifo_int_thresh; 1226 1227 #define for_each_port(adapter, iter) \ 1228 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1229 1230 static inline int is_bypass(struct adapter *adap) 1231 { 1232 return adap->params.bypass; 1233 } 1234 1235 static inline int is_bypass_device(int device) 1236 { 1237 /* this should be set based upon device capabilities */ 1238 switch (device) { 1239 case 0x440b: 1240 case 0x440c: 1241 return 1; 1242 default: 1243 return 0; 1244 } 1245 } 1246 1247 static inline int is_10gbt_device(int device) 1248 { 1249 /* this should be set based upon device capabilities */ 1250 switch (device) { 1251 case 0x4409: 1252 case 0x4486: 1253 return 1; 1254 1255 default: 1256 return 0; 1257 } 1258 } 1259 1260 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1261 { 1262 return adap->params.vpd.cclk / 1000; 1263 } 1264 1265 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1266 unsigned int us) 1267 { 1268 return (us * adap->params.vpd.cclk) / 1000; 1269 } 1270 1271 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1272 unsigned int ticks) 1273 { 1274 /* add Core Clock / 2 to round ticks to nearest uS */ 1275 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1276 adapter->params.vpd.cclk); 1277 } 1278 1279 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1280 u32 val); 1281 1282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1283 int size, void *rpl, bool sleep_ok, int timeout); 1284 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1285 void *rpl, bool sleep_ok); 1286 1287 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1288 const void *cmd, int size, void *rpl, 1289 int timeout) 1290 { 1291 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1292 timeout); 1293 } 1294 1295 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1296 int size, void *rpl) 1297 { 1298 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1299 } 1300 1301 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1302 int size, void *rpl) 1303 { 1304 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1305 } 1306 1307 /** 1308 * hash_mac_addr - return the hash value of a MAC address 1309 * @addr: the 48-bit Ethernet MAC address 1310 * 1311 * Hashes a MAC address according to the hash function used by HW inexact 1312 * (hash) address matching. 1313 */ 1314 static inline int hash_mac_addr(const u8 *addr) 1315 { 1316 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1317 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1318 1319 a ^= b; 1320 a ^= (a >> 12); 1321 a ^= (a >> 6); 1322 return a & 0x3f; 1323 } 1324 1325 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1326 unsigned int cnt); 1327 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1328 unsigned int us, unsigned int cnt, 1329 unsigned int size, unsigned int iqe_size) 1330 { 1331 q->adap = adap; 1332 cxgb4_set_rspq_intr_params(q, us, cnt); 1333 q->iqe_len = iqe_size; 1334 q->size = size; 1335 } 1336 1337 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1338 unsigned int data_reg, const u32 *vals, 1339 unsigned int nregs, unsigned int start_idx); 1340 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1341 unsigned int data_reg, u32 *vals, unsigned int nregs, 1342 unsigned int start_idx); 1343 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1344 1345 struct fw_filter_wr; 1346 1347 void t4_intr_enable(struct adapter *adapter); 1348 void t4_intr_disable(struct adapter *adapter); 1349 int t4_slow_intr_handler(struct adapter *adapter); 1350 1351 int t4_wait_dev_ready(void __iomem *regs); 1352 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1353 struct link_config *lc); 1354 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1355 1356 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1357 u32 t4_get_util_window(struct adapter *adap); 1358 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1359 1360 #define T4_MEMORY_WRITE 0 1361 #define T4_MEMORY_READ 1 1362 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1363 void *buf, int dir); 1364 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1365 u32 len, __be32 *buf) 1366 { 1367 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1368 } 1369 1370 unsigned int t4_get_regs_len(struct adapter *adapter); 1371 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1372 1373 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1374 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1375 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1376 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1377 unsigned int nwords, u32 *data, int byte_oriented); 1378 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1379 int t4_load_phy_fw(struct adapter *adap, 1380 int win, spinlock_t *lock, 1381 int (*phy_fw_version)(const u8 *, size_t), 1382 const u8 *phy_fw_data, size_t phy_fw_size); 1383 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1384 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1385 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1386 const u8 *fw_data, unsigned int size, int force); 1387 int t4_fl_pkt_align(struct adapter *adap); 1388 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1389 int t4_check_fw_version(struct adapter *adap); 1390 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1391 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1392 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1393 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1394 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1395 const u8 *fw_data, unsigned int fw_size, 1396 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1397 int t4_prep_adapter(struct adapter *adapter); 1398 int t4_shutdown_adapter(struct adapter *adapter); 1399 1400 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1401 int t4_bar2_sge_qregs(struct adapter *adapter, 1402 unsigned int qid, 1403 enum t4_bar2_qtype qtype, 1404 int user, 1405 u64 *pbar2_qoffset, 1406 unsigned int *pbar2_qid); 1407 1408 unsigned int qtimer_val(const struct adapter *adap, 1409 const struct sge_rspq *q); 1410 1411 int t4_init_devlog_params(struct adapter *adapter); 1412 int t4_init_sge_params(struct adapter *adapter); 1413 int t4_init_tp_params(struct adapter *adap); 1414 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1415 int t4_init_rss_mode(struct adapter *adap, int mbox); 1416 int t4_init_portinfo(struct port_info *pi, int mbox, 1417 int port, int pf, int vf, u8 mac[]); 1418 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1419 void t4_fatal_err(struct adapter *adapter); 1420 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1421 int start, int n, const u16 *rspq, unsigned int nrspq); 1422 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1423 unsigned int flags); 1424 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1425 unsigned int flags, unsigned int defq); 1426 int t4_read_rss(struct adapter *adapter, u16 *entries); 1427 void t4_read_rss_key(struct adapter *adapter, u32 *key); 1428 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1429 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1430 u32 *valp); 1431 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1432 u32 *vfl, u32 *vfh); 1433 u32 t4_read_rss_pf_map(struct adapter *adapter); 1434 u32 t4_read_rss_pf_mask(struct adapter *adapter); 1435 1436 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1437 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1438 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1439 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1440 size_t n); 1441 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1442 size_t n); 1443 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1444 unsigned int *valp); 1445 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1446 const unsigned int *valp); 1447 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1448 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1449 unsigned int *pif_req_wrptr, 1450 unsigned int *pif_rsp_wrptr); 1451 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1452 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1453 const char *t4_get_port_type_description(enum fw_port_type port_type); 1454 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1455 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1456 struct port_stats *stats, 1457 struct port_stats *offset); 1458 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1459 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1460 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1461 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1462 unsigned int mask, unsigned int val); 1463 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1464 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1465 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1466 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1467 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1468 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1469 struct tp_tcp_stats *v6); 1470 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1471 struct tp_fcoe_stats *st); 1472 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1473 const unsigned short *alpha, const unsigned short *beta); 1474 1475 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1476 1477 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1478 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1479 1480 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1481 const u8 *addr); 1482 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1483 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1484 1485 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1486 enum dev_master master, enum dev_state *state); 1487 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1488 int t4_early_init(struct adapter *adap, unsigned int mbox); 1489 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1490 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1491 unsigned int cache_line_size); 1492 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1493 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1494 unsigned int vf, unsigned int nparams, const u32 *params, 1495 u32 *val); 1496 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1497 unsigned int vf, unsigned int nparams, const u32 *params, 1498 u32 *val, int rw); 1499 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1500 unsigned int pf, unsigned int vf, 1501 unsigned int nparams, const u32 *params, 1502 const u32 *val, int timeout); 1503 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1504 unsigned int vf, unsigned int nparams, const u32 *params, 1505 const u32 *val); 1506 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1507 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1508 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1509 unsigned int vi, unsigned int cmask, unsigned int pmask, 1510 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1511 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1512 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1513 unsigned int *rss_size); 1514 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1515 unsigned int pf, unsigned int vf, 1516 unsigned int viid); 1517 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1518 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1519 bool sleep_ok); 1520 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1521 unsigned int viid, bool free, unsigned int naddr, 1522 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1523 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1524 unsigned int viid, unsigned int naddr, 1525 const u8 **addr, bool sleep_ok); 1526 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1527 int idx, const u8 *addr, bool persist, bool add_smt); 1528 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1529 bool ucast, u64 vec, bool sleep_ok); 1530 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1531 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1532 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1533 bool rx_en, bool tx_en); 1534 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1535 unsigned int nblinks); 1536 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1537 unsigned int mmd, unsigned int reg, u16 *valp); 1538 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1539 unsigned int mmd, unsigned int reg, u16 val); 1540 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1541 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1542 unsigned int fl0id, unsigned int fl1id); 1543 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1544 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1545 unsigned int fl0id, unsigned int fl1id); 1546 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1547 unsigned int vf, unsigned int eqid); 1548 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1549 unsigned int vf, unsigned int eqid); 1550 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1551 unsigned int vf, unsigned int eqid); 1552 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1553 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1554 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1555 void t4_db_full(struct adapter *adapter); 1556 void t4_db_dropped(struct adapter *adapter); 1557 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1558 int filter_index, int enable); 1559 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1560 int filter_index, int *enabled); 1561 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1562 u32 addr, u32 val); 1563 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1564 int rateunit, int ratemode, int channel, int class, 1565 int minrate, int maxrate, int weight, int pktsize); 1566 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1567 void t4_idma_monitor_init(struct adapter *adapter, 1568 struct sge_idma_monitor_state *idma); 1569 void t4_idma_monitor(struct adapter *adapter, 1570 struct sge_idma_monitor_state *idma, 1571 int hz, int ticks); 1572 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1573 unsigned int naddr, u8 *addr); 1574 void t4_uld_mem_free(struct adapter *adap); 1575 int t4_uld_mem_alloc(struct adapter *adap); 1576 void t4_uld_clean_up(struct adapter *adap); 1577 void t4_register_netevent_notifier(void); 1578 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1579 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1580 unsigned int n, bool unmap); 1581 void free_txq(struct adapter *adap, struct sge_txq *q); 1582 #endif /* __CXGB4_H__ */ 1583