1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/rhashtable.h> 50 #include <linux/etherdevice.h> 51 #include <linux/net_tstamp.h> 52 #include <linux/ptp_clock_kernel.h> 53 #include <linux/ptp_classify.h> 54 #include <linux/crash_dump.h> 55 #include <linux/thermal.h> 56 #include <asm/io.h> 57 #include "t4_chip_type.h" 58 #include "cxgb4_uld.h" 59 #include "t4fw_api.h" 60 61 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 62 extern struct list_head adapter_list; 63 extern struct mutex uld_mutex; 64 65 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 66 * This is the same as calc_tx_descs() for a TSO packet with 67 * nr_frags == MAX_SKB_FRAGS. 68 */ 69 #define ETHTXQ_STOP_THRES \ 70 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 71 72 #define FW_PARAM_DEV(param) \ 73 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 74 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 75 76 #define FW_PARAM_PFVF(param) \ 77 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 78 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 79 FW_PARAMS_PARAM_Y_V(0) | \ 80 FW_PARAMS_PARAM_Z_V(0)) 81 82 enum { 83 MAX_NPORTS = 4, /* max # of ports */ 84 SERNUM_LEN = 24, /* Serial # length */ 85 EC_LEN = 16, /* E/C length */ 86 ID_LEN = 16, /* ID length */ 87 PN_LEN = 16, /* Part Number length */ 88 MACADDR_LEN = 12, /* MAC Address length */ 89 }; 90 91 enum { 92 T4_REGMAP_SIZE = (160 * 1024), 93 T5_REGMAP_SIZE = (332 * 1024), 94 }; 95 96 enum { 97 MEM_EDC0, 98 MEM_EDC1, 99 MEM_MC, 100 MEM_MC0 = MEM_MC, 101 MEM_MC1, 102 MEM_HMA, 103 }; 104 105 enum { 106 MEMWIN0_APERTURE = 2048, 107 MEMWIN0_BASE = 0x1b800, 108 MEMWIN1_APERTURE = 32768, 109 MEMWIN1_BASE = 0x28000, 110 MEMWIN1_BASE_T5 = 0x52000, 111 MEMWIN2_APERTURE = 65536, 112 MEMWIN2_BASE = 0x30000, 113 MEMWIN2_APERTURE_T5 = 131072, 114 MEMWIN2_BASE_T5 = 0x60000, 115 }; 116 117 enum dev_master { 118 MASTER_CANT, 119 MASTER_MAY, 120 MASTER_MUST 121 }; 122 123 enum dev_state { 124 DEV_STATE_UNINIT, 125 DEV_STATE_INIT, 126 DEV_STATE_ERR 127 }; 128 129 enum cc_pause { 130 PAUSE_RX = 1 << 0, 131 PAUSE_TX = 1 << 1, 132 PAUSE_AUTONEG = 1 << 2 133 }; 134 135 enum cc_fec { 136 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 137 FEC_RS = 1 << 1, /* Reed-Solomon */ 138 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 139 }; 140 141 struct port_stats { 142 u64 tx_octets; /* total # of octets in good frames */ 143 u64 tx_frames; /* all good frames */ 144 u64 tx_bcast_frames; /* all broadcast frames */ 145 u64 tx_mcast_frames; /* all multicast frames */ 146 u64 tx_ucast_frames; /* all unicast frames */ 147 u64 tx_error_frames; /* all error frames */ 148 149 u64 tx_frames_64; /* # of Tx frames in a particular range */ 150 u64 tx_frames_65_127; 151 u64 tx_frames_128_255; 152 u64 tx_frames_256_511; 153 u64 tx_frames_512_1023; 154 u64 tx_frames_1024_1518; 155 u64 tx_frames_1519_max; 156 157 u64 tx_drop; /* # of dropped Tx frames */ 158 u64 tx_pause; /* # of transmitted pause frames */ 159 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 160 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 161 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 162 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 163 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 164 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 165 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 166 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 167 168 u64 rx_octets; /* total # of octets in good frames */ 169 u64 rx_frames; /* all good frames */ 170 u64 rx_bcast_frames; /* all broadcast frames */ 171 u64 rx_mcast_frames; /* all multicast frames */ 172 u64 rx_ucast_frames; /* all unicast frames */ 173 u64 rx_too_long; /* # of frames exceeding MTU */ 174 u64 rx_jabber; /* # of jabber frames */ 175 u64 rx_fcs_err; /* # of received frames with bad FCS */ 176 u64 rx_len_err; /* # of received frames with length error */ 177 u64 rx_symbol_err; /* symbol errors */ 178 u64 rx_runt; /* # of short frames */ 179 180 u64 rx_frames_64; /* # of Rx frames in a particular range */ 181 u64 rx_frames_65_127; 182 u64 rx_frames_128_255; 183 u64 rx_frames_256_511; 184 u64 rx_frames_512_1023; 185 u64 rx_frames_1024_1518; 186 u64 rx_frames_1519_max; 187 188 u64 rx_pause; /* # of received pause frames */ 189 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 190 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 191 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 192 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 193 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 194 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 195 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 196 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 197 198 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 199 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 200 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 201 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 202 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 203 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 204 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 205 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 206 }; 207 208 struct lb_port_stats { 209 u64 octets; 210 u64 frames; 211 u64 bcast_frames; 212 u64 mcast_frames; 213 u64 ucast_frames; 214 u64 error_frames; 215 216 u64 frames_64; 217 u64 frames_65_127; 218 u64 frames_128_255; 219 u64 frames_256_511; 220 u64 frames_512_1023; 221 u64 frames_1024_1518; 222 u64 frames_1519_max; 223 224 u64 drop; 225 226 u64 ovflow0; 227 u64 ovflow1; 228 u64 ovflow2; 229 u64 ovflow3; 230 u64 trunc0; 231 u64 trunc1; 232 u64 trunc2; 233 u64 trunc3; 234 }; 235 236 struct tp_tcp_stats { 237 u32 tcp_out_rsts; 238 u64 tcp_in_segs; 239 u64 tcp_out_segs; 240 u64 tcp_retrans_segs; 241 }; 242 243 struct tp_usm_stats { 244 u32 frames; 245 u32 drops; 246 u64 octets; 247 }; 248 249 struct tp_fcoe_stats { 250 u32 frames_ddp; 251 u32 frames_drop; 252 u64 octets_ddp; 253 }; 254 255 struct tp_err_stats { 256 u32 mac_in_errs[4]; 257 u32 hdr_in_errs[4]; 258 u32 tcp_in_errs[4]; 259 u32 tnl_cong_drops[4]; 260 u32 ofld_chan_drops[4]; 261 u32 tnl_tx_drops[4]; 262 u32 ofld_vlan_drops[4]; 263 u32 tcp6_in_errs[4]; 264 u32 ofld_no_neigh; 265 u32 ofld_cong_defer; 266 }; 267 268 struct tp_cpl_stats { 269 u32 req[4]; 270 u32 rsp[4]; 271 }; 272 273 struct tp_rdma_stats { 274 u32 rqe_dfr_pkt; 275 u32 rqe_dfr_mod; 276 }; 277 278 struct sge_params { 279 u32 hps; /* host page size for our PF/VF */ 280 u32 eq_qpp; /* egress queues/page for our PF/VF */ 281 u32 iq_qpp; /* egress queues/page for our PF/VF */ 282 }; 283 284 struct tp_params { 285 unsigned int tre; /* log2 of core clocks per TP tick */ 286 unsigned int la_mask; /* what events are recorded by TP LA */ 287 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 288 /* channel map */ 289 290 uint32_t dack_re; /* DACK timer resolution */ 291 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 292 293 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 294 u32 filter_mask; 295 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 296 297 /* cached TP_OUT_CONFIG compressed error vector 298 * and passing outer header info for encapsulated packets. 299 */ 300 int rx_pkt_encap; 301 302 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 303 * subset of the set of fields which may be present in the Compressed 304 * Filter Tuple portion of filters and TCP TCB connections. The 305 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 306 * Since a variable number of fields may or may not be present, their 307 * shifted field positions within the Compressed Filter Tuple may 308 * vary, or not even be present if the field isn't selected in 309 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 310 * places we store their offsets here, or a -1 if the field isn't 311 * present. 312 */ 313 int fcoe_shift; 314 int port_shift; 315 int vnic_shift; 316 int vlan_shift; 317 int tos_shift; 318 int protocol_shift; 319 int ethertype_shift; 320 int macmatch_shift; 321 int matchtype_shift; 322 int frag_shift; 323 324 u64 hash_filter_mask; 325 }; 326 327 struct vpd_params { 328 unsigned int cclk; 329 u8 ec[EC_LEN + 1]; 330 u8 sn[SERNUM_LEN + 1]; 331 u8 id[ID_LEN + 1]; 332 u8 pn[PN_LEN + 1]; 333 u8 na[MACADDR_LEN + 1]; 334 }; 335 336 /* Maximum resources provisioned for a PCI PF. 337 */ 338 struct pf_resources { 339 unsigned int nvi; /* N virtual interfaces */ 340 unsigned int neq; /* N egress Qs */ 341 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 342 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 343 unsigned int niq; /* N ingress Qs */ 344 unsigned int tc; /* PCI-E traffic class */ 345 unsigned int pmask; /* port access rights mask */ 346 unsigned int nexactf; /* N exact MPS filters */ 347 unsigned int r_caps; /* read capabilities */ 348 unsigned int wx_caps; /* write/execute capabilities */ 349 }; 350 351 struct pci_params { 352 unsigned int vpd_cap_addr; 353 unsigned char speed; 354 unsigned char width; 355 }; 356 357 struct devlog_params { 358 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 359 u32 start; /* start of log in firmware memory */ 360 u32 size; /* size of log */ 361 }; 362 363 /* Stores chip specific parameters */ 364 struct arch_specific_params { 365 u8 nchan; 366 u8 pm_stats_cnt; 367 u8 cng_ch_bits_log; /* congestion channel map bits width */ 368 u16 mps_rplc_size; 369 u16 vfcount; 370 u32 sge_fl_db; 371 u16 mps_tcam_size; 372 }; 373 374 struct adapter_params { 375 struct sge_params sge; 376 struct tp_params tp; 377 struct vpd_params vpd; 378 struct pf_resources pfres; 379 struct pci_params pci; 380 struct devlog_params devlog; 381 enum pcie_memwin drv_memwin; 382 383 unsigned int cim_la_size; 384 385 unsigned int sf_size; /* serial flash size in bytes */ 386 unsigned int sf_nsec; /* # of flash sectors */ 387 388 unsigned int fw_vers; /* firmware version */ 389 unsigned int bs_vers; /* bootstrap version */ 390 unsigned int tp_vers; /* TP microcode version */ 391 unsigned int er_vers; /* expansion ROM version */ 392 unsigned int scfg_vers; /* Serial Configuration version */ 393 unsigned int vpd_vers; /* VPD Version */ 394 u8 api_vers[7]; 395 396 unsigned short mtus[NMTUS]; 397 unsigned short a_wnd[NCCTRL_WIN]; 398 unsigned short b_wnd[NCCTRL_WIN]; 399 400 unsigned char nports; /* # of ethernet ports */ 401 unsigned char portvec; 402 enum chip_type chip; /* chip code */ 403 struct arch_specific_params arch; /* chip specific params */ 404 unsigned char offload; 405 unsigned char crypto; /* HW capability for crypto */ 406 unsigned char ethofld; /* QoS support */ 407 408 unsigned char bypass; 409 unsigned char hash_filter; 410 411 unsigned int ofldq_wr_cred; 412 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 413 414 unsigned int nsched_cls; /* number of traffic classes */ 415 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 416 unsigned int max_ird_adapter; /* Max read depth per adapter */ 417 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 418 u8 fw_caps_support; /* 32-bit Port Capabilities */ 419 bool filter2_wr_support; /* FW support for FILTER2_WR */ 420 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 421 422 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 423 * used by the Port 424 */ 425 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 426 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 427 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 428 }; 429 430 /* State needed to monitor the forward progress of SGE Ingress DMA activities 431 * and possible hangs. 432 */ 433 struct sge_idma_monitor_state { 434 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 435 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 436 unsigned int idma_state[2]; /* IDMA Hang detect state */ 437 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 438 unsigned int idma_warn[2]; /* time to warning in HZ */ 439 }; 440 441 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 442 * The access and execute times are signed in order to accommodate negative 443 * error returns. 444 */ 445 struct mbox_cmd { 446 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 447 u64 timestamp; /* OS-dependent timestamp */ 448 u32 seqno; /* sequence number */ 449 s16 access; /* time (ms) to access mailbox */ 450 s16 execute; /* time (ms) to execute */ 451 }; 452 453 struct mbox_cmd_log { 454 unsigned int size; /* number of entries in the log */ 455 unsigned int cursor; /* next position in the log to write */ 456 u32 seqno; /* next sequence number */ 457 /* variable length mailbox command log starts here */ 458 }; 459 460 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 461 * return a pointer to the specified entry. 462 */ 463 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 464 unsigned int entry_idx) 465 { 466 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 467 } 468 469 #include "t4fw_api.h" 470 471 #define FW_VERSION(chip) ( \ 472 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 473 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 474 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 475 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 476 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 477 478 struct fw_info { 479 u8 chip; 480 char *fs_name; 481 char *fw_mod_name; 482 struct fw_hdr fw_hdr; 483 }; 484 485 struct trace_params { 486 u32 data[TRACE_LEN / 4]; 487 u32 mask[TRACE_LEN / 4]; 488 unsigned short snap_len; 489 unsigned short min_len; 490 unsigned char skip_ofst; 491 unsigned char skip_len; 492 unsigned char invert; 493 unsigned char port; 494 }; 495 496 /* Firmware Port Capabilities types. */ 497 498 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 499 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 500 501 enum fw_caps { 502 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 503 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 504 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 505 }; 506 507 struct link_config { 508 fw_port_cap32_t pcaps; /* link capabilities */ 509 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 510 fw_port_cap32_t acaps; /* advertised capabilities */ 511 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 512 513 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 514 unsigned int speed; /* actual link speed (Mb/s) */ 515 516 enum cc_pause requested_fc; /* flow control user has requested */ 517 enum cc_pause fc; /* actual link flow control */ 518 519 enum cc_fec requested_fec; /* Forward Error Correction: */ 520 enum cc_fec fec; /* requested and actual in use */ 521 522 unsigned char autoneg; /* autonegotiating? */ 523 524 unsigned char link_ok; /* link up? */ 525 unsigned char link_down_rc; /* link down reason */ 526 527 bool new_module; /* ->OS Transceiver Module inserted */ 528 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 529 }; 530 531 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 532 533 enum { 534 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 535 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 536 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 537 }; 538 539 enum { 540 MAX_TXQ_ENTRIES = 16384, 541 MAX_CTRL_TXQ_ENTRIES = 1024, 542 MAX_RSPQ_ENTRIES = 16384, 543 MAX_RX_BUFFERS = 16384, 544 MIN_TXQ_ENTRIES = 32, 545 MIN_CTRL_TXQ_ENTRIES = 32, 546 MIN_RSPQ_ENTRIES = 128, 547 MIN_FL_ENTRIES = 16 548 }; 549 550 enum { 551 MAX_TXQ_DESC_SIZE = 64, 552 MAX_RXQ_DESC_SIZE = 128, 553 MAX_FL_DESC_SIZE = 8, 554 MAX_CTRL_TXQ_DESC_SIZE = 64, 555 }; 556 557 enum { 558 INGQ_EXTRAS = 2, /* firmware event queue and */ 559 /* forwarded interrupts */ 560 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 561 }; 562 563 enum { 564 PRIV_FLAG_PORT_TX_VM_BIT, 565 }; 566 567 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 568 569 #define PRIV_FLAGS_ADAP 0 570 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 571 572 struct adapter; 573 struct sge_rspq; 574 575 #include "cxgb4_dcb.h" 576 577 #ifdef CONFIG_CHELSIO_T4_FCOE 578 #include "cxgb4_fcoe.h" 579 #endif /* CONFIG_CHELSIO_T4_FCOE */ 580 581 struct port_info { 582 struct adapter *adapter; 583 u16 viid; 584 int xact_addr_filt; /* index of exact MAC address filter */ 585 u16 rss_size; /* size of VI's RSS table slice */ 586 s8 mdio_addr; 587 enum fw_port_type port_type; 588 u8 mod_type; 589 u8 port_id; 590 u8 tx_chan; 591 u8 lport; /* associated offload logical port */ 592 u8 nqsets; /* # of qsets */ 593 u8 first_qset; /* index of first qset */ 594 u8 rss_mode; 595 struct link_config link_cfg; 596 u16 *rss; 597 struct port_stats stats_base; 598 #ifdef CONFIG_CHELSIO_T4_DCB 599 struct port_dcb_info dcb; /* Data Center Bridging support */ 600 #endif 601 #ifdef CONFIG_CHELSIO_T4_FCOE 602 struct cxgb_fcoe fcoe; 603 #endif /* CONFIG_CHELSIO_T4_FCOE */ 604 bool rxtstamp; /* Enable TS */ 605 struct hwtstamp_config tstamp_config; 606 bool ptp_enable; 607 struct sched_table *sched_tbl; 608 u32 eth_flags; 609 610 /* viid and smt fields either returned by fw 611 * or decoded by parsing viid by driver. 612 */ 613 u8 vin; 614 u8 vivld; 615 u8 smt_idx; 616 u8 rx_cchan; 617 618 bool tc_block_shared; 619 }; 620 621 struct dentry; 622 struct work_struct; 623 624 enum { /* adapter flags */ 625 CXGB4_FULL_INIT_DONE = (1 << 0), 626 CXGB4_DEV_ENABLED = (1 << 1), 627 CXGB4_USING_MSI = (1 << 2), 628 CXGB4_USING_MSIX = (1 << 3), 629 CXGB4_FW_OK = (1 << 4), 630 CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 631 CXGB4_USING_SOFT_PARAMS = (1 << 6), 632 CXGB4_MASTER_PF = (1 << 7), 633 CXGB4_FW_OFLD_CONN = (1 << 9), 634 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 635 CXGB4_SHUTTING_DOWN = (1 << 11), 636 CXGB4_SGE_DBQ_TIMER = (1 << 12), 637 }; 638 639 enum { 640 ULP_CRYPTO_LOOKASIDE = 1 << 0, 641 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 642 }; 643 644 struct rx_sw_desc; 645 646 struct sge_fl { /* SGE free-buffer queue state */ 647 unsigned int avail; /* # of available Rx buffers */ 648 unsigned int pend_cred; /* new buffers since last FL DB ring */ 649 unsigned int cidx; /* consumer index */ 650 unsigned int pidx; /* producer index */ 651 unsigned long alloc_failed; /* # of times buffer allocation failed */ 652 unsigned long large_alloc_failed; 653 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 654 unsigned long low; /* # of times momentarily starving */ 655 unsigned long starving; 656 /* RO fields */ 657 unsigned int cntxt_id; /* SGE context id for the free list */ 658 unsigned int size; /* capacity of free list */ 659 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 660 __be64 *desc; /* address of HW Rx descriptor ring */ 661 dma_addr_t addr; /* bus address of HW ring start */ 662 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 663 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 664 }; 665 666 /* A packet gather list */ 667 struct pkt_gl { 668 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 669 struct page_frag frags[MAX_SKB_FRAGS]; 670 void *va; /* virtual address of first byte */ 671 unsigned int nfrags; /* # of fragments */ 672 unsigned int tot_len; /* total length of fragments */ 673 }; 674 675 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 676 const struct pkt_gl *gl); 677 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 678 /* LRO related declarations for ULD */ 679 struct t4_lro_mgr { 680 #define MAX_LRO_SESSIONS 64 681 u8 lro_session_cnt; /* # of sessions to aggregate */ 682 unsigned long lro_pkts; /* # of LRO super packets */ 683 unsigned long lro_merged; /* # of wire packets merged by LRO */ 684 struct sk_buff_head lroq; /* list of aggregated sessions */ 685 }; 686 687 struct sge_rspq { /* state for an SGE response queue */ 688 struct napi_struct napi; 689 const __be64 *cur_desc; /* current descriptor in queue */ 690 unsigned int cidx; /* consumer index */ 691 u8 gen; /* current generation bit */ 692 u8 intr_params; /* interrupt holdoff parameters */ 693 u8 next_intr_params; /* holdoff params for next interrupt */ 694 u8 adaptive_rx; 695 u8 pktcnt_idx; /* interrupt packet threshold */ 696 u8 uld; /* ULD handling this queue */ 697 u8 idx; /* queue index within its group */ 698 int offset; /* offset into current Rx buffer */ 699 u16 cntxt_id; /* SGE context id for the response q */ 700 u16 abs_id; /* absolute SGE id for the response q */ 701 __be64 *desc; /* address of HW response ring */ 702 dma_addr_t phys_addr; /* physical address of the ring */ 703 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 704 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 705 unsigned int iqe_len; /* entry size */ 706 unsigned int size; /* capacity of response queue */ 707 struct adapter *adap; 708 struct net_device *netdev; /* associated net device */ 709 rspq_handler_t handler; 710 rspq_flush_handler_t flush_handler; 711 struct t4_lro_mgr lro_mgr; 712 }; 713 714 struct sge_eth_stats { /* Ethernet queue statistics */ 715 unsigned long pkts; /* # of ethernet packets */ 716 unsigned long lro_pkts; /* # of LRO super packets */ 717 unsigned long lro_merged; /* # of wire packets merged by LRO */ 718 unsigned long rx_cso; /* # of Rx checksum offloads */ 719 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 720 unsigned long rx_drops; /* # of packets dropped due to no mem */ 721 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 722 }; 723 724 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 725 struct sge_rspq rspq; 726 struct sge_fl fl; 727 struct sge_eth_stats stats; 728 struct msix_info *msix; 729 } ____cacheline_aligned_in_smp; 730 731 struct sge_ofld_stats { /* offload queue statistics */ 732 unsigned long pkts; /* # of packets */ 733 unsigned long imm; /* # of immediate-data packets */ 734 unsigned long an; /* # of asynchronous notifications */ 735 unsigned long nomem; /* # of responses deferred due to no mem */ 736 }; 737 738 struct sge_ofld_rxq { /* SW offload Rx queue */ 739 struct sge_rspq rspq; 740 struct sge_fl fl; 741 struct sge_ofld_stats stats; 742 struct msix_info *msix; 743 } ____cacheline_aligned_in_smp; 744 745 struct tx_desc { 746 __be64 flit[8]; 747 }; 748 749 struct ulptx_sgl; 750 751 struct tx_sw_desc { 752 struct sk_buff *skb; /* SKB to free after getting completion */ 753 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 754 }; 755 756 struct sge_txq { 757 unsigned int in_use; /* # of in-use Tx descriptors */ 758 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 759 unsigned int size; /* # of descriptors */ 760 unsigned int cidx; /* SW consumer index */ 761 unsigned int pidx; /* producer index */ 762 unsigned long stops; /* # of times q has been stopped */ 763 unsigned long restarts; /* # of queue restarts */ 764 unsigned int cntxt_id; /* SGE context id for the Tx q */ 765 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 766 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 767 struct sge_qstat *stat; /* queue status entry */ 768 dma_addr_t phys_addr; /* physical address of the ring */ 769 spinlock_t db_lock; 770 int db_disabled; 771 unsigned short db_pidx; 772 unsigned short db_pidx_inc; 773 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 774 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 775 }; 776 777 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 778 struct sge_txq q; 779 struct netdev_queue *txq; /* associated netdev TX queue */ 780 #ifdef CONFIG_CHELSIO_T4_DCB 781 u8 dcb_prio; /* DCB Priority bound to queue */ 782 #endif 783 u8 dbqt; /* SGE Doorbell Queue Timer in use */ 784 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 785 unsigned long tso; /* # of TSO requests */ 786 unsigned long uso; /* # of USO requests */ 787 unsigned long tx_cso; /* # of Tx checksum offloads */ 788 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 789 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 790 } ____cacheline_aligned_in_smp; 791 792 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 793 struct sge_txq q; 794 struct adapter *adap; 795 struct sk_buff_head sendq; /* list of backpressured packets */ 796 struct tasklet_struct qresume_tsk; /* restarts the queue */ 797 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 798 u8 full; /* the Tx ring is full */ 799 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 800 } ____cacheline_aligned_in_smp; 801 802 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 803 struct sge_txq q; 804 struct adapter *adap; 805 struct sk_buff_head sendq; /* list of backpressured packets */ 806 struct tasklet_struct qresume_tsk; /* restarts the queue */ 807 u8 full; /* the Tx ring is full */ 808 } ____cacheline_aligned_in_smp; 809 810 struct sge_uld_rxq_info { 811 char name[IFNAMSIZ]; /* name of ULD driver */ 812 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 813 u16 *rspq_id; /* response queue id's of rxq */ 814 u16 nrxq; /* # of ingress uld queues */ 815 u16 nciq; /* # of completion queues */ 816 u8 uld; /* uld type */ 817 }; 818 819 struct sge_uld_txq_info { 820 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 821 atomic_t users; /* num users */ 822 u16 ntxq; /* # of egress uld queues */ 823 }; 824 825 enum sge_eosw_state { 826 CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 827 CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 828 CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 829 CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 830 CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 831 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 832 }; 833 834 struct sge_eosw_txq { 835 spinlock_t lock; /* Per queue lock to synchronize completions */ 836 enum sge_eosw_state state; /* Current ETHOFLD State */ 837 struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ 838 u32 ndesc; /* Number of descriptors */ 839 u32 pidx; /* Current Producer Index */ 840 u32 last_pidx; /* Last successfully transmitted Producer Index */ 841 u32 cidx; /* Current Consumer Index */ 842 u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 843 u32 flowc_idx; /* Descriptor containing a FLOWC request */ 844 u32 inuse; /* Number of packets held in ring */ 845 846 u32 cred; /* Current available credits */ 847 u32 ncompl; /* # of completions posted */ 848 u32 last_compl; /* # of credits consumed since last completion req */ 849 850 u32 eotid; /* Index into EOTID table in software */ 851 u32 hwtid; /* Hardware EOTID index */ 852 853 u32 hwqid; /* Underlying hardware queue index */ 854 struct net_device *netdev; /* Pointer to netdevice */ 855 struct tasklet_struct qresume_tsk; /* Restarts the queue */ 856 struct completion completion; /* completion for FLOWC rendezvous */ 857 }; 858 859 struct sge_eohw_txq { 860 spinlock_t lock; /* Per queue lock */ 861 struct sge_txq q; /* HW Txq */ 862 struct adapter *adap; /* Backpointer to adapter */ 863 unsigned long tso; /* # of TSO requests */ 864 unsigned long uso; /* # of USO requests */ 865 unsigned long tx_cso; /* # of Tx checksum offloads */ 866 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 867 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 868 }; 869 870 struct sge { 871 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 872 struct sge_eth_txq ptptxq; 873 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 874 875 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 876 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 877 struct sge_uld_rxq_info **uld_rxq_info; 878 struct sge_uld_txq_info **uld_txq_info; 879 880 struct sge_rspq intrq ____cacheline_aligned_in_smp; 881 spinlock_t intrq_lock; 882 883 struct sge_eohw_txq *eohw_txq; 884 struct sge_ofld_rxq *eohw_rxq; 885 886 u16 max_ethqsets; /* # of available Ethernet queue sets */ 887 u16 ethqsets; /* # of active Ethernet queue sets */ 888 u16 ethtxq_rover; /* Tx queue to clean up next */ 889 u16 ofldqsets; /* # of active ofld queue sets */ 890 u16 nqs_per_uld; /* # of Rx queues per ULD */ 891 u16 eoqsets; /* # of ETHOFLD queues */ 892 893 u16 timer_val[SGE_NTIMERS]; 894 u8 counter_val[SGE_NCOUNTERS]; 895 u16 dbqtimer_tick; 896 u16 dbqtimer_val[SGE_NDBQTIMERS]; 897 u32 fl_pg_order; /* large page allocation size */ 898 u32 stat_len; /* length of status page at ring end */ 899 u32 pktshift; /* padding between CPL & packet data */ 900 u32 fl_align; /* response queue message alignment */ 901 u32 fl_starve_thres; /* Free List starvation threshold */ 902 903 struct sge_idma_monitor_state idma_monitor; 904 unsigned int egr_start; 905 unsigned int egr_sz; 906 unsigned int ingr_start; 907 unsigned int ingr_sz; 908 void **egr_map; /* qid->queue egress queue map */ 909 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 910 unsigned long *starving_fl; 911 unsigned long *txq_maperr; 912 unsigned long *blocked_fl; 913 struct timer_list rx_timer; /* refills starving FLs */ 914 struct timer_list tx_timer; /* checks Tx queues */ 915 916 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 917 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 918 }; 919 920 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 921 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 922 923 struct l2t_data; 924 925 #ifdef CONFIG_PCI_IOV 926 927 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 928 * Configuration initialization for T5 only has SR-IOV functionality enabled 929 * on PF0-3 in order to simplify everything. 930 */ 931 #define NUM_OF_PF_WITH_SRIOV 4 932 933 #endif 934 935 struct doorbell_stats { 936 u32 db_drop; 937 u32 db_empty; 938 u32 db_full; 939 }; 940 941 struct hash_mac_addr { 942 struct list_head list; 943 u8 addr[ETH_ALEN]; 944 unsigned int iface_mac; 945 }; 946 947 struct msix_bmap { 948 unsigned long *msix_bmap; 949 unsigned int mapsize; 950 spinlock_t lock; /* lock for acquiring bitmap */ 951 }; 952 953 struct msix_info { 954 unsigned short vec; 955 char desc[IFNAMSIZ + 10]; 956 unsigned int idx; 957 cpumask_var_t aff_mask; 958 }; 959 960 struct vf_info { 961 unsigned char vf_mac_addr[ETH_ALEN]; 962 unsigned int tx_rate; 963 bool pf_set_mac; 964 u16 vlan; 965 int link_state; 966 }; 967 968 enum { 969 HMA_DMA_MAPPED_FLAG = 1 970 }; 971 972 struct hma_data { 973 unsigned char flags; 974 struct sg_table *sgt; 975 dma_addr_t *phy_addr; /* physical address of the page */ 976 }; 977 978 struct mbox_list { 979 struct list_head list; 980 }; 981 982 #if IS_ENABLED(CONFIG_THERMAL) 983 struct ch_thermal { 984 struct thermal_zone_device *tzdev; 985 int trip_temp; 986 int trip_type; 987 }; 988 #endif 989 990 struct mps_entries_ref { 991 struct list_head list; 992 u8 addr[ETH_ALEN]; 993 u8 mask[ETH_ALEN]; 994 u16 idx; 995 refcount_t refcnt; 996 }; 997 998 struct adapter { 999 void __iomem *regs; 1000 void __iomem *bar2; 1001 u32 t4_bar0; 1002 struct pci_dev *pdev; 1003 struct device *pdev_dev; 1004 const char *name; 1005 unsigned int mbox; 1006 unsigned int pf; 1007 unsigned int flags; 1008 unsigned int adap_idx; 1009 enum chip_type chip; 1010 u32 eth_flags; 1011 1012 int msg_enable; 1013 __be16 vxlan_port; 1014 u8 vxlan_port_cnt; 1015 __be16 geneve_port; 1016 u8 geneve_port_cnt; 1017 1018 struct adapter_params params; 1019 struct cxgb4_virt_res vres; 1020 unsigned int swintr; 1021 1022 /* MSI-X Info for NIC and OFLD queues */ 1023 struct msix_info *msix_info; 1024 struct msix_bmap msix_bmap; 1025 1026 struct doorbell_stats db_stats; 1027 struct sge sge; 1028 1029 struct net_device *port[MAX_NPORTS]; 1030 u8 chan_map[NCHAN]; /* channel -> port map */ 1031 1032 struct vf_info *vfinfo; 1033 u8 num_vfs; 1034 1035 u32 filter_mode; 1036 unsigned int l2t_start; 1037 unsigned int l2t_end; 1038 struct l2t_data *l2t; 1039 unsigned int clipt_start; 1040 unsigned int clipt_end; 1041 struct clip_tbl *clipt; 1042 unsigned int rawf_start; 1043 unsigned int rawf_cnt; 1044 struct smt_data *smt; 1045 struct cxgb4_uld_info *uld; 1046 void *uld_handle[CXGB4_ULD_MAX]; 1047 unsigned int num_uld; 1048 unsigned int num_ofld_uld; 1049 struct list_head list_node; 1050 struct list_head rcu_node; 1051 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 1052 struct list_head mps_ref; 1053 spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1054 1055 void *iscsi_ppm; 1056 1057 struct tid_info tids; 1058 void **tid_release_head; 1059 spinlock_t tid_release_lock; 1060 struct workqueue_struct *workq; 1061 struct work_struct tid_release_task; 1062 struct work_struct db_full_task; 1063 struct work_struct db_drop_task; 1064 struct work_struct fatal_err_notify_task; 1065 bool tid_release_task_busy; 1066 1067 /* lock for mailbox cmd list */ 1068 spinlock_t mbox_lock; 1069 struct mbox_list mlist; 1070 1071 /* support for mailbox command/reply logging */ 1072 #define T4_OS_LOG_MBOX_CMDS 256 1073 struct mbox_cmd_log *mbox_log; 1074 1075 struct mutex uld_mutex; 1076 1077 struct dentry *debugfs_root; 1078 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1079 bool trace_rss; /* 1 implies that different RSS flit per filter is 1080 * used per filter else if 0 default RSS flit is 1081 * used for all 4 filters. 1082 */ 1083 1084 struct ptp_clock *ptp_clock; 1085 struct ptp_clock_info ptp_clock_info; 1086 struct sk_buff *ptp_tx_skb; 1087 /* ptp lock */ 1088 spinlock_t ptp_lock; 1089 spinlock_t stats_lock; 1090 spinlock_t win0_lock ____cacheline_aligned_in_smp; 1091 1092 /* TC u32 offload */ 1093 struct cxgb4_tc_u32_table *tc_u32; 1094 struct chcr_stats_debug chcr_stats; 1095 1096 /* TC flower offload */ 1097 bool tc_flower_initialized; 1098 struct rhashtable flower_tbl; 1099 struct rhashtable_params flower_ht_params; 1100 struct timer_list flower_stats_timer; 1101 struct work_struct flower_stats_work; 1102 1103 /* Ethtool Dump */ 1104 struct ethtool_dump eth_dump; 1105 1106 /* HMA */ 1107 struct hma_data hma; 1108 1109 struct srq_data *srq; 1110 1111 /* Dump buffer for collecting logs in kdump kernel */ 1112 struct vmcoredd_data vmcoredd; 1113 #if IS_ENABLED(CONFIG_THERMAL) 1114 struct ch_thermal ch_thermal; 1115 #endif 1116 1117 /* TC MQPRIO offload */ 1118 struct cxgb4_tc_mqprio *tc_mqprio; 1119 1120 /* TC MATCHALL classifier offload */ 1121 struct cxgb4_tc_matchall *tc_matchall; 1122 }; 1123 1124 /* Support for "sched-class" command to allow a TX Scheduling Class to be 1125 * programmed with various parameters. 1126 */ 1127 struct ch_sched_params { 1128 s8 type; /* packet or flow */ 1129 union { 1130 struct { 1131 s8 level; /* scheduler hierarchy level */ 1132 s8 mode; /* per-class or per-flow */ 1133 s8 rateunit; /* bit or packet rate */ 1134 s8 ratemode; /* %port relative or kbps absolute */ 1135 s8 channel; /* scheduler channel [0..N] */ 1136 s8 class; /* scheduler class [0..N] */ 1137 s32 minrate; /* minimum rate */ 1138 s32 maxrate; /* maximum rate */ 1139 s16 weight; /* percent weight */ 1140 s16 pktsize; /* average packet size */ 1141 } params; 1142 } u; 1143 }; 1144 1145 enum { 1146 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 1147 }; 1148 1149 enum { 1150 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 1151 SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ 1152 }; 1153 1154 enum { 1155 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1156 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 1157 }; 1158 1159 enum { 1160 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1161 }; 1162 1163 enum { 1164 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1165 }; 1166 1167 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1168 * to be bound to a TX Scheduling Class. 1169 */ 1170 struct ch_sched_queue { 1171 s8 queue; /* queue index */ 1172 s8 class; /* class index */ 1173 }; 1174 1175 /* Support for "sched_flowc" command to allow one or more FLOWC 1176 * to be bound to a TX Scheduling Class. 1177 */ 1178 struct ch_sched_flowc { 1179 s32 tid; /* TID to bind */ 1180 s8 class; /* class index */ 1181 }; 1182 1183 /* Defined bit width of user definable filter tuples 1184 */ 1185 #define ETHTYPE_BITWIDTH 16 1186 #define FRAG_BITWIDTH 1 1187 #define MACIDX_BITWIDTH 9 1188 #define FCOE_BITWIDTH 1 1189 #define IPORT_BITWIDTH 3 1190 #define MATCHTYPE_BITWIDTH 3 1191 #define PROTO_BITWIDTH 8 1192 #define TOS_BITWIDTH 8 1193 #define PF_BITWIDTH 8 1194 #define VF_BITWIDTH 8 1195 #define IVLAN_BITWIDTH 16 1196 #define OVLAN_BITWIDTH 16 1197 #define ENCAP_VNI_BITWIDTH 24 1198 1199 /* Filter matching rules. These consist of a set of ingress packet field 1200 * (value, mask) tuples. The associated ingress packet field matches the 1201 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1202 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1203 * matches an ingress packet when all of the individual individual field 1204 * matching rules are true. 1205 * 1206 * Partial field masks are always valid, however, while it may be easy to 1207 * understand their meanings for some fields (e.g. IP address to match a 1208 * subnet), for others making sensible partial masks is less intuitive (e.g. 1209 * MPS match type) ... 1210 * 1211 * Most of the following data structures are modeled on T4 capabilities. 1212 * Drivers for earlier chips use the subsets which make sense for those chips. 1213 * We really need to come up with a hardware-independent mechanism to 1214 * represent hardware filter capabilities ... 1215 */ 1216 struct ch_filter_tuple { 1217 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1218 * register selects which of these fields will participate in the 1219 * filter match rules -- up to a maximum of 36 bits. Because 1220 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1221 * set of fields. 1222 */ 1223 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1224 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1225 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1226 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1227 uint32_t pfvf_vld:1; /* PF/VF valid */ 1228 uint32_t encap_vld:1; /* Encapsulation valid */ 1229 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1230 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1231 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1232 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1233 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1234 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1235 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1236 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1237 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1238 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1239 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1240 1241 /* Uncompressed header matching field rules. These are always 1242 * available for field rules. 1243 */ 1244 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1245 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1246 uint16_t lport; /* local port */ 1247 uint16_t fport; /* foreign port */ 1248 }; 1249 1250 /* A filter ioctl command. 1251 */ 1252 struct ch_filter_specification { 1253 /* Administrative fields for filter. 1254 */ 1255 uint32_t hitcnts:1; /* count filter hits in TCB */ 1256 uint32_t prio:1; /* filter has priority over active/server */ 1257 1258 /* Fundamental filter typing. This is the one element of filter 1259 * matching that doesn't exist as a (value, mask) tuple. 1260 */ 1261 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1262 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1263 1264 /* Packet dispatch information. Ingress packets which match the 1265 * filter rules will be dropped, passed to the host or switched back 1266 * out as egress packets. 1267 */ 1268 uint32_t action:2; /* drop, pass, switch */ 1269 1270 uint32_t rpttid:1; /* report TID in RSS hash field */ 1271 1272 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1273 uint32_t iq:10; /* ingress queue */ 1274 1275 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1276 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1277 /* 1 => TCB contains IQ ID */ 1278 1279 /* Switch proxy/rewrite fields. An ingress packet which matches a 1280 * filter with "switch" set will be looped back out as an egress 1281 * packet -- potentially with some Ethernet header rewriting. 1282 */ 1283 uint32_t eport:2; /* egress port to switch packet out */ 1284 uint32_t newdmac:1; /* rewrite destination MAC address */ 1285 uint32_t newsmac:1; /* rewrite source MAC address */ 1286 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1287 uint32_t nat_mode:3; /* specify NAT operation mode */ 1288 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1289 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1290 uint16_t vlan; /* VLAN Tag to insert */ 1291 1292 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1293 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1294 u16 nat_lport; /* local port to use after NAT'ing */ 1295 u16 nat_fport; /* foreign port to use after NAT'ing */ 1296 1297 u32 tc_prio; /* TC's filter priority index */ 1298 u64 tc_cookie; /* Unique cookie identifying TC rules */ 1299 1300 /* reservation for future additions */ 1301 u8 rsvd[12]; 1302 1303 /* Filter rule value/mask pairs. 1304 */ 1305 struct ch_filter_tuple val; 1306 struct ch_filter_tuple mask; 1307 }; 1308 1309 enum { 1310 FILTER_PASS = 0, /* default */ 1311 FILTER_DROP, 1312 FILTER_SWITCH 1313 }; 1314 1315 enum { 1316 VLAN_NOCHANGE = 0, /* default */ 1317 VLAN_REMOVE, 1318 VLAN_INSERT, 1319 VLAN_REWRITE 1320 }; 1321 1322 enum { 1323 NAT_MODE_NONE = 0, /* No NAT performed */ 1324 NAT_MODE_DIP, /* NAT on Dst IP */ 1325 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1326 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1327 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1328 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1329 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1330 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1331 }; 1332 1333 /* Host shadow copy of ingress filter entry. This is in host native format 1334 * and doesn't match the ordering or bit order, etc. of the hardware of the 1335 * firmware command. The use of bit-field structure elements is purely to 1336 * remind ourselves of the field size limitations and save memory in the case 1337 * where the filter table is large. 1338 */ 1339 struct filter_entry { 1340 /* Administrative fields for filter. */ 1341 u32 valid:1; /* filter allocated and valid */ 1342 u32 locked:1; /* filter is administratively locked */ 1343 1344 u32 pending:1; /* filter action is pending firmware reply */ 1345 struct filter_ctx *ctx; /* Caller's completion hook */ 1346 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1347 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1348 struct net_device *dev; /* Associated net device */ 1349 u32 tid; /* This will store the actual tid */ 1350 1351 /* The filter itself. Most of this is a straight copy of information 1352 * provided by the extended ioctl(). Some fields are translated to 1353 * internal forms -- for instance the Ingress Queue ID passed in from 1354 * the ioctl() is translated into the Absolute Ingress Queue ID. 1355 */ 1356 struct ch_filter_specification fs; 1357 }; 1358 1359 static inline int is_offload(const struct adapter *adap) 1360 { 1361 return adap->params.offload; 1362 } 1363 1364 static inline int is_hashfilter(const struct adapter *adap) 1365 { 1366 return adap->params.hash_filter; 1367 } 1368 1369 static inline int is_pci_uld(const struct adapter *adap) 1370 { 1371 return adap->params.crypto; 1372 } 1373 1374 static inline int is_uld(const struct adapter *adap) 1375 { 1376 return (adap->params.offload || adap->params.crypto); 1377 } 1378 1379 static inline int is_ethofld(const struct adapter *adap) 1380 { 1381 return adap->params.ethofld; 1382 } 1383 1384 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1385 { 1386 return readl(adap->regs + reg_addr); 1387 } 1388 1389 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1390 { 1391 writel(val, adap->regs + reg_addr); 1392 } 1393 1394 #ifndef readq 1395 static inline u64 readq(const volatile void __iomem *addr) 1396 { 1397 return readl(addr) + ((u64)readl(addr + 4) << 32); 1398 } 1399 1400 static inline void writeq(u64 val, volatile void __iomem *addr) 1401 { 1402 writel(val, addr); 1403 writel(val >> 32, addr + 4); 1404 } 1405 #endif 1406 1407 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1408 { 1409 return readq(adap->regs + reg_addr); 1410 } 1411 1412 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1413 { 1414 writeq(val, adap->regs + reg_addr); 1415 } 1416 1417 /** 1418 * t4_set_hw_addr - store a port's MAC address in SW 1419 * @adapter: the adapter 1420 * @port_idx: the port index 1421 * @hw_addr: the Ethernet address 1422 * 1423 * Store the Ethernet address of the given port in SW. Called by the common 1424 * code when it retrieves a port's Ethernet address from EEPROM. 1425 */ 1426 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1427 u8 hw_addr[]) 1428 { 1429 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1430 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1431 } 1432 1433 /** 1434 * netdev2pinfo - return the port_info structure associated with a net_device 1435 * @dev: the netdev 1436 * 1437 * Return the struct port_info associated with a net_device 1438 */ 1439 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1440 { 1441 return netdev_priv(dev); 1442 } 1443 1444 /** 1445 * adap2pinfo - return the port_info of a port 1446 * @adap: the adapter 1447 * @idx: the port index 1448 * 1449 * Return the port_info structure for the port of the given index. 1450 */ 1451 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1452 { 1453 return netdev_priv(adap->port[idx]); 1454 } 1455 1456 /** 1457 * netdev2adap - return the adapter structure associated with a net_device 1458 * @dev: the netdev 1459 * 1460 * Return the struct adapter associated with a net_device 1461 */ 1462 static inline struct adapter *netdev2adap(const struct net_device *dev) 1463 { 1464 return netdev2pinfo(dev)->adapter; 1465 } 1466 1467 /* Return a version number to identify the type of adapter. The scheme is: 1468 * - bits 0..9: chip version 1469 * - bits 10..15: chip revision 1470 * - bits 16..23: register dump version 1471 */ 1472 static inline unsigned int mk_adap_vers(struct adapter *ap) 1473 { 1474 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1475 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1476 } 1477 1478 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1479 static inline unsigned int qtimer_val(const struct adapter *adap, 1480 const struct sge_rspq *q) 1481 { 1482 unsigned int idx = q->intr_params >> 1; 1483 1484 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1485 } 1486 1487 /* driver version & name used for ethtool_drvinfo */ 1488 extern char cxgb4_driver_name[]; 1489 extern const char cxgb4_driver_version[]; 1490 1491 void t4_os_portmod_changed(struct adapter *adap, int port_id); 1492 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1493 1494 void t4_free_sge_resources(struct adapter *adap); 1495 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1496 irq_handler_t t4_intr_handler(struct adapter *adap); 1497 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1498 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1499 const struct pkt_gl *gl); 1500 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1501 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1502 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1503 struct net_device *dev, int intr_idx, 1504 struct sge_fl *fl, rspq_handler_t hnd, 1505 rspq_flush_handler_t flush_handler, int cong); 1506 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1507 struct net_device *dev, struct netdev_queue *netdevq, 1508 unsigned int iqid, u8 dbqt); 1509 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1510 struct net_device *dev, unsigned int iqid, 1511 unsigned int cmplqid); 1512 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1513 unsigned int cmplqid); 1514 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1515 struct net_device *dev, unsigned int iqid, 1516 unsigned int uld_type); 1517 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 1518 struct net_device *dev, u32 iqid); 1519 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1520 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1521 int t4_sge_init(struct adapter *adap); 1522 void t4_sge_start(struct adapter *adap); 1523 void t4_sge_stop(struct adapter *adap); 1524 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1525 int maxreclaim); 1526 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1527 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1528 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1529 extern int dbfifo_int_thresh; 1530 1531 #define for_each_port(adapter, iter) \ 1532 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1533 1534 static inline int is_bypass(struct adapter *adap) 1535 { 1536 return adap->params.bypass; 1537 } 1538 1539 static inline int is_bypass_device(int device) 1540 { 1541 /* this should be set based upon device capabilities */ 1542 switch (device) { 1543 case 0x440b: 1544 case 0x440c: 1545 return 1; 1546 default: 1547 return 0; 1548 } 1549 } 1550 1551 static inline int is_10gbt_device(int device) 1552 { 1553 /* this should be set based upon device capabilities */ 1554 switch (device) { 1555 case 0x4409: 1556 case 0x4486: 1557 return 1; 1558 1559 default: 1560 return 0; 1561 } 1562 } 1563 1564 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1565 { 1566 return adap->params.vpd.cclk / 1000; 1567 } 1568 1569 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1570 unsigned int us) 1571 { 1572 return (us * adap->params.vpd.cclk) / 1000; 1573 } 1574 1575 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1576 unsigned int ticks) 1577 { 1578 /* add Core Clock / 2 to round ticks to nearest uS */ 1579 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1580 adapter->params.vpd.cclk); 1581 } 1582 1583 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1584 unsigned int ticks) 1585 { 1586 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1587 } 1588 1589 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1590 u32 val); 1591 1592 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1593 int size, void *rpl, bool sleep_ok, int timeout); 1594 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1595 void *rpl, bool sleep_ok); 1596 1597 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1598 const void *cmd, int size, void *rpl, 1599 int timeout) 1600 { 1601 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1602 timeout); 1603 } 1604 1605 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1606 int size, void *rpl) 1607 { 1608 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1609 } 1610 1611 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1612 int size, void *rpl) 1613 { 1614 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1615 } 1616 1617 /** 1618 * hash_mac_addr - return the hash value of a MAC address 1619 * @addr: the 48-bit Ethernet MAC address 1620 * 1621 * Hashes a MAC address according to the hash function used by HW inexact 1622 * (hash) address matching. 1623 */ 1624 static inline int hash_mac_addr(const u8 *addr) 1625 { 1626 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1627 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1628 1629 a ^= b; 1630 a ^= (a >> 12); 1631 a ^= (a >> 6); 1632 return a & 0x3f; 1633 } 1634 1635 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1636 unsigned int cnt); 1637 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1638 unsigned int us, unsigned int cnt, 1639 unsigned int size, unsigned int iqe_size) 1640 { 1641 q->adap = adap; 1642 cxgb4_set_rspq_intr_params(q, us, cnt); 1643 q->iqe_len = iqe_size; 1644 q->size = size; 1645 } 1646 1647 /** 1648 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1649 * @fw_mod_type: the Firmware Mofule Type 1650 * 1651 * Return whether the Firmware Module Type represents a real Transceiver 1652 * Module/Cable Module Type which has been inserted. 1653 */ 1654 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1655 { 1656 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1657 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1658 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1659 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1660 } 1661 1662 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1663 unsigned int data_reg, const u32 *vals, 1664 unsigned int nregs, unsigned int start_idx); 1665 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1666 unsigned int data_reg, u32 *vals, unsigned int nregs, 1667 unsigned int start_idx); 1668 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1669 1670 struct fw_filter_wr; 1671 1672 void t4_intr_enable(struct adapter *adapter); 1673 void t4_intr_disable(struct adapter *adapter); 1674 int t4_slow_intr_handler(struct adapter *adapter); 1675 1676 int t4_wait_dev_ready(void __iomem *regs); 1677 1678 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 1679 struct link_config *lc); 1680 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 1681 unsigned int port, struct link_config *lc, 1682 u8 sleep_ok, int timeout); 1683 1684 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 1685 unsigned int port, struct link_config *lc) 1686 { 1687 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1688 true, FW_CMD_MAX_TIMEOUT); 1689 } 1690 1691 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 1692 unsigned int port, struct link_config *lc) 1693 { 1694 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1695 false, FW_CMD_MAX_TIMEOUT); 1696 } 1697 1698 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1699 1700 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1701 u32 t4_get_util_window(struct adapter *adap); 1702 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1703 1704 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1705 u32 *mem_base, u32 *mem_aperture); 1706 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1707 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1708 int dir); 1709 #define T4_MEMORY_WRITE 0 1710 #define T4_MEMORY_READ 1 1711 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1712 void *buf, int dir); 1713 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1714 u32 len, __be32 *buf) 1715 { 1716 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1717 } 1718 1719 unsigned int t4_get_regs_len(struct adapter *adapter); 1720 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1721 1722 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1723 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1724 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1725 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1726 int t4_get_pfres(struct adapter *adapter); 1727 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1728 unsigned int nwords, u32 *data, int byte_oriented); 1729 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1730 int t4_load_phy_fw(struct adapter *adap, 1731 int win, spinlock_t *lock, 1732 int (*phy_fw_version)(const u8 *, size_t), 1733 const u8 *phy_fw_data, size_t phy_fw_size); 1734 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1735 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1736 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1737 const u8 *fw_data, unsigned int size, int force); 1738 int t4_fl_pkt_align(struct adapter *adap); 1739 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1740 int t4_check_fw_version(struct adapter *adap); 1741 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1742 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1743 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1744 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1745 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1746 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1747 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1748 int t4_get_version_info(struct adapter *adapter); 1749 void t4_dump_version_info(struct adapter *adapter); 1750 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1751 const u8 *fw_data, unsigned int fw_size, 1752 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1753 int t4_prep_adapter(struct adapter *adapter); 1754 int t4_shutdown_adapter(struct adapter *adapter); 1755 1756 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1757 int t4_bar2_sge_qregs(struct adapter *adapter, 1758 unsigned int qid, 1759 enum t4_bar2_qtype qtype, 1760 int user, 1761 u64 *pbar2_qoffset, 1762 unsigned int *pbar2_qid); 1763 1764 unsigned int qtimer_val(const struct adapter *adap, 1765 const struct sge_rspq *q); 1766 1767 int t4_init_devlog_params(struct adapter *adapter); 1768 int t4_init_sge_params(struct adapter *adapter); 1769 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1770 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1771 int t4_init_rss_mode(struct adapter *adap, int mbox); 1772 int t4_init_portinfo(struct port_info *pi, int mbox, 1773 int port, int pf, int vf, u8 mac[]); 1774 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1775 void t4_fatal_err(struct adapter *adapter); 1776 unsigned int t4_chip_rss_size(struct adapter *adapter); 1777 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1778 int start, int n, const u16 *rspq, unsigned int nrspq); 1779 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1780 unsigned int flags); 1781 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1782 unsigned int flags, unsigned int defq); 1783 int t4_read_rss(struct adapter *adapter, u16 *entries); 1784 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1785 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1786 bool sleep_ok); 1787 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1788 u32 *valp, bool sleep_ok); 1789 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1790 u32 *vfl, u32 *vfh, bool sleep_ok); 1791 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1792 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1793 1794 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1795 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1796 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1797 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1798 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1799 size_t n); 1800 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1801 size_t n); 1802 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1803 unsigned int *valp); 1804 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1805 const unsigned int *valp); 1806 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1807 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1808 unsigned int *pif_req_wrptr, 1809 unsigned int *pif_rsp_wrptr); 1810 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1811 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1812 const char *t4_get_port_type_description(enum fw_port_type port_type); 1813 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1814 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1815 struct port_stats *stats, 1816 struct port_stats *offset); 1817 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1818 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1819 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1820 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1821 unsigned int mask, unsigned int val); 1822 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1823 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1824 bool sleep_ok); 1825 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1826 bool sleep_ok); 1827 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1828 bool sleep_ok); 1829 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1830 bool sleep_ok); 1831 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1832 struct tp_tcp_stats *v6, bool sleep_ok); 1833 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1834 struct tp_fcoe_stats *st, bool sleep_ok); 1835 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1836 const unsigned short *alpha, const unsigned short *beta); 1837 1838 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1839 1840 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1841 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1842 1843 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1844 const u8 *addr); 1845 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1846 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1847 1848 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1849 enum dev_master master, enum dev_state *state); 1850 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1851 int t4_early_init(struct adapter *adap, unsigned int mbox); 1852 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1853 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1854 unsigned int cache_line_size); 1855 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1856 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1857 unsigned int vf, unsigned int nparams, const u32 *params, 1858 u32 *val); 1859 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1860 unsigned int vf, unsigned int nparams, const u32 *params, 1861 u32 *val); 1862 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1863 unsigned int vf, unsigned int nparams, const u32 *params, 1864 u32 *val, int rw, bool sleep_ok); 1865 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1866 unsigned int pf, unsigned int vf, 1867 unsigned int nparams, const u32 *params, 1868 const u32 *val, int timeout); 1869 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1870 unsigned int vf, unsigned int nparams, const u32 *params, 1871 const u32 *val); 1872 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1873 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1874 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1875 unsigned int vi, unsigned int cmask, unsigned int pmask, 1876 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1877 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1878 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1879 unsigned int *rss_size, u8 *vivld, u8 *vin); 1880 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1881 unsigned int pf, unsigned int vf, 1882 unsigned int viid); 1883 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1884 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1885 bool sleep_ok); 1886 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1887 const u8 *addr, const u8 *mask, unsigned int idx, 1888 u8 lookup_type, u8 port_id, bool sleep_ok); 1889 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 1890 bool sleep_ok); 1891 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 1892 const u8 *addr, const u8 *mask, unsigned int vni, 1893 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 1894 bool sleep_ok); 1895 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1896 const u8 *addr, const u8 *mask, unsigned int idx, 1897 u8 lookup_type, u8 port_id, bool sleep_ok); 1898 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1899 unsigned int viid, bool free, unsigned int naddr, 1900 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1901 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1902 unsigned int viid, unsigned int naddr, 1903 const u8 **addr, bool sleep_ok); 1904 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1905 int idx, const u8 *addr, bool persist, u8 *smt_idx); 1906 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1907 bool ucast, u64 vec, bool sleep_ok); 1908 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1909 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1910 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1911 struct port_info *pi, 1912 bool rx_en, bool tx_en, bool dcb_en); 1913 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1914 bool rx_en, bool tx_en); 1915 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1916 unsigned int nblinks); 1917 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1918 unsigned int mmd, unsigned int reg, u16 *valp); 1919 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1920 unsigned int mmd, unsigned int reg, u16 val); 1921 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1922 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1923 unsigned int fl0id, unsigned int fl1id); 1924 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1925 unsigned int vf, unsigned int iqtype, unsigned int iqid, 1926 unsigned int fl0id, unsigned int fl1id); 1927 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1928 unsigned int vf, unsigned int eqid); 1929 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1930 unsigned int vf, unsigned int eqid); 1931 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1932 unsigned int vf, unsigned int eqid); 1933 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1934 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 1935 u16 *dbqtimers); 1936 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1937 int t4_update_port_info(struct port_info *pi); 1938 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1939 unsigned int *speedp, unsigned int *mtup); 1940 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1941 void t4_db_full(struct adapter *adapter); 1942 void t4_db_dropped(struct adapter *adapter); 1943 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 1944 int filter_index, int enable); 1945 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 1946 int filter_index, int *enabled); 1947 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 1948 u32 addr, u32 val); 1949 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 1950 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 1951 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 1952 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 1953 enum ctxt_type ctype, u32 *data); 1954 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 1955 enum ctxt_type ctype, u32 *data); 1956 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1957 int rateunit, int ratemode, int channel, int class, 1958 int minrate, int maxrate, int weight, int pktsize); 1959 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1960 void t4_idma_monitor_init(struct adapter *adapter, 1961 struct sge_idma_monitor_state *idma); 1962 void t4_idma_monitor(struct adapter *adapter, 1963 struct sge_idma_monitor_state *idma, 1964 int hz, int ticks); 1965 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1966 unsigned int naddr, u8 *addr); 1967 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1968 u32 start_index, bool sleep_ok); 1969 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 1970 u32 start_index, bool sleep_ok); 1971 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 1972 u32 start_index, bool sleep_ok); 1973 1974 void t4_uld_mem_free(struct adapter *adap); 1975 int t4_uld_mem_alloc(struct adapter *adap); 1976 void t4_uld_clean_up(struct adapter *adap); 1977 void t4_register_netevent_notifier(void); 1978 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1979 unsigned int devid, unsigned int offset, 1980 unsigned int len, u8 *buf); 1981 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1982 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1983 unsigned int n, bool unmap); 1984 void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 1985 u32 ndesc); 1986 int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 1987 void cxgb4_ethofld_restart(unsigned long data); 1988 int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 1989 const struct pkt_gl *si); 1990 void free_txq(struct adapter *adap, struct sge_txq *q); 1991 void cxgb4_reclaim_completed_tx(struct adapter *adap, 1992 struct sge_txq *q, bool unmap); 1993 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1994 dma_addr_t *addr); 1995 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1996 void *pos); 1997 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1998 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1999 const dma_addr_t *addr); 2000 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 2001 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 2002 u16 vlan); 2003 int cxgb4_dcb_enabled(const struct net_device *dev); 2004 2005 int cxgb4_thermal_init(struct adapter *adap); 2006 int cxgb4_thermal_remove(struct adapter *adap); 2007 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 2008 cpumask_var_t *aff_mask, int idx); 2009 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 2010 2011 int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 2012 int *tcam_idx, const u8 *addr, 2013 bool persistent, u8 *smt_idx); 2014 2015 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 2016 bool free, unsigned int naddr, 2017 const u8 **addr, u16 *idx, 2018 u64 *hash, bool sleep_ok); 2019 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2020 unsigned int naddr, const u8 **addr, bool sleep_ok); 2021 int cxgb4_init_mps_ref_entries(struct adapter *adap); 2022 void cxgb4_free_mps_ref_entries(struct adapter *adap); 2023 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 2024 const u8 *addr, const u8 *mask, 2025 unsigned int vni, unsigned int vni_mask, 2026 u8 dip_hit, u8 lookup_type, bool sleep_ok); 2027 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 2028 int idx, bool sleep_ok); 2029 int cxgb4_free_raw_mac_filt(struct adapter *adap, 2030 unsigned int viid, 2031 const u8 *addr, 2032 const u8 *mask, 2033 unsigned int idx, 2034 u8 lookup_type, 2035 u8 port_id, 2036 bool sleep_ok); 2037 int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 2038 unsigned int viid, 2039 const u8 *addr, 2040 const u8 *mask, 2041 unsigned int idx, 2042 u8 lookup_type, 2043 u8 port_id, 2044 bool sleep_ok); 2045 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 2046 int *tcam_idx, const u8 *addr, 2047 bool persistent, u8 *smt_idx); 2048 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 2049 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2050 int cxgb_open(struct net_device *dev); 2051 int cxgb_close(struct net_device *dev); 2052 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 2053 void cxgb4_quiesce_rx(struct sge_rspq *q); 2054 #endif /* __CXGB4_H__ */ 2055