1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_H__ 36 #define __CXGB4_H__ 37 38 #include "t4_hw.h" 39 40 #include <linux/bitops.h> 41 #include <linux/cache.h> 42 #include <linux/interrupt.h> 43 #include <linux/list.h> 44 #include <linux/netdevice.h> 45 #include <linux/pci.h> 46 #include <linux/spinlock.h> 47 #include <linux/timer.h> 48 #include <linux/vmalloc.h> 49 #include <linux/rhashtable.h> 50 #include <linux/etherdevice.h> 51 #include <linux/net_tstamp.h> 52 #include <linux/ptp_clock_kernel.h> 53 #include <linux/ptp_classify.h> 54 #include <linux/crash_dump.h> 55 #include <linux/thermal.h> 56 #include <asm/io.h> 57 #include "t4_chip_type.h" 58 #include "cxgb4_uld.h" 59 #include "t4fw_api.h" 60 61 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 62 extern struct list_head adapter_list; 63 extern struct list_head uld_list; 64 extern struct mutex uld_mutex; 65 66 /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 67 * This is the same as calc_tx_descs() for a TSO packet with 68 * nr_frags == MAX_SKB_FRAGS. 69 */ 70 #define ETHTXQ_STOP_THRES \ 71 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 72 73 #define FW_PARAM_DEV(param) \ 74 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 75 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 76 77 #define FW_PARAM_PFVF(param) \ 78 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 79 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 80 FW_PARAMS_PARAM_Y_V(0) | \ 81 FW_PARAMS_PARAM_Z_V(0)) 82 83 enum { 84 MAX_NPORTS = 4, /* max # of ports */ 85 SERNUM_LEN = 24, /* Serial # length */ 86 EC_LEN = 16, /* E/C length */ 87 ID_LEN = 16, /* ID length */ 88 PN_LEN = 16, /* Part Number length */ 89 MACADDR_LEN = 12, /* MAC Address length */ 90 }; 91 92 enum { 93 T4_REGMAP_SIZE = (160 * 1024), 94 T5_REGMAP_SIZE = (332 * 1024), 95 }; 96 97 enum { 98 MEM_EDC0, 99 MEM_EDC1, 100 MEM_MC, 101 MEM_MC0 = MEM_MC, 102 MEM_MC1, 103 MEM_HMA, 104 }; 105 106 enum { 107 MEMWIN0_APERTURE = 2048, 108 MEMWIN0_BASE = 0x1b800, 109 MEMWIN1_APERTURE = 32768, 110 MEMWIN1_BASE = 0x28000, 111 MEMWIN1_BASE_T5 = 0x52000, 112 MEMWIN2_APERTURE = 65536, 113 MEMWIN2_BASE = 0x30000, 114 MEMWIN2_APERTURE_T5 = 131072, 115 MEMWIN2_BASE_T5 = 0x60000, 116 }; 117 118 enum dev_master { 119 MASTER_CANT, 120 MASTER_MAY, 121 MASTER_MUST 122 }; 123 124 enum dev_state { 125 DEV_STATE_UNINIT, 126 DEV_STATE_INIT, 127 DEV_STATE_ERR 128 }; 129 130 enum cc_pause { 131 PAUSE_RX = 1 << 0, 132 PAUSE_TX = 1 << 1, 133 PAUSE_AUTONEG = 1 << 2 134 }; 135 136 enum cc_fec { 137 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 138 FEC_RS = 1 << 1, /* Reed-Solomon */ 139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 140 }; 141 142 enum { 143 CXGB4_ETHTOOL_FLASH_FW = 1, 144 CXGB4_ETHTOOL_FLASH_PHY = 2, 145 CXGB4_ETHTOOL_FLASH_BOOT = 3, 146 CXGB4_ETHTOOL_FLASH_BOOTCFG = 4 147 }; 148 149 struct cxgb4_bootcfg_data { 150 __le16 signature; 151 __u8 reserved[2]; 152 }; 153 154 struct cxgb4_pcir_data { 155 __le32 signature; /* Signature. The string "PCIR" */ 156 __le16 vendor_id; /* Vendor Identification */ 157 __le16 device_id; /* Device Identification */ 158 __u8 vital_product[2]; /* Pointer to Vital Product Data */ 159 __u8 length[2]; /* PCIR Data Structure Length */ 160 __u8 revision; /* PCIR Data Structure Revision */ 161 __u8 class_code[3]; /* Class Code */ 162 __u8 image_length[2]; /* Image Length. Multiple of 512B */ 163 __u8 code_revision[2]; /* Revision Level of Code/Data */ 164 __u8 code_type; 165 __u8 indicator; 166 __u8 reserved[2]; 167 }; 168 169 /* BIOS boot headers */ 170 struct cxgb4_pci_exp_rom_header { 171 __le16 signature; /* ROM Signature. Should be 0xaa55 */ 172 __u8 reserved[22]; /* Reserved per processor Architecture data */ 173 __le16 pcir_offset; /* Offset to PCI Data Structure */ 174 }; 175 176 /* Legacy PCI Expansion ROM Header */ 177 struct legacy_pci_rom_hdr { 178 __u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 179 __u8 size512; /* Current Image Size in units of 512 bytes */ 180 __u8 initentry_point[4]; 181 __u8 cksum; /* Checksum computed on the entire Image */ 182 __u8 reserved[16]; /* Reserved */ 183 __le16 pcir_offset; /* Offset to PCI Data Struture */ 184 }; 185 186 #define CXGB4_HDR_CODE1 0x00 187 #define CXGB4_HDR_CODE2 0x03 188 #define CXGB4_HDR_INDI 0x80 189 190 /* BOOT constants */ 191 enum { 192 BOOT_CFG_SIG = 0x4243, 193 BOOT_SIZE_INC = 512, 194 BOOT_SIGNATURE = 0xaa55, 195 BOOT_MIN_SIZE = sizeof(struct cxgb4_pci_exp_rom_header), 196 BOOT_MAX_SIZE = 1024 * BOOT_SIZE_INC, 197 PCIR_SIGNATURE = 0x52494350 198 }; 199 200 struct port_stats { 201 u64 tx_octets; /* total # of octets in good frames */ 202 u64 tx_frames; /* all good frames */ 203 u64 tx_bcast_frames; /* all broadcast frames */ 204 u64 tx_mcast_frames; /* all multicast frames */ 205 u64 tx_ucast_frames; /* all unicast frames */ 206 u64 tx_error_frames; /* all error frames */ 207 208 u64 tx_frames_64; /* # of Tx frames in a particular range */ 209 u64 tx_frames_65_127; 210 u64 tx_frames_128_255; 211 u64 tx_frames_256_511; 212 u64 tx_frames_512_1023; 213 u64 tx_frames_1024_1518; 214 u64 tx_frames_1519_max; 215 216 u64 tx_drop; /* # of dropped Tx frames */ 217 u64 tx_pause; /* # of transmitted pause frames */ 218 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 219 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 220 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 221 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 222 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 223 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 224 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 225 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 226 227 u64 rx_octets; /* total # of octets in good frames */ 228 u64 rx_frames; /* all good frames */ 229 u64 rx_bcast_frames; /* all broadcast frames */ 230 u64 rx_mcast_frames; /* all multicast frames */ 231 u64 rx_ucast_frames; /* all unicast frames */ 232 u64 rx_too_long; /* # of frames exceeding MTU */ 233 u64 rx_jabber; /* # of jabber frames */ 234 u64 rx_fcs_err; /* # of received frames with bad FCS */ 235 u64 rx_len_err; /* # of received frames with length error */ 236 u64 rx_symbol_err; /* symbol errors */ 237 u64 rx_runt; /* # of short frames */ 238 239 u64 rx_frames_64; /* # of Rx frames in a particular range */ 240 u64 rx_frames_65_127; 241 u64 rx_frames_128_255; 242 u64 rx_frames_256_511; 243 u64 rx_frames_512_1023; 244 u64 rx_frames_1024_1518; 245 u64 rx_frames_1519_max; 246 247 u64 rx_pause; /* # of received pause frames */ 248 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 249 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 250 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 251 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 252 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 253 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 254 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 255 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 256 257 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 258 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 259 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 260 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 261 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 262 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 263 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 264 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 265 }; 266 267 struct lb_port_stats { 268 u64 octets; 269 u64 frames; 270 u64 bcast_frames; 271 u64 mcast_frames; 272 u64 ucast_frames; 273 u64 error_frames; 274 275 u64 frames_64; 276 u64 frames_65_127; 277 u64 frames_128_255; 278 u64 frames_256_511; 279 u64 frames_512_1023; 280 u64 frames_1024_1518; 281 u64 frames_1519_max; 282 283 u64 drop; 284 285 u64 ovflow0; 286 u64 ovflow1; 287 u64 ovflow2; 288 u64 ovflow3; 289 u64 trunc0; 290 u64 trunc1; 291 u64 trunc2; 292 u64 trunc3; 293 }; 294 295 struct tp_tcp_stats { 296 u32 tcp_out_rsts; 297 u64 tcp_in_segs; 298 u64 tcp_out_segs; 299 u64 tcp_retrans_segs; 300 }; 301 302 struct tp_usm_stats { 303 u32 frames; 304 u32 drops; 305 u64 octets; 306 }; 307 308 struct tp_fcoe_stats { 309 u32 frames_ddp; 310 u32 frames_drop; 311 u64 octets_ddp; 312 }; 313 314 struct tp_err_stats { 315 u32 mac_in_errs[4]; 316 u32 hdr_in_errs[4]; 317 u32 tcp_in_errs[4]; 318 u32 tnl_cong_drops[4]; 319 u32 ofld_chan_drops[4]; 320 u32 tnl_tx_drops[4]; 321 u32 ofld_vlan_drops[4]; 322 u32 tcp6_in_errs[4]; 323 u32 ofld_no_neigh; 324 u32 ofld_cong_defer; 325 }; 326 327 struct tp_cpl_stats { 328 u32 req[4]; 329 u32 rsp[4]; 330 }; 331 332 struct tp_rdma_stats { 333 u32 rqe_dfr_pkt; 334 u32 rqe_dfr_mod; 335 }; 336 337 struct sge_params { 338 u32 hps; /* host page size for our PF/VF */ 339 u32 eq_qpp; /* egress queues/page for our PF/VF */ 340 u32 iq_qpp; /* egress queues/page for our PF/VF */ 341 }; 342 343 struct tp_params { 344 unsigned int tre; /* log2 of core clocks per TP tick */ 345 unsigned int la_mask; /* what events are recorded by TP LA */ 346 unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 347 /* channel map */ 348 349 uint32_t dack_re; /* DACK timer resolution */ 350 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 351 352 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 353 u32 filter_mask; 354 u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 355 356 /* cached TP_OUT_CONFIG compressed error vector 357 * and passing outer header info for encapsulated packets. 358 */ 359 int rx_pkt_encap; 360 361 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 362 * subset of the set of fields which may be present in the Compressed 363 * Filter Tuple portion of filters and TCP TCB connections. The 364 * fields which are present are controlled by the TP_VLAN_PRI_MAP. 365 * Since a variable number of fields may or may not be present, their 366 * shifted field positions within the Compressed Filter Tuple may 367 * vary, or not even be present if the field isn't selected in 368 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 369 * places we store their offsets here, or a -1 if the field isn't 370 * present. 371 */ 372 int fcoe_shift; 373 int port_shift; 374 int vnic_shift; 375 int vlan_shift; 376 int tos_shift; 377 int protocol_shift; 378 int ethertype_shift; 379 int macmatch_shift; 380 int matchtype_shift; 381 int frag_shift; 382 383 u64 hash_filter_mask; 384 }; 385 386 struct vpd_params { 387 unsigned int cclk; 388 u8 ec[EC_LEN + 1]; 389 u8 sn[SERNUM_LEN + 1]; 390 u8 id[ID_LEN + 1]; 391 u8 pn[PN_LEN + 1]; 392 u8 na[MACADDR_LEN + 1]; 393 }; 394 395 /* Maximum resources provisioned for a PCI PF. 396 */ 397 struct pf_resources { 398 unsigned int nvi; /* N virtual interfaces */ 399 unsigned int neq; /* N egress Qs */ 400 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 401 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 402 unsigned int niq; /* N ingress Qs */ 403 unsigned int tc; /* PCI-E traffic class */ 404 unsigned int pmask; /* port access rights mask */ 405 unsigned int nexactf; /* N exact MPS filters */ 406 unsigned int r_caps; /* read capabilities */ 407 unsigned int wx_caps; /* write/execute capabilities */ 408 }; 409 410 struct pci_params { 411 unsigned int vpd_cap_addr; 412 unsigned char speed; 413 unsigned char width; 414 }; 415 416 struct devlog_params { 417 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 418 u32 start; /* start of log in firmware memory */ 419 u32 size; /* size of log */ 420 }; 421 422 /* Stores chip specific parameters */ 423 struct arch_specific_params { 424 u8 nchan; 425 u8 pm_stats_cnt; 426 u8 cng_ch_bits_log; /* congestion channel map bits width */ 427 u16 mps_rplc_size; 428 u16 vfcount; 429 u32 sge_fl_db; 430 u16 mps_tcam_size; 431 }; 432 433 struct adapter_params { 434 struct sge_params sge; 435 struct tp_params tp; 436 struct vpd_params vpd; 437 struct pf_resources pfres; 438 struct pci_params pci; 439 struct devlog_params devlog; 440 enum pcie_memwin drv_memwin; 441 442 unsigned int cim_la_size; 443 444 unsigned int sf_size; /* serial flash size in bytes */ 445 unsigned int sf_nsec; /* # of flash sectors */ 446 447 unsigned int fw_vers; /* firmware version */ 448 unsigned int bs_vers; /* bootstrap version */ 449 unsigned int tp_vers; /* TP microcode version */ 450 unsigned int er_vers; /* expansion ROM version */ 451 unsigned int scfg_vers; /* Serial Configuration version */ 452 unsigned int vpd_vers; /* VPD Version */ 453 u8 api_vers[7]; 454 455 unsigned short mtus[NMTUS]; 456 unsigned short a_wnd[NCCTRL_WIN]; 457 unsigned short b_wnd[NCCTRL_WIN]; 458 459 unsigned char nports; /* # of ethernet ports */ 460 unsigned char portvec; 461 enum chip_type chip; /* chip code */ 462 struct arch_specific_params arch; /* chip specific params */ 463 unsigned char offload; 464 unsigned char crypto; /* HW capability for crypto */ 465 unsigned char ethofld; /* QoS support */ 466 467 unsigned char bypass; 468 unsigned char hash_filter; 469 470 unsigned int ofldq_wr_cred; 471 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 472 473 unsigned int nsched_cls; /* number of traffic classes */ 474 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 475 unsigned int max_ird_adapter; /* Max read depth per adapter */ 476 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 477 u8 fw_caps_support; /* 32-bit Port Capabilities */ 478 bool filter2_wr_support; /* FW support for FILTER2_WR */ 479 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 480 481 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 482 * used by the Port 483 */ 484 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 485 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 486 bool write_cmpl_support; /* FW supports WRITE_CMPL */ 487 }; 488 489 /* State needed to monitor the forward progress of SGE Ingress DMA activities 490 * and possible hangs. 491 */ 492 struct sge_idma_monitor_state { 493 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 494 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 495 unsigned int idma_state[2]; /* IDMA Hang detect state */ 496 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 497 unsigned int idma_warn[2]; /* time to warning in HZ */ 498 }; 499 500 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 501 * The access and execute times are signed in order to accommodate negative 502 * error returns. 503 */ 504 struct mbox_cmd { 505 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 506 u64 timestamp; /* OS-dependent timestamp */ 507 u32 seqno; /* sequence number */ 508 s16 access; /* time (ms) to access mailbox */ 509 s16 execute; /* time (ms) to execute */ 510 }; 511 512 struct mbox_cmd_log { 513 unsigned int size; /* number of entries in the log */ 514 unsigned int cursor; /* next position in the log to write */ 515 u32 seqno; /* next sequence number */ 516 /* variable length mailbox command log starts here */ 517 }; 518 519 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 520 * return a pointer to the specified entry. 521 */ 522 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 523 unsigned int entry_idx) 524 { 525 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 526 } 527 528 #define FW_VERSION(chip) ( \ 529 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 530 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 531 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 532 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 533 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 534 535 struct fw_info { 536 u8 chip; 537 char *fs_name; 538 char *fw_mod_name; 539 struct fw_hdr fw_hdr; 540 }; 541 542 struct trace_params { 543 u32 data[TRACE_LEN / 4]; 544 u32 mask[TRACE_LEN / 4]; 545 unsigned short snap_len; 546 unsigned short min_len; 547 unsigned char skip_ofst; 548 unsigned char skip_len; 549 unsigned char invert; 550 unsigned char port; 551 }; 552 553 struct cxgb4_fw_data { 554 __be32 signature; 555 __u8 reserved[4]; 556 }; 557 558 /* Firmware Port Capabilities types. */ 559 560 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 561 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 562 563 enum fw_caps { 564 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 565 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 566 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 567 }; 568 569 struct link_config { 570 fw_port_cap32_t pcaps; /* link capabilities */ 571 fw_port_cap32_t def_acaps; /* default advertised capabilities */ 572 fw_port_cap32_t acaps; /* advertised capabilities */ 573 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 574 575 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 576 unsigned int speed; /* actual link speed (Mb/s) */ 577 578 enum cc_pause requested_fc; /* flow control user has requested */ 579 enum cc_pause fc; /* actual link flow control */ 580 enum cc_pause advertised_fc; /* actual advertised flow control */ 581 582 enum cc_fec requested_fec; /* Forward Error Correction: */ 583 enum cc_fec fec; /* requested and actual in use */ 584 585 unsigned char autoneg; /* autonegotiating? */ 586 587 unsigned char link_ok; /* link up? */ 588 unsigned char link_down_rc; /* link down reason */ 589 590 bool new_module; /* ->OS Transceiver Module inserted */ 591 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 592 }; 593 594 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 595 596 enum { 597 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 598 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 599 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 600 }; 601 602 enum { 603 MAX_TXQ_ENTRIES = 16384, 604 MAX_CTRL_TXQ_ENTRIES = 1024, 605 MAX_RSPQ_ENTRIES = 16384, 606 MAX_RX_BUFFERS = 16384, 607 MIN_TXQ_ENTRIES = 32, 608 MIN_CTRL_TXQ_ENTRIES = 32, 609 MIN_RSPQ_ENTRIES = 128, 610 MIN_FL_ENTRIES = 16 611 }; 612 613 enum { 614 MAX_TXQ_DESC_SIZE = 64, 615 MAX_RXQ_DESC_SIZE = 128, 616 MAX_FL_DESC_SIZE = 8, 617 MAX_CTRL_TXQ_DESC_SIZE = 64, 618 }; 619 620 enum { 621 INGQ_EXTRAS = 2, /* firmware event queue and */ 622 /* forwarded interrupts */ 623 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 624 }; 625 626 enum { 627 PRIV_FLAG_PORT_TX_VM_BIT, 628 }; 629 630 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 631 632 #define PRIV_FLAGS_ADAP 0 633 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 634 635 struct adapter; 636 struct sge_rspq; 637 638 #include "cxgb4_dcb.h" 639 640 #ifdef CONFIG_CHELSIO_T4_FCOE 641 #include "cxgb4_fcoe.h" 642 #endif /* CONFIG_CHELSIO_T4_FCOE */ 643 644 struct port_info { 645 struct adapter *adapter; 646 u16 viid; 647 int xact_addr_filt; /* index of exact MAC address filter */ 648 u16 rss_size; /* size of VI's RSS table slice */ 649 s8 mdio_addr; 650 enum fw_port_type port_type; 651 u8 mod_type; 652 u8 port_id; 653 u8 tx_chan; 654 u8 lport; /* associated offload logical port */ 655 u8 nqsets; /* # of qsets */ 656 u8 first_qset; /* index of first qset */ 657 u8 rss_mode; 658 struct link_config link_cfg; 659 u16 *rss; 660 struct port_stats stats_base; 661 #ifdef CONFIG_CHELSIO_T4_DCB 662 struct port_dcb_info dcb; /* Data Center Bridging support */ 663 #endif 664 #ifdef CONFIG_CHELSIO_T4_FCOE 665 struct cxgb_fcoe fcoe; 666 #endif /* CONFIG_CHELSIO_T4_FCOE */ 667 bool rxtstamp; /* Enable TS */ 668 struct hwtstamp_config tstamp_config; 669 bool ptp_enable; 670 struct sched_table *sched_tbl; 671 u32 eth_flags; 672 673 /* viid and smt fields either returned by fw 674 * or decoded by parsing viid by driver. 675 */ 676 u8 vin; 677 u8 vivld; 678 u8 smt_idx; 679 u8 rx_cchan; 680 681 bool tc_block_shared; 682 }; 683 684 struct dentry; 685 struct work_struct; 686 687 enum { /* adapter flags */ 688 CXGB4_FULL_INIT_DONE = (1 << 0), 689 CXGB4_DEV_ENABLED = (1 << 1), 690 CXGB4_USING_MSI = (1 << 2), 691 CXGB4_USING_MSIX = (1 << 3), 692 CXGB4_FW_OK = (1 << 4), 693 CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 694 CXGB4_USING_SOFT_PARAMS = (1 << 6), 695 CXGB4_MASTER_PF = (1 << 7), 696 CXGB4_FW_OFLD_CONN = (1 << 9), 697 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 698 CXGB4_SHUTTING_DOWN = (1 << 11), 699 CXGB4_SGE_DBQ_TIMER = (1 << 12), 700 }; 701 702 enum { 703 ULP_CRYPTO_LOOKASIDE = 1 << 0, 704 ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 705 ULP_CRYPTO_KTLS_INLINE = 1 << 3, 706 }; 707 708 struct rx_sw_desc; 709 710 struct sge_fl { /* SGE free-buffer queue state */ 711 unsigned int avail; /* # of available Rx buffers */ 712 unsigned int pend_cred; /* new buffers since last FL DB ring */ 713 unsigned int cidx; /* consumer index */ 714 unsigned int pidx; /* producer index */ 715 unsigned long alloc_failed; /* # of times buffer allocation failed */ 716 unsigned long large_alloc_failed; 717 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 718 unsigned long low; /* # of times momentarily starving */ 719 unsigned long starving; 720 /* RO fields */ 721 unsigned int cntxt_id; /* SGE context id for the free list */ 722 unsigned int size; /* capacity of free list */ 723 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 724 __be64 *desc; /* address of HW Rx descriptor ring */ 725 dma_addr_t addr; /* bus address of HW ring start */ 726 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 727 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 728 }; 729 730 /* A packet gather list */ 731 struct pkt_gl { 732 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 733 struct page_frag frags[MAX_SKB_FRAGS]; 734 void *va; /* virtual address of first byte */ 735 unsigned int nfrags; /* # of fragments */ 736 unsigned int tot_len; /* total length of fragments */ 737 }; 738 739 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 740 const struct pkt_gl *gl); 741 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 742 /* LRO related declarations for ULD */ 743 struct t4_lro_mgr { 744 #define MAX_LRO_SESSIONS 64 745 u8 lro_session_cnt; /* # of sessions to aggregate */ 746 unsigned long lro_pkts; /* # of LRO super packets */ 747 unsigned long lro_merged; /* # of wire packets merged by LRO */ 748 struct sk_buff_head lroq; /* list of aggregated sessions */ 749 }; 750 751 struct sge_rspq { /* state for an SGE response queue */ 752 struct napi_struct napi; 753 const __be64 *cur_desc; /* current descriptor in queue */ 754 unsigned int cidx; /* consumer index */ 755 u8 gen; /* current generation bit */ 756 u8 intr_params; /* interrupt holdoff parameters */ 757 u8 next_intr_params; /* holdoff params for next interrupt */ 758 u8 adaptive_rx; 759 u8 pktcnt_idx; /* interrupt packet threshold */ 760 u8 uld; /* ULD handling this queue */ 761 u8 idx; /* queue index within its group */ 762 int offset; /* offset into current Rx buffer */ 763 u16 cntxt_id; /* SGE context id for the response q */ 764 u16 abs_id; /* absolute SGE id for the response q */ 765 __be64 *desc; /* address of HW response ring */ 766 dma_addr_t phys_addr; /* physical address of the ring */ 767 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 768 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 769 unsigned int iqe_len; /* entry size */ 770 unsigned int size; /* capacity of response queue */ 771 struct adapter *adap; 772 struct net_device *netdev; /* associated net device */ 773 rspq_handler_t handler; 774 rspq_flush_handler_t flush_handler; 775 struct t4_lro_mgr lro_mgr; 776 }; 777 778 struct sge_eth_stats { /* Ethernet queue statistics */ 779 unsigned long pkts; /* # of ethernet packets */ 780 unsigned long lro_pkts; /* # of LRO super packets */ 781 unsigned long lro_merged; /* # of wire packets merged by LRO */ 782 unsigned long rx_cso; /* # of Rx checksum offloads */ 783 unsigned long vlan_ex; /* # of Rx VLAN extractions */ 784 unsigned long rx_drops; /* # of packets dropped due to no mem */ 785 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 786 }; 787 788 struct sge_eth_rxq { /* SW Ethernet Rx queue */ 789 struct sge_rspq rspq; 790 struct sge_fl fl; 791 struct sge_eth_stats stats; 792 struct msix_info *msix; 793 } ____cacheline_aligned_in_smp; 794 795 struct sge_ofld_stats { /* offload queue statistics */ 796 unsigned long pkts; /* # of packets */ 797 unsigned long imm; /* # of immediate-data packets */ 798 unsigned long an; /* # of asynchronous notifications */ 799 unsigned long nomem; /* # of responses deferred due to no mem */ 800 }; 801 802 struct sge_ofld_rxq { /* SW offload Rx queue */ 803 struct sge_rspq rspq; 804 struct sge_fl fl; 805 struct sge_ofld_stats stats; 806 struct msix_info *msix; 807 } ____cacheline_aligned_in_smp; 808 809 struct tx_desc { 810 __be64 flit[8]; 811 }; 812 813 struct ulptx_sgl; 814 815 struct tx_sw_desc { 816 struct sk_buff *skb; /* SKB to free after getting completion */ 817 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 818 }; 819 820 struct sge_txq { 821 unsigned int in_use; /* # of in-use Tx descriptors */ 822 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 823 unsigned int size; /* # of descriptors */ 824 unsigned int cidx; /* SW consumer index */ 825 unsigned int pidx; /* producer index */ 826 unsigned long stops; /* # of times q has been stopped */ 827 unsigned long restarts; /* # of queue restarts */ 828 unsigned int cntxt_id; /* SGE context id for the Tx q */ 829 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 830 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 831 struct sge_qstat *stat; /* queue status entry */ 832 dma_addr_t phys_addr; /* physical address of the ring */ 833 spinlock_t db_lock; 834 int db_disabled; 835 unsigned short db_pidx; 836 unsigned short db_pidx_inc; 837 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 838 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 839 }; 840 841 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 842 struct sge_txq q; 843 struct netdev_queue *txq; /* associated netdev TX queue */ 844 #ifdef CONFIG_CHELSIO_T4_DCB 845 u8 dcb_prio; /* DCB Priority bound to queue */ 846 #endif 847 u8 dbqt; /* SGE Doorbell Queue Timer in use */ 848 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 849 unsigned long tso; /* # of TSO requests */ 850 unsigned long uso; /* # of USO requests */ 851 unsigned long tx_cso; /* # of Tx checksum offloads */ 852 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 853 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 854 } ____cacheline_aligned_in_smp; 855 856 struct sge_uld_txq { /* state for an SGE offload Tx queue */ 857 struct sge_txq q; 858 struct adapter *adap; 859 struct sk_buff_head sendq; /* list of backpressured packets */ 860 struct tasklet_struct qresume_tsk; /* restarts the queue */ 861 bool service_ofldq_running; /* service_ofldq() is processing sendq */ 862 u8 full; /* the Tx ring is full */ 863 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 864 } ____cacheline_aligned_in_smp; 865 866 struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 867 struct sge_txq q; 868 struct adapter *adap; 869 struct sk_buff_head sendq; /* list of backpressured packets */ 870 struct tasklet_struct qresume_tsk; /* restarts the queue */ 871 u8 full; /* the Tx ring is full */ 872 } ____cacheline_aligned_in_smp; 873 874 struct sge_uld_rxq_info { 875 char name[IFNAMSIZ]; /* name of ULD driver */ 876 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 877 u16 *rspq_id; /* response queue id's of rxq */ 878 u16 nrxq; /* # of ingress uld queues */ 879 u16 nciq; /* # of completion queues */ 880 u8 uld; /* uld type */ 881 }; 882 883 struct sge_uld_txq_info { 884 struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 885 atomic_t users; /* num users */ 886 u16 ntxq; /* # of egress uld queues */ 887 }; 888 889 /* struct to maintain ULD list to reallocate ULD resources on hotplug */ 890 struct cxgb4_uld_list { 891 struct cxgb4_uld_info uld_info; 892 struct list_head list_node; 893 enum cxgb4_uld uld_type; 894 }; 895 896 enum sge_eosw_state { 897 CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 898 CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 899 CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 900 CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 901 CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 902 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 903 }; 904 905 struct sge_eosw_txq { 906 spinlock_t lock; /* Per queue lock to synchronize completions */ 907 enum sge_eosw_state state; /* Current ETHOFLD State */ 908 struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ 909 u32 ndesc; /* Number of descriptors */ 910 u32 pidx; /* Current Producer Index */ 911 u32 last_pidx; /* Last successfully transmitted Producer Index */ 912 u32 cidx; /* Current Consumer Index */ 913 u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 914 u32 flowc_idx; /* Descriptor containing a FLOWC request */ 915 u32 inuse; /* Number of packets held in ring */ 916 917 u32 cred; /* Current available credits */ 918 u32 ncompl; /* # of completions posted */ 919 u32 last_compl; /* # of credits consumed since last completion req */ 920 921 u32 eotid; /* Index into EOTID table in software */ 922 u32 hwtid; /* Hardware EOTID index */ 923 924 u32 hwqid; /* Underlying hardware queue index */ 925 struct net_device *netdev; /* Pointer to netdevice */ 926 struct tasklet_struct qresume_tsk; /* Restarts the queue */ 927 struct completion completion; /* completion for FLOWC rendezvous */ 928 }; 929 930 struct sge_eohw_txq { 931 spinlock_t lock; /* Per queue lock */ 932 struct sge_txq q; /* HW Txq */ 933 struct adapter *adap; /* Backpointer to adapter */ 934 unsigned long tso; /* # of TSO requests */ 935 unsigned long uso; /* # of USO requests */ 936 unsigned long tx_cso; /* # of Tx checksum offloads */ 937 unsigned long vlan_ins; /* # of Tx VLAN insertions */ 938 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 939 }; 940 941 struct sge { 942 struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 943 struct sge_eth_txq ptptxq; 944 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 945 946 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 947 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 948 struct sge_uld_rxq_info **uld_rxq_info; 949 struct sge_uld_txq_info **uld_txq_info; 950 951 struct sge_rspq intrq ____cacheline_aligned_in_smp; 952 spinlock_t intrq_lock; 953 954 struct sge_eohw_txq *eohw_txq; 955 struct sge_ofld_rxq *eohw_rxq; 956 957 u16 max_ethqsets; /* # of available Ethernet queue sets */ 958 u16 ethqsets; /* # of active Ethernet queue sets */ 959 u16 ethtxq_rover; /* Tx queue to clean up next */ 960 u16 ofldqsets; /* # of active ofld queue sets */ 961 u16 nqs_per_uld; /* # of Rx queues per ULD */ 962 u16 eoqsets; /* # of ETHOFLD queues */ 963 964 u16 timer_val[SGE_NTIMERS]; 965 u8 counter_val[SGE_NCOUNTERS]; 966 u16 dbqtimer_tick; 967 u16 dbqtimer_val[SGE_NDBQTIMERS]; 968 u32 fl_pg_order; /* large page allocation size */ 969 u32 stat_len; /* length of status page at ring end */ 970 u32 pktshift; /* padding between CPL & packet data */ 971 u32 fl_align; /* response queue message alignment */ 972 u32 fl_starve_thres; /* Free List starvation threshold */ 973 974 struct sge_idma_monitor_state idma_monitor; 975 unsigned int egr_start; 976 unsigned int egr_sz; 977 unsigned int ingr_start; 978 unsigned int ingr_sz; 979 void **egr_map; /* qid->queue egress queue map */ 980 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 981 unsigned long *starving_fl; 982 unsigned long *txq_maperr; 983 unsigned long *blocked_fl; 984 struct timer_list rx_timer; /* refills starving FLs */ 985 struct timer_list tx_timer; /* checks Tx queues */ 986 987 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 988 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 989 }; 990 991 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 992 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 993 994 struct l2t_data; 995 996 #ifdef CONFIG_PCI_IOV 997 998 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 999 * Configuration initialization for T5 only has SR-IOV functionality enabled 1000 * on PF0-3 in order to simplify everything. 1001 */ 1002 #define NUM_OF_PF_WITH_SRIOV 4 1003 1004 #endif 1005 1006 struct doorbell_stats { 1007 u32 db_drop; 1008 u32 db_empty; 1009 u32 db_full; 1010 }; 1011 1012 struct hash_mac_addr { 1013 struct list_head list; 1014 u8 addr[ETH_ALEN]; 1015 unsigned int iface_mac; 1016 }; 1017 1018 struct msix_bmap { 1019 unsigned long *msix_bmap; 1020 unsigned int mapsize; 1021 spinlock_t lock; /* lock for acquiring bitmap */ 1022 }; 1023 1024 struct msix_info { 1025 unsigned short vec; 1026 char desc[IFNAMSIZ + 10]; 1027 unsigned int idx; 1028 cpumask_var_t aff_mask; 1029 }; 1030 1031 struct vf_info { 1032 unsigned char vf_mac_addr[ETH_ALEN]; 1033 unsigned int tx_rate; 1034 bool pf_set_mac; 1035 u16 vlan; 1036 int link_state; 1037 }; 1038 1039 enum { 1040 HMA_DMA_MAPPED_FLAG = 1 1041 }; 1042 1043 struct hma_data { 1044 unsigned char flags; 1045 struct sg_table *sgt; 1046 dma_addr_t *phy_addr; /* physical address of the page */ 1047 }; 1048 1049 struct mbox_list { 1050 struct list_head list; 1051 }; 1052 1053 #if IS_ENABLED(CONFIG_THERMAL) 1054 struct ch_thermal { 1055 struct thermal_zone_device *tzdev; 1056 int trip_temp; 1057 int trip_type; 1058 }; 1059 #endif 1060 1061 struct mps_entries_ref { 1062 struct list_head list; 1063 u8 addr[ETH_ALEN]; 1064 u8 mask[ETH_ALEN]; 1065 u16 idx; 1066 refcount_t refcnt; 1067 }; 1068 1069 struct cxgb4_ethtool_filter_info { 1070 u32 *loc_array; /* Array holding the actual TIDs set to filters */ 1071 unsigned long *bmap; /* Bitmap for managing filters in use */ 1072 u32 in_use; /* # of filters in use */ 1073 }; 1074 1075 struct cxgb4_ethtool_filter { 1076 u32 nentries; /* Adapter wide number of supported filters */ 1077 struct cxgb4_ethtool_filter_info *port; /* Per port entry */ 1078 }; 1079 1080 struct adapter { 1081 void __iomem *regs; 1082 void __iomem *bar2; 1083 u32 t4_bar0; 1084 struct pci_dev *pdev; 1085 struct device *pdev_dev; 1086 const char *name; 1087 unsigned int mbox; 1088 unsigned int pf; 1089 unsigned int flags; 1090 unsigned int adap_idx; 1091 enum chip_type chip; 1092 u32 eth_flags; 1093 1094 int msg_enable; 1095 __be16 vxlan_port; 1096 u8 vxlan_port_cnt; 1097 __be16 geneve_port; 1098 u8 geneve_port_cnt; 1099 1100 struct adapter_params params; 1101 struct cxgb4_virt_res vres; 1102 unsigned int swintr; 1103 1104 /* MSI-X Info for NIC and OFLD queues */ 1105 struct msix_info *msix_info; 1106 struct msix_bmap msix_bmap; 1107 1108 struct doorbell_stats db_stats; 1109 struct sge sge; 1110 1111 struct net_device *port[MAX_NPORTS]; 1112 u8 chan_map[NCHAN]; /* channel -> port map */ 1113 1114 struct vf_info *vfinfo; 1115 u8 num_vfs; 1116 1117 u32 filter_mode; 1118 unsigned int l2t_start; 1119 unsigned int l2t_end; 1120 struct l2t_data *l2t; 1121 unsigned int clipt_start; 1122 unsigned int clipt_end; 1123 struct clip_tbl *clipt; 1124 unsigned int rawf_start; 1125 unsigned int rawf_cnt; 1126 struct smt_data *smt; 1127 struct cxgb4_uld_info *uld; 1128 void *uld_handle[CXGB4_ULD_MAX]; 1129 unsigned int num_uld; 1130 unsigned int num_ofld_uld; 1131 struct list_head list_node; 1132 struct list_head rcu_node; 1133 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 1134 struct list_head mps_ref; 1135 spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1136 1137 void *iscsi_ppm; 1138 1139 struct tid_info tids; 1140 void **tid_release_head; 1141 spinlock_t tid_release_lock; 1142 struct workqueue_struct *workq; 1143 struct work_struct tid_release_task; 1144 struct work_struct db_full_task; 1145 struct work_struct db_drop_task; 1146 struct work_struct fatal_err_notify_task; 1147 bool tid_release_task_busy; 1148 1149 /* lock for mailbox cmd list */ 1150 spinlock_t mbox_lock; 1151 struct mbox_list mlist; 1152 1153 /* support for mailbox command/reply logging */ 1154 #define T4_OS_LOG_MBOX_CMDS 256 1155 struct mbox_cmd_log *mbox_log; 1156 1157 struct mutex uld_mutex; 1158 1159 struct dentry *debugfs_root; 1160 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1161 bool trace_rss; /* 1 implies that different RSS flit per filter is 1162 * used per filter else if 0 default RSS flit is 1163 * used for all 4 filters. 1164 */ 1165 1166 struct ptp_clock *ptp_clock; 1167 struct ptp_clock_info ptp_clock_info; 1168 struct sk_buff *ptp_tx_skb; 1169 /* ptp lock */ 1170 spinlock_t ptp_lock; 1171 spinlock_t stats_lock; 1172 spinlock_t win0_lock ____cacheline_aligned_in_smp; 1173 1174 /* TC u32 offload */ 1175 struct cxgb4_tc_u32_table *tc_u32; 1176 struct chcr_ktls chcr_ktls; 1177 struct chcr_stats_debug chcr_stats; 1178 1179 /* TC flower offload */ 1180 bool tc_flower_initialized; 1181 struct rhashtable flower_tbl; 1182 struct rhashtable_params flower_ht_params; 1183 struct timer_list flower_stats_timer; 1184 struct work_struct flower_stats_work; 1185 1186 /* Ethtool Dump */ 1187 struct ethtool_dump eth_dump; 1188 1189 /* HMA */ 1190 struct hma_data hma; 1191 1192 struct srq_data *srq; 1193 1194 /* Dump buffer for collecting logs in kdump kernel */ 1195 struct vmcoredd_data vmcoredd; 1196 #if IS_ENABLED(CONFIG_THERMAL) 1197 struct ch_thermal ch_thermal; 1198 #endif 1199 1200 /* TC MQPRIO offload */ 1201 struct cxgb4_tc_mqprio *tc_mqprio; 1202 1203 /* TC MATCHALL classifier offload */ 1204 struct cxgb4_tc_matchall *tc_matchall; 1205 1206 /* Ethtool n-tuple */ 1207 struct cxgb4_ethtool_filter *ethtool_filters; 1208 }; 1209 1210 /* Support for "sched-class" command to allow a TX Scheduling Class to be 1211 * programmed with various parameters. 1212 */ 1213 struct ch_sched_params { 1214 u8 type; /* packet or flow */ 1215 union { 1216 struct { 1217 u8 level; /* scheduler hierarchy level */ 1218 u8 mode; /* per-class or per-flow */ 1219 u8 rateunit; /* bit or packet rate */ 1220 u8 ratemode; /* %port relative or kbps absolute */ 1221 u8 channel; /* scheduler channel [0..N] */ 1222 u8 class; /* scheduler class [0..N] */ 1223 u32 minrate; /* minimum rate */ 1224 u32 maxrate; /* maximum rate */ 1225 u16 weight; /* percent weight */ 1226 u16 pktsize; /* average packet size */ 1227 u16 burstsize; /* burst buffer size */ 1228 } params; 1229 } u; 1230 }; 1231 1232 enum { 1233 SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 1234 }; 1235 1236 enum { 1237 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 1238 SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ 1239 }; 1240 1241 enum { 1242 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 1243 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 1244 }; 1245 1246 enum { 1247 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 1248 }; 1249 1250 enum { 1251 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 1252 }; 1253 1254 /* Support for "sched_queue" command to allow one or more NIC TX Queues 1255 * to be bound to a TX Scheduling Class. 1256 */ 1257 struct ch_sched_queue { 1258 s8 queue; /* queue index */ 1259 s8 class; /* class index */ 1260 }; 1261 1262 /* Support for "sched_flowc" command to allow one or more FLOWC 1263 * to be bound to a TX Scheduling Class. 1264 */ 1265 struct ch_sched_flowc { 1266 s32 tid; /* TID to bind */ 1267 s8 class; /* class index */ 1268 }; 1269 1270 /* Defined bit width of user definable filter tuples 1271 */ 1272 #define ETHTYPE_BITWIDTH 16 1273 #define FRAG_BITWIDTH 1 1274 #define MACIDX_BITWIDTH 9 1275 #define FCOE_BITWIDTH 1 1276 #define IPORT_BITWIDTH 3 1277 #define MATCHTYPE_BITWIDTH 3 1278 #define PROTO_BITWIDTH 8 1279 #define TOS_BITWIDTH 8 1280 #define PF_BITWIDTH 8 1281 #define VF_BITWIDTH 8 1282 #define IVLAN_BITWIDTH 16 1283 #define OVLAN_BITWIDTH 16 1284 #define ENCAP_VNI_BITWIDTH 24 1285 1286 /* Filter matching rules. These consist of a set of ingress packet field 1287 * (value, mask) tuples. The associated ingress packet field matches the 1288 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1289 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1290 * matches an ingress packet when all of the individual individual field 1291 * matching rules are true. 1292 * 1293 * Partial field masks are always valid, however, while it may be easy to 1294 * understand their meanings for some fields (e.g. IP address to match a 1295 * subnet), for others making sensible partial masks is less intuitive (e.g. 1296 * MPS match type) ... 1297 * 1298 * Most of the following data structures are modeled on T4 capabilities. 1299 * Drivers for earlier chips use the subsets which make sense for those chips. 1300 * We really need to come up with a hardware-independent mechanism to 1301 * represent hardware filter capabilities ... 1302 */ 1303 struct ch_filter_tuple { 1304 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1305 * register selects which of these fields will participate in the 1306 * filter match rules -- up to a maximum of 36 bits. Because 1307 * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1308 * set of fields. 1309 */ 1310 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1311 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1312 uint32_t ivlan_vld:1; /* inner VLAN valid */ 1313 uint32_t ovlan_vld:1; /* outer VLAN valid */ 1314 uint32_t pfvf_vld:1; /* PF/VF valid */ 1315 uint32_t encap_vld:1; /* Encapsulation valid */ 1316 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1317 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1318 uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1319 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1320 uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1321 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1322 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1323 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1324 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1325 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1326 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1327 1328 /* Uncompressed header matching field rules. These are always 1329 * available for field rules. 1330 */ 1331 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1332 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1333 uint16_t lport; /* local port */ 1334 uint16_t fport; /* foreign port */ 1335 }; 1336 1337 /* A filter ioctl command. 1338 */ 1339 struct ch_filter_specification { 1340 /* Administrative fields for filter. 1341 */ 1342 uint32_t hitcnts:1; /* count filter hits in TCB */ 1343 uint32_t prio:1; /* filter has priority over active/server */ 1344 1345 /* Fundamental filter typing. This is the one element of filter 1346 * matching that doesn't exist as a (value, mask) tuple. 1347 */ 1348 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1349 u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1350 1351 /* Packet dispatch information. Ingress packets which match the 1352 * filter rules will be dropped, passed to the host or switched back 1353 * out as egress packets. 1354 */ 1355 uint32_t action:2; /* drop, pass, switch */ 1356 1357 uint32_t rpttid:1; /* report TID in RSS hash field */ 1358 1359 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1360 uint32_t iq:10; /* ingress queue */ 1361 1362 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1363 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1364 /* 1 => TCB contains IQ ID */ 1365 1366 /* Switch proxy/rewrite fields. An ingress packet which matches a 1367 * filter with "switch" set will be looped back out as an egress 1368 * packet -- potentially with some Ethernet header rewriting. 1369 */ 1370 uint32_t eport:2; /* egress port to switch packet out */ 1371 uint32_t newdmac:1; /* rewrite destination MAC address */ 1372 uint32_t newsmac:1; /* rewrite source MAC address */ 1373 uint32_t newvlan:2; /* rewrite VLAN Tag */ 1374 uint32_t nat_mode:3; /* specify NAT operation mode */ 1375 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1376 uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1377 uint16_t vlan; /* VLAN Tag to insert */ 1378 1379 u8 nat_lip[16]; /* local IP to use after NAT'ing */ 1380 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 1381 u16 nat_lport; /* local port to use after NAT'ing */ 1382 u16 nat_fport; /* foreign port to use after NAT'ing */ 1383 1384 u32 tc_prio; /* TC's filter priority index */ 1385 u64 tc_cookie; /* Unique cookie identifying TC rules */ 1386 1387 /* reservation for future additions */ 1388 u8 rsvd[12]; 1389 1390 /* Filter rule value/mask pairs. 1391 */ 1392 struct ch_filter_tuple val; 1393 struct ch_filter_tuple mask; 1394 }; 1395 1396 enum { 1397 FILTER_PASS = 0, /* default */ 1398 FILTER_DROP, 1399 FILTER_SWITCH 1400 }; 1401 1402 enum { 1403 VLAN_NOCHANGE = 0, /* default */ 1404 VLAN_REMOVE, 1405 VLAN_INSERT, 1406 VLAN_REWRITE 1407 }; 1408 1409 enum { 1410 NAT_MODE_NONE = 0, /* No NAT performed */ 1411 NAT_MODE_DIP, /* NAT on Dst IP */ 1412 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 1413 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 1414 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 1415 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 1416 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 1417 NAT_MODE_ALL /* NAT on entire 4-tuple */ 1418 }; 1419 1420 /* Host shadow copy of ingress filter entry. This is in host native format 1421 * and doesn't match the ordering or bit order, etc. of the hardware of the 1422 * firmware command. The use of bit-field structure elements is purely to 1423 * remind ourselves of the field size limitations and save memory in the case 1424 * where the filter table is large. 1425 */ 1426 struct filter_entry { 1427 /* Administrative fields for filter. */ 1428 u32 valid:1; /* filter allocated and valid */ 1429 u32 locked:1; /* filter is administratively locked */ 1430 1431 u32 pending:1; /* filter action is pending firmware reply */ 1432 struct filter_ctx *ctx; /* Caller's completion hook */ 1433 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1434 struct smt_entry *smt; /* Source Mac Table entry for smac */ 1435 struct net_device *dev; /* Associated net device */ 1436 u32 tid; /* This will store the actual tid */ 1437 1438 /* The filter itself. Most of this is a straight copy of information 1439 * provided by the extended ioctl(). Some fields are translated to 1440 * internal forms -- for instance the Ingress Queue ID passed in from 1441 * the ioctl() is translated into the Absolute Ingress Queue ID. 1442 */ 1443 struct ch_filter_specification fs; 1444 }; 1445 1446 static inline int is_offload(const struct adapter *adap) 1447 { 1448 return adap->params.offload; 1449 } 1450 1451 static inline int is_hashfilter(const struct adapter *adap) 1452 { 1453 return adap->params.hash_filter; 1454 } 1455 1456 static inline int is_pci_uld(const struct adapter *adap) 1457 { 1458 return adap->params.crypto; 1459 } 1460 1461 static inline int is_uld(const struct adapter *adap) 1462 { 1463 return (adap->params.offload || adap->params.crypto); 1464 } 1465 1466 static inline int is_ethofld(const struct adapter *adap) 1467 { 1468 return adap->params.ethofld; 1469 } 1470 1471 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1472 { 1473 return readl(adap->regs + reg_addr); 1474 } 1475 1476 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1477 { 1478 writel(val, adap->regs + reg_addr); 1479 } 1480 1481 #ifndef readq 1482 static inline u64 readq(const volatile void __iomem *addr) 1483 { 1484 return readl(addr) + ((u64)readl(addr + 4) << 32); 1485 } 1486 1487 static inline void writeq(u64 val, volatile void __iomem *addr) 1488 { 1489 writel(val, addr); 1490 writel(val >> 32, addr + 4); 1491 } 1492 #endif 1493 1494 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1495 { 1496 return readq(adap->regs + reg_addr); 1497 } 1498 1499 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1500 { 1501 writeq(val, adap->regs + reg_addr); 1502 } 1503 1504 /** 1505 * t4_set_hw_addr - store a port's MAC address in SW 1506 * @adapter: the adapter 1507 * @port_idx: the port index 1508 * @hw_addr: the Ethernet address 1509 * 1510 * Store the Ethernet address of the given port in SW. Called by the common 1511 * code when it retrieves a port's Ethernet address from EEPROM. 1512 */ 1513 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1514 u8 hw_addr[]) 1515 { 1516 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1517 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1518 } 1519 1520 /** 1521 * netdev2pinfo - return the port_info structure associated with a net_device 1522 * @dev: the netdev 1523 * 1524 * Return the struct port_info associated with a net_device 1525 */ 1526 static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1527 { 1528 return netdev_priv(dev); 1529 } 1530 1531 /** 1532 * adap2pinfo - return the port_info of a port 1533 * @adap: the adapter 1534 * @idx: the port index 1535 * 1536 * Return the port_info structure for the port of the given index. 1537 */ 1538 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1539 { 1540 return netdev_priv(adap->port[idx]); 1541 } 1542 1543 /** 1544 * netdev2adap - return the adapter structure associated with a net_device 1545 * @dev: the netdev 1546 * 1547 * Return the struct adapter associated with a net_device 1548 */ 1549 static inline struct adapter *netdev2adap(const struct net_device *dev) 1550 { 1551 return netdev2pinfo(dev)->adapter; 1552 } 1553 1554 /* Return a version number to identify the type of adapter. The scheme is: 1555 * - bits 0..9: chip version 1556 * - bits 10..15: chip revision 1557 * - bits 16..23: register dump version 1558 */ 1559 static inline unsigned int mk_adap_vers(struct adapter *ap) 1560 { 1561 return CHELSIO_CHIP_VERSION(ap->params.chip) | 1562 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1563 } 1564 1565 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1566 static inline unsigned int qtimer_val(const struct adapter *adap, 1567 const struct sge_rspq *q) 1568 { 1569 unsigned int idx = q->intr_params >> 1; 1570 1571 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1572 } 1573 1574 /* driver name used for ethtool_drvinfo */ 1575 extern char cxgb4_driver_name[]; 1576 1577 void t4_os_portmod_changed(struct adapter *adap, int port_id); 1578 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1579 1580 void t4_free_sge_resources(struct adapter *adap); 1581 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1582 irq_handler_t t4_intr_handler(struct adapter *adap); 1583 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1584 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1585 const struct pkt_gl *gl); 1586 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1587 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1588 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1589 struct net_device *dev, int intr_idx, 1590 struct sge_fl *fl, rspq_handler_t hnd, 1591 rspq_flush_handler_t flush_handler, int cong); 1592 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1593 struct net_device *dev, struct netdev_queue *netdevq, 1594 unsigned int iqid, u8 dbqt); 1595 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1596 struct net_device *dev, unsigned int iqid, 1597 unsigned int cmplqid); 1598 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 1599 unsigned int cmplqid); 1600 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1601 struct net_device *dev, unsigned int iqid, 1602 unsigned int uld_type); 1603 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 1604 struct net_device *dev, u32 iqid); 1605 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1606 irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 1607 int t4_sge_init(struct adapter *adap); 1608 void t4_sge_start(struct adapter *adap); 1609 void t4_sge_stop(struct adapter *adap); 1610 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1611 int maxreclaim); 1612 void cxgb4_set_ethtool_ops(struct net_device *netdev); 1613 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1614 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 1615 extern int dbfifo_int_thresh; 1616 1617 #define for_each_port(adapter, iter) \ 1618 for (iter = 0; iter < (adapter)->params.nports; ++iter) 1619 1620 static inline int is_bypass(struct adapter *adap) 1621 { 1622 return adap->params.bypass; 1623 } 1624 1625 static inline int is_bypass_device(int device) 1626 { 1627 /* this should be set based upon device capabilities */ 1628 switch (device) { 1629 case 0x440b: 1630 case 0x440c: 1631 return 1; 1632 default: 1633 return 0; 1634 } 1635 } 1636 1637 static inline int is_10gbt_device(int device) 1638 { 1639 /* this should be set based upon device capabilities */ 1640 switch (device) { 1641 case 0x4409: 1642 case 0x4486: 1643 return 1; 1644 1645 default: 1646 return 0; 1647 } 1648 } 1649 1650 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1651 { 1652 return adap->params.vpd.cclk / 1000; 1653 } 1654 1655 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1656 unsigned int us) 1657 { 1658 return (us * adap->params.vpd.cclk) / 1000; 1659 } 1660 1661 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 1662 unsigned int ticks) 1663 { 1664 /* add Core Clock / 2 to round ticks to nearest uS */ 1665 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 1666 adapter->params.vpd.cclk); 1667 } 1668 1669 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 1670 unsigned int ticks) 1671 { 1672 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 1673 } 1674 1675 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1676 u32 val); 1677 1678 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 1679 int size, void *rpl, bool sleep_ok, int timeout); 1680 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1681 void *rpl, bool sleep_ok); 1682 1683 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 1684 const void *cmd, int size, void *rpl, 1685 int timeout) 1686 { 1687 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 1688 timeout); 1689 } 1690 1691 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1692 int size, void *rpl) 1693 { 1694 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1695 } 1696 1697 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1698 int size, void *rpl) 1699 { 1700 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1701 } 1702 1703 /** 1704 * hash_mac_addr - return the hash value of a MAC address 1705 * @addr: the 48-bit Ethernet MAC address 1706 * 1707 * Hashes a MAC address according to the hash function used by HW inexact 1708 * (hash) address matching. 1709 */ 1710 static inline int hash_mac_addr(const u8 *addr) 1711 { 1712 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1713 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1714 1715 a ^= b; 1716 a ^= (a >> 12); 1717 a ^= (a >> 6); 1718 return a & 0x3f; 1719 } 1720 1721 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1722 unsigned int cnt); 1723 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 1724 unsigned int us, unsigned int cnt, 1725 unsigned int size, unsigned int iqe_size) 1726 { 1727 q->adap = adap; 1728 cxgb4_set_rspq_intr_params(q, us, cnt); 1729 q->iqe_len = iqe_size; 1730 q->size = size; 1731 } 1732 1733 /** 1734 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1735 * @fw_mod_type: the Firmware Mofule Type 1736 * 1737 * Return whether the Firmware Module Type represents a real Transceiver 1738 * Module/Cable Module Type which has been inserted. 1739 */ 1740 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1741 { 1742 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1743 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1744 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1745 fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1746 } 1747 1748 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 1749 unsigned int data_reg, const u32 *vals, 1750 unsigned int nregs, unsigned int start_idx); 1751 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1752 unsigned int data_reg, u32 *vals, unsigned int nregs, 1753 unsigned int start_idx); 1754 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1755 1756 struct fw_filter_wr; 1757 1758 void t4_intr_enable(struct adapter *adapter); 1759 void t4_intr_disable(struct adapter *adapter); 1760 int t4_slow_intr_handler(struct adapter *adapter); 1761 1762 int t4_wait_dev_ready(void __iomem *regs); 1763 1764 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 1765 struct link_config *lc); 1766 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 1767 unsigned int port, struct link_config *lc, 1768 u8 sleep_ok, int timeout); 1769 1770 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 1771 unsigned int port, struct link_config *lc) 1772 { 1773 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1774 true, FW_CMD_MAX_TIMEOUT); 1775 } 1776 1777 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 1778 unsigned int port, struct link_config *lc) 1779 { 1780 return t4_link_l1cfg_core(adapter, mbox, port, lc, 1781 false, FW_CMD_MAX_TIMEOUT); 1782 } 1783 1784 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1785 1786 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1787 u32 t4_get_util_window(struct adapter *adap); 1788 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1789 1790 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 1791 u32 *mem_base, u32 *mem_aperture); 1792 void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 1793 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 1794 int dir); 1795 #define T4_MEMORY_WRITE 0 1796 #define T4_MEMORY_READ 1 1797 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1798 void *buf, int dir); 1799 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1800 u32 len, __be32 *buf) 1801 { 1802 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1803 } 1804 1805 unsigned int t4_get_regs_len(struct adapter *adapter); 1806 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1807 1808 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1809 int t4_seeprom_wp(struct adapter *adapter, bool enable); 1810 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1811 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 1812 int t4_get_pfres(struct adapter *adapter); 1813 int t4_read_flash(struct adapter *adapter, unsigned int addr, 1814 unsigned int nwords, u32 *data, int byte_oriented); 1815 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 1816 int t4_load_phy_fw(struct adapter *adap, int win, 1817 int (*phy_fw_version)(const u8 *, size_t), 1818 const u8 *phy_fw_data, size_t phy_fw_size); 1819 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 1820 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 1821 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 1822 const u8 *fw_data, unsigned int size, int force); 1823 int t4_fl_pkt_align(struct adapter *adap); 1824 unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1825 int t4_check_fw_version(struct adapter *adap); 1826 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 1827 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 1828 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 1829 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1830 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1831 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1832 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1833 int t4_get_version_info(struct adapter *adapter); 1834 void t4_dump_version_info(struct adapter *adapter); 1835 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 1836 const u8 *fw_data, unsigned int fw_size, 1837 struct fw_hdr *card_fw, enum dev_state state, int *reset); 1838 int t4_prep_adapter(struct adapter *adapter); 1839 int t4_shutdown_adapter(struct adapter *adapter); 1840 1841 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1842 int t4_bar2_sge_qregs(struct adapter *adapter, 1843 unsigned int qid, 1844 enum t4_bar2_qtype qtype, 1845 int user, 1846 u64 *pbar2_qoffset, 1847 unsigned int *pbar2_qid); 1848 1849 unsigned int qtimer_val(const struct adapter *adap, 1850 const struct sge_rspq *q); 1851 1852 int t4_init_devlog_params(struct adapter *adapter); 1853 int t4_init_sge_params(struct adapter *adapter); 1854 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1855 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1856 int t4_init_rss_mode(struct adapter *adap, int mbox); 1857 int t4_init_portinfo(struct port_info *pi, int mbox, 1858 int port, int pf, int vf, u8 mac[]); 1859 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1860 void t4_fatal_err(struct adapter *adapter); 1861 unsigned int t4_chip_rss_size(struct adapter *adapter); 1862 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1863 int start, int n, const u16 *rspq, unsigned int nrspq); 1864 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1865 unsigned int flags); 1866 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1867 unsigned int flags, unsigned int defq); 1868 int t4_read_rss(struct adapter *adapter, u16 *entries); 1869 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 1870 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 1871 bool sleep_ok); 1872 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1873 u32 *valp, bool sleep_ok); 1874 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1875 u32 *vfl, u32 *vfh, bool sleep_ok); 1876 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 1877 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1878 1879 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1880 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1881 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1882 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1883 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1884 size_t n); 1885 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1886 size_t n); 1887 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1888 unsigned int *valp); 1889 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1890 const unsigned int *valp); 1891 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 1892 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1893 unsigned int *pif_req_wrptr, 1894 unsigned int *pif_rsp_wrptr); 1895 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 1896 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 1897 const char *t4_get_port_type_description(enum fw_port_type port_type); 1898 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1899 void t4_get_port_stats_offset(struct adapter *adap, int idx, 1900 struct port_stats *stats, 1901 struct port_stats *offset); 1902 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1903 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1904 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1905 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1906 unsigned int mask, unsigned int val); 1907 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1908 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 1909 bool sleep_ok); 1910 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 1911 bool sleep_ok); 1912 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 1913 bool sleep_ok); 1914 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 1915 bool sleep_ok); 1916 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1917 struct tp_tcp_stats *v6, bool sleep_ok); 1918 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1919 struct tp_fcoe_stats *st, bool sleep_ok); 1920 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1921 const unsigned short *alpha, const unsigned short *beta); 1922 1923 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1924 1925 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1926 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1927 1928 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1929 const u8 *addr); 1930 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1931 u64 mask0, u64 mask1, unsigned int crc, bool enable); 1932 1933 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1934 enum dev_master master, enum dev_state *state); 1935 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1936 int t4_early_init(struct adapter *adap, unsigned int mbox); 1937 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1938 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1939 unsigned int cache_line_size); 1940 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1941 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1942 unsigned int vf, unsigned int nparams, const u32 *params, 1943 u32 *val); 1944 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 1945 unsigned int vf, unsigned int nparams, const u32 *params, 1946 u32 *val); 1947 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1948 unsigned int vf, unsigned int nparams, const u32 *params, 1949 u32 *val, int rw, bool sleep_ok); 1950 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1951 unsigned int pf, unsigned int vf, 1952 unsigned int nparams, const u32 *params, 1953 const u32 *val, int timeout); 1954 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1955 unsigned int vf, unsigned int nparams, const u32 *params, 1956 const u32 *val); 1957 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1958 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1959 unsigned int rxqi, unsigned int rxq, unsigned int tc, 1960 unsigned int vi, unsigned int cmask, unsigned int pmask, 1961 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1962 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1963 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1964 unsigned int *rss_size, u8 *vivld, u8 *vin); 1965 int t4_free_vi(struct adapter *adap, unsigned int mbox, 1966 unsigned int pf, unsigned int vf, 1967 unsigned int viid); 1968 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1969 int mtu, int promisc, int all_multi, int bcast, int vlanex, 1970 bool sleep_ok); 1971 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1972 const u8 *addr, const u8 *mask, unsigned int idx, 1973 u8 lookup_type, u8 port_id, bool sleep_ok); 1974 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 1975 bool sleep_ok); 1976 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 1977 const u8 *addr, const u8 *mask, unsigned int vni, 1978 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 1979 bool sleep_ok); 1980 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1981 const u8 *addr, const u8 *mask, unsigned int idx, 1982 u8 lookup_type, u8 port_id, bool sleep_ok); 1983 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1984 unsigned int viid, bool free, unsigned int naddr, 1985 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1986 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1987 unsigned int viid, unsigned int naddr, 1988 const u8 **addr, bool sleep_ok); 1989 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1990 int idx, const u8 *addr, bool persist, u8 *smt_idx); 1991 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1992 bool ucast, u64 vec, bool sleep_ok); 1993 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1994 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1995 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1996 struct port_info *pi, 1997 bool rx_en, bool tx_en, bool dcb_en); 1998 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1999 bool rx_en, bool tx_en); 2000 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 2001 unsigned int nblinks); 2002 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 2003 unsigned int mmd, unsigned int reg, u16 *valp); 2004 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 2005 unsigned int mmd, unsigned int reg, u16 val); 2006 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 2007 unsigned int vf, unsigned int iqtype, unsigned int iqid, 2008 unsigned int fl0id, unsigned int fl1id); 2009 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2010 unsigned int vf, unsigned int iqtype, unsigned int iqid, 2011 unsigned int fl0id, unsigned int fl1id); 2012 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2013 unsigned int vf, unsigned int eqid); 2014 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2015 unsigned int vf, unsigned int eqid); 2016 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2017 unsigned int vf, unsigned int eqid); 2018 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 2019 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 2020 u16 *dbqtimers); 2021 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 2022 int t4_update_port_info(struct port_info *pi); 2023 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 2024 unsigned int *speedp, unsigned int *mtup); 2025 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 2026 void t4_db_full(struct adapter *adapter); 2027 void t4_db_dropped(struct adapter *adapter); 2028 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 2029 int filter_index, int enable); 2030 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 2031 int filter_index, int *enabled); 2032 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 2033 u32 addr, u32 val); 2034 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 2035 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 2036 unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 2037 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 2038 enum ctxt_type ctype, u32 *data); 2039 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 2040 enum ctxt_type ctype, u32 *data); 2041 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode, 2042 u8 rateunit, u8 ratemode, u8 channel, u8 class, 2043 u32 minrate, u32 maxrate, u16 weight, u16 pktsize, 2044 u16 burstsize); 2045 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 2046 void t4_idma_monitor_init(struct adapter *adapter, 2047 struct sge_idma_monitor_state *idma); 2048 void t4_idma_monitor(struct adapter *adapter, 2049 struct sge_idma_monitor_state *idma, 2050 int hz, int ticks); 2051 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 2052 unsigned int naddr, u8 *addr); 2053 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 2054 u32 start_index, bool sleep_ok); 2055 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 2056 u32 start_index, bool sleep_ok); 2057 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 2058 u32 start_index, bool sleep_ok); 2059 2060 void t4_uld_mem_free(struct adapter *adap); 2061 int t4_uld_mem_alloc(struct adapter *adap); 2062 void t4_uld_clean_up(struct adapter *adap); 2063 void t4_register_netevent_notifier(void); 2064 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 2065 unsigned int devid, unsigned int offset, 2066 unsigned int len, u8 *buf); 2067 int t4_load_boot(struct adapter *adap, u8 *boot_data, 2068 unsigned int boot_addr, unsigned int size); 2069 int t4_load_bootcfg(struct adapter *adap, 2070 const u8 *cfg_data, unsigned int size); 2071 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 2072 void free_tx_desc(struct adapter *adap, struct sge_txq *q, 2073 unsigned int n, bool unmap); 2074 void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 2075 u32 ndesc); 2076 int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 2077 void cxgb4_ethofld_restart(unsigned long data); 2078 int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 2079 const struct pkt_gl *si); 2080 void free_txq(struct adapter *adap, struct sge_txq *q); 2081 void cxgb4_reclaim_completed_tx(struct adapter *adap, 2082 struct sge_txq *q, bool unmap); 2083 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 2084 dma_addr_t *addr); 2085 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 2086 void *pos); 2087 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 2088 struct ulptx_sgl *sgl, u64 *end, unsigned int start, 2089 const dma_addr_t *addr); 2090 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 2091 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 2092 u16 vlan); 2093 int cxgb4_dcb_enabled(const struct net_device *dev); 2094 2095 int cxgb4_thermal_init(struct adapter *adap); 2096 int cxgb4_thermal_remove(struct adapter *adap); 2097 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 2098 cpumask_var_t *aff_mask, int idx); 2099 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 2100 2101 int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 2102 int *tcam_idx, const u8 *addr, 2103 bool persistent, u8 *smt_idx); 2104 2105 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 2106 bool free, unsigned int naddr, 2107 const u8 **addr, u16 *idx, 2108 u64 *hash, bool sleep_ok); 2109 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2110 unsigned int naddr, const u8 **addr, bool sleep_ok); 2111 int cxgb4_init_mps_ref_entries(struct adapter *adap); 2112 void cxgb4_free_mps_ref_entries(struct adapter *adap); 2113 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 2114 const u8 *addr, const u8 *mask, 2115 unsigned int vni, unsigned int vni_mask, 2116 u8 dip_hit, u8 lookup_type, bool sleep_ok); 2117 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 2118 int idx, bool sleep_ok); 2119 int cxgb4_free_raw_mac_filt(struct adapter *adap, 2120 unsigned int viid, 2121 const u8 *addr, 2122 const u8 *mask, 2123 unsigned int idx, 2124 u8 lookup_type, 2125 u8 port_id, 2126 bool sleep_ok); 2127 int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 2128 unsigned int viid, 2129 const u8 *addr, 2130 const u8 *mask, 2131 unsigned int idx, 2132 u8 lookup_type, 2133 u8 port_id, 2134 bool sleep_ok); 2135 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 2136 int *tcam_idx, const u8 *addr, 2137 bool persistent, u8 *smt_idx); 2138 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 2139 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2140 int cxgb_open(struct net_device *dev); 2141 int cxgb_close(struct net_device *dev); 2142 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 2143 void cxgb4_quiesce_rx(struct sge_rspq *q); 2144 #ifdef CONFIG_CHELSIO_TLS_DEVICE 2145 int cxgb4_set_ktls_feature(struct adapter *adap, bool enable); 2146 #endif 2147 #endif /* __CXGB4_H__ */ 2148