1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 490eb71a9dSNeilBrown #include <linux/rhashtable.h> 50098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 515e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 52a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 53a4569504SAtul Gupta #include <linux/ptp_classify.h> 541dde532dSRahul Lakkireddy #include <linux/crash_dump.h> 55b1871915SGanesh Goudar #include <linux/thermal.h> 56f7917c00SJeff Kirsher #include <asm/io.h> 5727999805SHariprasad S #include "t4_chip_type.h" 58f7917c00SJeff Kirsher #include "cxgb4_uld.h" 59c2193999SShahjada Abul Husain #include "t4fw_api.h" 60f7917c00SJeff Kirsher 613069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 6294cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 6393a09e74SPotnuri Bharat Teja extern struct list_head uld_list; 6494cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 653069ee9bSVipul Pandya 66a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 67a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 68a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 69a6ec572bSAtul Gupta */ 70a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 71a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 72a6ec572bSAtul Gupta 73c2193999SShahjada Abul Husain #define FW_PARAM_DEV(param) \ 74c2193999SShahjada Abul Husain (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 75c2193999SShahjada Abul Husain FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 76c2193999SShahjada Abul Husain 77c2193999SShahjada Abul Husain #define FW_PARAM_PFVF(param) \ 78c2193999SShahjada Abul Husain (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 79c2193999SShahjada Abul Husain FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 80c2193999SShahjada Abul Husain FW_PARAMS_PARAM_Y_V(0) | \ 81c2193999SShahjada Abul Husain FW_PARAMS_PARAM_Z_V(0)) 82c2193999SShahjada Abul Husain 83f7917c00SJeff Kirsher enum { 84f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 85f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 86f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 87f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 88a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 89098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 90f7917c00SJeff Kirsher }; 91f7917c00SJeff Kirsher 92f7917c00SJeff Kirsher enum { 93812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 94812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 95812034f1SHariprasad Shenai }; 96812034f1SHariprasad Shenai 97812034f1SHariprasad Shenai enum { 98f7917c00SJeff Kirsher MEM_EDC0, 99f7917c00SJeff Kirsher MEM_EDC1, 1002422d9a3SSantosh Rastapur MEM_MC, 1012422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 1024db0401fSRahul Lakkireddy MEM_MC1, 1034db0401fSRahul Lakkireddy MEM_HMA, 104f7917c00SJeff Kirsher }; 105f7917c00SJeff Kirsher 1063069ee9bSVipul Pandya enum { 1073eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 1083eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 1093069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 1103069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 1112422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 1123eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 1133eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 1140abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 1150abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1163069ee9bSVipul Pandya }; 1173069ee9bSVipul Pandya 118f7917c00SJeff Kirsher enum dev_master { 119f7917c00SJeff Kirsher MASTER_CANT, 120f7917c00SJeff Kirsher MASTER_MAY, 121f7917c00SJeff Kirsher MASTER_MUST 122f7917c00SJeff Kirsher }; 123f7917c00SJeff Kirsher 124f7917c00SJeff Kirsher enum dev_state { 125f7917c00SJeff Kirsher DEV_STATE_UNINIT, 126f7917c00SJeff Kirsher DEV_STATE_INIT, 127f7917c00SJeff Kirsher DEV_STATE_ERR 128f7917c00SJeff Kirsher }; 129f7917c00SJeff Kirsher 130c3168cabSGanesh Goudar enum cc_pause { 131f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 132f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 133f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 134f7917c00SJeff Kirsher }; 135f7917c00SJeff Kirsher 136c3168cabSGanesh Goudar enum cc_fec { 1373bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1383bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1393bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1403bb4858fSGanesh Goudar }; 1413bb4858fSGanesh Goudar 1423893c905SVishal Kulkarni enum { 1433893c905SVishal Kulkarni CXGB4_ETHTOOL_FLASH_FW = 1, 1444ee339e1SVishal Kulkarni CXGB4_ETHTOOL_FLASH_PHY = 2, 14555088355SVishal Kulkarni CXGB4_ETHTOOL_FLASH_BOOT = 3, 146d5002c9aSVishal Kulkarni CXGB4_ETHTOOL_FLASH_BOOTCFG = 4 147d5002c9aSVishal Kulkarni }; 148d5002c9aSVishal Kulkarni 149d5002c9aSVishal Kulkarni struct cxgb4_bootcfg_data { 150d5002c9aSVishal Kulkarni __le16 signature; 151d5002c9aSVishal Kulkarni __u8 reserved[2]; 15255088355SVishal Kulkarni }; 15355088355SVishal Kulkarni 15455088355SVishal Kulkarni struct cxgb4_pcir_data { 15555088355SVishal Kulkarni __le32 signature; /* Signature. The string "PCIR" */ 15655088355SVishal Kulkarni __le16 vendor_id; /* Vendor Identification */ 15755088355SVishal Kulkarni __le16 device_id; /* Device Identification */ 15855088355SVishal Kulkarni __u8 vital_product[2]; /* Pointer to Vital Product Data */ 15955088355SVishal Kulkarni __u8 length[2]; /* PCIR Data Structure Length */ 16055088355SVishal Kulkarni __u8 revision; /* PCIR Data Structure Revision */ 16155088355SVishal Kulkarni __u8 class_code[3]; /* Class Code */ 16255088355SVishal Kulkarni __u8 image_length[2]; /* Image Length. Multiple of 512B */ 16355088355SVishal Kulkarni __u8 code_revision[2]; /* Revision Level of Code/Data */ 16455088355SVishal Kulkarni __u8 code_type; 16555088355SVishal Kulkarni __u8 indicator; 16655088355SVishal Kulkarni __u8 reserved[2]; 16755088355SVishal Kulkarni }; 16855088355SVishal Kulkarni 16955088355SVishal Kulkarni /* BIOS boot headers */ 17055088355SVishal Kulkarni struct cxgb4_pci_exp_rom_header { 17155088355SVishal Kulkarni __le16 signature; /* ROM Signature. Should be 0xaa55 */ 17255088355SVishal Kulkarni __u8 reserved[22]; /* Reserved per processor Architecture data */ 17355088355SVishal Kulkarni __le16 pcir_offset; /* Offset to PCI Data Structure */ 17455088355SVishal Kulkarni }; 17555088355SVishal Kulkarni 17655088355SVishal Kulkarni /* Legacy PCI Expansion ROM Header */ 17755088355SVishal Kulkarni struct legacy_pci_rom_hdr { 17855088355SVishal Kulkarni __u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 17955088355SVishal Kulkarni __u8 size512; /* Current Image Size in units of 512 bytes */ 18055088355SVishal Kulkarni __u8 initentry_point[4]; 18155088355SVishal Kulkarni __u8 cksum; /* Checksum computed on the entire Image */ 18255088355SVishal Kulkarni __u8 reserved[16]; /* Reserved */ 18355088355SVishal Kulkarni __le16 pcir_offset; /* Offset to PCI Data Struture */ 18455088355SVishal Kulkarni }; 18555088355SVishal Kulkarni 18655088355SVishal Kulkarni #define CXGB4_HDR_CODE1 0x00 18755088355SVishal Kulkarni #define CXGB4_HDR_CODE2 0x03 18855088355SVishal Kulkarni #define CXGB4_HDR_INDI 0x80 18955088355SVishal Kulkarni 19055088355SVishal Kulkarni /* BOOT constants */ 19155088355SVishal Kulkarni enum { 192d5002c9aSVishal Kulkarni BOOT_CFG_SIG = 0x4243, 19355088355SVishal Kulkarni BOOT_SIZE_INC = 512, 19455088355SVishal Kulkarni BOOT_SIGNATURE = 0xaa55, 19555088355SVishal Kulkarni BOOT_MIN_SIZE = sizeof(struct cxgb4_pci_exp_rom_header), 19655088355SVishal Kulkarni BOOT_MAX_SIZE = 1024 * BOOT_SIZE_INC, 19755088355SVishal Kulkarni PCIR_SIGNATURE = 0x52494350 1983893c905SVishal Kulkarni }; 1993893c905SVishal Kulkarni 200f7917c00SJeff Kirsher struct port_stats { 201f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 202f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 203f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 204f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 205f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 206f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 207f7917c00SJeff Kirsher 208f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 209f7917c00SJeff Kirsher u64 tx_frames_65_127; 210f7917c00SJeff Kirsher u64 tx_frames_128_255; 211f7917c00SJeff Kirsher u64 tx_frames_256_511; 212f7917c00SJeff Kirsher u64 tx_frames_512_1023; 213f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 214f7917c00SJeff Kirsher u64 tx_frames_1519_max; 215f7917c00SJeff Kirsher 216f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 217f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 218f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 219f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 220f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 221f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 222f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 223f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 224f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 225f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 226f7917c00SJeff Kirsher 227f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 228f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 229f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 230f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 231f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 232f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 233f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 234f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 235f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 236f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 237f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 238f7917c00SJeff Kirsher 239f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 240f7917c00SJeff Kirsher u64 rx_frames_65_127; 241f7917c00SJeff Kirsher u64 rx_frames_128_255; 242f7917c00SJeff Kirsher u64 rx_frames_256_511; 243f7917c00SJeff Kirsher u64 rx_frames_512_1023; 244f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 245f7917c00SJeff Kirsher u64 rx_frames_1519_max; 246f7917c00SJeff Kirsher 247f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 248f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 249f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 250f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 251f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 252f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 253f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 254f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 255f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 256f7917c00SJeff Kirsher 257f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 258f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 259f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 260f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 261f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 262f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 263f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 264f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 265f7917c00SJeff Kirsher }; 266f7917c00SJeff Kirsher 267f7917c00SJeff Kirsher struct lb_port_stats { 268f7917c00SJeff Kirsher u64 octets; 269f7917c00SJeff Kirsher u64 frames; 270f7917c00SJeff Kirsher u64 bcast_frames; 271f7917c00SJeff Kirsher u64 mcast_frames; 272f7917c00SJeff Kirsher u64 ucast_frames; 273f7917c00SJeff Kirsher u64 error_frames; 274f7917c00SJeff Kirsher 275f7917c00SJeff Kirsher u64 frames_64; 276f7917c00SJeff Kirsher u64 frames_65_127; 277f7917c00SJeff Kirsher u64 frames_128_255; 278f7917c00SJeff Kirsher u64 frames_256_511; 279f7917c00SJeff Kirsher u64 frames_512_1023; 280f7917c00SJeff Kirsher u64 frames_1024_1518; 281f7917c00SJeff Kirsher u64 frames_1519_max; 282f7917c00SJeff Kirsher 283f7917c00SJeff Kirsher u64 drop; 284f7917c00SJeff Kirsher 285f7917c00SJeff Kirsher u64 ovflow0; 286f7917c00SJeff Kirsher u64 ovflow1; 287f7917c00SJeff Kirsher u64 ovflow2; 288f7917c00SJeff Kirsher u64 ovflow3; 289f7917c00SJeff Kirsher u64 trunc0; 290f7917c00SJeff Kirsher u64 trunc1; 291f7917c00SJeff Kirsher u64 trunc2; 292f7917c00SJeff Kirsher u64 trunc3; 293f7917c00SJeff Kirsher }; 294f7917c00SJeff Kirsher 295f7917c00SJeff Kirsher struct tp_tcp_stats { 296a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 297a4cfd929SHariprasad Shenai u64 tcp_in_segs; 298a4cfd929SHariprasad Shenai u64 tcp_out_segs; 299a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 300a4cfd929SHariprasad Shenai }; 301a4cfd929SHariprasad Shenai 302a4cfd929SHariprasad Shenai struct tp_usm_stats { 303a4cfd929SHariprasad Shenai u32 frames; 304a4cfd929SHariprasad Shenai u32 drops; 305a4cfd929SHariprasad Shenai u64 octets; 306f7917c00SJeff Kirsher }; 307f7917c00SJeff Kirsher 308a6222975SHariprasad Shenai struct tp_fcoe_stats { 309a6222975SHariprasad Shenai u32 frames_ddp; 310a6222975SHariprasad Shenai u32 frames_drop; 311a6222975SHariprasad Shenai u64 octets_ddp; 312f7917c00SJeff Kirsher }; 313f7917c00SJeff Kirsher 314f7917c00SJeff Kirsher struct tp_err_stats { 315a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 316a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 317a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 318a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 319a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 320a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 321a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 322a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 323a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 324a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 325a4cfd929SHariprasad Shenai }; 326a4cfd929SHariprasad Shenai 327a6222975SHariprasad Shenai struct tp_cpl_stats { 328a6222975SHariprasad Shenai u32 req[4]; 329a6222975SHariprasad Shenai u32 rsp[4]; 330a6222975SHariprasad Shenai }; 331a6222975SHariprasad Shenai 332a4cfd929SHariprasad Shenai struct tp_rdma_stats { 333a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 334a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 335f7917c00SJeff Kirsher }; 336f7917c00SJeff Kirsher 337e85c9a7aSHariprasad Shenai struct sge_params { 338e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 339e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 340e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 341e85c9a7aSHariprasad Shenai }; 342e85c9a7aSHariprasad Shenai 343f7917c00SJeff Kirsher struct tp_params { 344f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 3452d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 346dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 347dca4faebSVipul Pandya /* channel map */ 348636f9d37SVipul Pandya 349636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 350636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 351dcf7b6f5SKumar Sanghvi 352dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 353dcf10ec7SRaju Rangoju u32 filter_mask; 354dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 355dcf7b6f5SKumar Sanghvi 3568eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 3578eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 3588eb9f2f9SArjun V */ 3598eb9f2f9SArjun V int rx_pkt_encap; 3608eb9f2f9SArjun V 361dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 362dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 363dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 364dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 365dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 366dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 367dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 368dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 369dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 370dcf7b6f5SKumar Sanghvi * present. 371dcf7b6f5SKumar Sanghvi */ 3720ba9a3b6SKumar Sanghvi int fcoe_shift; 373dcf7b6f5SKumar Sanghvi int port_shift; 3740ba9a3b6SKumar Sanghvi int vnic_shift; 3750ba9a3b6SKumar Sanghvi int vlan_shift; 3760ba9a3b6SKumar Sanghvi int tos_shift; 377dcf7b6f5SKumar Sanghvi int protocol_shift; 3780ba9a3b6SKumar Sanghvi int ethertype_shift; 3790ba9a3b6SKumar Sanghvi int macmatch_shift; 3800ba9a3b6SKumar Sanghvi int matchtype_shift; 3810ba9a3b6SKumar Sanghvi int frag_shift; 3820ba9a3b6SKumar Sanghvi 3830ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 384f7917c00SJeff Kirsher }; 385f7917c00SJeff Kirsher 386f7917c00SJeff Kirsher struct vpd_params { 387f7917c00SJeff Kirsher unsigned int cclk; 388f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 389f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 390f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 391a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 392098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 393f7917c00SJeff Kirsher }; 394f7917c00SJeff Kirsher 3950eaec62aSCasey Leedom /* Maximum resources provisioned for a PCI PF. 3960eaec62aSCasey Leedom */ 3970eaec62aSCasey Leedom struct pf_resources { 3980eaec62aSCasey Leedom unsigned int nvi; /* N virtual interfaces */ 3990eaec62aSCasey Leedom unsigned int neq; /* N egress Qs */ 4000eaec62aSCasey Leedom unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 4010eaec62aSCasey Leedom unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 4020eaec62aSCasey Leedom unsigned int niq; /* N ingress Qs */ 4030eaec62aSCasey Leedom unsigned int tc; /* PCI-E traffic class */ 4040eaec62aSCasey Leedom unsigned int pmask; /* port access rights mask */ 4050eaec62aSCasey Leedom unsigned int nexactf; /* N exact MPS filters */ 4060eaec62aSCasey Leedom unsigned int r_caps; /* read capabilities */ 4070eaec62aSCasey Leedom unsigned int wx_caps; /* write/execute capabilities */ 4080eaec62aSCasey Leedom }; 4090eaec62aSCasey Leedom 410f7917c00SJeff Kirsher struct pci_params { 411baf50868SGanesh Goudar unsigned int vpd_cap_addr; 412f7917c00SJeff Kirsher unsigned char speed; 413f7917c00SJeff Kirsher unsigned char width; 414f7917c00SJeff Kirsher }; 415f7917c00SJeff Kirsher 41649aa284fSHariprasad Shenai struct devlog_params { 41749aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 41849aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 41949aa284fSHariprasad Shenai u32 size; /* size of log */ 42049aa284fSHariprasad Shenai }; 42149aa284fSHariprasad Shenai 4223ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 4233ccc6cf7SHariprasad Shenai struct arch_specific_params { 4243ccc6cf7SHariprasad Shenai u8 nchan; 42544588560SHariprasad Shenai u8 pm_stats_cnt; 4262216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 4273ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 4283ccc6cf7SHariprasad Shenai u16 vfcount; 4293ccc6cf7SHariprasad Shenai u32 sge_fl_db; 4303ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 4313ccc6cf7SHariprasad Shenai }; 4323ccc6cf7SHariprasad Shenai 433f7917c00SJeff Kirsher struct adapter_params { 434e85c9a7aSHariprasad Shenai struct sge_params sge; 435f7917c00SJeff Kirsher struct tp_params tp; 436f7917c00SJeff Kirsher struct vpd_params vpd; 4370eaec62aSCasey Leedom struct pf_resources pfres; 438f7917c00SJeff Kirsher struct pci_params pci; 43949aa284fSHariprasad Shenai struct devlog_params devlog; 44049aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 441f7917c00SJeff Kirsher 442f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 443f1ff24aaSHariprasad Shenai 444f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 445f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 446f7917c00SJeff Kirsher 447760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 4480de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 449760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 4500de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 451760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 452760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 453f7917c00SJeff Kirsher u8 api_vers[7]; 454f7917c00SJeff Kirsher 455f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 456f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 457f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 458f7917c00SJeff Kirsher 459f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 460f7917c00SJeff Kirsher unsigned char portvec; 461d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 4623ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 463f7917c00SJeff Kirsher unsigned char offload; 46494cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 465ab0367eaSRahul Lakkireddy unsigned char ethofld; /* QoS support */ 466f7917c00SJeff Kirsher 4679a4da2cdSVipul Pandya unsigned char bypass; 4685c31254eSKumar Sanghvi unsigned char hash_filter; 4699a4da2cdSVipul Pandya 470f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 4711ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 4724c2c5763SHariprasad Shenai 473b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 4744c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 4754c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 476086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 477c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 4780ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 47902d805dcSSantosh Rastapur unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 4808f46d467SArjun Vynipadath 4818f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 4828f46d467SArjun Vynipadath * used by the Port 4838f46d467SArjun Vynipadath */ 4848f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 48543db9296SRaju Rangoju bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 486f3910c62SRaju Rangoju bool write_cmpl_support; /* FW supports WRITE_CMPL */ 487f7917c00SJeff Kirsher }; 488f7917c00SJeff Kirsher 489a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 490a3bfb617SHariprasad Shenai * and possible hangs. 491a3bfb617SHariprasad Shenai */ 492a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 493a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 494a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 495a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 496a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 497a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 498a3bfb617SHariprasad Shenai }; 499a3bfb617SHariprasad Shenai 5007f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 5017f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 5027f080c3fSHariprasad Shenai * error returns. 5037f080c3fSHariprasad Shenai */ 5047f080c3fSHariprasad Shenai struct mbox_cmd { 5057f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 5067f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 5077f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 5087f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 5097f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 5107f080c3fSHariprasad Shenai }; 5117f080c3fSHariprasad Shenai 5127f080c3fSHariprasad Shenai struct mbox_cmd_log { 5137f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 5147f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 5157f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 5167f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 5177f080c3fSHariprasad Shenai }; 5187f080c3fSHariprasad Shenai 5197f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 5207f080c3fSHariprasad Shenai * return a pointer to the specified entry. 5217f080c3fSHariprasad Shenai */ 5227f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 5237f080c3fSHariprasad Shenai unsigned int entry_idx) 5247f080c3fSHariprasad Shenai { 5257f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 5267f080c3fSHariprasad Shenai } 5277f080c3fSHariprasad Shenai 52816e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 529b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 530b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 531b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 532b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 53316e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 53416e47624SHariprasad Shenai 53516e47624SHariprasad Shenai struct fw_info { 53616e47624SHariprasad Shenai u8 chip; 53716e47624SHariprasad Shenai char *fs_name; 53816e47624SHariprasad Shenai char *fw_mod_name; 53916e47624SHariprasad Shenai struct fw_hdr fw_hdr; 54016e47624SHariprasad Shenai }; 54116e47624SHariprasad Shenai 542f7917c00SJeff Kirsher struct trace_params { 543f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 544f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 545f7917c00SJeff Kirsher unsigned short snap_len; 546f7917c00SJeff Kirsher unsigned short min_len; 547f7917c00SJeff Kirsher unsigned char skip_ofst; 548f7917c00SJeff Kirsher unsigned char skip_len; 549f7917c00SJeff Kirsher unsigned char invert; 550f7917c00SJeff Kirsher unsigned char port; 551f7917c00SJeff Kirsher }; 552f7917c00SJeff Kirsher 5533893c905SVishal Kulkarni struct cxgb4_fw_data { 5543893c905SVishal Kulkarni __be32 signature; 5553893c905SVishal Kulkarni __u8 reserved[4]; 5563893c905SVishal Kulkarni }; 5573893c905SVishal Kulkarni 558c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 559c3168cabSGanesh Goudar 560c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 561c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 562c3168cabSGanesh Goudar 563c3168cabSGanesh Goudar enum fw_caps { 564c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 565c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 566c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 567c3168cabSGanesh Goudar }; 568c3168cabSGanesh Goudar 569f7917c00SJeff Kirsher struct link_config { 570c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 571c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 572c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 573c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 574c3168cabSGanesh Goudar 575c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 576c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 577c3168cabSGanesh Goudar 578c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 579c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 5800caeaf6aSRahul Lakkireddy enum cc_pause advertised_fc; /* actual advertised flow control */ 581c3168cabSGanesh Goudar 582c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 583c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 584c3168cabSGanesh Goudar 585f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 586c3168cabSGanesh Goudar 587f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 588ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 5898156b0baSGanesh Goudar 5908156b0baSGanesh Goudar bool new_module; /* ->OS Transceiver Module inserted */ 5918156b0baSGanesh Goudar bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 592f7917c00SJeff Kirsher }; 593f7917c00SJeff Kirsher 594e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 595f7917c00SJeff Kirsher 596f7917c00SJeff Kirsher enum { 597f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 598f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 599f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 600f7917c00SJeff Kirsher }; 601f7917c00SJeff Kirsher 602f7917c00SJeff Kirsher enum { 603812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 604812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 605812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 606812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 607812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 608812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 609812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 610812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 611812034f1SHariprasad Shenai }; 612812034f1SHariprasad Shenai 613812034f1SHariprasad Shenai enum { 61468ddc82aSRahul Lakkireddy MAX_TXQ_DESC_SIZE = 64, 61568ddc82aSRahul Lakkireddy MAX_RXQ_DESC_SIZE = 128, 61668ddc82aSRahul Lakkireddy MAX_FL_DESC_SIZE = 8, 61768ddc82aSRahul Lakkireddy MAX_CTRL_TXQ_DESC_SIZE = 64, 61868ddc82aSRahul Lakkireddy }; 61968ddc82aSRahul Lakkireddy 62068ddc82aSRahul Lakkireddy enum { 621cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 622cf38be6dSHariprasad Shenai /* forwarded interrupts */ 6230fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 624f7917c00SJeff Kirsher }; 625f7917c00SJeff Kirsher 626d5fbda61SArjun Vynipadath enum { 627d5fbda61SArjun Vynipadath PRIV_FLAG_PORT_TX_VM_BIT, 628d5fbda61SArjun Vynipadath }; 629d5fbda61SArjun Vynipadath 630d5fbda61SArjun Vynipadath #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 631d5fbda61SArjun Vynipadath 632d5fbda61SArjun Vynipadath #define PRIV_FLAGS_ADAP 0 633d5fbda61SArjun Vynipadath #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 634d5fbda61SArjun Vynipadath 635f7917c00SJeff Kirsher struct adapter; 636f7917c00SJeff Kirsher struct sge_rspq; 637f7917c00SJeff Kirsher 638688848b1SAnish Bhatt #include "cxgb4_dcb.h" 639688848b1SAnish Bhatt 64076fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 64176fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 64276fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 64376fed8a9SVarun Prakash 644f7917c00SJeff Kirsher struct port_info { 645f7917c00SJeff Kirsher struct adapter *adapter; 646f7917c00SJeff Kirsher u16 viid; 6473f8cfd0dSArjun Vynipadath int xact_addr_filt; /* index of exact MAC address filter */ 648f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 649f7917c00SJeff Kirsher s8 mdio_addr; 65040e9de4bSHariprasad Shenai enum fw_port_type port_type; 651f7917c00SJeff Kirsher u8 mod_type; 652f7917c00SJeff Kirsher u8 port_id; 653f7917c00SJeff Kirsher u8 tx_chan; 654f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 655f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 656f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 657f7917c00SJeff Kirsher u8 rss_mode; 658f7917c00SJeff Kirsher struct link_config link_cfg; 659f7917c00SJeff Kirsher u16 *rss; 660a4cfd929SHariprasad Shenai struct port_stats stats_base; 661688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 662688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 663688848b1SAnish Bhatt #endif 66476fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 66576fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 66676fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 6675e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 6685e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 669a4569504SAtul Gupta bool ptp_enable; 670b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 671d5fbda61SArjun Vynipadath u32 eth_flags; 67202d805dcSSantosh Rastapur 67302d805dcSSantosh Rastapur /* viid and smt fields either returned by fw 67402d805dcSSantosh Rastapur * or decoded by parsing viid by driver. 67502d805dcSSantosh Rastapur */ 67602d805dcSSantosh Rastapur u8 vin; 67702d805dcSSantosh Rastapur u8 vivld; 67802d805dcSSantosh Rastapur u8 smt_idx; 67974dd5aa1SVishal Kulkarni u8 rx_cchan; 6804ec4762dSRahul Lakkireddy 6814ec4762dSRahul Lakkireddy bool tc_block_shared; 682f7917c00SJeff Kirsher }; 683f7917c00SJeff Kirsher 684f7917c00SJeff Kirsher struct dentry; 685f7917c00SJeff Kirsher struct work_struct; 686f7917c00SJeff Kirsher 687f7917c00SJeff Kirsher enum { /* adapter flags */ 68880f61f19SArjun Vynipadath CXGB4_FULL_INIT_DONE = (1 << 0), 68980f61f19SArjun Vynipadath CXGB4_DEV_ENABLED = (1 << 1), 69080f61f19SArjun Vynipadath CXGB4_USING_MSI = (1 << 2), 69180f61f19SArjun Vynipadath CXGB4_USING_MSIX = (1 << 3), 69280f61f19SArjun Vynipadath CXGB4_FW_OK = (1 << 4), 69380f61f19SArjun Vynipadath CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 69480f61f19SArjun Vynipadath CXGB4_USING_SOFT_PARAMS = (1 << 6), 69580f61f19SArjun Vynipadath CXGB4_MASTER_PF = (1 << 7), 69680f61f19SArjun Vynipadath CXGB4_FW_OFLD_CONN = (1 << 9), 69780f61f19SArjun Vynipadath CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 69880f61f19SArjun Vynipadath CXGB4_SHUTTING_DOWN = (1 << 11), 69980f61f19SArjun Vynipadath CXGB4_SGE_DBQ_TIMER = (1 << 12), 700f7917c00SJeff Kirsher }; 701f7917c00SJeff Kirsher 70294cdb8bbSHariprasad Shenai enum { 70394cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 704a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 70534aba2c4SRohit Maheshwari ULP_CRYPTO_KTLS_INLINE = 1 << 3, 70694cdb8bbSHariprasad Shenai }; 70794cdb8bbSHariprasad Shenai 708f7917c00SJeff Kirsher struct rx_sw_desc; 709f7917c00SJeff Kirsher 710f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 711f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 712f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 713f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 714f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 715f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 716f7917c00SJeff Kirsher unsigned long large_alloc_failed; 71770055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 71870055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 719f7917c00SJeff Kirsher unsigned long starving; 720f7917c00SJeff Kirsher /* RO fields */ 721f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 722f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 723f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 724f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 725f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 726df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 727df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 728f7917c00SJeff Kirsher }; 729f7917c00SJeff Kirsher 730f7917c00SJeff Kirsher /* A packet gather list */ 731f7917c00SJeff Kirsher struct pkt_gl { 7325e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 733e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 734f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 735f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 736f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 737f7917c00SJeff Kirsher }; 738f7917c00SJeff Kirsher 739f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 740f7917c00SJeff Kirsher const struct pkt_gl *gl); 7412337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 7422337ba42SVarun Prakash /* LRO related declarations for ULD */ 7432337ba42SVarun Prakash struct t4_lro_mgr { 7442337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 7452337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 7462337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 7472337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 7482337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 7492337ba42SVarun Prakash }; 750f7917c00SJeff Kirsher 751f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 752f7917c00SJeff Kirsher struct napi_struct napi; 753f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 754f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 755f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 756f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 757f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 758e553ec3fSHariprasad Shenai u8 adaptive_rx; 759f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 760f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 761f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 762f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 763f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 764f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 765f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 766f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 767df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 768df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 769f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 770f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 771f7917c00SJeff Kirsher struct adapter *adap; 772f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 773f7917c00SJeff Kirsher rspq_handler_t handler; 7742337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 7752337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 776f7917c00SJeff Kirsher }; 777f7917c00SJeff Kirsher 778f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 779f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 780f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 781f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 782f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 783f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 784f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 785992bea8eSGanesh Goudar unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 786f7917c00SJeff Kirsher }; 787f7917c00SJeff Kirsher 788f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 789f7917c00SJeff Kirsher struct sge_rspq rspq; 790f7917c00SJeff Kirsher struct sge_fl fl; 791f7917c00SJeff Kirsher struct sge_eth_stats stats; 79276c3a552SRahul Lakkireddy struct msix_info *msix; 793f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 794f7917c00SJeff Kirsher 795f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 796f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 797f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 798f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 799f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 800f7917c00SJeff Kirsher }; 801f7917c00SJeff Kirsher 802f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 803f7917c00SJeff Kirsher struct sge_rspq rspq; 804f7917c00SJeff Kirsher struct sge_fl fl; 805f7917c00SJeff Kirsher struct sge_ofld_stats stats; 80676c3a552SRahul Lakkireddy struct msix_info *msix; 807f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 808f7917c00SJeff Kirsher 809f7917c00SJeff Kirsher struct tx_desc { 810f7917c00SJeff Kirsher __be64 flit[8]; 811f7917c00SJeff Kirsher }; 812f7917c00SJeff Kirsher 8130ed96b46SRahul Lakkireddy struct ulptx_sgl; 8140ed96b46SRahul Lakkireddy 8150ed96b46SRahul Lakkireddy struct tx_sw_desc { 8160ed96b46SRahul Lakkireddy struct sk_buff *skb; /* SKB to free after getting completion */ 8170ed96b46SRahul Lakkireddy dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 8180ed96b46SRahul Lakkireddy }; 819f7917c00SJeff Kirsher 820f7917c00SJeff Kirsher struct sge_txq { 821f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 822ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 823f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 824f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 825f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 826f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 827f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 828f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 829f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 830f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 831f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 832f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 8333069ee9bSVipul Pandya spinlock_t db_lock; 8343069ee9bSVipul Pandya int db_disabled; 8353069ee9bSVipul Pandya unsigned short db_pidx; 83605eb2389SSteve Wise unsigned short db_pidx_inc; 837df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 838df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 839f7917c00SJeff Kirsher }; 840f7917c00SJeff Kirsher 841f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 842f7917c00SJeff Kirsher struct sge_txq q; 843f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 84410b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 84510b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 84610b00466SAnish Bhatt #endif 847d429005fSVishal Kulkarni u8 dbqt; /* SGE Doorbell Queue Timer in use */ 848d429005fSVishal Kulkarni unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 849f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 8501a2a14fbSRahul Lakkireddy unsigned long uso; /* # of USO requests */ 851f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 852f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 853f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 854f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 855f7917c00SJeff Kirsher 856ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 857f7917c00SJeff Kirsher struct sge_txq q; 858f7917c00SJeff Kirsher struct adapter *adap; 859f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 860f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 861126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 862f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 863f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 864f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 865f7917c00SJeff Kirsher 866f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 867f7917c00SJeff Kirsher struct sge_txq q; 868f7917c00SJeff Kirsher struct adapter *adap; 869f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 870f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 871f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 872f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 873f7917c00SJeff Kirsher 87494cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 87594cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 87694cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 87794cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 87894cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 87994cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 88094cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 88194cdb8bbSHariprasad Shenai }; 88294cdb8bbSHariprasad Shenai 883ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 884ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 885ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 886ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 887ab677ff4SHariprasad Shenai }; 888ab677ff4SHariprasad Shenai 88993a09e74SPotnuri Bharat Teja /* struct to maintain ULD list to reallocate ULD resources on hotplug */ 89093a09e74SPotnuri Bharat Teja struct cxgb4_uld_list { 89193a09e74SPotnuri Bharat Teja struct cxgb4_uld_info uld_info; 89293a09e74SPotnuri Bharat Teja struct list_head list_node; 89393a09e74SPotnuri Bharat Teja enum cxgb4_uld uld_type; 89493a09e74SPotnuri Bharat Teja }; 89593a09e74SPotnuri Bharat Teja 896b1396c2bSRahul Lakkireddy enum sge_eosw_state { 897b1396c2bSRahul Lakkireddy CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 8980e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 8990e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 9004846d533SRahul Lakkireddy CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 9010e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 9020e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 903b1396c2bSRahul Lakkireddy }; 904b1396c2bSRahul Lakkireddy 905b1396c2bSRahul Lakkireddy struct sge_eosw_txq { 906b1396c2bSRahul Lakkireddy spinlock_t lock; /* Per queue lock to synchronize completions */ 907b1396c2bSRahul Lakkireddy enum sge_eosw_state state; /* Current ETHOFLD State */ 9080ed96b46SRahul Lakkireddy struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ 909b1396c2bSRahul Lakkireddy u32 ndesc; /* Number of descriptors */ 910b1396c2bSRahul Lakkireddy u32 pidx; /* Current Producer Index */ 911b1396c2bSRahul Lakkireddy u32 last_pidx; /* Last successfully transmitted Producer Index */ 912b1396c2bSRahul Lakkireddy u32 cidx; /* Current Consumer Index */ 913b1396c2bSRahul Lakkireddy u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 9140e395b3cSRahul Lakkireddy u32 flowc_idx; /* Descriptor containing a FLOWC request */ 915b1396c2bSRahul Lakkireddy u32 inuse; /* Number of packets held in ring */ 916b1396c2bSRahul Lakkireddy 917b1396c2bSRahul Lakkireddy u32 cred; /* Current available credits */ 918b1396c2bSRahul Lakkireddy u32 ncompl; /* # of completions posted */ 919b1396c2bSRahul Lakkireddy u32 last_compl; /* # of credits consumed since last completion req */ 920b1396c2bSRahul Lakkireddy 921b1396c2bSRahul Lakkireddy u32 eotid; /* Index into EOTID table in software */ 922b1396c2bSRahul Lakkireddy u32 hwtid; /* Hardware EOTID index */ 923b1396c2bSRahul Lakkireddy 924b1396c2bSRahul Lakkireddy u32 hwqid; /* Underlying hardware queue index */ 925b1396c2bSRahul Lakkireddy struct net_device *netdev; /* Pointer to netdevice */ 926b1396c2bSRahul Lakkireddy struct tasklet_struct qresume_tsk; /* Restarts the queue */ 9270e395b3cSRahul Lakkireddy struct completion completion; /* completion for FLOWC rendezvous */ 928b1396c2bSRahul Lakkireddy }; 929b1396c2bSRahul Lakkireddy 9302d0cb84dSRahul Lakkireddy struct sge_eohw_txq { 9312d0cb84dSRahul Lakkireddy spinlock_t lock; /* Per queue lock */ 9322d0cb84dSRahul Lakkireddy struct sge_txq q; /* HW Txq */ 9332d0cb84dSRahul Lakkireddy struct adapter *adap; /* Backpointer to adapter */ 9342d0cb84dSRahul Lakkireddy unsigned long tso; /* # of TSO requests */ 9358311f0beSRahul Lakkireddy unsigned long uso; /* # of USO requests */ 9362d0cb84dSRahul Lakkireddy unsigned long tx_cso; /* # of Tx checksum offloads */ 9372d0cb84dSRahul Lakkireddy unsigned long vlan_ins; /* # of Tx VLAN insertions */ 9382d0cb84dSRahul Lakkireddy unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 9392d0cb84dSRahul Lakkireddy }; 9402d0cb84dSRahul Lakkireddy 941f7917c00SJeff Kirsher struct sge { 942f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 943a4569504SAtul Gupta struct sge_eth_txq ptptxq; 944f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 945f7917c00SJeff Kirsher 946f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 947f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 94894cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 949ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 950f7917c00SJeff Kirsher 951f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 952f7917c00SJeff Kirsher spinlock_t intrq_lock; 953f7917c00SJeff Kirsher 9542d0cb84dSRahul Lakkireddy struct sge_eohw_txq *eohw_txq; 9552d0cb84dSRahul Lakkireddy struct sge_ofld_rxq *eohw_rxq; 9562d0cb84dSRahul Lakkireddy 957f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 958f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 959f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 9600fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 96194cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 9622d0cb84dSRahul Lakkireddy u16 eoqsets; /* # of ETHOFLD queues */ 9632d0cb84dSRahul Lakkireddy 964f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 965f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 966543a1b85SVishal Kulkarni u16 dbqtimer_tick; 967d429005fSVishal Kulkarni u16 dbqtimer_val[SGE_NDBQTIMERS]; 96852367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 96952367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 97052367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 97152367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 97252367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 9730f4d201fSKumar Sanghvi 974a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 975f7917c00SJeff Kirsher unsigned int egr_start; 9764b8e27a8SHariprasad Shenai unsigned int egr_sz; 977f7917c00SJeff Kirsher unsigned int ingr_start; 9784b8e27a8SHariprasad Shenai unsigned int ingr_sz; 9794b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 9804b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 9814b8e27a8SHariprasad Shenai unsigned long *starving_fl; 9824b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 9835b377d11SHariprasad Shenai unsigned long *blocked_fl; 984f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 985f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 98676c3a552SRahul Lakkireddy 98776c3a552SRahul Lakkireddy int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 98876c3a552SRahul Lakkireddy int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 989f7917c00SJeff Kirsher }; 990f7917c00SJeff Kirsher 991f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 9920fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 993f7917c00SJeff Kirsher 994f7917c00SJeff Kirsher struct l2t_data; 995f7917c00SJeff Kirsher 9962422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 9972422d9a3SSantosh Rastapur 9987d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 9997d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 10007d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 10012422d9a3SSantosh Rastapur */ 10027d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 10032422d9a3SSantosh Rastapur 10042422d9a3SSantosh Rastapur #endif 10052422d9a3SSantosh Rastapur 1006a4cfd929SHariprasad Shenai struct doorbell_stats { 1007a4cfd929SHariprasad Shenai u32 db_drop; 1008a4cfd929SHariprasad Shenai u32 db_empty; 1009a4cfd929SHariprasad Shenai u32 db_full; 1010a4cfd929SHariprasad Shenai }; 1011a4cfd929SHariprasad Shenai 1012fc08a01aSHariprasad Shenai struct hash_mac_addr { 1013fc08a01aSHariprasad Shenai struct list_head list; 1014fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 10153f8cfd0dSArjun Vynipadath unsigned int iface_mac; 1016fc08a01aSHariprasad Shenai }; 1017fc08a01aSHariprasad Shenai 101876c3a552SRahul Lakkireddy struct msix_bmap { 101994cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 102094cdb8bbSHariprasad Shenai unsigned int mapsize; 102194cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 102294cdb8bbSHariprasad Shenai }; 102394cdb8bbSHariprasad Shenai 102476c3a552SRahul Lakkireddy struct msix_info { 102594cdb8bbSHariprasad Shenai unsigned short vec; 102694cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 10270fbc81b3SHariprasad Shenai unsigned int idx; 1028c9765074SNirranjan Kirubaharan cpumask_var_t aff_mask; 102994cdb8bbSHariprasad Shenai }; 103094cdb8bbSHariprasad Shenai 1031661dbeb9SHariprasad Shenai struct vf_info { 1032661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 10338ea4fae9SGanesh Goudar unsigned int tx_rate; 1034661dbeb9SHariprasad Shenai bool pf_set_mac; 10359d5fd927SGanesh Goudar u16 vlan; 10368b965f3fSArjun Vynipadath int link_state; 1037661dbeb9SHariprasad Shenai }; 1038661dbeb9SHariprasad Shenai 10398b4e6b3cSArjun Vynipadath enum { 10408b4e6b3cSArjun Vynipadath HMA_DMA_MAPPED_FLAG = 1 10418b4e6b3cSArjun Vynipadath }; 10428b4e6b3cSArjun Vynipadath 10438b4e6b3cSArjun Vynipadath struct hma_data { 10448b4e6b3cSArjun Vynipadath unsigned char flags; 10458b4e6b3cSArjun Vynipadath struct sg_table *sgt; 10468b4e6b3cSArjun Vynipadath dma_addr_t *phy_addr; /* physical address of the page */ 10478b4e6b3cSArjun Vynipadath }; 10488b4e6b3cSArjun Vynipadath 10494055ae5eSHariprasad Shenai struct mbox_list { 10504055ae5eSHariprasad Shenai struct list_head list; 10514055ae5eSHariprasad Shenai }; 10524055ae5eSHariprasad Shenai 1053e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 1054b1871915SGanesh Goudar struct ch_thermal { 1055b1871915SGanesh Goudar struct thermal_zone_device *tzdev; 1056b1871915SGanesh Goudar int trip_temp; 1057b1871915SGanesh Goudar int trip_type; 1058b1871915SGanesh Goudar }; 1059b1871915SGanesh Goudar #endif 1060b1871915SGanesh Goudar 106128b38705SRaju Rangoju struct mps_entries_ref { 106228b38705SRaju Rangoju struct list_head list; 106328b38705SRaju Rangoju u8 addr[ETH_ALEN]; 106428b38705SRaju Rangoju u8 mask[ETH_ALEN]; 106528b38705SRaju Rangoju u16 idx; 106628b38705SRaju Rangoju refcount_t refcnt; 106728b38705SRaju Rangoju }; 106828b38705SRaju Rangoju 1069f7917c00SJeff Kirsher struct adapter { 1070f7917c00SJeff Kirsher void __iomem *regs; 107122adfe0aSSantosh Rastapur void __iomem *bar2; 10720abfd152SHariprasad Shenai u32 t4_bar0; 1073f7917c00SJeff Kirsher struct pci_dev *pdev; 1074f7917c00SJeff Kirsher struct device *pdev_dev; 10750de72738SHariprasad Shenai const char *name; 10763069ee9bSVipul Pandya unsigned int mbox; 1077b2612722SHariprasad Shenai unsigned int pf; 1078f7917c00SJeff Kirsher unsigned int flags; 1079e7b48a32SHariprasad Shenai unsigned int adap_idx; 10802422d9a3SSantosh Rastapur enum chip_type chip; 1081d5fbda61SArjun Vynipadath u32 eth_flags; 1082f7917c00SJeff Kirsher 1083f7917c00SJeff Kirsher int msg_enable; 1084846eac3fSGanesh Goudar __be16 vxlan_port; 1085846eac3fSGanesh Goudar u8 vxlan_port_cnt; 1086c746fc0eSGanesh Goudar __be16 geneve_port; 1087c746fc0eSGanesh Goudar u8 geneve_port_cnt; 1088f7917c00SJeff Kirsher 1089f7917c00SJeff Kirsher struct adapter_params params; 1090f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 1091f7917c00SJeff Kirsher unsigned int swintr; 1092f7917c00SJeff Kirsher 109376c3a552SRahul Lakkireddy /* MSI-X Info for NIC and OFLD queues */ 109476c3a552SRahul Lakkireddy struct msix_info *msix_info; 109576c3a552SRahul Lakkireddy struct msix_bmap msix_bmap; 1096f7917c00SJeff Kirsher 1097a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 1098f7917c00SJeff Kirsher struct sge sge; 1099f7917c00SJeff Kirsher 1100f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 1101f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 1102f7917c00SJeff Kirsher 1103661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 1104661dbeb9SHariprasad Shenai u8 num_vfs; 1105661dbeb9SHariprasad Shenai 1106793dad94SVipul Pandya u32 filter_mode; 1107636f9d37SVipul Pandya unsigned int l2t_start; 1108636f9d37SVipul Pandya unsigned int l2t_end; 1109f7917c00SJeff Kirsher struct l2t_data *l2t; 1110b5a02f50SAnish Bhatt unsigned int clipt_start; 1111b5a02f50SAnish Bhatt unsigned int clipt_end; 1112b5a02f50SAnish Bhatt struct clip_tbl *clipt; 1113846eac3fSGanesh Goudar unsigned int rawf_start; 1114846eac3fSGanesh Goudar unsigned int rawf_cnt; 11153bdb376eSKumar Sanghvi struct smt_data *smt; 11160fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 1117f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 111894cdb8bbSHariprasad Shenai unsigned int num_uld; 11190fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 1120f7917c00SJeff Kirsher struct list_head list_node; 112101bcca68SVipul Pandya struct list_head rcu_node; 1122fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 112328b38705SRaju Rangoju struct list_head mps_ref; 112428b38705SRaju Rangoju spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1125f7917c00SJeff Kirsher 11267714cb9eSVarun Prakash void *iscsi_ppm; 11277714cb9eSVarun Prakash 1128f7917c00SJeff Kirsher struct tid_info tids; 1129f7917c00SJeff Kirsher void **tid_release_head; 1130f7917c00SJeff Kirsher spinlock_t tid_release_lock; 113129aaee65SAnish Bhatt struct workqueue_struct *workq; 1132f7917c00SJeff Kirsher struct work_struct tid_release_task; 1133881806bcSVipul Pandya struct work_struct db_full_task; 1134881806bcSVipul Pandya struct work_struct db_drop_task; 11358b7372c1SGanesh Goudar struct work_struct fatal_err_notify_task; 1136f7917c00SJeff Kirsher bool tid_release_task_busy; 1137f7917c00SJeff Kirsher 11384055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 11394055ae5eSHariprasad Shenai spinlock_t mbox_lock; 11404055ae5eSHariprasad Shenai struct mbox_list mlist; 11414055ae5eSHariprasad Shenai 11427f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 11437f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 11447f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 11457f080c3fSHariprasad Shenai 11460fbc81b3SHariprasad Shenai struct mutex uld_mutex; 11470fbc81b3SHariprasad Shenai 1148f7917c00SJeff Kirsher struct dentry *debugfs_root; 1149621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1150621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 11518e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 11528e3d04fdSHariprasad Shenai * used for all 4 filters. 11538e3d04fdSHariprasad Shenai */ 1154f7917c00SJeff Kirsher 1155a4569504SAtul Gupta struct ptp_clock *ptp_clock; 1156a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 1157a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 1158a4569504SAtul Gupta /* ptp lock */ 1159a4569504SAtul Gupta spinlock_t ptp_lock; 1160f7917c00SJeff Kirsher spinlock_t stats_lock; 1161fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 1162d8931847SRahul Lakkireddy 1163d8931847SRahul Lakkireddy /* TC u32 offload */ 1164d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 1165a3ac249aSRohit Maheshwari struct chcr_ktls chcr_ktls; 1166ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 116762488e4bSKumar Sanghvi 116862488e4bSKumar Sanghvi /* TC flower offload */ 1169a081e115SCasey Leedom bool tc_flower_initialized; 117079e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 117179e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 1172e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 117379e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 1174ad75b7d3SRahul Lakkireddy 1175ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 1176ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 11778b4e6b3cSArjun Vynipadath 11788b4e6b3cSArjun Vynipadath /* HMA */ 11798b4e6b3cSArjun Vynipadath struct hma_data hma; 1180e4709475SRaju Rangoju 1181e4709475SRaju Rangoju struct srq_data *srq; 11821dde532dSRahul Lakkireddy 11831dde532dSRahul Lakkireddy /* Dump buffer for collecting logs in kdump kernel */ 11841dde532dSRahul Lakkireddy struct vmcoredd_data vmcoredd; 1185e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 1186b1871915SGanesh Goudar struct ch_thermal ch_thermal; 1187b1871915SGanesh Goudar #endif 1188b1396c2bSRahul Lakkireddy 1189b1396c2bSRahul Lakkireddy /* TC MQPRIO offload */ 1190b1396c2bSRahul Lakkireddy struct cxgb4_tc_mqprio *tc_mqprio; 11914ec4762dSRahul Lakkireddy 11924ec4762dSRahul Lakkireddy /* TC MATCHALL classifier offload */ 11934ec4762dSRahul Lakkireddy struct cxgb4_tc_matchall *tc_matchall; 1194f7917c00SJeff Kirsher }; 1195f7917c00SJeff Kirsher 1196b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 1197b72a32daSRahul Lakkireddy * programmed with various parameters. 1198b72a32daSRahul Lakkireddy */ 1199b72a32daSRahul Lakkireddy struct ch_sched_params { 12004bccfc03SRahul Lakkireddy u8 type; /* packet or flow */ 1201b72a32daSRahul Lakkireddy union { 1202b72a32daSRahul Lakkireddy struct { 12034bccfc03SRahul Lakkireddy u8 level; /* scheduler hierarchy level */ 12044bccfc03SRahul Lakkireddy u8 mode; /* per-class or per-flow */ 12054bccfc03SRahul Lakkireddy u8 rateunit; /* bit or packet rate */ 12064bccfc03SRahul Lakkireddy u8 ratemode; /* %port relative or kbps absolute */ 12074bccfc03SRahul Lakkireddy u8 channel; /* scheduler channel [0..N] */ 12084bccfc03SRahul Lakkireddy u8 class; /* scheduler class [0..N] */ 12094bccfc03SRahul Lakkireddy u32 minrate; /* minimum rate */ 12104bccfc03SRahul Lakkireddy u32 maxrate; /* maximum rate */ 12114bccfc03SRahul Lakkireddy u16 weight; /* percent weight */ 12124bccfc03SRahul Lakkireddy u16 pktsize; /* average packet size */ 12134bccfc03SRahul Lakkireddy u16 burstsize; /* burst buffer size */ 1214b72a32daSRahul Lakkireddy } params; 1215b72a32daSRahul Lakkireddy } u; 1216b72a32daSRahul Lakkireddy }; 1217b72a32daSRahul Lakkireddy 121810a2604eSRahul Lakkireddy enum { 121910a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 122010a2604eSRahul Lakkireddy }; 122110a2604eSRahul Lakkireddy 122210a2604eSRahul Lakkireddy enum { 122310a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 12244ec4762dSRahul Lakkireddy SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ 122510a2604eSRahul Lakkireddy }; 122610a2604eSRahul Lakkireddy 122710a2604eSRahul Lakkireddy enum { 122810a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 12290e395b3cSRahul Lakkireddy SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 123010a2604eSRahul Lakkireddy }; 123110a2604eSRahul Lakkireddy 123210a2604eSRahul Lakkireddy enum { 123310a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 123410a2604eSRahul Lakkireddy }; 123510a2604eSRahul Lakkireddy 123610a2604eSRahul Lakkireddy enum { 123710a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 123810a2604eSRahul Lakkireddy }; 123910a2604eSRahul Lakkireddy 12406cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 12416cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 12426cede1f1SRahul Lakkireddy */ 12436cede1f1SRahul Lakkireddy struct ch_sched_queue { 12446cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 12456cede1f1SRahul Lakkireddy s8 class; /* class index */ 12466cede1f1SRahul Lakkireddy }; 12476cede1f1SRahul Lakkireddy 12480e395b3cSRahul Lakkireddy /* Support for "sched_flowc" command to allow one or more FLOWC 12490e395b3cSRahul Lakkireddy * to be bound to a TX Scheduling Class. 12500e395b3cSRahul Lakkireddy */ 12510e395b3cSRahul Lakkireddy struct ch_sched_flowc { 12520e395b3cSRahul Lakkireddy s32 tid; /* TID to bind */ 12530e395b3cSRahul Lakkireddy s8 class; /* class index */ 12540e395b3cSRahul Lakkireddy }; 12550e395b3cSRahul Lakkireddy 1256f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 1257f2b7e78dSVipul Pandya */ 1258f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 1259f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 1260f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 1261f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 1262f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 1263f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1264f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1265f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1266f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1267f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1268f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1269f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 127098f3697fSKumar Sanghvi #define ENCAP_VNI_BITWIDTH 24 1271f2b7e78dSVipul Pandya 1272f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1273f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1274f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1275f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1276f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1277f2b7e78dSVipul Pandya * matching rules are true. 1278f2b7e78dSVipul Pandya * 1279f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1280f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1281f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1282f2b7e78dSVipul Pandya * MPS match type) ... 1283f2b7e78dSVipul Pandya * 1284f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1285f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1286f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1287f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1288f2b7e78dSVipul Pandya */ 1289f2b7e78dSVipul Pandya struct ch_filter_tuple { 1290f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1291f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1292f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1293f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1294f2b7e78dSVipul Pandya * set of fields. 1295f2b7e78dSVipul Pandya */ 1296f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1297f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1298f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1299f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1300f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 130198f3697fSKumar Sanghvi uint32_t encap_vld:1; /* Encapsulation valid */ 1302f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1303f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1304f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1305f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1306f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1307f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1308f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1309f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1310f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1311f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 131298f3697fSKumar Sanghvi uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1313f2b7e78dSVipul Pandya 1314f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1315f2b7e78dSVipul Pandya * available for field rules. 1316f2b7e78dSVipul Pandya */ 1317f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1318f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1319f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1320f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1321f2b7e78dSVipul Pandya }; 1322f2b7e78dSVipul Pandya 1323f2b7e78dSVipul Pandya /* A filter ioctl command. 1324f2b7e78dSVipul Pandya */ 1325f2b7e78dSVipul Pandya struct ch_filter_specification { 1326f2b7e78dSVipul Pandya /* Administrative fields for filter. 1327f2b7e78dSVipul Pandya */ 1328f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1329f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1330f2b7e78dSVipul Pandya 1331f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1332f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1333f2b7e78dSVipul Pandya */ 1334f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 133512b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1336f2b7e78dSVipul Pandya 1337f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1338f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1339f2b7e78dSVipul Pandya * out as egress packets. 1340f2b7e78dSVipul Pandya */ 1341f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1342f2b7e78dSVipul Pandya 1343f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1344f2b7e78dSVipul Pandya 1345f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1346f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1347f2b7e78dSVipul Pandya 1348f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1349f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1350f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1351f2b7e78dSVipul Pandya 1352f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1353f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1354f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1355f2b7e78dSVipul Pandya */ 1356f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1357f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1358f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1359f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 13600ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1361f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1362f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1363f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1364f2b7e78dSVipul Pandya 13650ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 13660ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 13670ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 13680ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 13690ff90994SKumar Sanghvi 137041ec03e5SRahul Lakkireddy u32 tc_prio; /* TC's filter priority index */ 137141ec03e5SRahul Lakkireddy u64 tc_cookie; /* Unique cookie identifying TC rules */ 137241ec03e5SRahul Lakkireddy 13730ff90994SKumar Sanghvi /* reservation for future additions */ 137441ec03e5SRahul Lakkireddy u8 rsvd[12]; 13750ff90994SKumar Sanghvi 1376f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1377f2b7e78dSVipul Pandya */ 1378f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1379f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1380f2b7e78dSVipul Pandya }; 1381f2b7e78dSVipul Pandya 1382f2b7e78dSVipul Pandya enum { 1383f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1384f2b7e78dSVipul Pandya FILTER_DROP, 1385f2b7e78dSVipul Pandya FILTER_SWITCH 1386f2b7e78dSVipul Pandya }; 1387f2b7e78dSVipul Pandya 1388f2b7e78dSVipul Pandya enum { 1389f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1390f2b7e78dSVipul Pandya VLAN_REMOVE, 1391f2b7e78dSVipul Pandya VLAN_INSERT, 1392f2b7e78dSVipul Pandya VLAN_REWRITE 1393f2b7e78dSVipul Pandya }; 1394f2b7e78dSVipul Pandya 1395557ccbf9SKumar Sanghvi enum { 139612b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 139712b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 139812b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 139912b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 140012b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 140112b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 140212b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 140312b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1404557ccbf9SKumar Sanghvi }; 1405557ccbf9SKumar Sanghvi 1406d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1407d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1408d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1409d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1410d57fd6caSRahul Lakkireddy * where the filter table is large. 1411d57fd6caSRahul Lakkireddy */ 1412d57fd6caSRahul Lakkireddy struct filter_entry { 1413d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1414d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1415d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1416d57fd6caSRahul Lakkireddy 1417d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1418578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1419d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 14203bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1421578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1422578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1423d57fd6caSRahul Lakkireddy 1424d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1425d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1426d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1427d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1428d57fd6caSRahul Lakkireddy */ 1429d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1430d57fd6caSRahul Lakkireddy }; 1431d57fd6caSRahul Lakkireddy 1432a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1433a4cfd929SHariprasad Shenai { 1434a4cfd929SHariprasad Shenai return adap->params.offload; 1435a4cfd929SHariprasad Shenai } 1436a4cfd929SHariprasad Shenai 14375c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 14385c31254eSKumar Sanghvi { 14395c31254eSKumar Sanghvi return adap->params.hash_filter; 14405c31254eSKumar Sanghvi } 14415c31254eSKumar Sanghvi 144294cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 144394cdb8bbSHariprasad Shenai { 144494cdb8bbSHariprasad Shenai return adap->params.crypto; 144594cdb8bbSHariprasad Shenai } 144694cdb8bbSHariprasad Shenai 14470fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 14480fbc81b3SHariprasad Shenai { 14490fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 14500fbc81b3SHariprasad Shenai } 14510fbc81b3SHariprasad Shenai 1452ab0367eaSRahul Lakkireddy static inline int is_ethofld(const struct adapter *adap) 1453ab0367eaSRahul Lakkireddy { 1454ab0367eaSRahul Lakkireddy return adap->params.ethofld; 1455ab0367eaSRahul Lakkireddy } 1456ab0367eaSRahul Lakkireddy 1457f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1458f7917c00SJeff Kirsher { 1459f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1460f7917c00SJeff Kirsher } 1461f7917c00SJeff Kirsher 1462f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1463f7917c00SJeff Kirsher { 1464f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1465f7917c00SJeff Kirsher } 1466f7917c00SJeff Kirsher 1467f7917c00SJeff Kirsher #ifndef readq 1468f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1469f7917c00SJeff Kirsher { 1470f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1471f7917c00SJeff Kirsher } 1472f7917c00SJeff Kirsher 1473f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1474f7917c00SJeff Kirsher { 1475f7917c00SJeff Kirsher writel(val, addr); 1476f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1477f7917c00SJeff Kirsher } 1478f7917c00SJeff Kirsher #endif 1479f7917c00SJeff Kirsher 1480f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1481f7917c00SJeff Kirsher { 1482f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1483f7917c00SJeff Kirsher } 1484f7917c00SJeff Kirsher 1485f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1486f7917c00SJeff Kirsher { 1487f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1488f7917c00SJeff Kirsher } 1489f7917c00SJeff Kirsher 1490f7917c00SJeff Kirsher /** 1491098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1492098ef6c2SHariprasad Shenai * @adapter: the adapter 1493098ef6c2SHariprasad Shenai * @port_idx: the port index 1494098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1495098ef6c2SHariprasad Shenai * 1496098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1497098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1498098ef6c2SHariprasad Shenai */ 1499098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1500098ef6c2SHariprasad Shenai u8 hw_addr[]) 1501098ef6c2SHariprasad Shenai { 1502098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1503098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1504098ef6c2SHariprasad Shenai } 1505098ef6c2SHariprasad Shenai 1506098ef6c2SHariprasad Shenai /** 1507f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1508f7917c00SJeff Kirsher * @dev: the netdev 1509f7917c00SJeff Kirsher * 1510f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1511f7917c00SJeff Kirsher */ 1512f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1513f7917c00SJeff Kirsher { 1514f7917c00SJeff Kirsher return netdev_priv(dev); 1515f7917c00SJeff Kirsher } 1516f7917c00SJeff Kirsher 1517f7917c00SJeff Kirsher /** 1518f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1519f7917c00SJeff Kirsher * @adap: the adapter 1520f7917c00SJeff Kirsher * @idx: the port index 1521f7917c00SJeff Kirsher * 1522f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1523f7917c00SJeff Kirsher */ 1524f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1525f7917c00SJeff Kirsher { 1526f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1527f7917c00SJeff Kirsher } 1528f7917c00SJeff Kirsher 1529f7917c00SJeff Kirsher /** 1530f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1531f7917c00SJeff Kirsher * @dev: the netdev 1532f7917c00SJeff Kirsher * 1533f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1534f7917c00SJeff Kirsher */ 1535f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1536f7917c00SJeff Kirsher { 1537f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1538f7917c00SJeff Kirsher } 1539f7917c00SJeff Kirsher 1540812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1541812034f1SHariprasad Shenai * - bits 0..9: chip version 1542812034f1SHariprasad Shenai * - bits 10..15: chip revision 1543812034f1SHariprasad Shenai * - bits 16..23: register dump version 1544812034f1SHariprasad Shenai */ 1545812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1546812034f1SHariprasad Shenai { 1547812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1548812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1549812034f1SHariprasad Shenai } 1550812034f1SHariprasad Shenai 1551812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1552812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1553812034f1SHariprasad Shenai const struct sge_rspq *q) 1554812034f1SHariprasad Shenai { 1555812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1556812034f1SHariprasad Shenai 1557812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1558812034f1SHariprasad Shenai } 1559812034f1SHariprasad Shenai 156001e392aaSLeon Romanovsky /* driver name used for ethtool_drvinfo */ 1561812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1562812034f1SHariprasad Shenai 15638156b0baSGanesh Goudar void t4_os_portmod_changed(struct adapter *adap, int port_id); 1564f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1565f7917c00SJeff Kirsher 1566f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 15675fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1568f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1569d5fbda61SArjun Vynipadath netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1570f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1571f7917c00SJeff Kirsher const struct pkt_gl *gl); 1572f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1573f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1574f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1575f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 15762337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 15772337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1578f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1579f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1580d429005fSVishal Kulkarni unsigned int iqid, u8 dbqt); 1581f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1582f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1583f7917c00SJeff Kirsher unsigned int cmplqid); 15840fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 15850fbc81b3SHariprasad Shenai unsigned int cmplqid); 1586ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1587ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1588ab677ff4SHariprasad Shenai unsigned int uld_type); 15892d0cb84dSRahul Lakkireddy int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 15902d0cb84dSRahul Lakkireddy struct net_device *dev, u32 iqid); 15912d0cb84dSRahul Lakkireddy void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1592f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 159352367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1594f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1595f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1596d429005fSVishal Kulkarni int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1597d429005fSVishal Kulkarni int maxreclaim); 1598812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1599812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1600d0a1299cSGanesh Goudar enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 16013069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1602f7917c00SJeff Kirsher 1603f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1604f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1605f7917c00SJeff Kirsher 16069a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 16079a4da2cdSVipul Pandya { 16089a4da2cdSVipul Pandya return adap->params.bypass; 16099a4da2cdSVipul Pandya } 16109a4da2cdSVipul Pandya 16119a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 16129a4da2cdSVipul Pandya { 16139a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 16149a4da2cdSVipul Pandya switch (device) { 16159a4da2cdSVipul Pandya case 0x440b: 16169a4da2cdSVipul Pandya case 0x440c: 16179a4da2cdSVipul Pandya return 1; 16189a4da2cdSVipul Pandya default: 16199a4da2cdSVipul Pandya return 0; 16209a4da2cdSVipul Pandya } 16219a4da2cdSVipul Pandya } 16229a4da2cdSVipul Pandya 162301b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 162401b69614SHariprasad Shenai { 162501b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 162601b69614SHariprasad Shenai switch (device) { 162701b69614SHariprasad Shenai case 0x4409: 162801b69614SHariprasad Shenai case 0x4486: 162901b69614SHariprasad Shenai return 1; 163001b69614SHariprasad Shenai 163101b69614SHariprasad Shenai default: 163201b69614SHariprasad Shenai return 0; 163301b69614SHariprasad Shenai } 163401b69614SHariprasad Shenai } 163501b69614SHariprasad Shenai 1636f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1637f7917c00SJeff Kirsher { 1638f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1639f7917c00SJeff Kirsher } 1640f7917c00SJeff Kirsher 1641f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1642f7917c00SJeff Kirsher unsigned int us) 1643f7917c00SJeff Kirsher { 1644f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1645f7917c00SJeff Kirsher } 1646f7917c00SJeff Kirsher 164752367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 164852367a76SVipul Pandya unsigned int ticks) 164952367a76SVipul Pandya { 165052367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 165152367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 165252367a76SVipul Pandya adapter->params.vpd.cclk); 165352367a76SVipul Pandya } 165452367a76SVipul Pandya 165508c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 165608c4901bSRahul Lakkireddy unsigned int ticks) 165708c4901bSRahul Lakkireddy { 165808c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 165908c4901bSRahul Lakkireddy } 166008c4901bSRahul Lakkireddy 1661f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1662f7917c00SJeff Kirsher u32 val); 1663f7917c00SJeff Kirsher 166401b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 166501b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1666f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1667f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1668f7917c00SJeff Kirsher 166901b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 167001b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 167101b69614SHariprasad Shenai int timeout) 167201b69614SHariprasad Shenai { 167301b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 167401b69614SHariprasad Shenai timeout); 167501b69614SHariprasad Shenai } 167601b69614SHariprasad Shenai 1677f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1678f7917c00SJeff Kirsher int size, void *rpl) 1679f7917c00SJeff Kirsher { 1680f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1681f7917c00SJeff Kirsher } 1682f7917c00SJeff Kirsher 1683f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1684f7917c00SJeff Kirsher int size, void *rpl) 1685f7917c00SJeff Kirsher { 1686f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1687f7917c00SJeff Kirsher } 1688f7917c00SJeff Kirsher 1689fc08a01aSHariprasad Shenai /** 1690fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1691fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1692fc08a01aSHariprasad Shenai * 1693fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1694fc08a01aSHariprasad Shenai * (hash) address matching. 1695fc08a01aSHariprasad Shenai */ 1696fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1697fc08a01aSHariprasad Shenai { 1698fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1699fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1700fc08a01aSHariprasad Shenai 1701fc08a01aSHariprasad Shenai a ^= b; 1702fc08a01aSHariprasad Shenai a ^= (a >> 12); 1703fc08a01aSHariprasad Shenai a ^= (a >> 6); 1704fc08a01aSHariprasad Shenai return a & 0x3f; 1705fc08a01aSHariprasad Shenai } 1706fc08a01aSHariprasad Shenai 170794cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 170894cdb8bbSHariprasad Shenai unsigned int cnt); 170994cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 171094cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 171194cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 171294cdb8bbSHariprasad Shenai { 171394cdb8bbSHariprasad Shenai q->adap = adap; 171494cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 171594cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 171694cdb8bbSHariprasad Shenai q->size = size; 171794cdb8bbSHariprasad Shenai } 171894cdb8bbSHariprasad Shenai 1719f56ec676SArjun Vynipadath /** 1720f56ec676SArjun Vynipadath * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1721f56ec676SArjun Vynipadath * @fw_mod_type: the Firmware Mofule Type 1722f56ec676SArjun Vynipadath * 1723f56ec676SArjun Vynipadath * Return whether the Firmware Module Type represents a real Transceiver 1724f56ec676SArjun Vynipadath * Module/Cable Module Type which has been inserted. 1725f56ec676SArjun Vynipadath */ 1726f56ec676SArjun Vynipadath static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1727f56ec676SArjun Vynipadath { 1728f56ec676SArjun Vynipadath return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1729f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1730f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1731f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1732f56ec676SArjun Vynipadath } 1733f56ec676SArjun Vynipadath 173413ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 173513ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 173613ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1737f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1738f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1739f2b7e78dSVipul Pandya unsigned int start_idx); 17400abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1741f2b7e78dSVipul Pandya 1742f2b7e78dSVipul Pandya struct fw_filter_wr; 1743f2b7e78dSVipul Pandya 1744f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1745f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1746f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1747f7917c00SJeff Kirsher 17488203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 17498156b0baSGanesh Goudar 17509f764898SVishal Kulkarni fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 17519f764898SVishal Kulkarni struct link_config *lc); 17528156b0baSGanesh Goudar int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 17538156b0baSGanesh Goudar unsigned int port, struct link_config *lc, 17549f764898SVishal Kulkarni u8 sleep_ok, int timeout); 17558156b0baSGanesh Goudar 17568156b0baSGanesh Goudar static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 17578156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 17588156b0baSGanesh Goudar { 17598156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 17608156b0baSGanesh Goudar true, FW_CMD_MAX_TIMEOUT); 17618156b0baSGanesh Goudar } 17628156b0baSGanesh Goudar 17638156b0baSGanesh Goudar static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 17648156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 17658156b0baSGanesh Goudar { 17668156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 17678156b0baSGanesh Goudar false, FW_CMD_MAX_TIMEOUT); 17688156b0baSGanesh Goudar } 17698156b0baSGanesh Goudar 1770f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1771fc5ab020SHariprasad Shenai 1772b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1773b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1774b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1775b562fc37SHariprasad Shenai 17761a4330cdSRahul Lakkireddy int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 17771a4330cdSRahul Lakkireddy u32 *mem_base, u32 *mem_aperture); 17781a4330cdSRahul Lakkireddy void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 17791a4330cdSRahul Lakkireddy void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 17801a4330cdSRahul Lakkireddy int dir); 1781fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1782fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1783fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1784f01aa633SHariprasad Shenai void *buf, int dir); 1785fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1786fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1787fc5ab020SHariprasad Shenai { 1788fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1789fc5ab020SHariprasad Shenai } 1790fc5ab020SHariprasad Shenai 1791812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1792812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1793812034f1SHariprasad Shenai 1794940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1795f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1796098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1797098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 17980eaec62aSCasey Leedom int t4_get_pfres(struct adapter *adapter); 179949216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 180049216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1801f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 180201b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 180301b69614SHariprasad Shenai int win, spinlock_t *lock, 180401b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 180501b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 180601b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 180749216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 180822c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 180922c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1810acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1811636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1812a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 18134da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 181416e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 18150de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 181616e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1817ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1818760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1819760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1820760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1821760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 182216e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 182316e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 182416e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1825f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 18263be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1827e85c9a7aSHariprasad Shenai 1828e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1829b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1830e85c9a7aSHariprasad Shenai unsigned int qid, 1831e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 183266cf188eSHariprasad S int user, 1833e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1834e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1835e85c9a7aSHariprasad Shenai 1836dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1837dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1838ae469b68SHariprasad Shenai 1839ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1840e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 18415ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1842dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1843c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1844c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1845c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1846f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1847f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1848f988008aSGanesh Goudar unsigned int t4_chip_rss_size(struct adapter *adapter); 1849f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1850f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1851f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1852f7917c00SJeff Kirsher unsigned int flags); 1853c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1854c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1855688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 18565ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 18575ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 18585ccf9d04SRahul Lakkireddy bool sleep_ok); 1859688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 18605ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1861688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 18625ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 18635ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 18645ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1865688ea5feSHariprasad Shenai 1866193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1867193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1868b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1869b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1870e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1871e5f0e43bSHariprasad Shenai size_t n); 1872c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1873c778af7dSHariprasad Shenai size_t n); 1874f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1875f1ff24aaSHariprasad Shenai unsigned int *valp); 1876f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1877f1ff24aaSHariprasad Shenai const unsigned int *valp); 1878f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 187919689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 188019689609SHariprasad Shenai unsigned int *pif_req_wrptr, 188119689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 188226fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 188374b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 188472aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1885f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1886a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1887a4cfd929SHariprasad Shenai struct port_stats *stats, 1888a4cfd929SHariprasad Shenai struct port_stats *offset); 188965046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1890f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1891bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1892636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1893636f9d37SVipul Pandya unsigned int mask, unsigned int val); 18942d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 18955ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 18965ccf9d04SRahul Lakkireddy bool sleep_ok); 18975ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 18985ccf9d04SRahul Lakkireddy bool sleep_ok); 18995ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 19005ccf9d04SRahul Lakkireddy bool sleep_ok); 19015ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 19025ccf9d04SRahul Lakkireddy bool sleep_ok); 1903f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 19045ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1905a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 19065ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1907f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1908f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1909f7917c00SJeff Kirsher 1910797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1911797ff0f5SHariprasad Shenai 19127864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1913f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1914f2b7e78dSVipul Pandya 1915f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1916f7917c00SJeff Kirsher const u8 *addr); 1917f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1918f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1919f7917c00SJeff Kirsher 1920f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1921f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1922f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1923f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1924f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1925636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1926636f9d37SVipul Pandya unsigned int cache_line_size); 1927636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1928f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1929f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1930f7917c00SJeff Kirsher u32 *val); 19318f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 19328f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 19338f46d467SArjun Vynipadath u32 *val); 193401b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1935f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 19368f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 193701b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1938688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1939688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 194001b69614SHariprasad Shenai const u32 *val, int timeout); 194101b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 194201b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1943688848b1SAnish Bhatt const u32 *val); 1944f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1945f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1946f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1947f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1948f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1949f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1950f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 195102d805dcSSantosh Rastapur unsigned int *rss_size, u8 *vivld, u8 *vin); 19524f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 19534f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 19544f3a0fcfSHariprasad Shenai unsigned int viid); 1955f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1956f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1957f7917c00SJeff Kirsher bool sleep_ok); 1958846eac3fSGanesh Goudar int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1959846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1960846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 196198f3697fSKumar Sanghvi int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 196298f3697fSKumar Sanghvi bool sleep_ok); 196398f3697fSKumar Sanghvi int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 196498f3697fSKumar Sanghvi const u8 *addr, const u8 *mask, unsigned int vni, 196598f3697fSKumar Sanghvi unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 196698f3697fSKumar Sanghvi bool sleep_ok); 1967846eac3fSGanesh Goudar int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1968846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1969846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 1970f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1971f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1972f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1973fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1974fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1975fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1976f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 197702d805dcSSantosh Rastapur int idx, const u8 *addr, bool persist, u8 *smt_idx); 1978f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1979f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1980688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1981688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1982e2f4f4e9SArjun Vynipadath int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1983e2f4f4e9SArjun Vynipadath struct port_info *pi, 1984e2f4f4e9SArjun Vynipadath bool rx_en, bool tx_en, bool dcb_en); 1985f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1986f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1987f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1988f7917c00SJeff Kirsher unsigned int nblinks); 1989f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1990f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1991f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1992f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1993ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1994ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1995ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1996f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1997f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1998f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1999f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2000f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 2001f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2002f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 2003f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2004f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 2005736c3b94SRahul Lakkireddy int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 2006d429005fSVishal Kulkarni int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 2007d429005fSVishal Kulkarni u16 *dbqtimers); 200823853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 20092061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 2010c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 2011c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 2012f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 2013881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 2014881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 20158e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 20168e3d04fdSHariprasad Shenai int filter_index, int enable); 20178e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 20188e3d04fdSHariprasad Shenai int filter_index, int *enabled); 20198caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 20208caa1e84SVipul Pandya u32 addr, u32 val); 202108c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 202208c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 202308c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 20249e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 20259e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 20269e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 20279e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 20284bccfc03SRahul Lakkireddy int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode, 20294bccfc03SRahul Lakkireddy u8 rateunit, u8 ratemode, u8 channel, u8 class, 20304bccfc03SRahul Lakkireddy u32 minrate, u32 maxrate, u16 weight, u16 pktsize, 20314bccfc03SRahul Lakkireddy u16 burstsize); 203268bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 2033a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 2034a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 2035a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 2036a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 2037a3bfb617SHariprasad Shenai int hz, int ticks); 2038858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 2039858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 20405ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 20415ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 20424359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 20434359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 20445ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 20455ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 20465ccf9d04SRahul Lakkireddy 20470fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 20480fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 20490fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 20500fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 2051f56ec676SArjun Vynipadath int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 2052f56ec676SArjun Vynipadath unsigned int devid, unsigned int offset, 2053f56ec676SArjun Vynipadath unsigned int len, u8 *buf); 205455088355SVishal Kulkarni int t4_load_boot(struct adapter *adap, u8 *boot_data, 205555088355SVishal Kulkarni unsigned int boot_addr, unsigned int size); 2056d5002c9aSVishal Kulkarni int t4_load_bootcfg(struct adapter *adap, 2057d5002c9aSVishal Kulkarni const u8 *cfg_data, unsigned int size); 205894cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 2059ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 2060ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 2061b1396c2bSRahul Lakkireddy void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 2062b1396c2bSRahul Lakkireddy u32 ndesc); 20630e395b3cSRahul Lakkireddy int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 2064b1396c2bSRahul Lakkireddy void cxgb4_ethofld_restart(unsigned long data); 20654846d533SRahul Lakkireddy int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 20664846d533SRahul Lakkireddy const struct pkt_gl *si); 2067ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 2068a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 2069a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 2070a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 2071a6ec572bSAtul Gupta dma_addr_t *addr); 2072a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 2073a6ec572bSAtul Gupta void *pos); 2074a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 2075a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 2076a6ec572bSAtul Gupta const dma_addr_t *addr); 2077a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 20789d5fd927SGanesh Goudar int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 20799d5fd927SGanesh Goudar u16 vlan); 2080ebddd97aSGanesh Goudar int cxgb4_dcb_enabled(const struct net_device *dev); 2081b1871915SGanesh Goudar 2082b1871915SGanesh Goudar int cxgb4_thermal_init(struct adapter *adap); 2083b1871915SGanesh Goudar int cxgb4_thermal_remove(struct adapter *adap); 2084c9765074SNirranjan Kirubaharan int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 2085c9765074SNirranjan Kirubaharan cpumask_var_t *aff_mask, int idx); 2086c9765074SNirranjan Kirubaharan void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 2087b1871915SGanesh Goudar 20882f0b9406SRaju Rangoju int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 20892f0b9406SRaju Rangoju int *tcam_idx, const u8 *addr, 20902f0b9406SRaju Rangoju bool persistent, u8 *smt_idx); 20912f0b9406SRaju Rangoju 2092f9f329adSRaju Rangoju int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 2093f9f329adSRaju Rangoju bool free, unsigned int naddr, 2094f9f329adSRaju Rangoju const u8 **addr, u16 *idx, 2095f9f329adSRaju Rangoju u64 *hash, bool sleep_ok); 2096f9f329adSRaju Rangoju int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2097f9f329adSRaju Rangoju unsigned int naddr, const u8 **addr, bool sleep_ok); 209828b38705SRaju Rangoju int cxgb4_init_mps_ref_entries(struct adapter *adap); 209928b38705SRaju Rangoju void cxgb4_free_mps_ref_entries(struct adapter *adap); 210028b38705SRaju Rangoju int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 210128b38705SRaju Rangoju const u8 *addr, const u8 *mask, 210228b38705SRaju Rangoju unsigned int vni, unsigned int vni_mask, 210328b38705SRaju Rangoju u8 dip_hit, u8 lookup_type, bool sleep_ok); 210428b38705SRaju Rangoju int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 210528b38705SRaju Rangoju int idx, bool sleep_ok); 21065fab5158SRaju Rangoju int cxgb4_free_raw_mac_filt(struct adapter *adap, 21075fab5158SRaju Rangoju unsigned int viid, 21085fab5158SRaju Rangoju const u8 *addr, 21095fab5158SRaju Rangoju const u8 *mask, 21105fab5158SRaju Rangoju unsigned int idx, 21115fab5158SRaju Rangoju u8 lookup_type, 21125fab5158SRaju Rangoju u8 port_id, 21135fab5158SRaju Rangoju bool sleep_ok); 21145fab5158SRaju Rangoju int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 21155fab5158SRaju Rangoju unsigned int viid, 21165fab5158SRaju Rangoju const u8 *addr, 21175fab5158SRaju Rangoju const u8 *mask, 21185fab5158SRaju Rangoju unsigned int idx, 21195fab5158SRaju Rangoju u8 lookup_type, 21205fab5158SRaju Rangoju u8 port_id, 21215fab5158SRaju Rangoju bool sleep_ok); 21222f0b9406SRaju Rangoju int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 21232f0b9406SRaju Rangoju int *tcam_idx, const u8 *addr, 21242f0b9406SRaju Rangoju bool persistent, u8 *smt_idx); 212576c3a552SRahul Lakkireddy int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 212676c3a552SRahul Lakkireddy void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2127b1396c2bSRahul Lakkireddy int cxgb_open(struct net_device *dev); 2128b1396c2bSRahul Lakkireddy int cxgb_close(struct net_device *dev); 21292d0cb84dSRahul Lakkireddy void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 21302d0cb84dSRahul Lakkireddy void cxgb4_quiesce_rx(struct sge_rspq *q); 2131a3ac249aSRohit Maheshwari #ifdef CONFIG_CHELSIO_TLS_DEVICE 2132a3ac249aSRohit Maheshwari int cxgb4_set_ktls_feature(struct adapter *adap, bool enable); 2133a3ac249aSRohit Maheshwari #endif 2134f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 2135