1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 490eb71a9dSNeilBrown #include <linux/rhashtable.h> 50098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 515e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 52a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 53a4569504SAtul Gupta #include <linux/ptp_classify.h> 541dde532dSRahul Lakkireddy #include <linux/crash_dump.h> 55b1871915SGanesh Goudar #include <linux/thermal.h> 56f7917c00SJeff Kirsher #include <asm/io.h> 5727999805SHariprasad S #include "t4_chip_type.h" 58f7917c00SJeff Kirsher #include "cxgb4_uld.h" 59f7917c00SJeff Kirsher 603069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 6194cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 6294cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 633069ee9bSVipul Pandya 64a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 65a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 66a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 67a6ec572bSAtul Gupta */ 68a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 69a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 70a6ec572bSAtul Gupta 71f7917c00SJeff Kirsher enum { 72f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 73f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 74f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 75f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 76a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 77098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 78f7917c00SJeff Kirsher }; 79f7917c00SJeff Kirsher 80f7917c00SJeff Kirsher enum { 81812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 82812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 83812034f1SHariprasad Shenai }; 84812034f1SHariprasad Shenai 85812034f1SHariprasad Shenai enum { 86f7917c00SJeff Kirsher MEM_EDC0, 87f7917c00SJeff Kirsher MEM_EDC1, 882422d9a3SSantosh Rastapur MEM_MC, 892422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 904db0401fSRahul Lakkireddy MEM_MC1, 914db0401fSRahul Lakkireddy MEM_HMA, 92f7917c00SJeff Kirsher }; 93f7917c00SJeff Kirsher 943069ee9bSVipul Pandya enum { 953eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 963eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 973069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 983069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 992422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 1003eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 1013eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 1020abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 1030abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1043069ee9bSVipul Pandya }; 1053069ee9bSVipul Pandya 106f7917c00SJeff Kirsher enum dev_master { 107f7917c00SJeff Kirsher MASTER_CANT, 108f7917c00SJeff Kirsher MASTER_MAY, 109f7917c00SJeff Kirsher MASTER_MUST 110f7917c00SJeff Kirsher }; 111f7917c00SJeff Kirsher 112f7917c00SJeff Kirsher enum dev_state { 113f7917c00SJeff Kirsher DEV_STATE_UNINIT, 114f7917c00SJeff Kirsher DEV_STATE_INIT, 115f7917c00SJeff Kirsher DEV_STATE_ERR 116f7917c00SJeff Kirsher }; 117f7917c00SJeff Kirsher 118c3168cabSGanesh Goudar enum cc_pause { 119f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 120f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 121f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 122f7917c00SJeff Kirsher }; 123f7917c00SJeff Kirsher 124c3168cabSGanesh Goudar enum cc_fec { 1253bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1263bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1273bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1283bb4858fSGanesh Goudar }; 1293bb4858fSGanesh Goudar 130f7917c00SJeff Kirsher struct port_stats { 131f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 132f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 133f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 134f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 135f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 136f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 137f7917c00SJeff Kirsher 138f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 139f7917c00SJeff Kirsher u64 tx_frames_65_127; 140f7917c00SJeff Kirsher u64 tx_frames_128_255; 141f7917c00SJeff Kirsher u64 tx_frames_256_511; 142f7917c00SJeff Kirsher u64 tx_frames_512_1023; 143f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 144f7917c00SJeff Kirsher u64 tx_frames_1519_max; 145f7917c00SJeff Kirsher 146f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 147f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 148f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 149f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 150f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 151f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 152f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 153f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 154f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 155f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 156f7917c00SJeff Kirsher 157f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 158f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 159f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 160f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 161f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 162f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 163f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 164f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 165f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 166f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 167f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 168f7917c00SJeff Kirsher 169f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 170f7917c00SJeff Kirsher u64 rx_frames_65_127; 171f7917c00SJeff Kirsher u64 rx_frames_128_255; 172f7917c00SJeff Kirsher u64 rx_frames_256_511; 173f7917c00SJeff Kirsher u64 rx_frames_512_1023; 174f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 175f7917c00SJeff Kirsher u64 rx_frames_1519_max; 176f7917c00SJeff Kirsher 177f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 178f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 179f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 180f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 181f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 182f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 183f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 184f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 185f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 186f7917c00SJeff Kirsher 187f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 188f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 189f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 190f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 191f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 192f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 193f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 194f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 195f7917c00SJeff Kirsher }; 196f7917c00SJeff Kirsher 197f7917c00SJeff Kirsher struct lb_port_stats { 198f7917c00SJeff Kirsher u64 octets; 199f7917c00SJeff Kirsher u64 frames; 200f7917c00SJeff Kirsher u64 bcast_frames; 201f7917c00SJeff Kirsher u64 mcast_frames; 202f7917c00SJeff Kirsher u64 ucast_frames; 203f7917c00SJeff Kirsher u64 error_frames; 204f7917c00SJeff Kirsher 205f7917c00SJeff Kirsher u64 frames_64; 206f7917c00SJeff Kirsher u64 frames_65_127; 207f7917c00SJeff Kirsher u64 frames_128_255; 208f7917c00SJeff Kirsher u64 frames_256_511; 209f7917c00SJeff Kirsher u64 frames_512_1023; 210f7917c00SJeff Kirsher u64 frames_1024_1518; 211f7917c00SJeff Kirsher u64 frames_1519_max; 212f7917c00SJeff Kirsher 213f7917c00SJeff Kirsher u64 drop; 214f7917c00SJeff Kirsher 215f7917c00SJeff Kirsher u64 ovflow0; 216f7917c00SJeff Kirsher u64 ovflow1; 217f7917c00SJeff Kirsher u64 ovflow2; 218f7917c00SJeff Kirsher u64 ovflow3; 219f7917c00SJeff Kirsher u64 trunc0; 220f7917c00SJeff Kirsher u64 trunc1; 221f7917c00SJeff Kirsher u64 trunc2; 222f7917c00SJeff Kirsher u64 trunc3; 223f7917c00SJeff Kirsher }; 224f7917c00SJeff Kirsher 225f7917c00SJeff Kirsher struct tp_tcp_stats { 226a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 227a4cfd929SHariprasad Shenai u64 tcp_in_segs; 228a4cfd929SHariprasad Shenai u64 tcp_out_segs; 229a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 230a4cfd929SHariprasad Shenai }; 231a4cfd929SHariprasad Shenai 232a4cfd929SHariprasad Shenai struct tp_usm_stats { 233a4cfd929SHariprasad Shenai u32 frames; 234a4cfd929SHariprasad Shenai u32 drops; 235a4cfd929SHariprasad Shenai u64 octets; 236f7917c00SJeff Kirsher }; 237f7917c00SJeff Kirsher 238a6222975SHariprasad Shenai struct tp_fcoe_stats { 239a6222975SHariprasad Shenai u32 frames_ddp; 240a6222975SHariprasad Shenai u32 frames_drop; 241a6222975SHariprasad Shenai u64 octets_ddp; 242f7917c00SJeff Kirsher }; 243f7917c00SJeff Kirsher 244f7917c00SJeff Kirsher struct tp_err_stats { 245a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 246a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 247a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 248a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 249a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 250a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 251a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 252a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 253a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 254a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 255a4cfd929SHariprasad Shenai }; 256a4cfd929SHariprasad Shenai 257a6222975SHariprasad Shenai struct tp_cpl_stats { 258a6222975SHariprasad Shenai u32 req[4]; 259a6222975SHariprasad Shenai u32 rsp[4]; 260a6222975SHariprasad Shenai }; 261a6222975SHariprasad Shenai 262a4cfd929SHariprasad Shenai struct tp_rdma_stats { 263a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 264a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 265f7917c00SJeff Kirsher }; 266f7917c00SJeff Kirsher 267e85c9a7aSHariprasad Shenai struct sge_params { 268e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 269e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 270e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 271e85c9a7aSHariprasad Shenai }; 272e85c9a7aSHariprasad Shenai 273f7917c00SJeff Kirsher struct tp_params { 274f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2752d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 276dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 277dca4faebSVipul Pandya /* channel map */ 278636f9d37SVipul Pandya 279636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 280636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 281dcf7b6f5SKumar Sanghvi 282dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 283dcf10ec7SRaju Rangoju u32 filter_mask; 284dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 285dcf7b6f5SKumar Sanghvi 2868eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2878eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2888eb9f2f9SArjun V */ 2898eb9f2f9SArjun V int rx_pkt_encap; 2908eb9f2f9SArjun V 291dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 292dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 293dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 294dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 295dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 296dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 297dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 298dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 299dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 300dcf7b6f5SKumar Sanghvi * present. 301dcf7b6f5SKumar Sanghvi */ 3020ba9a3b6SKumar Sanghvi int fcoe_shift; 303dcf7b6f5SKumar Sanghvi int port_shift; 3040ba9a3b6SKumar Sanghvi int vnic_shift; 3050ba9a3b6SKumar Sanghvi int vlan_shift; 3060ba9a3b6SKumar Sanghvi int tos_shift; 307dcf7b6f5SKumar Sanghvi int protocol_shift; 3080ba9a3b6SKumar Sanghvi int ethertype_shift; 3090ba9a3b6SKumar Sanghvi int macmatch_shift; 3100ba9a3b6SKumar Sanghvi int matchtype_shift; 3110ba9a3b6SKumar Sanghvi int frag_shift; 3120ba9a3b6SKumar Sanghvi 3130ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 314f7917c00SJeff Kirsher }; 315f7917c00SJeff Kirsher 316f7917c00SJeff Kirsher struct vpd_params { 317f7917c00SJeff Kirsher unsigned int cclk; 318f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 319f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 320f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 321a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 322098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 323f7917c00SJeff Kirsher }; 324f7917c00SJeff Kirsher 3250eaec62aSCasey Leedom /* Maximum resources provisioned for a PCI PF. 3260eaec62aSCasey Leedom */ 3270eaec62aSCasey Leedom struct pf_resources { 3280eaec62aSCasey Leedom unsigned int nvi; /* N virtual interfaces */ 3290eaec62aSCasey Leedom unsigned int neq; /* N egress Qs */ 3300eaec62aSCasey Leedom unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 3310eaec62aSCasey Leedom unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 3320eaec62aSCasey Leedom unsigned int niq; /* N ingress Qs */ 3330eaec62aSCasey Leedom unsigned int tc; /* PCI-E traffic class */ 3340eaec62aSCasey Leedom unsigned int pmask; /* port access rights mask */ 3350eaec62aSCasey Leedom unsigned int nexactf; /* N exact MPS filters */ 3360eaec62aSCasey Leedom unsigned int r_caps; /* read capabilities */ 3370eaec62aSCasey Leedom unsigned int wx_caps; /* write/execute capabilities */ 3380eaec62aSCasey Leedom }; 3390eaec62aSCasey Leedom 340f7917c00SJeff Kirsher struct pci_params { 341baf50868SGanesh Goudar unsigned int vpd_cap_addr; 342f7917c00SJeff Kirsher unsigned char speed; 343f7917c00SJeff Kirsher unsigned char width; 344f7917c00SJeff Kirsher }; 345f7917c00SJeff Kirsher 34649aa284fSHariprasad Shenai struct devlog_params { 34749aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 34849aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 34949aa284fSHariprasad Shenai u32 size; /* size of log */ 35049aa284fSHariprasad Shenai }; 35149aa284fSHariprasad Shenai 3523ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3533ccc6cf7SHariprasad Shenai struct arch_specific_params { 3543ccc6cf7SHariprasad Shenai u8 nchan; 35544588560SHariprasad Shenai u8 pm_stats_cnt; 3562216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3573ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3583ccc6cf7SHariprasad Shenai u16 vfcount; 3593ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3603ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3613ccc6cf7SHariprasad Shenai }; 3623ccc6cf7SHariprasad Shenai 363f7917c00SJeff Kirsher struct adapter_params { 364e85c9a7aSHariprasad Shenai struct sge_params sge; 365f7917c00SJeff Kirsher struct tp_params tp; 366f7917c00SJeff Kirsher struct vpd_params vpd; 3670eaec62aSCasey Leedom struct pf_resources pfres; 368f7917c00SJeff Kirsher struct pci_params pci; 36949aa284fSHariprasad Shenai struct devlog_params devlog; 37049aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 371f7917c00SJeff Kirsher 372f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 373f1ff24aaSHariprasad Shenai 374f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 375f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 376f7917c00SJeff Kirsher 377760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3780de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 379760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3800de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 381760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 382760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 383f7917c00SJeff Kirsher u8 api_vers[7]; 384f7917c00SJeff Kirsher 385f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 386f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 387f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 388f7917c00SJeff Kirsher 389f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 390f7917c00SJeff Kirsher unsigned char portvec; 391d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3923ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 393f7917c00SJeff Kirsher unsigned char offload; 39494cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 395f7917c00SJeff Kirsher 3969a4da2cdSVipul Pandya unsigned char bypass; 3975c31254eSKumar Sanghvi unsigned char hash_filter; 3989a4da2cdSVipul Pandya 399f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 4001ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 4014c2c5763SHariprasad Shenai 402b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 4034c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 4044c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 405086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 406c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 4070ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 40802d805dcSSantosh Rastapur unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 4098f46d467SArjun Vynipadath 4108f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 4118f46d467SArjun Vynipadath * used by the Port 4128f46d467SArjun Vynipadath */ 4138f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 41443db9296SRaju Rangoju bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 415f3910c62SRaju Rangoju bool write_cmpl_support; /* FW supports WRITE_CMPL */ 416f7917c00SJeff Kirsher }; 417f7917c00SJeff Kirsher 418a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 419a3bfb617SHariprasad Shenai * and possible hangs. 420a3bfb617SHariprasad Shenai */ 421a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 422a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 423a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 424a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 425a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 426a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 427a3bfb617SHariprasad Shenai }; 428a3bfb617SHariprasad Shenai 4297f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 4307f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 4317f080c3fSHariprasad Shenai * error returns. 4327f080c3fSHariprasad Shenai */ 4337f080c3fSHariprasad Shenai struct mbox_cmd { 4347f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 4357f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 4367f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 4377f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 4387f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 4397f080c3fSHariprasad Shenai }; 4407f080c3fSHariprasad Shenai 4417f080c3fSHariprasad Shenai struct mbox_cmd_log { 4427f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4437f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4447f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4457f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4467f080c3fSHariprasad Shenai }; 4477f080c3fSHariprasad Shenai 4487f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4497f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4507f080c3fSHariprasad Shenai */ 4517f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4527f080c3fSHariprasad Shenai unsigned int entry_idx) 4537f080c3fSHariprasad Shenai { 4547f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4557f080c3fSHariprasad Shenai } 4567f080c3fSHariprasad Shenai 45716e47624SHariprasad Shenai #include "t4fw_api.h" 45816e47624SHariprasad Shenai 45916e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 460b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 461b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 462b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 463b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 46416e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 46516e47624SHariprasad Shenai 46616e47624SHariprasad Shenai struct fw_info { 46716e47624SHariprasad Shenai u8 chip; 46816e47624SHariprasad Shenai char *fs_name; 46916e47624SHariprasad Shenai char *fw_mod_name; 47016e47624SHariprasad Shenai struct fw_hdr fw_hdr; 47116e47624SHariprasad Shenai }; 47216e47624SHariprasad Shenai 473f7917c00SJeff Kirsher struct trace_params { 474f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 475f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 476f7917c00SJeff Kirsher unsigned short snap_len; 477f7917c00SJeff Kirsher unsigned short min_len; 478f7917c00SJeff Kirsher unsigned char skip_ofst; 479f7917c00SJeff Kirsher unsigned char skip_len; 480f7917c00SJeff Kirsher unsigned char invert; 481f7917c00SJeff Kirsher unsigned char port; 482f7917c00SJeff Kirsher }; 483f7917c00SJeff Kirsher 484c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 485c3168cabSGanesh Goudar 486c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 487c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 488c3168cabSGanesh Goudar 489c3168cabSGanesh Goudar enum fw_caps { 490c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 491c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 492c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 493c3168cabSGanesh Goudar }; 494c3168cabSGanesh Goudar 495f7917c00SJeff Kirsher struct link_config { 496c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 497c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 498c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 499c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 500c3168cabSGanesh Goudar 501c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 502c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 503c3168cabSGanesh Goudar 504c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 505c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 506c3168cabSGanesh Goudar 507c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 508c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 509c3168cabSGanesh Goudar 510f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 511c3168cabSGanesh Goudar 512f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 513ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 5148156b0baSGanesh Goudar 5158156b0baSGanesh Goudar bool new_module; /* ->OS Transceiver Module inserted */ 5168156b0baSGanesh Goudar bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 517f7917c00SJeff Kirsher }; 518f7917c00SJeff Kirsher 519e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 520f7917c00SJeff Kirsher 521f7917c00SJeff Kirsher enum { 522f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 523f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 524f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 525f7917c00SJeff Kirsher }; 526f7917c00SJeff Kirsher 527f7917c00SJeff Kirsher enum { 528812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 529812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 530812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 531812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 532812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 533812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 534812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 535812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 536812034f1SHariprasad Shenai }; 537812034f1SHariprasad Shenai 538812034f1SHariprasad Shenai enum { 53968ddc82aSRahul Lakkireddy MAX_TXQ_DESC_SIZE = 64, 54068ddc82aSRahul Lakkireddy MAX_RXQ_DESC_SIZE = 128, 54168ddc82aSRahul Lakkireddy MAX_FL_DESC_SIZE = 8, 54268ddc82aSRahul Lakkireddy MAX_CTRL_TXQ_DESC_SIZE = 64, 54368ddc82aSRahul Lakkireddy }; 54468ddc82aSRahul Lakkireddy 54568ddc82aSRahul Lakkireddy enum { 546cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 547cf38be6dSHariprasad Shenai /* forwarded interrupts */ 5480fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 549f7917c00SJeff Kirsher }; 550f7917c00SJeff Kirsher 551d5fbda61SArjun Vynipadath enum { 552d5fbda61SArjun Vynipadath PRIV_FLAG_PORT_TX_VM_BIT, 553d5fbda61SArjun Vynipadath }; 554d5fbda61SArjun Vynipadath 555d5fbda61SArjun Vynipadath #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 556d5fbda61SArjun Vynipadath 557d5fbda61SArjun Vynipadath #define PRIV_FLAGS_ADAP 0 558d5fbda61SArjun Vynipadath #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 559d5fbda61SArjun Vynipadath 560f7917c00SJeff Kirsher struct adapter; 561f7917c00SJeff Kirsher struct sge_rspq; 562f7917c00SJeff Kirsher 563688848b1SAnish Bhatt #include "cxgb4_dcb.h" 564688848b1SAnish Bhatt 56576fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 56676fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 56776fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 56876fed8a9SVarun Prakash 569f7917c00SJeff Kirsher struct port_info { 570f7917c00SJeff Kirsher struct adapter *adapter; 571f7917c00SJeff Kirsher u16 viid; 5723f8cfd0dSArjun Vynipadath int xact_addr_filt; /* index of exact MAC address filter */ 573f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 574f7917c00SJeff Kirsher s8 mdio_addr; 57540e9de4bSHariprasad Shenai enum fw_port_type port_type; 576f7917c00SJeff Kirsher u8 mod_type; 577f7917c00SJeff Kirsher u8 port_id; 578f7917c00SJeff Kirsher u8 tx_chan; 579f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 580f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 581f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 582f7917c00SJeff Kirsher u8 rss_mode; 583f7917c00SJeff Kirsher struct link_config link_cfg; 584f7917c00SJeff Kirsher u16 *rss; 585a4cfd929SHariprasad Shenai struct port_stats stats_base; 586688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 587688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 588688848b1SAnish Bhatt #endif 58976fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 59076fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 59176fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5925e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5935e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 594a4569504SAtul Gupta bool ptp_enable; 595b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 596d5fbda61SArjun Vynipadath u32 eth_flags; 59702d805dcSSantosh Rastapur 59802d805dcSSantosh Rastapur /* viid and smt fields either returned by fw 59902d805dcSSantosh Rastapur * or decoded by parsing viid by driver. 60002d805dcSSantosh Rastapur */ 60102d805dcSSantosh Rastapur u8 vin; 60202d805dcSSantosh Rastapur u8 vivld; 60302d805dcSSantosh Rastapur u8 smt_idx; 60474dd5aa1SVishal Kulkarni u8 rx_cchan; 605f7917c00SJeff Kirsher }; 606f7917c00SJeff Kirsher 607f7917c00SJeff Kirsher struct dentry; 608f7917c00SJeff Kirsher struct work_struct; 609f7917c00SJeff Kirsher 610f7917c00SJeff Kirsher enum { /* adapter flags */ 61180f61f19SArjun Vynipadath CXGB4_FULL_INIT_DONE = (1 << 0), 61280f61f19SArjun Vynipadath CXGB4_DEV_ENABLED = (1 << 1), 61380f61f19SArjun Vynipadath CXGB4_USING_MSI = (1 << 2), 61480f61f19SArjun Vynipadath CXGB4_USING_MSIX = (1 << 3), 61580f61f19SArjun Vynipadath CXGB4_FW_OK = (1 << 4), 61680f61f19SArjun Vynipadath CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 61780f61f19SArjun Vynipadath CXGB4_USING_SOFT_PARAMS = (1 << 6), 61880f61f19SArjun Vynipadath CXGB4_MASTER_PF = (1 << 7), 61980f61f19SArjun Vynipadath CXGB4_FW_OFLD_CONN = (1 << 9), 62080f61f19SArjun Vynipadath CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 62180f61f19SArjun Vynipadath CXGB4_SHUTTING_DOWN = (1 << 11), 62280f61f19SArjun Vynipadath CXGB4_SGE_DBQ_TIMER = (1 << 12), 623f7917c00SJeff Kirsher }; 624f7917c00SJeff Kirsher 62594cdb8bbSHariprasad Shenai enum { 62694cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 627a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 62894cdb8bbSHariprasad Shenai }; 62994cdb8bbSHariprasad Shenai 630f7917c00SJeff Kirsher struct rx_sw_desc; 631f7917c00SJeff Kirsher 632f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 633f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 634f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 635f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 636f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 637f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 638f7917c00SJeff Kirsher unsigned long large_alloc_failed; 63970055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 64070055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 641f7917c00SJeff Kirsher unsigned long starving; 642f7917c00SJeff Kirsher /* RO fields */ 643f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 644f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 645f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 646f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 647f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 648df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 649df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 650f7917c00SJeff Kirsher }; 651f7917c00SJeff Kirsher 652f7917c00SJeff Kirsher /* A packet gather list */ 653f7917c00SJeff Kirsher struct pkt_gl { 6545e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 655e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 656f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 657f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 658f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 659f7917c00SJeff Kirsher }; 660f7917c00SJeff Kirsher 661f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 662f7917c00SJeff Kirsher const struct pkt_gl *gl); 6632337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 6642337ba42SVarun Prakash /* LRO related declarations for ULD */ 6652337ba42SVarun Prakash struct t4_lro_mgr { 6662337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 6672337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 6682337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 6692337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6702337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6712337ba42SVarun Prakash }; 672f7917c00SJeff Kirsher 673f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 674f7917c00SJeff Kirsher struct napi_struct napi; 675f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 676f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 677f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 678f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 679f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 680e553ec3fSHariprasad Shenai u8 adaptive_rx; 681f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 682f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 683f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 684f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 685f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 686f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 687f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 688f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 689df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 690df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 691f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 692f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 693f7917c00SJeff Kirsher struct adapter *adap; 694f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 695f7917c00SJeff Kirsher rspq_handler_t handler; 6962337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 6972337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 698f7917c00SJeff Kirsher }; 699f7917c00SJeff Kirsher 700f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 701f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 702f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 703f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 704f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 705f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 706f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 707992bea8eSGanesh Goudar unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 708f7917c00SJeff Kirsher }; 709f7917c00SJeff Kirsher 710f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 711f7917c00SJeff Kirsher struct sge_rspq rspq; 712f7917c00SJeff Kirsher struct sge_fl fl; 713f7917c00SJeff Kirsher struct sge_eth_stats stats; 714f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 715f7917c00SJeff Kirsher 716f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 717f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 718f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 719f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 720f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 721f7917c00SJeff Kirsher }; 722f7917c00SJeff Kirsher 723f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 724f7917c00SJeff Kirsher struct sge_rspq rspq; 725f7917c00SJeff Kirsher struct sge_fl fl; 726f7917c00SJeff Kirsher struct sge_ofld_stats stats; 727f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 728f7917c00SJeff Kirsher 729f7917c00SJeff Kirsher struct tx_desc { 730f7917c00SJeff Kirsher __be64 flit[8]; 731f7917c00SJeff Kirsher }; 732f7917c00SJeff Kirsher 733f7917c00SJeff Kirsher struct tx_sw_desc; 734f7917c00SJeff Kirsher 735f7917c00SJeff Kirsher struct sge_txq { 736f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 737ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 738f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 739f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 740f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 741f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 742f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 743f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 744f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 745f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 746f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 747f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 7483069ee9bSVipul Pandya spinlock_t db_lock; 7493069ee9bSVipul Pandya int db_disabled; 7503069ee9bSVipul Pandya unsigned short db_pidx; 75105eb2389SSteve Wise unsigned short db_pidx_inc; 752df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 753df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 754f7917c00SJeff Kirsher }; 755f7917c00SJeff Kirsher 756f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 757f7917c00SJeff Kirsher struct sge_txq q; 758f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 75910b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 76010b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 76110b00466SAnish Bhatt #endif 762d429005fSVishal Kulkarni u8 dbqt; /* SGE Doorbell Queue Timer in use */ 763d429005fSVishal Kulkarni unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 764f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 765f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 766f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 767f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 768f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 769f7917c00SJeff Kirsher 770ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 771f7917c00SJeff Kirsher struct sge_txq q; 772f7917c00SJeff Kirsher struct adapter *adap; 773f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 774f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 775126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 776f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 777f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 778f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 779f7917c00SJeff Kirsher 780f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 781f7917c00SJeff Kirsher struct sge_txq q; 782f7917c00SJeff Kirsher struct adapter *adap; 783f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 784f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 785f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 786f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 787f7917c00SJeff Kirsher 78894cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 78994cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 79094cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 79194cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 79294cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 79394cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 79494cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 79594cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 79694cdb8bbSHariprasad Shenai }; 79794cdb8bbSHariprasad Shenai 798ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 799ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 800ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 801ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 802ab677ff4SHariprasad Shenai }; 803ab677ff4SHariprasad Shenai 804f7917c00SJeff Kirsher struct sge { 805f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 806a4569504SAtul Gupta struct sge_eth_txq ptptxq; 807f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 808f7917c00SJeff Kirsher 809f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 810f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 81194cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 812ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 813f7917c00SJeff Kirsher 814f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 815f7917c00SJeff Kirsher spinlock_t intrq_lock; 816f7917c00SJeff Kirsher 817f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 818f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 819f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 8200fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 82194cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 822f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 823f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 824543a1b85SVishal Kulkarni u16 dbqtimer_tick; 825d429005fSVishal Kulkarni u16 dbqtimer_val[SGE_NDBQTIMERS]; 82652367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 82752367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 82852367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 82952367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 83052367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 8310f4d201fSKumar Sanghvi 832a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 833f7917c00SJeff Kirsher unsigned int egr_start; 8344b8e27a8SHariprasad Shenai unsigned int egr_sz; 835f7917c00SJeff Kirsher unsigned int ingr_start; 8364b8e27a8SHariprasad Shenai unsigned int ingr_sz; 8374b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 8384b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 8394b8e27a8SHariprasad Shenai unsigned long *starving_fl; 8404b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 8415b377d11SHariprasad Shenai unsigned long *blocked_fl; 842f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 843f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 844f7917c00SJeff Kirsher }; 845f7917c00SJeff Kirsher 846f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 8470fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 848f7917c00SJeff Kirsher 849f7917c00SJeff Kirsher struct l2t_data; 850f7917c00SJeff Kirsher 8512422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 8522422d9a3SSantosh Rastapur 8537d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 8547d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 8557d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 8562422d9a3SSantosh Rastapur */ 8577d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 8582422d9a3SSantosh Rastapur 8592422d9a3SSantosh Rastapur #endif 8602422d9a3SSantosh Rastapur 861a4cfd929SHariprasad Shenai struct doorbell_stats { 862a4cfd929SHariprasad Shenai u32 db_drop; 863a4cfd929SHariprasad Shenai u32 db_empty; 864a4cfd929SHariprasad Shenai u32 db_full; 865a4cfd929SHariprasad Shenai }; 866a4cfd929SHariprasad Shenai 867fc08a01aSHariprasad Shenai struct hash_mac_addr { 868fc08a01aSHariprasad Shenai struct list_head list; 869fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 8703f8cfd0dSArjun Vynipadath unsigned int iface_mac; 871fc08a01aSHariprasad Shenai }; 872fc08a01aSHariprasad Shenai 87394cdb8bbSHariprasad Shenai struct uld_msix_bmap { 87494cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 87594cdb8bbSHariprasad Shenai unsigned int mapsize; 87694cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 87794cdb8bbSHariprasad Shenai }; 87894cdb8bbSHariprasad Shenai 87994cdb8bbSHariprasad Shenai struct uld_msix_info { 88094cdb8bbSHariprasad Shenai unsigned short vec; 88194cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 8820fbc81b3SHariprasad Shenai unsigned int idx; 883c9765074SNirranjan Kirubaharan cpumask_var_t aff_mask; 88494cdb8bbSHariprasad Shenai }; 88594cdb8bbSHariprasad Shenai 886661dbeb9SHariprasad Shenai struct vf_info { 887661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 8888ea4fae9SGanesh Goudar unsigned int tx_rate; 889661dbeb9SHariprasad Shenai bool pf_set_mac; 8909d5fd927SGanesh Goudar u16 vlan; 8918b965f3fSArjun Vynipadath int link_state; 892661dbeb9SHariprasad Shenai }; 893661dbeb9SHariprasad Shenai 8948b4e6b3cSArjun Vynipadath enum { 8958b4e6b3cSArjun Vynipadath HMA_DMA_MAPPED_FLAG = 1 8968b4e6b3cSArjun Vynipadath }; 8978b4e6b3cSArjun Vynipadath 8988b4e6b3cSArjun Vynipadath struct hma_data { 8998b4e6b3cSArjun Vynipadath unsigned char flags; 9008b4e6b3cSArjun Vynipadath struct sg_table *sgt; 9018b4e6b3cSArjun Vynipadath dma_addr_t *phy_addr; /* physical address of the page */ 9028b4e6b3cSArjun Vynipadath }; 9038b4e6b3cSArjun Vynipadath 9044055ae5eSHariprasad Shenai struct mbox_list { 9054055ae5eSHariprasad Shenai struct list_head list; 9064055ae5eSHariprasad Shenai }; 9074055ae5eSHariprasad Shenai 908846eac3fSGanesh Goudar struct mps_encap_entry { 909846eac3fSGanesh Goudar atomic_t refcnt; 910846eac3fSGanesh Goudar }; 911846eac3fSGanesh Goudar 912e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 913b1871915SGanesh Goudar struct ch_thermal { 914b1871915SGanesh Goudar struct thermal_zone_device *tzdev; 915b1871915SGanesh Goudar int trip_temp; 916b1871915SGanesh Goudar int trip_type; 917b1871915SGanesh Goudar }; 918b1871915SGanesh Goudar #endif 919b1871915SGanesh Goudar 920f7917c00SJeff Kirsher struct adapter { 921f7917c00SJeff Kirsher void __iomem *regs; 92222adfe0aSSantosh Rastapur void __iomem *bar2; 9230abfd152SHariprasad Shenai u32 t4_bar0; 924f7917c00SJeff Kirsher struct pci_dev *pdev; 925f7917c00SJeff Kirsher struct device *pdev_dev; 9260de72738SHariprasad Shenai const char *name; 9273069ee9bSVipul Pandya unsigned int mbox; 928b2612722SHariprasad Shenai unsigned int pf; 929f7917c00SJeff Kirsher unsigned int flags; 930e7b48a32SHariprasad Shenai unsigned int adap_idx; 9312422d9a3SSantosh Rastapur enum chip_type chip; 932d5fbda61SArjun Vynipadath u32 eth_flags; 933f7917c00SJeff Kirsher 934f7917c00SJeff Kirsher int msg_enable; 935846eac3fSGanesh Goudar __be16 vxlan_port; 936846eac3fSGanesh Goudar u8 vxlan_port_cnt; 937c746fc0eSGanesh Goudar __be16 geneve_port; 938c746fc0eSGanesh Goudar u8 geneve_port_cnt; 939f7917c00SJeff Kirsher 940f7917c00SJeff Kirsher struct adapter_params params; 941f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 942f7917c00SJeff Kirsher unsigned int swintr; 943f7917c00SJeff Kirsher 944c9765074SNirranjan Kirubaharan struct msix_info { 945f7917c00SJeff Kirsher unsigned short vec; 946f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 947c9765074SNirranjan Kirubaharan cpumask_var_t aff_mask; 948f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 94994cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 95094cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 9510fbc81b3SHariprasad Shenai int msi_idx; 952f7917c00SJeff Kirsher 953a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 954f7917c00SJeff Kirsher struct sge sge; 955f7917c00SJeff Kirsher 956f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 957f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 958f7917c00SJeff Kirsher 959661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 960661dbeb9SHariprasad Shenai u8 num_vfs; 961661dbeb9SHariprasad Shenai 962793dad94SVipul Pandya u32 filter_mode; 963636f9d37SVipul Pandya unsigned int l2t_start; 964636f9d37SVipul Pandya unsigned int l2t_end; 965f7917c00SJeff Kirsher struct l2t_data *l2t; 966b5a02f50SAnish Bhatt unsigned int clipt_start; 967b5a02f50SAnish Bhatt unsigned int clipt_end; 968b5a02f50SAnish Bhatt struct clip_tbl *clipt; 969846eac3fSGanesh Goudar unsigned int rawf_start; 970846eac3fSGanesh Goudar unsigned int rawf_cnt; 9713bdb376eSKumar Sanghvi struct smt_data *smt; 972846eac3fSGanesh Goudar struct mps_encap_entry *mps_encap; 9730fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 974f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 97594cdb8bbSHariprasad Shenai unsigned int num_uld; 9760fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 977f7917c00SJeff Kirsher struct list_head list_node; 97801bcca68SVipul Pandya struct list_head rcu_node; 979fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 980f7917c00SJeff Kirsher 9817714cb9eSVarun Prakash void *iscsi_ppm; 9827714cb9eSVarun Prakash 983f7917c00SJeff Kirsher struct tid_info tids; 984f7917c00SJeff Kirsher void **tid_release_head; 985f7917c00SJeff Kirsher spinlock_t tid_release_lock; 98629aaee65SAnish Bhatt struct workqueue_struct *workq; 987f7917c00SJeff Kirsher struct work_struct tid_release_task; 988881806bcSVipul Pandya struct work_struct db_full_task; 989881806bcSVipul Pandya struct work_struct db_drop_task; 9908b7372c1SGanesh Goudar struct work_struct fatal_err_notify_task; 991f7917c00SJeff Kirsher bool tid_release_task_busy; 992f7917c00SJeff Kirsher 9934055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 9944055ae5eSHariprasad Shenai spinlock_t mbox_lock; 9954055ae5eSHariprasad Shenai struct mbox_list mlist; 9964055ae5eSHariprasad Shenai 9977f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 9987f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 9997f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 10007f080c3fSHariprasad Shenai 10010fbc81b3SHariprasad Shenai struct mutex uld_mutex; 10020fbc81b3SHariprasad Shenai 1003f7917c00SJeff Kirsher struct dentry *debugfs_root; 1004621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1005621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 10068e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 10078e3d04fdSHariprasad Shenai * used for all 4 filters. 10088e3d04fdSHariprasad Shenai */ 1009f7917c00SJeff Kirsher 1010a4569504SAtul Gupta struct ptp_clock *ptp_clock; 1011a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 1012a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 1013a4569504SAtul Gupta /* ptp lock */ 1014a4569504SAtul Gupta spinlock_t ptp_lock; 1015f7917c00SJeff Kirsher spinlock_t stats_lock; 1016fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 1017d8931847SRahul Lakkireddy 1018d8931847SRahul Lakkireddy /* TC u32 offload */ 1019d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 1020ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 102162488e4bSKumar Sanghvi 102262488e4bSKumar Sanghvi /* TC flower offload */ 1023a081e115SCasey Leedom bool tc_flower_initialized; 102479e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 102579e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 1026e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 102779e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 1028ad75b7d3SRahul Lakkireddy 1029ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 1030ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 10318b4e6b3cSArjun Vynipadath 10328b4e6b3cSArjun Vynipadath /* HMA */ 10338b4e6b3cSArjun Vynipadath struct hma_data hma; 1034e4709475SRaju Rangoju 1035e4709475SRaju Rangoju struct srq_data *srq; 10361dde532dSRahul Lakkireddy 10371dde532dSRahul Lakkireddy /* Dump buffer for collecting logs in kdump kernel */ 10381dde532dSRahul Lakkireddy struct vmcoredd_data vmcoredd; 1039e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 1040b1871915SGanesh Goudar struct ch_thermal ch_thermal; 1041b1871915SGanesh Goudar #endif 1042f7917c00SJeff Kirsher }; 1043f7917c00SJeff Kirsher 1044b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 1045b72a32daSRahul Lakkireddy * programmed with various parameters. 1046b72a32daSRahul Lakkireddy */ 1047b72a32daSRahul Lakkireddy struct ch_sched_params { 1048b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 1049b72a32daSRahul Lakkireddy union { 1050b72a32daSRahul Lakkireddy struct { 1051b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 1052b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 1053b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 1054b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 1055b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 1056b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 1057b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 1058b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 1059b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 1060b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 1061b72a32daSRahul Lakkireddy } params; 1062b72a32daSRahul Lakkireddy } u; 1063b72a32daSRahul Lakkireddy }; 1064b72a32daSRahul Lakkireddy 106510a2604eSRahul Lakkireddy enum { 106610a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 106710a2604eSRahul Lakkireddy }; 106810a2604eSRahul Lakkireddy 106910a2604eSRahul Lakkireddy enum { 107010a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 107110a2604eSRahul Lakkireddy }; 107210a2604eSRahul Lakkireddy 107310a2604eSRahul Lakkireddy enum { 107410a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 107510a2604eSRahul Lakkireddy }; 107610a2604eSRahul Lakkireddy 107710a2604eSRahul Lakkireddy enum { 107810a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 107910a2604eSRahul Lakkireddy }; 108010a2604eSRahul Lakkireddy 108110a2604eSRahul Lakkireddy enum { 108210a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 108310a2604eSRahul Lakkireddy }; 108410a2604eSRahul Lakkireddy 1085a6ec572bSAtul Gupta struct tx_sw_desc { /* SW state per Tx descriptor */ 1086a6ec572bSAtul Gupta struct sk_buff *skb; 1087a6ec572bSAtul Gupta struct ulptx_sgl *sgl; 1088a6ec572bSAtul Gupta }; 1089a6ec572bSAtul Gupta 10906cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 10916cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 10926cede1f1SRahul Lakkireddy */ 10936cede1f1SRahul Lakkireddy struct ch_sched_queue { 10946cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 10956cede1f1SRahul Lakkireddy s8 class; /* class index */ 10966cede1f1SRahul Lakkireddy }; 10976cede1f1SRahul Lakkireddy 1098f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 1099f2b7e78dSVipul Pandya */ 1100f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 1101f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 1102f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 1103f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 1104f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 1105f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1106f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1107f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1108f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1109f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1110f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1111f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 111298f3697fSKumar Sanghvi #define ENCAP_VNI_BITWIDTH 24 1113f2b7e78dSVipul Pandya 1114f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1115f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1116f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1117f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1118f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1119f2b7e78dSVipul Pandya * matching rules are true. 1120f2b7e78dSVipul Pandya * 1121f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1122f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1123f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1124f2b7e78dSVipul Pandya * MPS match type) ... 1125f2b7e78dSVipul Pandya * 1126f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1127f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1128f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1129f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1130f2b7e78dSVipul Pandya */ 1131f2b7e78dSVipul Pandya struct ch_filter_tuple { 1132f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1133f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1134f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1135f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1136f2b7e78dSVipul Pandya * set of fields. 1137f2b7e78dSVipul Pandya */ 1138f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1139f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1140f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1141f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1142f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 114398f3697fSKumar Sanghvi uint32_t encap_vld:1; /* Encapsulation valid */ 1144f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1145f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1146f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1147f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1148f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1149f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1150f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1151f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1152f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1153f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 115498f3697fSKumar Sanghvi uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1155f2b7e78dSVipul Pandya 1156f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1157f2b7e78dSVipul Pandya * available for field rules. 1158f2b7e78dSVipul Pandya */ 1159f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1160f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1161f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1162f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1163f2b7e78dSVipul Pandya }; 1164f2b7e78dSVipul Pandya 1165f2b7e78dSVipul Pandya /* A filter ioctl command. 1166f2b7e78dSVipul Pandya */ 1167f2b7e78dSVipul Pandya struct ch_filter_specification { 1168f2b7e78dSVipul Pandya /* Administrative fields for filter. 1169f2b7e78dSVipul Pandya */ 1170f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1171f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1172f2b7e78dSVipul Pandya 1173f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1174f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1175f2b7e78dSVipul Pandya */ 1176f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 117712b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1178f2b7e78dSVipul Pandya 1179f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1180f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1181f2b7e78dSVipul Pandya * out as egress packets. 1182f2b7e78dSVipul Pandya */ 1183f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1184f2b7e78dSVipul Pandya 1185f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1186f2b7e78dSVipul Pandya 1187f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1188f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1189f2b7e78dSVipul Pandya 1190f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1191f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1192f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1193f2b7e78dSVipul Pandya 1194f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1195f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1196f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1197f2b7e78dSVipul Pandya */ 1198f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1199f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1200f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1201f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 12020ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1203f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1204f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1205f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1206f2b7e78dSVipul Pandya 12070ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 12080ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 12090ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 12100ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 12110ff90994SKumar Sanghvi 12120ff90994SKumar Sanghvi /* reservation for future additions */ 12130ff90994SKumar Sanghvi u8 rsvd[24]; 12140ff90994SKumar Sanghvi 1215f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1216f2b7e78dSVipul Pandya */ 1217f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1218f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1219f2b7e78dSVipul Pandya }; 1220f2b7e78dSVipul Pandya 1221f2b7e78dSVipul Pandya enum { 1222f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1223f2b7e78dSVipul Pandya FILTER_DROP, 1224f2b7e78dSVipul Pandya FILTER_SWITCH 1225f2b7e78dSVipul Pandya }; 1226f2b7e78dSVipul Pandya 1227f2b7e78dSVipul Pandya enum { 1228f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1229f2b7e78dSVipul Pandya VLAN_REMOVE, 1230f2b7e78dSVipul Pandya VLAN_INSERT, 1231f2b7e78dSVipul Pandya VLAN_REWRITE 1232f2b7e78dSVipul Pandya }; 1233f2b7e78dSVipul Pandya 1234557ccbf9SKumar Sanghvi enum { 123512b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 123612b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 123712b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 123812b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 123912b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 124012b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 124112b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 124212b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1243557ccbf9SKumar Sanghvi }; 1244557ccbf9SKumar Sanghvi 1245d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1246d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1247d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1248d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1249d57fd6caSRahul Lakkireddy * where the filter table is large. 1250d57fd6caSRahul Lakkireddy */ 1251d57fd6caSRahul Lakkireddy struct filter_entry { 1252d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1253d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1254d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1255d57fd6caSRahul Lakkireddy 1256d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1257578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1258d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 12593bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1260578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1261578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1262d57fd6caSRahul Lakkireddy 1263d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1264d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1265d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1266d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1267d57fd6caSRahul Lakkireddy */ 1268d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1269d57fd6caSRahul Lakkireddy }; 1270d57fd6caSRahul Lakkireddy 1271a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1272a4cfd929SHariprasad Shenai { 1273a4cfd929SHariprasad Shenai return adap->params.offload; 1274a4cfd929SHariprasad Shenai } 1275a4cfd929SHariprasad Shenai 12765c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 12775c31254eSKumar Sanghvi { 12785c31254eSKumar Sanghvi return adap->params.hash_filter; 12795c31254eSKumar Sanghvi } 12805c31254eSKumar Sanghvi 128194cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 128294cdb8bbSHariprasad Shenai { 128394cdb8bbSHariprasad Shenai return adap->params.crypto; 128494cdb8bbSHariprasad Shenai } 128594cdb8bbSHariprasad Shenai 12860fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 12870fbc81b3SHariprasad Shenai { 12880fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 12890fbc81b3SHariprasad Shenai } 12900fbc81b3SHariprasad Shenai 1291f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1292f7917c00SJeff Kirsher { 1293f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1294f7917c00SJeff Kirsher } 1295f7917c00SJeff Kirsher 1296f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1297f7917c00SJeff Kirsher { 1298f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1299f7917c00SJeff Kirsher } 1300f7917c00SJeff Kirsher 1301f7917c00SJeff Kirsher #ifndef readq 1302f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1303f7917c00SJeff Kirsher { 1304f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1305f7917c00SJeff Kirsher } 1306f7917c00SJeff Kirsher 1307f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1308f7917c00SJeff Kirsher { 1309f7917c00SJeff Kirsher writel(val, addr); 1310f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1311f7917c00SJeff Kirsher } 1312f7917c00SJeff Kirsher #endif 1313f7917c00SJeff Kirsher 1314f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1315f7917c00SJeff Kirsher { 1316f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1317f7917c00SJeff Kirsher } 1318f7917c00SJeff Kirsher 1319f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1320f7917c00SJeff Kirsher { 1321f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1322f7917c00SJeff Kirsher } 1323f7917c00SJeff Kirsher 1324f7917c00SJeff Kirsher /** 1325098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1326098ef6c2SHariprasad Shenai * @adapter: the adapter 1327098ef6c2SHariprasad Shenai * @port_idx: the port index 1328098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1329098ef6c2SHariprasad Shenai * 1330098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1331098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1332098ef6c2SHariprasad Shenai */ 1333098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1334098ef6c2SHariprasad Shenai u8 hw_addr[]) 1335098ef6c2SHariprasad Shenai { 1336098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1337098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1338098ef6c2SHariprasad Shenai } 1339098ef6c2SHariprasad Shenai 1340098ef6c2SHariprasad Shenai /** 1341f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1342f7917c00SJeff Kirsher * @dev: the netdev 1343f7917c00SJeff Kirsher * 1344f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1345f7917c00SJeff Kirsher */ 1346f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1347f7917c00SJeff Kirsher { 1348f7917c00SJeff Kirsher return netdev_priv(dev); 1349f7917c00SJeff Kirsher } 1350f7917c00SJeff Kirsher 1351f7917c00SJeff Kirsher /** 1352f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1353f7917c00SJeff Kirsher * @adap: the adapter 1354f7917c00SJeff Kirsher * @idx: the port index 1355f7917c00SJeff Kirsher * 1356f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1357f7917c00SJeff Kirsher */ 1358f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1359f7917c00SJeff Kirsher { 1360f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1361f7917c00SJeff Kirsher } 1362f7917c00SJeff Kirsher 1363f7917c00SJeff Kirsher /** 1364f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1365f7917c00SJeff Kirsher * @dev: the netdev 1366f7917c00SJeff Kirsher * 1367f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1368f7917c00SJeff Kirsher */ 1369f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1370f7917c00SJeff Kirsher { 1371f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1372f7917c00SJeff Kirsher } 1373f7917c00SJeff Kirsher 1374812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1375812034f1SHariprasad Shenai * - bits 0..9: chip version 1376812034f1SHariprasad Shenai * - bits 10..15: chip revision 1377812034f1SHariprasad Shenai * - bits 16..23: register dump version 1378812034f1SHariprasad Shenai */ 1379812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1380812034f1SHariprasad Shenai { 1381812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1382812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1383812034f1SHariprasad Shenai } 1384812034f1SHariprasad Shenai 1385812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1386812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1387812034f1SHariprasad Shenai const struct sge_rspq *q) 1388812034f1SHariprasad Shenai { 1389812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1390812034f1SHariprasad Shenai 1391812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1392812034f1SHariprasad Shenai } 1393812034f1SHariprasad Shenai 1394812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1395812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1396812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1397812034f1SHariprasad Shenai 13988156b0baSGanesh Goudar void t4_os_portmod_changed(struct adapter *adap, int port_id); 1399f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1400f7917c00SJeff Kirsher 1401f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 14025fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1403f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1404d5fbda61SArjun Vynipadath netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1405f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1406f7917c00SJeff Kirsher const struct pkt_gl *gl); 1407f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1408f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1409f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1410f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 14112337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 14122337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1413f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1414f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1415d429005fSVishal Kulkarni unsigned int iqid, u8 dbqt); 1416f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1417f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1418f7917c00SJeff Kirsher unsigned int cmplqid); 14190fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 14200fbc81b3SHariprasad Shenai unsigned int cmplqid); 1421ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1422ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1423ab677ff4SHariprasad Shenai unsigned int uld_type); 1424f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 142552367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1426f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1427f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1428d429005fSVishal Kulkarni int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1429d429005fSVishal Kulkarni int maxreclaim); 1430812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1431812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1432d0a1299cSGanesh Goudar enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 14333069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1434f7917c00SJeff Kirsher 1435f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1436f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1437f7917c00SJeff Kirsher 14389a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 14399a4da2cdSVipul Pandya { 14409a4da2cdSVipul Pandya return adap->params.bypass; 14419a4da2cdSVipul Pandya } 14429a4da2cdSVipul Pandya 14439a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 14449a4da2cdSVipul Pandya { 14459a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 14469a4da2cdSVipul Pandya switch (device) { 14479a4da2cdSVipul Pandya case 0x440b: 14489a4da2cdSVipul Pandya case 0x440c: 14499a4da2cdSVipul Pandya return 1; 14509a4da2cdSVipul Pandya default: 14519a4da2cdSVipul Pandya return 0; 14529a4da2cdSVipul Pandya } 14539a4da2cdSVipul Pandya } 14549a4da2cdSVipul Pandya 145501b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 145601b69614SHariprasad Shenai { 145701b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 145801b69614SHariprasad Shenai switch (device) { 145901b69614SHariprasad Shenai case 0x4409: 146001b69614SHariprasad Shenai case 0x4486: 146101b69614SHariprasad Shenai return 1; 146201b69614SHariprasad Shenai 146301b69614SHariprasad Shenai default: 146401b69614SHariprasad Shenai return 0; 146501b69614SHariprasad Shenai } 146601b69614SHariprasad Shenai } 146701b69614SHariprasad Shenai 1468f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1469f7917c00SJeff Kirsher { 1470f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1471f7917c00SJeff Kirsher } 1472f7917c00SJeff Kirsher 1473f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1474f7917c00SJeff Kirsher unsigned int us) 1475f7917c00SJeff Kirsher { 1476f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1477f7917c00SJeff Kirsher } 1478f7917c00SJeff Kirsher 147952367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 148052367a76SVipul Pandya unsigned int ticks) 148152367a76SVipul Pandya { 148252367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 148352367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 148452367a76SVipul Pandya adapter->params.vpd.cclk); 148552367a76SVipul Pandya } 148652367a76SVipul Pandya 148708c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 148808c4901bSRahul Lakkireddy unsigned int ticks) 148908c4901bSRahul Lakkireddy { 149008c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 149108c4901bSRahul Lakkireddy } 149208c4901bSRahul Lakkireddy 1493f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1494f7917c00SJeff Kirsher u32 val); 1495f7917c00SJeff Kirsher 149601b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 149701b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1498f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1499f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1500f7917c00SJeff Kirsher 150101b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 150201b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 150301b69614SHariprasad Shenai int timeout) 150401b69614SHariprasad Shenai { 150501b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 150601b69614SHariprasad Shenai timeout); 150701b69614SHariprasad Shenai } 150801b69614SHariprasad Shenai 1509f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1510f7917c00SJeff Kirsher int size, void *rpl) 1511f7917c00SJeff Kirsher { 1512f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1513f7917c00SJeff Kirsher } 1514f7917c00SJeff Kirsher 1515f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1516f7917c00SJeff Kirsher int size, void *rpl) 1517f7917c00SJeff Kirsher { 1518f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1519f7917c00SJeff Kirsher } 1520f7917c00SJeff Kirsher 1521fc08a01aSHariprasad Shenai /** 1522fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1523fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1524fc08a01aSHariprasad Shenai * 1525fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1526fc08a01aSHariprasad Shenai * (hash) address matching. 1527fc08a01aSHariprasad Shenai */ 1528fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1529fc08a01aSHariprasad Shenai { 1530fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1531fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1532fc08a01aSHariprasad Shenai 1533fc08a01aSHariprasad Shenai a ^= b; 1534fc08a01aSHariprasad Shenai a ^= (a >> 12); 1535fc08a01aSHariprasad Shenai a ^= (a >> 6); 1536fc08a01aSHariprasad Shenai return a & 0x3f; 1537fc08a01aSHariprasad Shenai } 1538fc08a01aSHariprasad Shenai 153994cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 154094cdb8bbSHariprasad Shenai unsigned int cnt); 154194cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 154294cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 154394cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 154494cdb8bbSHariprasad Shenai { 154594cdb8bbSHariprasad Shenai q->adap = adap; 154694cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 154794cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 154894cdb8bbSHariprasad Shenai q->size = size; 154994cdb8bbSHariprasad Shenai } 155094cdb8bbSHariprasad Shenai 1551f56ec676SArjun Vynipadath /** 1552f56ec676SArjun Vynipadath * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1553f56ec676SArjun Vynipadath * @fw_mod_type: the Firmware Mofule Type 1554f56ec676SArjun Vynipadath * 1555f56ec676SArjun Vynipadath * Return whether the Firmware Module Type represents a real Transceiver 1556f56ec676SArjun Vynipadath * Module/Cable Module Type which has been inserted. 1557f56ec676SArjun Vynipadath */ 1558f56ec676SArjun Vynipadath static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1559f56ec676SArjun Vynipadath { 1560f56ec676SArjun Vynipadath return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1561f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1562f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1563f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1564f56ec676SArjun Vynipadath } 1565f56ec676SArjun Vynipadath 156613ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 156713ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 156813ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1569f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1570f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1571f2b7e78dSVipul Pandya unsigned int start_idx); 15720abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1573f2b7e78dSVipul Pandya 1574f2b7e78dSVipul Pandya struct fw_filter_wr; 1575f2b7e78dSVipul Pandya 1576f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1577f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1578f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1579f7917c00SJeff Kirsher 15808203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 15818156b0baSGanesh Goudar 15829f764898SVishal Kulkarni fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 15839f764898SVishal Kulkarni struct link_config *lc); 15848156b0baSGanesh Goudar int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 15858156b0baSGanesh Goudar unsigned int port, struct link_config *lc, 15869f764898SVishal Kulkarni u8 sleep_ok, int timeout); 15878156b0baSGanesh Goudar 15888156b0baSGanesh Goudar static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 15898156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 15908156b0baSGanesh Goudar { 15918156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 15928156b0baSGanesh Goudar true, FW_CMD_MAX_TIMEOUT); 15938156b0baSGanesh Goudar } 15948156b0baSGanesh Goudar 15958156b0baSGanesh Goudar static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 15968156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 15978156b0baSGanesh Goudar { 15988156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 15998156b0baSGanesh Goudar false, FW_CMD_MAX_TIMEOUT); 16008156b0baSGanesh Goudar } 16018156b0baSGanesh Goudar 1602f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1603fc5ab020SHariprasad Shenai 1604b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1605b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1606b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1607b562fc37SHariprasad Shenai 16081a4330cdSRahul Lakkireddy int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 16091a4330cdSRahul Lakkireddy u32 *mem_base, u32 *mem_aperture); 16101a4330cdSRahul Lakkireddy void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 16111a4330cdSRahul Lakkireddy void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 16121a4330cdSRahul Lakkireddy int dir); 1613fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1614fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1615fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1616f01aa633SHariprasad Shenai void *buf, int dir); 1617fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1618fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1619fc5ab020SHariprasad Shenai { 1620fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1621fc5ab020SHariprasad Shenai } 1622fc5ab020SHariprasad Shenai 1623812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1624812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1625812034f1SHariprasad Shenai 1626940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1627f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1628098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1629098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 16300eaec62aSCasey Leedom int t4_get_pfres(struct adapter *adapter); 163149216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 163249216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1633f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 163401b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 163501b69614SHariprasad Shenai int win, spinlock_t *lock, 163601b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 163701b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 163801b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 163949216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 164022c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 164122c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1642acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1643636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1644a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 16454da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 164616e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 16470de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 164816e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1649ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1650760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1651760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1652760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1653760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 165416e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 165516e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 165616e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1657f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 16583be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1659e85c9a7aSHariprasad Shenai 1660e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1661b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1662e85c9a7aSHariprasad Shenai unsigned int qid, 1663e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 166466cf188eSHariprasad S int user, 1665e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1666e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1667e85c9a7aSHariprasad Shenai 1668dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1669dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1670ae469b68SHariprasad Shenai 1671ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1672e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 16735ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1674dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1675c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1676c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1677c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1678f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1679f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1680f988008aSGanesh Goudar unsigned int t4_chip_rss_size(struct adapter *adapter); 1681f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1682f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1683f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1684f7917c00SJeff Kirsher unsigned int flags); 1685c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1686c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1687688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 16885ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 16895ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 16905ccf9d04SRahul Lakkireddy bool sleep_ok); 1691688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 16925ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1693688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 16945ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 16955ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 16965ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1697688ea5feSHariprasad Shenai 1698193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1699193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1700b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1701b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1702e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1703e5f0e43bSHariprasad Shenai size_t n); 1704c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1705c778af7dSHariprasad Shenai size_t n); 1706f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1707f1ff24aaSHariprasad Shenai unsigned int *valp); 1708f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1709f1ff24aaSHariprasad Shenai const unsigned int *valp); 1710f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 171119689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 171219689609SHariprasad Shenai unsigned int *pif_req_wrptr, 171319689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 171426fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 171574b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 171672aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1717f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1718a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1719a4cfd929SHariprasad Shenai struct port_stats *stats, 1720a4cfd929SHariprasad Shenai struct port_stats *offset); 172165046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1722f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1723bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1724636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1725636f9d37SVipul Pandya unsigned int mask, unsigned int val); 17262d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 17275ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 17285ccf9d04SRahul Lakkireddy bool sleep_ok); 17295ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 17305ccf9d04SRahul Lakkireddy bool sleep_ok); 17315ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 17325ccf9d04SRahul Lakkireddy bool sleep_ok); 17335ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 17345ccf9d04SRahul Lakkireddy bool sleep_ok); 1735f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 17365ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1737a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 17385ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1739f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1740f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1741f7917c00SJeff Kirsher 1742797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1743797ff0f5SHariprasad Shenai 17447864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1745f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1746f2b7e78dSVipul Pandya 1747f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1748f7917c00SJeff Kirsher const u8 *addr); 1749f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1750f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1751f7917c00SJeff Kirsher 1752f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1753f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1754f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1755f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1756f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1757636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1758636f9d37SVipul Pandya unsigned int cache_line_size); 1759636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1760f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1761f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1762f7917c00SJeff Kirsher u32 *val); 17638f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 17648f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 17658f46d467SArjun Vynipadath u32 *val); 176601b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1767f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 17688f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 176901b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1770688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1771688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 177201b69614SHariprasad Shenai const u32 *val, int timeout); 177301b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 177401b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1775688848b1SAnish Bhatt const u32 *val); 1776f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1777f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1778f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1779f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1780f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1781f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1782f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 178302d805dcSSantosh Rastapur unsigned int *rss_size, u8 *vivld, u8 *vin); 17844f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 17854f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 17864f3a0fcfSHariprasad Shenai unsigned int viid); 1787f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1788f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1789f7917c00SJeff Kirsher bool sleep_ok); 1790846eac3fSGanesh Goudar int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1791846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1792846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 179398f3697fSKumar Sanghvi int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 179498f3697fSKumar Sanghvi bool sleep_ok); 179598f3697fSKumar Sanghvi int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 179698f3697fSKumar Sanghvi const u8 *addr, const u8 *mask, unsigned int vni, 179798f3697fSKumar Sanghvi unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 179898f3697fSKumar Sanghvi bool sleep_ok); 1799846eac3fSGanesh Goudar int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1800846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1801846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 1802f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1803f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1804f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1805fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1806fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1807fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1808f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 180902d805dcSSantosh Rastapur int idx, const u8 *addr, bool persist, u8 *smt_idx); 1810f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1811f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1812688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1813688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1814e2f4f4e9SArjun Vynipadath int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1815e2f4f4e9SArjun Vynipadath struct port_info *pi, 1816e2f4f4e9SArjun Vynipadath bool rx_en, bool tx_en, bool dcb_en); 1817f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1818f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1819f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1820f7917c00SJeff Kirsher unsigned int nblinks); 1821f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1822f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1823f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1824f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1825ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1826ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1827ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1828f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1829f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1830f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1831f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1832f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1833f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1834f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1835f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1836f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1837736c3b94SRahul Lakkireddy int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1838d429005fSVishal Kulkarni int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 1839d429005fSVishal Kulkarni u16 *dbqtimers); 184023853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 18412061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1842c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1843c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1844f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1845881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1846881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 18478e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 18488e3d04fdSHariprasad Shenai int filter_index, int enable); 18498e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 18508e3d04fdSHariprasad Shenai int filter_index, int *enabled); 18518caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 18528caa1e84SVipul Pandya u32 addr, u32 val); 185308c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 185408c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 185508c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 18569e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 18579e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 18589e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 18599e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 1860b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1861b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1862b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 186368bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1864a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1865a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1866a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1867a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1868a3bfb617SHariprasad Shenai int hz, int ticks); 1869858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1870858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 18715ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 18725ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 18734359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 18744359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 18755ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 18765ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 18775ccf9d04SRahul Lakkireddy 18780fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 18790fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 18800fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 18810fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 1882f56ec676SArjun Vynipadath int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1883f56ec676SArjun Vynipadath unsigned int devid, unsigned int offset, 1884f56ec676SArjun Vynipadath unsigned int len, u8 *buf); 188594cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1886ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1887ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1888ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1889a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 1890a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 1891a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1892a6ec572bSAtul Gupta dma_addr_t *addr); 1893a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1894a6ec572bSAtul Gupta void *pos); 1895a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1896a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1897a6ec572bSAtul Gupta const dma_addr_t *addr); 1898a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 18999d5fd927SGanesh Goudar int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 19009d5fd927SGanesh Goudar u16 vlan); 1901ebddd97aSGanesh Goudar int cxgb4_dcb_enabled(const struct net_device *dev); 1902b1871915SGanesh Goudar 1903b1871915SGanesh Goudar int cxgb4_thermal_init(struct adapter *adap); 1904b1871915SGanesh Goudar int cxgb4_thermal_remove(struct adapter *adap); 1905c9765074SNirranjan Kirubaharan int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 1906c9765074SNirranjan Kirubaharan cpumask_var_t *aff_mask, int idx); 1907c9765074SNirranjan Kirubaharan void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 1908b1871915SGanesh Goudar 1909f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1910