1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4ce100b8bSAnish Bhatt * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 505e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 51f7917c00SJeff Kirsher #include <asm/io.h> 5227999805SHariprasad S #include "t4_chip_type.h" 53f7917c00SJeff Kirsher #include "cxgb4_uld.h" 54f7917c00SJeff Kirsher 553069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 563069ee9bSVipul Pandya 57f7917c00SJeff Kirsher enum { 58f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 59f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 60f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 61f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 62a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 63098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 64f7917c00SJeff Kirsher }; 65f7917c00SJeff Kirsher 66f7917c00SJeff Kirsher enum { 67812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 68812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 69812034f1SHariprasad Shenai }; 70812034f1SHariprasad Shenai 71812034f1SHariprasad Shenai enum { 72f7917c00SJeff Kirsher MEM_EDC0, 73f7917c00SJeff Kirsher MEM_EDC1, 742422d9a3SSantosh Rastapur MEM_MC, 752422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 762422d9a3SSantosh Rastapur MEM_MC1 77f7917c00SJeff Kirsher }; 78f7917c00SJeff Kirsher 793069ee9bSVipul Pandya enum { 803eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 813eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 823069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 833069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 842422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 853eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 863eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 870abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 880abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 893069ee9bSVipul Pandya }; 903069ee9bSVipul Pandya 91f7917c00SJeff Kirsher enum dev_master { 92f7917c00SJeff Kirsher MASTER_CANT, 93f7917c00SJeff Kirsher MASTER_MAY, 94f7917c00SJeff Kirsher MASTER_MUST 95f7917c00SJeff Kirsher }; 96f7917c00SJeff Kirsher 97f7917c00SJeff Kirsher enum dev_state { 98f7917c00SJeff Kirsher DEV_STATE_UNINIT, 99f7917c00SJeff Kirsher DEV_STATE_INIT, 100f7917c00SJeff Kirsher DEV_STATE_ERR 101f7917c00SJeff Kirsher }; 102f7917c00SJeff Kirsher 103f7917c00SJeff Kirsher enum { 104f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 105f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 106f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 107f7917c00SJeff Kirsher }; 108f7917c00SJeff Kirsher 109f7917c00SJeff Kirsher struct port_stats { 110f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 111f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 112f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 113f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 114f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 115f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 116f7917c00SJeff Kirsher 117f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 118f7917c00SJeff Kirsher u64 tx_frames_65_127; 119f7917c00SJeff Kirsher u64 tx_frames_128_255; 120f7917c00SJeff Kirsher u64 tx_frames_256_511; 121f7917c00SJeff Kirsher u64 tx_frames_512_1023; 122f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 123f7917c00SJeff Kirsher u64 tx_frames_1519_max; 124f7917c00SJeff Kirsher 125f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 126f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 127f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 128f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 129f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 130f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 131f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 132f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 133f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 134f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 135f7917c00SJeff Kirsher 136f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 137f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 138f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 139f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 140f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 141f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 142f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 143f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 144f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 145f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 146f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 147f7917c00SJeff Kirsher 148f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 149f7917c00SJeff Kirsher u64 rx_frames_65_127; 150f7917c00SJeff Kirsher u64 rx_frames_128_255; 151f7917c00SJeff Kirsher u64 rx_frames_256_511; 152f7917c00SJeff Kirsher u64 rx_frames_512_1023; 153f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 154f7917c00SJeff Kirsher u64 rx_frames_1519_max; 155f7917c00SJeff Kirsher 156f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 157f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 158f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 159f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 160f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 161f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 162f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 163f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 164f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 165f7917c00SJeff Kirsher 166f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 167f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 168f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 169f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 170f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 171f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 172f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 173f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 174f7917c00SJeff Kirsher }; 175f7917c00SJeff Kirsher 176f7917c00SJeff Kirsher struct lb_port_stats { 177f7917c00SJeff Kirsher u64 octets; 178f7917c00SJeff Kirsher u64 frames; 179f7917c00SJeff Kirsher u64 bcast_frames; 180f7917c00SJeff Kirsher u64 mcast_frames; 181f7917c00SJeff Kirsher u64 ucast_frames; 182f7917c00SJeff Kirsher u64 error_frames; 183f7917c00SJeff Kirsher 184f7917c00SJeff Kirsher u64 frames_64; 185f7917c00SJeff Kirsher u64 frames_65_127; 186f7917c00SJeff Kirsher u64 frames_128_255; 187f7917c00SJeff Kirsher u64 frames_256_511; 188f7917c00SJeff Kirsher u64 frames_512_1023; 189f7917c00SJeff Kirsher u64 frames_1024_1518; 190f7917c00SJeff Kirsher u64 frames_1519_max; 191f7917c00SJeff Kirsher 192f7917c00SJeff Kirsher u64 drop; 193f7917c00SJeff Kirsher 194f7917c00SJeff Kirsher u64 ovflow0; 195f7917c00SJeff Kirsher u64 ovflow1; 196f7917c00SJeff Kirsher u64 ovflow2; 197f7917c00SJeff Kirsher u64 ovflow3; 198f7917c00SJeff Kirsher u64 trunc0; 199f7917c00SJeff Kirsher u64 trunc1; 200f7917c00SJeff Kirsher u64 trunc2; 201f7917c00SJeff Kirsher u64 trunc3; 202f7917c00SJeff Kirsher }; 203f7917c00SJeff Kirsher 204f7917c00SJeff Kirsher struct tp_tcp_stats { 205a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 206a4cfd929SHariprasad Shenai u64 tcp_in_segs; 207a4cfd929SHariprasad Shenai u64 tcp_out_segs; 208a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 209a4cfd929SHariprasad Shenai }; 210a4cfd929SHariprasad Shenai 211a4cfd929SHariprasad Shenai struct tp_usm_stats { 212a4cfd929SHariprasad Shenai u32 frames; 213a4cfd929SHariprasad Shenai u32 drops; 214a4cfd929SHariprasad Shenai u64 octets; 215f7917c00SJeff Kirsher }; 216f7917c00SJeff Kirsher 217a6222975SHariprasad Shenai struct tp_fcoe_stats { 218a6222975SHariprasad Shenai u32 frames_ddp; 219a6222975SHariprasad Shenai u32 frames_drop; 220a6222975SHariprasad Shenai u64 octets_ddp; 221f7917c00SJeff Kirsher }; 222f7917c00SJeff Kirsher 223f7917c00SJeff Kirsher struct tp_err_stats { 224a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 225a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 226a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 227a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 228a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 229a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 230a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 231a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 232a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 233a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 234a4cfd929SHariprasad Shenai }; 235a4cfd929SHariprasad Shenai 236a6222975SHariprasad Shenai struct tp_cpl_stats { 237a6222975SHariprasad Shenai u32 req[4]; 238a6222975SHariprasad Shenai u32 rsp[4]; 239a6222975SHariprasad Shenai }; 240a6222975SHariprasad Shenai 241a4cfd929SHariprasad Shenai struct tp_rdma_stats { 242a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 243a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 244f7917c00SJeff Kirsher }; 245f7917c00SJeff Kirsher 246e85c9a7aSHariprasad Shenai struct sge_params { 247e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 248e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 249e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 250e85c9a7aSHariprasad Shenai }; 251e85c9a7aSHariprasad Shenai 252f7917c00SJeff Kirsher struct tp_params { 253f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2542d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 255dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 256dca4faebSVipul Pandya /* channel map */ 257636f9d37SVipul Pandya 258636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 259636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 260dcf7b6f5SKumar Sanghvi 261dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 262dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 263dcf7b6f5SKumar Sanghvi 264dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 265dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 266dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 267dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 268dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 269dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 270dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 271dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 272dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 273dcf7b6f5SKumar Sanghvi * present. 274dcf7b6f5SKumar Sanghvi */ 275dcf7b6f5SKumar Sanghvi int vlan_shift; 276dcf7b6f5SKumar Sanghvi int vnic_shift; 277dcf7b6f5SKumar Sanghvi int port_shift; 278dcf7b6f5SKumar Sanghvi int protocol_shift; 279f7917c00SJeff Kirsher }; 280f7917c00SJeff Kirsher 281f7917c00SJeff Kirsher struct vpd_params { 282f7917c00SJeff Kirsher unsigned int cclk; 283f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 284f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 285f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 286a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 287098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 288f7917c00SJeff Kirsher }; 289f7917c00SJeff Kirsher 290f7917c00SJeff Kirsher struct pci_params { 291f7917c00SJeff Kirsher unsigned char speed; 292f7917c00SJeff Kirsher unsigned char width; 293f7917c00SJeff Kirsher }; 294f7917c00SJeff Kirsher 29549aa284fSHariprasad Shenai struct devlog_params { 29649aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 29749aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 29849aa284fSHariprasad Shenai u32 size; /* size of log */ 29949aa284fSHariprasad Shenai }; 30049aa284fSHariprasad Shenai 3013ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3023ccc6cf7SHariprasad Shenai struct arch_specific_params { 3033ccc6cf7SHariprasad Shenai u8 nchan; 30444588560SHariprasad Shenai u8 pm_stats_cnt; 3052216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3063ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3073ccc6cf7SHariprasad Shenai u16 vfcount; 3083ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3093ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3103ccc6cf7SHariprasad Shenai }; 3113ccc6cf7SHariprasad Shenai 312f7917c00SJeff Kirsher struct adapter_params { 313e85c9a7aSHariprasad Shenai struct sge_params sge; 314f7917c00SJeff Kirsher struct tp_params tp; 315f7917c00SJeff Kirsher struct vpd_params vpd; 316f7917c00SJeff Kirsher struct pci_params pci; 31749aa284fSHariprasad Shenai struct devlog_params devlog; 31849aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 319f7917c00SJeff Kirsher 320f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 321f1ff24aaSHariprasad Shenai 322f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 323f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 324f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 325f7917c00SJeff Kirsher 326f7917c00SJeff Kirsher unsigned int fw_vers; 3270de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 328f7917c00SJeff Kirsher unsigned int tp_vers; 3290de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 330f7917c00SJeff Kirsher u8 api_vers[7]; 331f7917c00SJeff Kirsher 332f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 333f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 334f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 335f7917c00SJeff Kirsher 336f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 337f7917c00SJeff Kirsher unsigned char portvec; 338d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3393ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 340f7917c00SJeff Kirsher unsigned char offload; 341f7917c00SJeff Kirsher 3429a4da2cdSVipul Pandya unsigned char bypass; 3439a4da2cdSVipul Pandya 344f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3451ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3464c2c5763SHariprasad Shenai 3474c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3484c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 349f7917c00SJeff Kirsher }; 350f7917c00SJeff Kirsher 351a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 352a3bfb617SHariprasad Shenai * and possible hangs. 353a3bfb617SHariprasad Shenai */ 354a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 355a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 356a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 357a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 358a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 359a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 360a3bfb617SHariprasad Shenai }; 361a3bfb617SHariprasad Shenai 36216e47624SHariprasad Shenai #include "t4fw_api.h" 36316e47624SHariprasad Shenai 36416e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 365b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 366b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 367b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 368b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 36916e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 37016e47624SHariprasad Shenai 37116e47624SHariprasad Shenai struct fw_info { 37216e47624SHariprasad Shenai u8 chip; 37316e47624SHariprasad Shenai char *fs_name; 37416e47624SHariprasad Shenai char *fw_mod_name; 37516e47624SHariprasad Shenai struct fw_hdr fw_hdr; 37616e47624SHariprasad Shenai }; 37716e47624SHariprasad Shenai 37816e47624SHariprasad Shenai 379f7917c00SJeff Kirsher struct trace_params { 380f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 381f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 382f7917c00SJeff Kirsher unsigned short snap_len; 383f7917c00SJeff Kirsher unsigned short min_len; 384f7917c00SJeff Kirsher unsigned char skip_ofst; 385f7917c00SJeff Kirsher unsigned char skip_len; 386f7917c00SJeff Kirsher unsigned char invert; 387f7917c00SJeff Kirsher unsigned char port; 388f7917c00SJeff Kirsher }; 389f7917c00SJeff Kirsher 390f7917c00SJeff Kirsher struct link_config { 391f7917c00SJeff Kirsher unsigned short supported; /* link capabilities */ 392f7917c00SJeff Kirsher unsigned short advertising; /* advertised capabilities */ 393f7917c00SJeff Kirsher unsigned short requested_speed; /* speed user has requested */ 394f7917c00SJeff Kirsher unsigned short speed; /* actual link speed */ 395f7917c00SJeff Kirsher unsigned char requested_fc; /* flow control user has requested */ 396f7917c00SJeff Kirsher unsigned char fc; /* actual link flow control */ 397f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 398f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 399f7917c00SJeff Kirsher }; 400f7917c00SJeff Kirsher 401e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 402f7917c00SJeff Kirsher 403f7917c00SJeff Kirsher enum { 404f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 405f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 406f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 407f7917c00SJeff Kirsher MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 408f36e58e5SHariprasad Shenai MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ 409f2692d16SVarun Prakash 410f2692d16SVarun Prakash /* # of streaming iSCSIT Rx queues */ 411f2692d16SVarun Prakash MAX_ISCSIT_QUEUES = MAX_OFLD_QSETS, 412f7917c00SJeff Kirsher }; 413f7917c00SJeff Kirsher 414f7917c00SJeff Kirsher enum { 415812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 416812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 417812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 418812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 419812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 420812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 421812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 422812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 423812034f1SHariprasad Shenai }; 424812034f1SHariprasad Shenai 425812034f1SHariprasad Shenai enum { 426cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 427cf38be6dSHariprasad Shenai /* forwarded interrupts */ 428f2692d16SVarun Prakash MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES + 429f2692d16SVarun Prakash MAX_RDMA_CIQS + MAX_ISCSIT_QUEUES + INGQ_EXTRAS, 430f7917c00SJeff Kirsher }; 431f7917c00SJeff Kirsher 432f7917c00SJeff Kirsher struct adapter; 433f7917c00SJeff Kirsher struct sge_rspq; 434f7917c00SJeff Kirsher 435688848b1SAnish Bhatt #include "cxgb4_dcb.h" 436688848b1SAnish Bhatt 43776fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 43876fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 43976fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 44076fed8a9SVarun Prakash 441f7917c00SJeff Kirsher struct port_info { 442f7917c00SJeff Kirsher struct adapter *adapter; 443f7917c00SJeff Kirsher u16 viid; 444f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 445f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 446f7917c00SJeff Kirsher s8 mdio_addr; 44740e9de4bSHariprasad Shenai enum fw_port_type port_type; 448f7917c00SJeff Kirsher u8 mod_type; 449f7917c00SJeff Kirsher u8 port_id; 450f7917c00SJeff Kirsher u8 tx_chan; 451f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 452f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 453f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 454f7917c00SJeff Kirsher u8 rss_mode; 455f7917c00SJeff Kirsher struct link_config link_cfg; 456f7917c00SJeff Kirsher u16 *rss; 457a4cfd929SHariprasad Shenai struct port_stats stats_base; 458688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 459688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 460688848b1SAnish Bhatt #endif 46176fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 46276fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 46376fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 4645e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 4655e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 466f7917c00SJeff Kirsher }; 467f7917c00SJeff Kirsher 468f7917c00SJeff Kirsher struct dentry; 469f7917c00SJeff Kirsher struct work_struct; 470f7917c00SJeff Kirsher 471f7917c00SJeff Kirsher enum { /* adapter flags */ 472f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 473144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 474144be3d9SGavin Shan USING_MSI = (1 << 2), 475144be3d9SGavin Shan USING_MSIX = (1 << 3), 476f7917c00SJeff Kirsher FW_OK = (1 << 4), 47713ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 47852367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 47952367a76SVipul Pandya MASTER_PF = (1 << 7), 48052367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 481f7917c00SJeff Kirsher }; 482f7917c00SJeff Kirsher 483f7917c00SJeff Kirsher struct rx_sw_desc; 484f7917c00SJeff Kirsher 485f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 486f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 487f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 488f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 489f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 490f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 491f7917c00SJeff Kirsher unsigned long large_alloc_failed; 49270055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 49370055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 494f7917c00SJeff Kirsher unsigned long starving; 495f7917c00SJeff Kirsher /* RO fields */ 496f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 497f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 498f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 499f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 500f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 501df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 502df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 503f7917c00SJeff Kirsher }; 504f7917c00SJeff Kirsher 505f7917c00SJeff Kirsher /* A packet gather list */ 506f7917c00SJeff Kirsher struct pkt_gl { 5075e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 508e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 509f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 510f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 511f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 512f7917c00SJeff Kirsher }; 513f7917c00SJeff Kirsher 514f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 515f7917c00SJeff Kirsher const struct pkt_gl *gl); 5162337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 5172337ba42SVarun Prakash /* LRO related declarations for ULD */ 5182337ba42SVarun Prakash struct t4_lro_mgr { 5192337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 5202337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 5212337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 5222337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 5232337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 5242337ba42SVarun Prakash }; 525f7917c00SJeff Kirsher 526f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 527f7917c00SJeff Kirsher struct napi_struct napi; 528f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 529f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 530f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 531f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 532f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 533e553ec3fSHariprasad Shenai u8 adaptive_rx; 534f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 535f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 536f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 537f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 538f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 539f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 540f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 541f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 542df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 543df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 544f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 545f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 546f7917c00SJeff Kirsher struct adapter *adap; 547f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 548f7917c00SJeff Kirsher rspq_handler_t handler; 5492337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 5502337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 5513a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 5523a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_IDLE 0 5533a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 5543a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 5553a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 5563a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 5573a336cb1SHariprasad Shenai #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 5583a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5593a336cb1SHariprasad Shenai #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 5603a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL) 5613a336cb1SHariprasad Shenai #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 5623a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5633a336cb1SHariprasad Shenai unsigned int bpoll_state; 5643a336cb1SHariprasad Shenai spinlock_t bpoll_lock; /* lock for busy poll */ 5653a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 5663a336cb1SHariprasad Shenai 567f7917c00SJeff Kirsher }; 568f7917c00SJeff Kirsher 569f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 570f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 571f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 572f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 573f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 574f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 575f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 576f7917c00SJeff Kirsher }; 577f7917c00SJeff Kirsher 578f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 579f7917c00SJeff Kirsher struct sge_rspq rspq; 580f7917c00SJeff Kirsher struct sge_fl fl; 581f7917c00SJeff Kirsher struct sge_eth_stats stats; 582f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 583f7917c00SJeff Kirsher 584f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 585f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 586f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 587f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 588f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 589f7917c00SJeff Kirsher }; 590f7917c00SJeff Kirsher 591f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 592f7917c00SJeff Kirsher struct sge_rspq rspq; 593f7917c00SJeff Kirsher struct sge_fl fl; 594f7917c00SJeff Kirsher struct sge_ofld_stats stats; 595f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 596f7917c00SJeff Kirsher 597f7917c00SJeff Kirsher struct tx_desc { 598f7917c00SJeff Kirsher __be64 flit[8]; 599f7917c00SJeff Kirsher }; 600f7917c00SJeff Kirsher 601f7917c00SJeff Kirsher struct tx_sw_desc; 602f7917c00SJeff Kirsher 603f7917c00SJeff Kirsher struct sge_txq { 604f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 605f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 606f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 607f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 608f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 609f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 610f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 611f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 612f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 613f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 614f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 6153069ee9bSVipul Pandya spinlock_t db_lock; 6163069ee9bSVipul Pandya int db_disabled; 6173069ee9bSVipul Pandya unsigned short db_pidx; 61805eb2389SSteve Wise unsigned short db_pidx_inc; 619df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 620df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 621f7917c00SJeff Kirsher }; 622f7917c00SJeff Kirsher 623f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 624f7917c00SJeff Kirsher struct sge_txq q; 625f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 62610b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 62710b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 62810b00466SAnish Bhatt #endif 629f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 630f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 631f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 632f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 633f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 634f7917c00SJeff Kirsher 635f7917c00SJeff Kirsher struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 636f7917c00SJeff Kirsher struct sge_txq q; 637f7917c00SJeff Kirsher struct adapter *adap; 638f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 639f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 640126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 641f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 642f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 643f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 644f7917c00SJeff Kirsher 645f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 646f7917c00SJeff Kirsher struct sge_txq q; 647f7917c00SJeff Kirsher struct adapter *adap; 648f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 649f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 650f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 651f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 652f7917c00SJeff Kirsher 653f7917c00SJeff Kirsher struct sge { 654f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 655f7917c00SJeff Kirsher struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 656f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 657f7917c00SJeff Kirsher 658f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 659f90ce561SHariprasad Shenai struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS]; 660f2692d16SVarun Prakash struct sge_ofld_rxq iscsitrxq[MAX_ISCSIT_QUEUES]; 661f7917c00SJeff Kirsher struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 662cf38be6dSHariprasad Shenai struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 663f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 664f7917c00SJeff Kirsher 665f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 666f7917c00SJeff Kirsher spinlock_t intrq_lock; 667f7917c00SJeff Kirsher 668f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 669f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 670f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 671f90ce561SHariprasad Shenai u16 iscsiqsets; /* # of active iSCSI queue sets */ 672f2692d16SVarun Prakash u16 niscsitq; /* # of available iSCST Rx queues */ 673f7917c00SJeff Kirsher u16 rdmaqs; /* # of available RDMA Rx queues */ 674cf38be6dSHariprasad Shenai u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 675f90ce561SHariprasad Shenai u16 iscsi_rxq[MAX_OFLD_QSETS]; 676f2692d16SVarun Prakash u16 iscsit_rxq[MAX_ISCSIT_QUEUES]; 677f36e58e5SHariprasad Shenai u16 rdma_rxq[MAX_RDMA_QUEUES]; 678f36e58e5SHariprasad Shenai u16 rdma_ciq[MAX_RDMA_CIQS]; 679f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 680f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 68152367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 68252367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 68352367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 68452367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 68552367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 6860f4d201fSKumar Sanghvi 687a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 688f7917c00SJeff Kirsher unsigned int egr_start; 6894b8e27a8SHariprasad Shenai unsigned int egr_sz; 690f7917c00SJeff Kirsher unsigned int ingr_start; 6914b8e27a8SHariprasad Shenai unsigned int ingr_sz; 6924b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 6934b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 6944b8e27a8SHariprasad Shenai unsigned long *starving_fl; 6954b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 6965b377d11SHariprasad Shenai unsigned long *blocked_fl; 697f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 698f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 699f7917c00SJeff Kirsher }; 700f7917c00SJeff Kirsher 701f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 702f90ce561SHariprasad Shenai #define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++) 703f2692d16SVarun Prakash #define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++) 704f7917c00SJeff Kirsher #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 705cf38be6dSHariprasad Shenai #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 706f7917c00SJeff Kirsher 707f7917c00SJeff Kirsher struct l2t_data; 708f7917c00SJeff Kirsher 7092422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 7102422d9a3SSantosh Rastapur 7117d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 7127d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 7137d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 7142422d9a3SSantosh Rastapur */ 7157d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 7162422d9a3SSantosh Rastapur 7172422d9a3SSantosh Rastapur #endif 7182422d9a3SSantosh Rastapur 719a4cfd929SHariprasad Shenai struct doorbell_stats { 720a4cfd929SHariprasad Shenai u32 db_drop; 721a4cfd929SHariprasad Shenai u32 db_empty; 722a4cfd929SHariprasad Shenai u32 db_full; 723a4cfd929SHariprasad Shenai }; 724a4cfd929SHariprasad Shenai 725fc08a01aSHariprasad Shenai struct hash_mac_addr { 726fc08a01aSHariprasad Shenai struct list_head list; 727fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 728fc08a01aSHariprasad Shenai }; 729fc08a01aSHariprasad Shenai 730f7917c00SJeff Kirsher struct adapter { 731f7917c00SJeff Kirsher void __iomem *regs; 73222adfe0aSSantosh Rastapur void __iomem *bar2; 7330abfd152SHariprasad Shenai u32 t4_bar0; 734f7917c00SJeff Kirsher struct pci_dev *pdev; 735f7917c00SJeff Kirsher struct device *pdev_dev; 7360de72738SHariprasad Shenai const char *name; 7373069ee9bSVipul Pandya unsigned int mbox; 738b2612722SHariprasad Shenai unsigned int pf; 739f7917c00SJeff Kirsher unsigned int flags; 7402422d9a3SSantosh Rastapur enum chip_type chip; 741f7917c00SJeff Kirsher 742f7917c00SJeff Kirsher int msg_enable; 743f7917c00SJeff Kirsher 744f7917c00SJeff Kirsher struct adapter_params params; 745f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 746f7917c00SJeff Kirsher unsigned int swintr; 747f7917c00SJeff Kirsher 748f7917c00SJeff Kirsher struct { 749f7917c00SJeff Kirsher unsigned short vec; 750f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 751f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 752f7917c00SJeff Kirsher 753a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 754f7917c00SJeff Kirsher struct sge sge; 755f7917c00SJeff Kirsher 756f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 757f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 758f7917c00SJeff Kirsher 759793dad94SVipul Pandya u32 filter_mode; 760636f9d37SVipul Pandya unsigned int l2t_start; 761636f9d37SVipul Pandya unsigned int l2t_end; 762f7917c00SJeff Kirsher struct l2t_data *l2t; 763b5a02f50SAnish Bhatt unsigned int clipt_start; 764b5a02f50SAnish Bhatt unsigned int clipt_end; 765b5a02f50SAnish Bhatt struct clip_tbl *clipt; 766f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 767f7917c00SJeff Kirsher struct list_head list_node; 76801bcca68SVipul Pandya struct list_head rcu_node; 769fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 770f7917c00SJeff Kirsher 7717714cb9eSVarun Prakash void *iscsi_ppm; 7727714cb9eSVarun Prakash 773f7917c00SJeff Kirsher struct tid_info tids; 774f7917c00SJeff Kirsher void **tid_release_head; 775f7917c00SJeff Kirsher spinlock_t tid_release_lock; 77629aaee65SAnish Bhatt struct workqueue_struct *workq; 777f7917c00SJeff Kirsher struct work_struct tid_release_task; 778881806bcSVipul Pandya struct work_struct db_full_task; 779881806bcSVipul Pandya struct work_struct db_drop_task; 780f7917c00SJeff Kirsher bool tid_release_task_busy; 781f7917c00SJeff Kirsher 782f7917c00SJeff Kirsher struct dentry *debugfs_root; 783621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 784621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 7858e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 7868e3d04fdSHariprasad Shenai * used for all 4 filters. 7878e3d04fdSHariprasad Shenai */ 788f7917c00SJeff Kirsher 789f7917c00SJeff Kirsher spinlock_t stats_lock; 790fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 791f7917c00SJeff Kirsher }; 792f7917c00SJeff Kirsher 793f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 794f2b7e78dSVipul Pandya */ 795f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 796f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 797f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 798f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 799f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 800f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 801f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 802f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 803f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 804f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 805f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 806f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 807f2b7e78dSVipul Pandya 808f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 809f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 810f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 811f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 812f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 813f2b7e78dSVipul Pandya * matching rules are true. 814f2b7e78dSVipul Pandya * 815f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 816f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 817f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 818f2b7e78dSVipul Pandya * MPS match type) ... 819f2b7e78dSVipul Pandya * 820f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 821f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 822f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 823f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 824f2b7e78dSVipul Pandya */ 825f2b7e78dSVipul Pandya struct ch_filter_tuple { 826f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 827f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 828f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 829f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 830f2b7e78dSVipul Pandya * set of fields. 831f2b7e78dSVipul Pandya */ 832f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 833f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 834f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 835f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 836f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 837f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 838f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 839f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 840f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 841f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 842f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 843f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 844f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 845f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 846f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 847f2b7e78dSVipul Pandya 848f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 849f2b7e78dSVipul Pandya * available for field rules. 850f2b7e78dSVipul Pandya */ 851f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 852f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 853f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 854f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 855f2b7e78dSVipul Pandya }; 856f2b7e78dSVipul Pandya 857f2b7e78dSVipul Pandya /* A filter ioctl command. 858f2b7e78dSVipul Pandya */ 859f2b7e78dSVipul Pandya struct ch_filter_specification { 860f2b7e78dSVipul Pandya /* Administrative fields for filter. 861f2b7e78dSVipul Pandya */ 862f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 863f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 864f2b7e78dSVipul Pandya 865f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 866f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 867f2b7e78dSVipul Pandya */ 868f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 869f2b7e78dSVipul Pandya 870f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 871f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 872f2b7e78dSVipul Pandya * out as egress packets. 873f2b7e78dSVipul Pandya */ 874f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 875f2b7e78dSVipul Pandya 876f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 877f2b7e78dSVipul Pandya 878f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 879f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 880f2b7e78dSVipul Pandya 881f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 882f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 883f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 884f2b7e78dSVipul Pandya 885f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 886f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 887f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 888f2b7e78dSVipul Pandya */ 889f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 890f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 891f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 892f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 893f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 894f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 895f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 896f2b7e78dSVipul Pandya 897f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 898f2b7e78dSVipul Pandya */ 899f2b7e78dSVipul Pandya struct ch_filter_tuple val; 900f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 901f2b7e78dSVipul Pandya }; 902f2b7e78dSVipul Pandya 903f2b7e78dSVipul Pandya enum { 904f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 905f2b7e78dSVipul Pandya FILTER_DROP, 906f2b7e78dSVipul Pandya FILTER_SWITCH 907f2b7e78dSVipul Pandya }; 908f2b7e78dSVipul Pandya 909f2b7e78dSVipul Pandya enum { 910f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 911f2b7e78dSVipul Pandya VLAN_REMOVE, 912f2b7e78dSVipul Pandya VLAN_INSERT, 913f2b7e78dSVipul Pandya VLAN_REWRITE 914f2b7e78dSVipul Pandya }; 915f2b7e78dSVipul Pandya 916a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 917a4cfd929SHariprasad Shenai { 918a4cfd929SHariprasad Shenai return adap->params.offload; 919a4cfd929SHariprasad Shenai } 920a4cfd929SHariprasad Shenai 921f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 922f7917c00SJeff Kirsher { 923f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 924f7917c00SJeff Kirsher } 925f7917c00SJeff Kirsher 926f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 927f7917c00SJeff Kirsher { 928f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 929f7917c00SJeff Kirsher } 930f7917c00SJeff Kirsher 931f7917c00SJeff Kirsher #ifndef readq 932f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 933f7917c00SJeff Kirsher { 934f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 935f7917c00SJeff Kirsher } 936f7917c00SJeff Kirsher 937f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 938f7917c00SJeff Kirsher { 939f7917c00SJeff Kirsher writel(val, addr); 940f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 941f7917c00SJeff Kirsher } 942f7917c00SJeff Kirsher #endif 943f7917c00SJeff Kirsher 944f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 945f7917c00SJeff Kirsher { 946f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 947f7917c00SJeff Kirsher } 948f7917c00SJeff Kirsher 949f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 950f7917c00SJeff Kirsher { 951f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 952f7917c00SJeff Kirsher } 953f7917c00SJeff Kirsher 954f7917c00SJeff Kirsher /** 955098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 956098ef6c2SHariprasad Shenai * @adapter: the adapter 957098ef6c2SHariprasad Shenai * @port_idx: the port index 958098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 959098ef6c2SHariprasad Shenai * 960098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 961098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 962098ef6c2SHariprasad Shenai */ 963098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 964098ef6c2SHariprasad Shenai u8 hw_addr[]) 965098ef6c2SHariprasad Shenai { 966098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 967098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 968098ef6c2SHariprasad Shenai } 969098ef6c2SHariprasad Shenai 970098ef6c2SHariprasad Shenai /** 971f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 972f7917c00SJeff Kirsher * @dev: the netdev 973f7917c00SJeff Kirsher * 974f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 975f7917c00SJeff Kirsher */ 976f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 977f7917c00SJeff Kirsher { 978f7917c00SJeff Kirsher return netdev_priv(dev); 979f7917c00SJeff Kirsher } 980f7917c00SJeff Kirsher 981f7917c00SJeff Kirsher /** 982f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 983f7917c00SJeff Kirsher * @adap: the adapter 984f7917c00SJeff Kirsher * @idx: the port index 985f7917c00SJeff Kirsher * 986f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 987f7917c00SJeff Kirsher */ 988f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 989f7917c00SJeff Kirsher { 990f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 991f7917c00SJeff Kirsher } 992f7917c00SJeff Kirsher 993f7917c00SJeff Kirsher /** 994f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 995f7917c00SJeff Kirsher * @dev: the netdev 996f7917c00SJeff Kirsher * 997f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 998f7917c00SJeff Kirsher */ 999f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1000f7917c00SJeff Kirsher { 1001f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1002f7917c00SJeff Kirsher } 1003f7917c00SJeff Kirsher 10043a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 10053a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 10063a336cb1SHariprasad Shenai { 10073a336cb1SHariprasad Shenai spin_lock_init(&q->bpoll_lock); 10083a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 10093a336cb1SHariprasad Shenai } 10103a336cb1SHariprasad Shenai 10113a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 10123a336cb1SHariprasad Shenai { 10133a336cb1SHariprasad Shenai bool rc = true; 10143a336cb1SHariprasad Shenai 10153a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 10163a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 10173a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 10183a336cb1SHariprasad Shenai rc = false; 10193a336cb1SHariprasad Shenai } else { 10203a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_NAPI; 10213a336cb1SHariprasad Shenai } 10223a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 10233a336cb1SHariprasad Shenai return rc; 10243a336cb1SHariprasad Shenai } 10253a336cb1SHariprasad Shenai 10263a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 10273a336cb1SHariprasad Shenai { 10283a336cb1SHariprasad Shenai bool rc = false; 10293a336cb1SHariprasad Shenai 10303a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 10313a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 10323a336cb1SHariprasad Shenai rc = true; 10333a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 10343a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 10353a336cb1SHariprasad Shenai return rc; 10363a336cb1SHariprasad Shenai } 10373a336cb1SHariprasad Shenai 10383a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 10393a336cb1SHariprasad Shenai { 10403a336cb1SHariprasad Shenai bool rc = true; 10413a336cb1SHariprasad Shenai 10423a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 10433a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 10443a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 10453a336cb1SHariprasad Shenai rc = false; 10463a336cb1SHariprasad Shenai } else { 10473a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL; 10483a336cb1SHariprasad Shenai } 10493a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 10503a336cb1SHariprasad Shenai return rc; 10513a336cb1SHariprasad Shenai } 10523a336cb1SHariprasad Shenai 10533a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 10543a336cb1SHariprasad Shenai { 10553a336cb1SHariprasad Shenai bool rc = false; 10563a336cb1SHariprasad Shenai 10573a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 10583a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 10593a336cb1SHariprasad Shenai rc = true; 10603a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 10613a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 10623a336cb1SHariprasad Shenai return rc; 10633a336cb1SHariprasad Shenai } 10643a336cb1SHariprasad Shenai 10653a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 10663a336cb1SHariprasad Shenai { 10673a336cb1SHariprasad Shenai return q->bpoll_state & CXGB_POLL_USER_PEND; 10683a336cb1SHariprasad Shenai } 10693a336cb1SHariprasad Shenai #else 10703a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 10713a336cb1SHariprasad Shenai { 10723a336cb1SHariprasad Shenai } 10733a336cb1SHariprasad Shenai 10743a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 10753a336cb1SHariprasad Shenai { 10763a336cb1SHariprasad Shenai return true; 10773a336cb1SHariprasad Shenai } 10783a336cb1SHariprasad Shenai 10793a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 10803a336cb1SHariprasad Shenai { 10813a336cb1SHariprasad Shenai return false; 10823a336cb1SHariprasad Shenai } 10833a336cb1SHariprasad Shenai 10843a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 10853a336cb1SHariprasad Shenai { 10863a336cb1SHariprasad Shenai return false; 10873a336cb1SHariprasad Shenai } 10883a336cb1SHariprasad Shenai 10893a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 10903a336cb1SHariprasad Shenai { 10913a336cb1SHariprasad Shenai return false; 10923a336cb1SHariprasad Shenai } 10933a336cb1SHariprasad Shenai 10943a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 10953a336cb1SHariprasad Shenai { 10963a336cb1SHariprasad Shenai return false; 10973a336cb1SHariprasad Shenai } 10983a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 10993a336cb1SHariprasad Shenai 1100812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1101812034f1SHariprasad Shenai * - bits 0..9: chip version 1102812034f1SHariprasad Shenai * - bits 10..15: chip revision 1103812034f1SHariprasad Shenai * - bits 16..23: register dump version 1104812034f1SHariprasad Shenai */ 1105812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1106812034f1SHariprasad Shenai { 1107812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1108812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1109812034f1SHariprasad Shenai } 1110812034f1SHariprasad Shenai 1111812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1112812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1113812034f1SHariprasad Shenai const struct sge_rspq *q) 1114812034f1SHariprasad Shenai { 1115812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1116812034f1SHariprasad Shenai 1117812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1118812034f1SHariprasad Shenai } 1119812034f1SHariprasad Shenai 1120812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1121812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1122812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1123812034f1SHariprasad Shenai 1124f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1125f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1126f7917c00SJeff Kirsher 1127f7917c00SJeff Kirsher void *t4_alloc_mem(size_t size); 1128f7917c00SJeff Kirsher 1129f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 11305fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1131f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1132f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1133f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1134f7917c00SJeff Kirsher const struct pkt_gl *gl); 1135f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1136f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1137f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1138f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 11392337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 11402337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1141f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1142f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1143f7917c00SJeff Kirsher unsigned int iqid); 1144f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1145f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1146f7917c00SJeff Kirsher unsigned int cmplqid); 1147f7917c00SJeff Kirsher int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1148f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid); 1149f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 115052367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1151f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1152f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 11533a336cb1SHariprasad Shenai int cxgb_busy_poll(struct napi_struct *napi); 1154812034f1SHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1155812034f1SHariprasad Shenai unsigned int cnt); 1156812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1157812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 11583069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1159f7917c00SJeff Kirsher 1160f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1161f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1162f7917c00SJeff Kirsher 11639a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 11649a4da2cdSVipul Pandya { 11659a4da2cdSVipul Pandya return adap->params.bypass; 11669a4da2cdSVipul Pandya } 11679a4da2cdSVipul Pandya 11689a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 11699a4da2cdSVipul Pandya { 11709a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 11719a4da2cdSVipul Pandya switch (device) { 11729a4da2cdSVipul Pandya case 0x440b: 11739a4da2cdSVipul Pandya case 0x440c: 11749a4da2cdSVipul Pandya return 1; 11759a4da2cdSVipul Pandya default: 11769a4da2cdSVipul Pandya return 0; 11779a4da2cdSVipul Pandya } 11789a4da2cdSVipul Pandya } 11799a4da2cdSVipul Pandya 118001b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 118101b69614SHariprasad Shenai { 118201b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 118301b69614SHariprasad Shenai switch (device) { 118401b69614SHariprasad Shenai case 0x4409: 118501b69614SHariprasad Shenai case 0x4486: 118601b69614SHariprasad Shenai return 1; 118701b69614SHariprasad Shenai 118801b69614SHariprasad Shenai default: 118901b69614SHariprasad Shenai return 0; 119001b69614SHariprasad Shenai } 119101b69614SHariprasad Shenai } 119201b69614SHariprasad Shenai 1193f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1194f7917c00SJeff Kirsher { 1195f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1196f7917c00SJeff Kirsher } 1197f7917c00SJeff Kirsher 1198f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1199f7917c00SJeff Kirsher unsigned int us) 1200f7917c00SJeff Kirsher { 1201f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1202f7917c00SJeff Kirsher } 1203f7917c00SJeff Kirsher 120452367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 120552367a76SVipul Pandya unsigned int ticks) 120652367a76SVipul Pandya { 120752367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 120852367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 120952367a76SVipul Pandya adapter->params.vpd.cclk); 121052367a76SVipul Pandya } 121152367a76SVipul Pandya 1212f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1213f7917c00SJeff Kirsher u32 val); 1214f7917c00SJeff Kirsher 121501b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 121601b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1217f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1218f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1219f7917c00SJeff Kirsher 122001b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 122101b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 122201b69614SHariprasad Shenai int timeout) 122301b69614SHariprasad Shenai { 122401b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 122501b69614SHariprasad Shenai timeout); 122601b69614SHariprasad Shenai } 122701b69614SHariprasad Shenai 1228f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1229f7917c00SJeff Kirsher int size, void *rpl) 1230f7917c00SJeff Kirsher { 1231f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1232f7917c00SJeff Kirsher } 1233f7917c00SJeff Kirsher 1234f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1235f7917c00SJeff Kirsher int size, void *rpl) 1236f7917c00SJeff Kirsher { 1237f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1238f7917c00SJeff Kirsher } 1239f7917c00SJeff Kirsher 1240fc08a01aSHariprasad Shenai /** 1241fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1242fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1243fc08a01aSHariprasad Shenai * 1244fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1245fc08a01aSHariprasad Shenai * (hash) address matching. 1246fc08a01aSHariprasad Shenai */ 1247fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1248fc08a01aSHariprasad Shenai { 1249fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1250fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1251fc08a01aSHariprasad Shenai 1252fc08a01aSHariprasad Shenai a ^= b; 1253fc08a01aSHariprasad Shenai a ^= (a >> 12); 1254fc08a01aSHariprasad Shenai a ^= (a >> 6); 1255fc08a01aSHariprasad Shenai return a & 0x3f; 1256fc08a01aSHariprasad Shenai } 1257fc08a01aSHariprasad Shenai 125813ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 125913ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 126013ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1261f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1262f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1263f2b7e78dSVipul Pandya unsigned int start_idx); 12640abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1265f2b7e78dSVipul Pandya 1266f2b7e78dSVipul Pandya struct fw_filter_wr; 1267f2b7e78dSVipul Pandya 1268f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1269f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1270f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1271f7917c00SJeff Kirsher 12728203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 12734036da90SHariprasad Shenai int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1274f7917c00SJeff Kirsher struct link_config *lc); 1275f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1276fc5ab020SHariprasad Shenai 1277b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1278b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1279b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1280b562fc37SHariprasad Shenai 1281fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1282fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1283fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1284f01aa633SHariprasad Shenai void *buf, int dir); 1285fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1286fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1287fc5ab020SHariprasad Shenai { 1288fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1289fc5ab020SHariprasad Shenai } 1290fc5ab020SHariprasad Shenai 1291812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1292812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1293812034f1SHariprasad Shenai 1294f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1295098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1296098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 129749216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 129849216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1299f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 130001b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 130101b69614SHariprasad Shenai int win, spinlock_t *lock, 130201b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 130301b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 130401b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 130549216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 130622c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 130722c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1308acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1309636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1310a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 131116e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 13120de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 131316e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1314ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 131516e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 131616e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 131716e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1318f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 1319e85c9a7aSHariprasad Shenai 1320e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1321b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1322e85c9a7aSHariprasad Shenai unsigned int qid, 1323e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 132466cf188eSHariprasad S int user, 1325e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1326e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1327e85c9a7aSHariprasad Shenai 1328dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1329dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1330ae469b68SHariprasad Shenai 1331ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1332e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 1333dcf7b6f5SKumar Sanghvi int t4_init_tp_params(struct adapter *adap); 1334dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1335c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1336c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1337c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1338f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1339f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1340f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1341f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1342f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1343f7917c00SJeff Kirsher unsigned int flags); 1344c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1345c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1346688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 1347688ea5feSHariprasad Shenai void t4_read_rss_key(struct adapter *adapter, u32 *key); 1348688ea5feSHariprasad Shenai void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1349688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1350688ea5feSHariprasad Shenai u32 *valp); 1351688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1352688ea5feSHariprasad Shenai u32 *vfl, u32 *vfh); 1353688ea5feSHariprasad Shenai u32 t4_read_rss_pf_map(struct adapter *adapter); 1354688ea5feSHariprasad Shenai u32 t4_read_rss_pf_mask(struct adapter *adapter); 1355688ea5feSHariprasad Shenai 1356145ef8a5SHariprasad Shenai unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1357b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1358b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1359e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1360e5f0e43bSHariprasad Shenai size_t n); 1361c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1362c778af7dSHariprasad Shenai size_t n); 1363f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1364f1ff24aaSHariprasad Shenai unsigned int *valp); 1365f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1366f1ff24aaSHariprasad Shenai const unsigned int *valp); 1367f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 136819689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 136919689609SHariprasad Shenai unsigned int *pif_req_wrptr, 137019689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 137126fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 137274b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 137372aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1374f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1375a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1376a4cfd929SHariprasad Shenai struct port_stats *stats, 1377a4cfd929SHariprasad Shenai struct port_stats *offset); 137865046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1379f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1380bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1381636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1382636f9d37SVipul Pandya unsigned int mask, unsigned int val); 13832d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1384a4cfd929SHariprasad Shenai void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1385a6222975SHariprasad Shenai void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1386a4cfd929SHariprasad Shenai void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1387a4cfd929SHariprasad Shenai void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1388f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1389f7917c00SJeff Kirsher struct tp_tcp_stats *v6); 1390a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1391a6222975SHariprasad Shenai struct tp_fcoe_stats *st); 1392f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1393f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1394f7917c00SJeff Kirsher 1395797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1396797ff0f5SHariprasad Shenai 13977864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1398f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1399f2b7e78dSVipul Pandya 1400f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1401f7917c00SJeff Kirsher const u8 *addr); 1402f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1403f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1404f7917c00SJeff Kirsher 1405f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1406f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1407f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1408f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1409f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1410636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1411636f9d37SVipul Pandya unsigned int cache_line_size); 1412636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1413f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1414f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1415f7917c00SJeff Kirsher u32 *val); 141601b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1417f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 141801b69614SHariprasad Shenai u32 *val, int rw); 141901b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1420688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1421688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 142201b69614SHariprasad Shenai const u32 *val, int timeout); 142301b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 142401b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1425688848b1SAnish Bhatt const u32 *val); 1426f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1427f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1428f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1429f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1430f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1431f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1432f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1433f7917c00SJeff Kirsher unsigned int *rss_size); 14344f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 14354f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 14364f3a0fcfSHariprasad Shenai unsigned int viid); 1437f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1438f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1439f7917c00SJeff Kirsher bool sleep_ok); 1440f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1441f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1442f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1443fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1444fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1445fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1446f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1447f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1448f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1449f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1450688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1451688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1452f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1453f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1454f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1455f7917c00SJeff Kirsher unsigned int nblinks); 1456f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1457f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1458f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1459f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1460ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1461ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1462ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1463f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1464f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1465f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1466f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1467f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1468f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1469f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1470f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1471f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 14725d700ecbSHariprasad Shenai int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1473f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1474881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1475881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 14768e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 14778e3d04fdSHariprasad Shenai int filter_index, int enable); 14788e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 14798e3d04fdSHariprasad Shenai int filter_index, int *enabled); 14808caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 14818caa1e84SVipul Pandya u32 addr, u32 val); 148268bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1483fd88b31aSHariprasad Shenai void t4_free_mem(void *addr); 1484a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1485a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1486a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1487a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1488a3bfb617SHariprasad Shenai int hz, int ticks); 1489f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1490