1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4ce100b8bSAnish Bhatt * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49f7917c00SJeff Kirsher #include <asm/io.h> 50f7917c00SJeff Kirsher #include "cxgb4_uld.h" 51f7917c00SJeff Kirsher 523069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 533069ee9bSVipul Pandya 54f7917c00SJeff Kirsher enum { 55f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 56f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 57f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 58f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 59a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 60f7917c00SJeff Kirsher }; 61f7917c00SJeff Kirsher 62f7917c00SJeff Kirsher enum { 63812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 64812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 65812034f1SHariprasad Shenai }; 66812034f1SHariprasad Shenai 67812034f1SHariprasad Shenai enum { 68f7917c00SJeff Kirsher MEM_EDC0, 69f7917c00SJeff Kirsher MEM_EDC1, 702422d9a3SSantosh Rastapur MEM_MC, 712422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 722422d9a3SSantosh Rastapur MEM_MC1 73f7917c00SJeff Kirsher }; 74f7917c00SJeff Kirsher 753069ee9bSVipul Pandya enum { 763eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 773eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 783069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 793069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 802422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 813eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 823eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 830abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 840abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 853069ee9bSVipul Pandya }; 863069ee9bSVipul Pandya 87f7917c00SJeff Kirsher enum dev_master { 88f7917c00SJeff Kirsher MASTER_CANT, 89f7917c00SJeff Kirsher MASTER_MAY, 90f7917c00SJeff Kirsher MASTER_MUST 91f7917c00SJeff Kirsher }; 92f7917c00SJeff Kirsher 93f7917c00SJeff Kirsher enum dev_state { 94f7917c00SJeff Kirsher DEV_STATE_UNINIT, 95f7917c00SJeff Kirsher DEV_STATE_INIT, 96f7917c00SJeff Kirsher DEV_STATE_ERR 97f7917c00SJeff Kirsher }; 98f7917c00SJeff Kirsher 99f7917c00SJeff Kirsher enum { 100f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 101f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 102f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 103f7917c00SJeff Kirsher }; 104f7917c00SJeff Kirsher 105f7917c00SJeff Kirsher struct port_stats { 106f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 107f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 108f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 109f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 110f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 111f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 112f7917c00SJeff Kirsher 113f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 114f7917c00SJeff Kirsher u64 tx_frames_65_127; 115f7917c00SJeff Kirsher u64 tx_frames_128_255; 116f7917c00SJeff Kirsher u64 tx_frames_256_511; 117f7917c00SJeff Kirsher u64 tx_frames_512_1023; 118f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 119f7917c00SJeff Kirsher u64 tx_frames_1519_max; 120f7917c00SJeff Kirsher 121f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 122f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 123f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 124f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 125f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 126f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 127f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 128f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 129f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 130f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 131f7917c00SJeff Kirsher 132f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 133f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 134f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 135f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 136f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 137f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 138f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 139f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 140f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 141f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 142f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 143f7917c00SJeff Kirsher 144f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 145f7917c00SJeff Kirsher u64 rx_frames_65_127; 146f7917c00SJeff Kirsher u64 rx_frames_128_255; 147f7917c00SJeff Kirsher u64 rx_frames_256_511; 148f7917c00SJeff Kirsher u64 rx_frames_512_1023; 149f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 150f7917c00SJeff Kirsher u64 rx_frames_1519_max; 151f7917c00SJeff Kirsher 152f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 153f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 154f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 155f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 156f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 157f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 158f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 159f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 160f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 161f7917c00SJeff Kirsher 162f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 163f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 164f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 165f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 166f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 167f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 168f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 169f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 170f7917c00SJeff Kirsher }; 171f7917c00SJeff Kirsher 172f7917c00SJeff Kirsher struct lb_port_stats { 173f7917c00SJeff Kirsher u64 octets; 174f7917c00SJeff Kirsher u64 frames; 175f7917c00SJeff Kirsher u64 bcast_frames; 176f7917c00SJeff Kirsher u64 mcast_frames; 177f7917c00SJeff Kirsher u64 ucast_frames; 178f7917c00SJeff Kirsher u64 error_frames; 179f7917c00SJeff Kirsher 180f7917c00SJeff Kirsher u64 frames_64; 181f7917c00SJeff Kirsher u64 frames_65_127; 182f7917c00SJeff Kirsher u64 frames_128_255; 183f7917c00SJeff Kirsher u64 frames_256_511; 184f7917c00SJeff Kirsher u64 frames_512_1023; 185f7917c00SJeff Kirsher u64 frames_1024_1518; 186f7917c00SJeff Kirsher u64 frames_1519_max; 187f7917c00SJeff Kirsher 188f7917c00SJeff Kirsher u64 drop; 189f7917c00SJeff Kirsher 190f7917c00SJeff Kirsher u64 ovflow0; 191f7917c00SJeff Kirsher u64 ovflow1; 192f7917c00SJeff Kirsher u64 ovflow2; 193f7917c00SJeff Kirsher u64 ovflow3; 194f7917c00SJeff Kirsher u64 trunc0; 195f7917c00SJeff Kirsher u64 trunc1; 196f7917c00SJeff Kirsher u64 trunc2; 197f7917c00SJeff Kirsher u64 trunc3; 198f7917c00SJeff Kirsher }; 199f7917c00SJeff Kirsher 200f7917c00SJeff Kirsher struct tp_tcp_stats { 201f7917c00SJeff Kirsher u32 tcpOutRsts; 202f7917c00SJeff Kirsher u64 tcpInSegs; 203f7917c00SJeff Kirsher u64 tcpOutSegs; 204f7917c00SJeff Kirsher u64 tcpRetransSegs; 205f7917c00SJeff Kirsher }; 206f7917c00SJeff Kirsher 207f7917c00SJeff Kirsher struct tp_err_stats { 208f7917c00SJeff Kirsher u32 macInErrs[4]; 209f7917c00SJeff Kirsher u32 hdrInErrs[4]; 210f7917c00SJeff Kirsher u32 tcpInErrs[4]; 211f7917c00SJeff Kirsher u32 tnlCongDrops[4]; 212f7917c00SJeff Kirsher u32 ofldChanDrops[4]; 213f7917c00SJeff Kirsher u32 tnlTxDrops[4]; 214f7917c00SJeff Kirsher u32 ofldVlanDrops[4]; 215f7917c00SJeff Kirsher u32 tcp6InErrs[4]; 216f7917c00SJeff Kirsher u32 ofldNoNeigh; 217f7917c00SJeff Kirsher u32 ofldCongDefer; 218f7917c00SJeff Kirsher }; 219f7917c00SJeff Kirsher 220e85c9a7aSHariprasad Shenai struct sge_params { 221e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 222e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 223e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 224e85c9a7aSHariprasad Shenai }; 225e85c9a7aSHariprasad Shenai 226f7917c00SJeff Kirsher struct tp_params { 227f7917c00SJeff Kirsher unsigned int ntxchan; /* # of Tx channels */ 228f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2292d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 230dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 231dca4faebSVipul Pandya /* channel map */ 232636f9d37SVipul Pandya 233636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 234636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 235dcf7b6f5SKumar Sanghvi 236dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 237dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 238dcf7b6f5SKumar Sanghvi 239dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 240dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 241dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 242dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 243dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 244dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 245dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 246dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 247dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 248dcf7b6f5SKumar Sanghvi * present. 249dcf7b6f5SKumar Sanghvi */ 250dcf7b6f5SKumar Sanghvi int vlan_shift; 251dcf7b6f5SKumar Sanghvi int vnic_shift; 252dcf7b6f5SKumar Sanghvi int port_shift; 253dcf7b6f5SKumar Sanghvi int protocol_shift; 254f7917c00SJeff Kirsher }; 255f7917c00SJeff Kirsher 256f7917c00SJeff Kirsher struct vpd_params { 257f7917c00SJeff Kirsher unsigned int cclk; 258f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 259f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 260f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 261a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 262f7917c00SJeff Kirsher }; 263f7917c00SJeff Kirsher 264f7917c00SJeff Kirsher struct pci_params { 265f7917c00SJeff Kirsher unsigned char speed; 266f7917c00SJeff Kirsher unsigned char width; 267f7917c00SJeff Kirsher }; 268f7917c00SJeff Kirsher 269d14807ddSHariprasad Shenai #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) 270d14807ddSHariprasad Shenai #define CHELSIO_CHIP_FPGA 0x100 271d14807ddSHariprasad Shenai #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) 272d14807ddSHariprasad Shenai #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) 273d14807ddSHariprasad Shenai 274d14807ddSHariprasad Shenai #define CHELSIO_T4 0x4 275d14807ddSHariprasad Shenai #define CHELSIO_T5 0x5 276d14807ddSHariprasad Shenai 277d14807ddSHariprasad Shenai enum chip_type { 278d14807ddSHariprasad Shenai T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 279d14807ddSHariprasad Shenai T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), 280d14807ddSHariprasad Shenai T4_FIRST_REV = T4_A1, 281d14807ddSHariprasad Shenai T4_LAST_REV = T4_A2, 282d14807ddSHariprasad Shenai 283d14807ddSHariprasad Shenai T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 284d14807ddSHariprasad Shenai T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), 285d14807ddSHariprasad Shenai T5_FIRST_REV = T5_A0, 286d14807ddSHariprasad Shenai T5_LAST_REV = T5_A1, 287d14807ddSHariprasad Shenai }; 288d14807ddSHariprasad Shenai 28949aa284fSHariprasad Shenai struct devlog_params { 29049aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 29149aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 29249aa284fSHariprasad Shenai u32 size; /* size of log */ 29349aa284fSHariprasad Shenai }; 29449aa284fSHariprasad Shenai 295f7917c00SJeff Kirsher struct adapter_params { 296e85c9a7aSHariprasad Shenai struct sge_params sge; 297f7917c00SJeff Kirsher struct tp_params tp; 298f7917c00SJeff Kirsher struct vpd_params vpd; 299f7917c00SJeff Kirsher struct pci_params pci; 30049aa284fSHariprasad Shenai struct devlog_params devlog; 30149aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 302f7917c00SJeff Kirsher 303f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 304f1ff24aaSHariprasad Shenai 305f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 306f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 307f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 308f7917c00SJeff Kirsher 309f7917c00SJeff Kirsher unsigned int fw_vers; 310f7917c00SJeff Kirsher unsigned int tp_vers; 311f7917c00SJeff Kirsher u8 api_vers[7]; 312f7917c00SJeff Kirsher 313f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 314f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 315f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 316f7917c00SJeff Kirsher 317f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 318f7917c00SJeff Kirsher unsigned char portvec; 319d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 320f7917c00SJeff Kirsher unsigned char offload; 321f7917c00SJeff Kirsher 3229a4da2cdSVipul Pandya unsigned char bypass; 3239a4da2cdSVipul Pandya 324f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3251ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3264c2c5763SHariprasad Shenai 3274c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3284c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 329f7917c00SJeff Kirsher }; 330f7917c00SJeff Kirsher 331a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 332a3bfb617SHariprasad Shenai * and possible hangs. 333a3bfb617SHariprasad Shenai */ 334a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 335a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 336a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 337a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 338a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 339a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 340a3bfb617SHariprasad Shenai }; 341a3bfb617SHariprasad Shenai 34216e47624SHariprasad Shenai #include "t4fw_api.h" 34316e47624SHariprasad Shenai 34416e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 345b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 346b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 347b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 348b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 34916e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 35016e47624SHariprasad Shenai 35116e47624SHariprasad Shenai struct fw_info { 35216e47624SHariprasad Shenai u8 chip; 35316e47624SHariprasad Shenai char *fs_name; 35416e47624SHariprasad Shenai char *fw_mod_name; 35516e47624SHariprasad Shenai struct fw_hdr fw_hdr; 35616e47624SHariprasad Shenai }; 35716e47624SHariprasad Shenai 35816e47624SHariprasad Shenai 359f7917c00SJeff Kirsher struct trace_params { 360f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 361f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 362f7917c00SJeff Kirsher unsigned short snap_len; 363f7917c00SJeff Kirsher unsigned short min_len; 364f7917c00SJeff Kirsher unsigned char skip_ofst; 365f7917c00SJeff Kirsher unsigned char skip_len; 366f7917c00SJeff Kirsher unsigned char invert; 367f7917c00SJeff Kirsher unsigned char port; 368f7917c00SJeff Kirsher }; 369f7917c00SJeff Kirsher 370f7917c00SJeff Kirsher struct link_config { 371f7917c00SJeff Kirsher unsigned short supported; /* link capabilities */ 372f7917c00SJeff Kirsher unsigned short advertising; /* advertised capabilities */ 373f7917c00SJeff Kirsher unsigned short requested_speed; /* speed user has requested */ 374f7917c00SJeff Kirsher unsigned short speed; /* actual link speed */ 375f7917c00SJeff Kirsher unsigned char requested_fc; /* flow control user has requested */ 376f7917c00SJeff Kirsher unsigned char fc; /* actual link flow control */ 377f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 378f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 379f7917c00SJeff Kirsher }; 380f7917c00SJeff Kirsher 381e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 382f7917c00SJeff Kirsher 383f7917c00SJeff Kirsher enum { 384f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 385f7917c00SJeff Kirsher MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 386f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 387f7917c00SJeff Kirsher MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 388f36e58e5SHariprasad Shenai MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ 389cf38be6dSHariprasad Shenai MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */ 390f7917c00SJeff Kirsher }; 391f7917c00SJeff Kirsher 392f7917c00SJeff Kirsher enum { 393812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 394812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 395812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 396812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 397812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 398812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 399812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 400812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 401812034f1SHariprasad Shenai }; 402812034f1SHariprasad Shenai 403812034f1SHariprasad Shenai enum { 404cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 405cf38be6dSHariprasad Shenai /* forwarded interrupts */ 406cf38be6dSHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES 407cf38be6dSHariprasad Shenai + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS, 408f7917c00SJeff Kirsher }; 409f7917c00SJeff Kirsher 410f7917c00SJeff Kirsher struct adapter; 411f7917c00SJeff Kirsher struct sge_rspq; 412f7917c00SJeff Kirsher 413688848b1SAnish Bhatt #include "cxgb4_dcb.h" 414688848b1SAnish Bhatt 41576fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 41676fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 41776fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 41876fed8a9SVarun Prakash 419f7917c00SJeff Kirsher struct port_info { 420f7917c00SJeff Kirsher struct adapter *adapter; 421f7917c00SJeff Kirsher u16 viid; 422f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 423f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 424f7917c00SJeff Kirsher s8 mdio_addr; 42540e9de4bSHariprasad Shenai enum fw_port_type port_type; 426f7917c00SJeff Kirsher u8 mod_type; 427f7917c00SJeff Kirsher u8 port_id; 428f7917c00SJeff Kirsher u8 tx_chan; 429f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 430f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 431f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 432f7917c00SJeff Kirsher u8 rss_mode; 433f7917c00SJeff Kirsher struct link_config link_cfg; 434f7917c00SJeff Kirsher u16 *rss; 435688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 436688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 437688848b1SAnish Bhatt #endif 43876fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 43976fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 44076fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 441f7917c00SJeff Kirsher }; 442f7917c00SJeff Kirsher 443f7917c00SJeff Kirsher struct dentry; 444f7917c00SJeff Kirsher struct work_struct; 445f7917c00SJeff Kirsher 446f7917c00SJeff Kirsher enum { /* adapter flags */ 447f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 448144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 449144be3d9SGavin Shan USING_MSI = (1 << 2), 450144be3d9SGavin Shan USING_MSIX = (1 << 3), 451f7917c00SJeff Kirsher FW_OK = (1 << 4), 45213ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 45352367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 45452367a76SVipul Pandya MASTER_PF = (1 << 7), 45552367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 456f7917c00SJeff Kirsher }; 457f7917c00SJeff Kirsher 458f7917c00SJeff Kirsher struct rx_sw_desc; 459f7917c00SJeff Kirsher 460f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 461f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 462f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 463f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 464f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 465f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 466f7917c00SJeff Kirsher unsigned long large_alloc_failed; 467f7917c00SJeff Kirsher unsigned long starving; 468f7917c00SJeff Kirsher /* RO fields */ 469f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 470f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 471f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 472f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 473f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 474df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 475df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 476f7917c00SJeff Kirsher }; 477f7917c00SJeff Kirsher 478f7917c00SJeff Kirsher /* A packet gather list */ 479f7917c00SJeff Kirsher struct pkt_gl { 480e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 481f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 482f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 483f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 484f7917c00SJeff Kirsher }; 485f7917c00SJeff Kirsher 486f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 487f7917c00SJeff Kirsher const struct pkt_gl *gl); 488f7917c00SJeff Kirsher 489f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 490f7917c00SJeff Kirsher struct napi_struct napi; 491f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 492f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 493f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 494f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 495f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 496e553ec3fSHariprasad Shenai u8 adaptive_rx; 497f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 498f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 499f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 500f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 501f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 502f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 503f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 504f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 505df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 506df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 507f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 508f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 509f7917c00SJeff Kirsher struct adapter *adap; 510f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 511f7917c00SJeff Kirsher rspq_handler_t handler; 5123a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 5133a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_IDLE 0 5143a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 5153a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 5163a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 5173a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 5183a336cb1SHariprasad Shenai #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 5193a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5203a336cb1SHariprasad Shenai #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 5213a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL) 5223a336cb1SHariprasad Shenai #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 5233a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5243a336cb1SHariprasad Shenai unsigned int bpoll_state; 5253a336cb1SHariprasad Shenai spinlock_t bpoll_lock; /* lock for busy poll */ 5263a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 5273a336cb1SHariprasad Shenai 528f7917c00SJeff Kirsher }; 529f7917c00SJeff Kirsher 530f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 531f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 532f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 533f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 534f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 535f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 536f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 537f7917c00SJeff Kirsher }; 538f7917c00SJeff Kirsher 539f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 540f7917c00SJeff Kirsher struct sge_rspq rspq; 541f7917c00SJeff Kirsher struct sge_fl fl; 542f7917c00SJeff Kirsher struct sge_eth_stats stats; 543f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 544f7917c00SJeff Kirsher 545f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 546f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 547f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 548f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 549f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 550f7917c00SJeff Kirsher }; 551f7917c00SJeff Kirsher 552f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 553f7917c00SJeff Kirsher struct sge_rspq rspq; 554f7917c00SJeff Kirsher struct sge_fl fl; 555f7917c00SJeff Kirsher struct sge_ofld_stats stats; 556f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 557f7917c00SJeff Kirsher 558f7917c00SJeff Kirsher struct tx_desc { 559f7917c00SJeff Kirsher __be64 flit[8]; 560f7917c00SJeff Kirsher }; 561f7917c00SJeff Kirsher 562f7917c00SJeff Kirsher struct tx_sw_desc; 563f7917c00SJeff Kirsher 564f7917c00SJeff Kirsher struct sge_txq { 565f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 566f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 567f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 568f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 569f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 570f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 571f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 572f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 573f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 574f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 575f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 5763069ee9bSVipul Pandya spinlock_t db_lock; 5773069ee9bSVipul Pandya int db_disabled; 5783069ee9bSVipul Pandya unsigned short db_pidx; 57905eb2389SSteve Wise unsigned short db_pidx_inc; 580df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 581df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 582f7917c00SJeff Kirsher }; 583f7917c00SJeff Kirsher 584f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 585f7917c00SJeff Kirsher struct sge_txq q; 586f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 58710b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 58810b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 58910b00466SAnish Bhatt #endif 590f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 591f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 592f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 593f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 594f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 595f7917c00SJeff Kirsher 596f7917c00SJeff Kirsher struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 597f7917c00SJeff Kirsher struct sge_txq q; 598f7917c00SJeff Kirsher struct adapter *adap; 599f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 600f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 601f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 602f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 603f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 604f7917c00SJeff Kirsher 605f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 606f7917c00SJeff Kirsher struct sge_txq q; 607f7917c00SJeff Kirsher struct adapter *adap; 608f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 609f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 610f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 611f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 612f7917c00SJeff Kirsher 613f7917c00SJeff Kirsher struct sge { 614f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 615f7917c00SJeff Kirsher struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 616f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 617f7917c00SJeff Kirsher 618f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 619f7917c00SJeff Kirsher struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 620f7917c00SJeff Kirsher struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 621cf38be6dSHariprasad Shenai struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 622f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 623f7917c00SJeff Kirsher 624f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 625f7917c00SJeff Kirsher spinlock_t intrq_lock; 626f7917c00SJeff Kirsher 627f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 628f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 629f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 630f7917c00SJeff Kirsher u16 ofldqsets; /* # of active offload queue sets */ 631f7917c00SJeff Kirsher u16 rdmaqs; /* # of available RDMA Rx queues */ 632cf38be6dSHariprasad Shenai u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 633f7917c00SJeff Kirsher u16 ofld_rxq[MAX_OFLD_QSETS]; 634f36e58e5SHariprasad Shenai u16 rdma_rxq[MAX_RDMA_QUEUES]; 635f36e58e5SHariprasad Shenai u16 rdma_ciq[MAX_RDMA_CIQS]; 636f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 637f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 63852367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 63952367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 64052367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 64152367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 64252367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 6430f4d201fSKumar Sanghvi 644a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 645f7917c00SJeff Kirsher unsigned int egr_start; 6464b8e27a8SHariprasad Shenai unsigned int egr_sz; 647f7917c00SJeff Kirsher unsigned int ingr_start; 6484b8e27a8SHariprasad Shenai unsigned int ingr_sz; 6494b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 6504b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 6514b8e27a8SHariprasad Shenai unsigned long *starving_fl; 6524b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 653f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 654f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 655f7917c00SJeff Kirsher }; 656f7917c00SJeff Kirsher 657f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 658f7917c00SJeff Kirsher #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 659f7917c00SJeff Kirsher #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 660cf38be6dSHariprasad Shenai #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 661f7917c00SJeff Kirsher 662f7917c00SJeff Kirsher struct l2t_data; 663f7917c00SJeff Kirsher 6642422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 6652422d9a3SSantosh Rastapur 6667d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 6677d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 6687d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 6692422d9a3SSantosh Rastapur */ 6707d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 6712422d9a3SSantosh Rastapur 6722422d9a3SSantosh Rastapur #endif 6732422d9a3SSantosh Rastapur 674f7917c00SJeff Kirsher struct adapter { 675f7917c00SJeff Kirsher void __iomem *regs; 67622adfe0aSSantosh Rastapur void __iomem *bar2; 6770abfd152SHariprasad Shenai u32 t4_bar0; 678f7917c00SJeff Kirsher struct pci_dev *pdev; 679f7917c00SJeff Kirsher struct device *pdev_dev; 6803069ee9bSVipul Pandya unsigned int mbox; 681f7917c00SJeff Kirsher unsigned int fn; 682f7917c00SJeff Kirsher unsigned int flags; 6832422d9a3SSantosh Rastapur enum chip_type chip; 684f7917c00SJeff Kirsher 685f7917c00SJeff Kirsher int msg_enable; 686f7917c00SJeff Kirsher 687f7917c00SJeff Kirsher struct adapter_params params; 688f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 689f7917c00SJeff Kirsher unsigned int swintr; 690f7917c00SJeff Kirsher 691f7917c00SJeff Kirsher unsigned int wol; 692f7917c00SJeff Kirsher 693f7917c00SJeff Kirsher struct { 694f7917c00SJeff Kirsher unsigned short vec; 695f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 696f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 697f7917c00SJeff Kirsher 698f7917c00SJeff Kirsher struct sge sge; 699f7917c00SJeff Kirsher 700f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 701f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 702f7917c00SJeff Kirsher 703793dad94SVipul Pandya u32 filter_mode; 704636f9d37SVipul Pandya unsigned int l2t_start; 705636f9d37SVipul Pandya unsigned int l2t_end; 706f7917c00SJeff Kirsher struct l2t_data *l2t; 707b5a02f50SAnish Bhatt unsigned int clipt_start; 708b5a02f50SAnish Bhatt unsigned int clipt_end; 709b5a02f50SAnish Bhatt struct clip_tbl *clipt; 710f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 711f7917c00SJeff Kirsher struct list_head list_node; 71201bcca68SVipul Pandya struct list_head rcu_node; 713f7917c00SJeff Kirsher 714f7917c00SJeff Kirsher struct tid_info tids; 715f7917c00SJeff Kirsher void **tid_release_head; 716f7917c00SJeff Kirsher spinlock_t tid_release_lock; 71729aaee65SAnish Bhatt struct workqueue_struct *workq; 718f7917c00SJeff Kirsher struct work_struct tid_release_task; 719881806bcSVipul Pandya struct work_struct db_full_task; 720881806bcSVipul Pandya struct work_struct db_drop_task; 721f7917c00SJeff Kirsher bool tid_release_task_busy; 722f7917c00SJeff Kirsher 723f7917c00SJeff Kirsher struct dentry *debugfs_root; 724f7917c00SJeff Kirsher 725f7917c00SJeff Kirsher spinlock_t stats_lock; 726fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 727f7917c00SJeff Kirsher }; 728f7917c00SJeff Kirsher 729f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 730f2b7e78dSVipul Pandya */ 731f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 732f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 733f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 734f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 735f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 736f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 737f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 738f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 739f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 740f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 741f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 742f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 743f2b7e78dSVipul Pandya 744f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 745f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 746f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 747f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 748f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 749f2b7e78dSVipul Pandya * matching rules are true. 750f2b7e78dSVipul Pandya * 751f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 752f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 753f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 754f2b7e78dSVipul Pandya * MPS match type) ... 755f2b7e78dSVipul Pandya * 756f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 757f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 758f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 759f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 760f2b7e78dSVipul Pandya */ 761f2b7e78dSVipul Pandya struct ch_filter_tuple { 762f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 763f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 764f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 765f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 766f2b7e78dSVipul Pandya * set of fields. 767f2b7e78dSVipul Pandya */ 768f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 769f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 770f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 771f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 772f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 773f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 774f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 775f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 776f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 777f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 778f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 779f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 780f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 781f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 782f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 783f2b7e78dSVipul Pandya 784f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 785f2b7e78dSVipul Pandya * available for field rules. 786f2b7e78dSVipul Pandya */ 787f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 788f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 789f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 790f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 791f2b7e78dSVipul Pandya }; 792f2b7e78dSVipul Pandya 793f2b7e78dSVipul Pandya /* A filter ioctl command. 794f2b7e78dSVipul Pandya */ 795f2b7e78dSVipul Pandya struct ch_filter_specification { 796f2b7e78dSVipul Pandya /* Administrative fields for filter. 797f2b7e78dSVipul Pandya */ 798f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 799f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 800f2b7e78dSVipul Pandya 801f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 802f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 803f2b7e78dSVipul Pandya */ 804f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 805f2b7e78dSVipul Pandya 806f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 807f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 808f2b7e78dSVipul Pandya * out as egress packets. 809f2b7e78dSVipul Pandya */ 810f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 811f2b7e78dSVipul Pandya 812f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 813f2b7e78dSVipul Pandya 814f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 815f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 816f2b7e78dSVipul Pandya 817f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 818f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 819f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 820f2b7e78dSVipul Pandya 821f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 822f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 823f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 824f2b7e78dSVipul Pandya */ 825f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 826f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 827f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 828f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 829f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 830f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 831f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 832f2b7e78dSVipul Pandya 833f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 834f2b7e78dSVipul Pandya */ 835f2b7e78dSVipul Pandya struct ch_filter_tuple val; 836f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 837f2b7e78dSVipul Pandya }; 838f2b7e78dSVipul Pandya 839f2b7e78dSVipul Pandya enum { 840f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 841f2b7e78dSVipul Pandya FILTER_DROP, 842f2b7e78dSVipul Pandya FILTER_SWITCH 843f2b7e78dSVipul Pandya }; 844f2b7e78dSVipul Pandya 845f2b7e78dSVipul Pandya enum { 846f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 847f2b7e78dSVipul Pandya VLAN_REMOVE, 848f2b7e78dSVipul Pandya VLAN_INSERT, 849f2b7e78dSVipul Pandya VLAN_REWRITE 850f2b7e78dSVipul Pandya }; 851f2b7e78dSVipul Pandya 8522422d9a3SSantosh Rastapur static inline int is_t5(enum chip_type chip) 8532422d9a3SSantosh Rastapur { 854d14807ddSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5; 8552422d9a3SSantosh Rastapur } 8562422d9a3SSantosh Rastapur 8572422d9a3SSantosh Rastapur static inline int is_t4(enum chip_type chip) 8582422d9a3SSantosh Rastapur { 859d14807ddSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; 8602422d9a3SSantosh Rastapur } 8612422d9a3SSantosh Rastapur 862f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 863f7917c00SJeff Kirsher { 864f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 865f7917c00SJeff Kirsher } 866f7917c00SJeff Kirsher 867f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 868f7917c00SJeff Kirsher { 869f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 870f7917c00SJeff Kirsher } 871f7917c00SJeff Kirsher 872f7917c00SJeff Kirsher #ifndef readq 873f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 874f7917c00SJeff Kirsher { 875f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 876f7917c00SJeff Kirsher } 877f7917c00SJeff Kirsher 878f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 879f7917c00SJeff Kirsher { 880f7917c00SJeff Kirsher writel(val, addr); 881f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 882f7917c00SJeff Kirsher } 883f7917c00SJeff Kirsher #endif 884f7917c00SJeff Kirsher 885f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 886f7917c00SJeff Kirsher { 887f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 888f7917c00SJeff Kirsher } 889f7917c00SJeff Kirsher 890f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 891f7917c00SJeff Kirsher { 892f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 893f7917c00SJeff Kirsher } 894f7917c00SJeff Kirsher 895f7917c00SJeff Kirsher /** 896f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 897f7917c00SJeff Kirsher * @dev: the netdev 898f7917c00SJeff Kirsher * 899f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 900f7917c00SJeff Kirsher */ 901f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 902f7917c00SJeff Kirsher { 903f7917c00SJeff Kirsher return netdev_priv(dev); 904f7917c00SJeff Kirsher } 905f7917c00SJeff Kirsher 906f7917c00SJeff Kirsher /** 907f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 908f7917c00SJeff Kirsher * @adap: the adapter 909f7917c00SJeff Kirsher * @idx: the port index 910f7917c00SJeff Kirsher * 911f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 912f7917c00SJeff Kirsher */ 913f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 914f7917c00SJeff Kirsher { 915f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 916f7917c00SJeff Kirsher } 917f7917c00SJeff Kirsher 918f7917c00SJeff Kirsher /** 919f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 920f7917c00SJeff Kirsher * @dev: the netdev 921f7917c00SJeff Kirsher * 922f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 923f7917c00SJeff Kirsher */ 924f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 925f7917c00SJeff Kirsher { 926f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 927f7917c00SJeff Kirsher } 928f7917c00SJeff Kirsher 9293a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 9303a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 9313a336cb1SHariprasad Shenai { 9323a336cb1SHariprasad Shenai spin_lock_init(&q->bpoll_lock); 9333a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 9343a336cb1SHariprasad Shenai } 9353a336cb1SHariprasad Shenai 9363a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 9373a336cb1SHariprasad Shenai { 9383a336cb1SHariprasad Shenai bool rc = true; 9393a336cb1SHariprasad Shenai 9403a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 9413a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 9423a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 9433a336cb1SHariprasad Shenai rc = false; 9443a336cb1SHariprasad Shenai } else { 9453a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_NAPI; 9463a336cb1SHariprasad Shenai } 9473a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 9483a336cb1SHariprasad Shenai return rc; 9493a336cb1SHariprasad Shenai } 9503a336cb1SHariprasad Shenai 9513a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 9523a336cb1SHariprasad Shenai { 9533a336cb1SHariprasad Shenai bool rc = false; 9543a336cb1SHariprasad Shenai 9553a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 9563a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 9573a336cb1SHariprasad Shenai rc = true; 9583a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 9593a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 9603a336cb1SHariprasad Shenai return rc; 9613a336cb1SHariprasad Shenai } 9623a336cb1SHariprasad Shenai 9633a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 9643a336cb1SHariprasad Shenai { 9653a336cb1SHariprasad Shenai bool rc = true; 9663a336cb1SHariprasad Shenai 9673a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 9683a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 9693a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 9703a336cb1SHariprasad Shenai rc = false; 9713a336cb1SHariprasad Shenai } else { 9723a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL; 9733a336cb1SHariprasad Shenai } 9743a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 9753a336cb1SHariprasad Shenai return rc; 9763a336cb1SHariprasad Shenai } 9773a336cb1SHariprasad Shenai 9783a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 9793a336cb1SHariprasad Shenai { 9803a336cb1SHariprasad Shenai bool rc = false; 9813a336cb1SHariprasad Shenai 9823a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 9833a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 9843a336cb1SHariprasad Shenai rc = true; 9853a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 9863a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 9873a336cb1SHariprasad Shenai return rc; 9883a336cb1SHariprasad Shenai } 9893a336cb1SHariprasad Shenai 9903a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 9913a336cb1SHariprasad Shenai { 9923a336cb1SHariprasad Shenai return q->bpoll_state & CXGB_POLL_USER_PEND; 9933a336cb1SHariprasad Shenai } 9943a336cb1SHariprasad Shenai #else 9953a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 9963a336cb1SHariprasad Shenai { 9973a336cb1SHariprasad Shenai } 9983a336cb1SHariprasad Shenai 9993a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 10003a336cb1SHariprasad Shenai { 10013a336cb1SHariprasad Shenai return true; 10023a336cb1SHariprasad Shenai } 10033a336cb1SHariprasad Shenai 10043a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 10053a336cb1SHariprasad Shenai { 10063a336cb1SHariprasad Shenai return false; 10073a336cb1SHariprasad Shenai } 10083a336cb1SHariprasad Shenai 10093a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 10103a336cb1SHariprasad Shenai { 10113a336cb1SHariprasad Shenai return false; 10123a336cb1SHariprasad Shenai } 10133a336cb1SHariprasad Shenai 10143a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 10153a336cb1SHariprasad Shenai { 10163a336cb1SHariprasad Shenai return false; 10173a336cb1SHariprasad Shenai } 10183a336cb1SHariprasad Shenai 10193a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 10203a336cb1SHariprasad Shenai { 10213a336cb1SHariprasad Shenai return false; 10223a336cb1SHariprasad Shenai } 10233a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 10243a336cb1SHariprasad Shenai 1025812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1026812034f1SHariprasad Shenai * - bits 0..9: chip version 1027812034f1SHariprasad Shenai * - bits 10..15: chip revision 1028812034f1SHariprasad Shenai * - bits 16..23: register dump version 1029812034f1SHariprasad Shenai */ 1030812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1031812034f1SHariprasad Shenai { 1032812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1033812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1034812034f1SHariprasad Shenai } 1035812034f1SHariprasad Shenai 1036812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1037812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1038812034f1SHariprasad Shenai const struct sge_rspq *q) 1039812034f1SHariprasad Shenai { 1040812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1041812034f1SHariprasad Shenai 1042812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1043812034f1SHariprasad Shenai } 1044812034f1SHariprasad Shenai 1045812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1046812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1047812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1048812034f1SHariprasad Shenai 1049f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1050f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1051f7917c00SJeff Kirsher 1052f7917c00SJeff Kirsher void *t4_alloc_mem(size_t size); 1053f7917c00SJeff Kirsher 1054f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 10555fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1056f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1057f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1058f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1059f7917c00SJeff Kirsher const struct pkt_gl *gl); 1060f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1061f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1062f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1063f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 1064145ef8a5SHariprasad Shenai struct sge_fl *fl, rspq_handler_t hnd, int cong); 1065f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1066f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1067f7917c00SJeff Kirsher unsigned int iqid); 1068f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1069f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1070f7917c00SJeff Kirsher unsigned int cmplqid); 1071f7917c00SJeff Kirsher int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1072f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid); 1073f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 107452367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1075f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1076f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 10773a336cb1SHariprasad Shenai int cxgb_busy_poll(struct napi_struct *napi); 1078812034f1SHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1079812034f1SHariprasad Shenai unsigned int cnt); 1080812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1081812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 10823069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1083f7917c00SJeff Kirsher 1084f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1085f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1086f7917c00SJeff Kirsher 10879a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 10889a4da2cdSVipul Pandya { 10899a4da2cdSVipul Pandya return adap->params.bypass; 10909a4da2cdSVipul Pandya } 10919a4da2cdSVipul Pandya 10929a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 10939a4da2cdSVipul Pandya { 10949a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 10959a4da2cdSVipul Pandya switch (device) { 10969a4da2cdSVipul Pandya case 0x440b: 10979a4da2cdSVipul Pandya case 0x440c: 10989a4da2cdSVipul Pandya return 1; 10999a4da2cdSVipul Pandya default: 11009a4da2cdSVipul Pandya return 0; 11019a4da2cdSVipul Pandya } 11029a4da2cdSVipul Pandya } 11039a4da2cdSVipul Pandya 1104f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1105f7917c00SJeff Kirsher { 1106f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1107f7917c00SJeff Kirsher } 1108f7917c00SJeff Kirsher 1109f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1110f7917c00SJeff Kirsher unsigned int us) 1111f7917c00SJeff Kirsher { 1112f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1113f7917c00SJeff Kirsher } 1114f7917c00SJeff Kirsher 111552367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 111652367a76SVipul Pandya unsigned int ticks) 111752367a76SVipul Pandya { 111852367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 111952367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 112052367a76SVipul Pandya adapter->params.vpd.cclk); 112152367a76SVipul Pandya } 112252367a76SVipul Pandya 1123f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1124f7917c00SJeff Kirsher u32 val); 1125f7917c00SJeff Kirsher 1126f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1127f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1128f7917c00SJeff Kirsher 1129f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1130f7917c00SJeff Kirsher int size, void *rpl) 1131f7917c00SJeff Kirsher { 1132f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1133f7917c00SJeff Kirsher } 1134f7917c00SJeff Kirsher 1135f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1136f7917c00SJeff Kirsher int size, void *rpl) 1137f7917c00SJeff Kirsher { 1138f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1139f7917c00SJeff Kirsher } 1140f7917c00SJeff Kirsher 114113ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 114213ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 114313ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1144f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1145f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1146f2b7e78dSVipul Pandya unsigned int start_idx); 11470abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1148f2b7e78dSVipul Pandya 1149f2b7e78dSVipul Pandya struct fw_filter_wr; 1150f2b7e78dSVipul Pandya 1151f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1152f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1153f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1154f7917c00SJeff Kirsher 11558203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 1156f7917c00SJeff Kirsher int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 1157f7917c00SJeff Kirsher struct link_config *lc); 1158f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1159fc5ab020SHariprasad Shenai 1160fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1161fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1162fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1163f01aa633SHariprasad Shenai void *buf, int dir); 1164fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1165fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1166fc5ab020SHariprasad Shenai { 1167fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1168fc5ab020SHariprasad Shenai } 1169fc5ab020SHariprasad Shenai 1170812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1171812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1172812034f1SHariprasad Shenai 1173f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1174636f9d37SVipul Pandya int get_vpd_params(struct adapter *adapter, struct vpd_params *p); 117549216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 117649216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1177f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 117849216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 117922c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 118022c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1181636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 118216e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 118316e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1184ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 118516e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 118616e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 118716e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1188f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 1189e85c9a7aSHariprasad Shenai 1190e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1191dd0bcc0bSStephen Rothwell int cxgb4_t4_bar2_sge_qregs(struct adapter *adapter, 1192e85c9a7aSHariprasad Shenai unsigned int qid, 1193e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 1194e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1195e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1196e85c9a7aSHariprasad Shenai 1197dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1198dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1199ae469b68SHariprasad Shenai 1200ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1201e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 1202dcf7b6f5SKumar Sanghvi int t4_init_tp_params(struct adapter *adap); 1203dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1204c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1205f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1206f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1207f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1208f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1209f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1210f7917c00SJeff Kirsher unsigned int flags); 1211c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1212c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1213688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 1214688ea5feSHariprasad Shenai void t4_read_rss_key(struct adapter *adapter, u32 *key); 1215688ea5feSHariprasad Shenai void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1216688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1217688ea5feSHariprasad Shenai u32 *valp); 1218688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1219688ea5feSHariprasad Shenai u32 *vfl, u32 *vfh); 1220688ea5feSHariprasad Shenai u32 t4_read_rss_pf_map(struct adapter *adapter); 1221688ea5feSHariprasad Shenai u32 t4_read_rss_pf_mask(struct adapter *adapter); 1222688ea5feSHariprasad Shenai 122319dd37baSSantosh Rastapur int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 122419dd37baSSantosh Rastapur u64 *parity); 1225f7917c00SJeff Kirsher int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 1226f7917c00SJeff Kirsher u64 *parity); 1227145ef8a5SHariprasad Shenai unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1228b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1229b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1230e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1231e5f0e43bSHariprasad Shenai size_t n); 1232c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1233c778af7dSHariprasad Shenai size_t n); 1234f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1235f1ff24aaSHariprasad Shenai unsigned int *valp); 1236f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1237f1ff24aaSHariprasad Shenai const unsigned int *valp); 1238f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 123974b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 124072aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1241f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1242f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1243bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1244636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1245636f9d37SVipul Pandya unsigned int mask, unsigned int val); 12462d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1247f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1248f7917c00SJeff Kirsher struct tp_tcp_stats *v6); 1249f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1250f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1251f7917c00SJeff Kirsher 1252797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1253797ff0f5SHariprasad Shenai 1254f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1255f2b7e78dSVipul Pandya 1256f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1257f7917c00SJeff Kirsher const u8 *addr); 1258f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1259f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1260f7917c00SJeff Kirsher 1261f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1262f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1263f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1264f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1265f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1266636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1267636f9d37SVipul Pandya unsigned int cache_line_size); 1268636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1269f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1270f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1271f7917c00SJeff Kirsher u32 *val); 1272f7917c00SJeff Kirsher int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1273f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1274f7917c00SJeff Kirsher const u32 *val); 1275688848b1SAnish Bhatt int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox, 1276688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1277688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 1278688848b1SAnish Bhatt const u32 *val); 1279f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1280f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1281f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1282f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1283f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1284f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1285f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1286f7917c00SJeff Kirsher unsigned int *rss_size); 1287f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1288f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1289f7917c00SJeff Kirsher bool sleep_ok); 1290f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1291f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1292f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1293f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1294f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1295f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1296f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1297688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1298688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1299f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1300f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1301f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1302f7917c00SJeff Kirsher unsigned int nblinks); 1303f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1304f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1305f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1306f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1307f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1308f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1309f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1310f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1311f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1312f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1313f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1314f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1315f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1316f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1317881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1318881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 13198caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 13208caa1e84SVipul Pandya u32 addr, u32 val); 132168bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1322fd88b31aSHariprasad Shenai void t4_free_mem(void *addr); 1323a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1324a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1325a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1326a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1327a3bfb617SHariprasad Shenai int hz, int ticks); 1328f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1329