1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 505e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 51a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 52a4569504SAtul Gupta #include <linux/ptp_classify.h> 53f7917c00SJeff Kirsher #include <asm/io.h> 5427999805SHariprasad S #include "t4_chip_type.h" 55f7917c00SJeff Kirsher #include "cxgb4_uld.h" 56f7917c00SJeff Kirsher 573069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 5894cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 5994cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 603069ee9bSVipul Pandya 61a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 62a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 63a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 64a6ec572bSAtul Gupta */ 65a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 66a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 67a6ec572bSAtul Gupta 68f7917c00SJeff Kirsher enum { 69f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 70f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 71f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 72f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 73a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 74098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 75f7917c00SJeff Kirsher }; 76f7917c00SJeff Kirsher 77f7917c00SJeff Kirsher enum { 78812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 79812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 80812034f1SHariprasad Shenai }; 81812034f1SHariprasad Shenai 82812034f1SHariprasad Shenai enum { 83f7917c00SJeff Kirsher MEM_EDC0, 84f7917c00SJeff Kirsher MEM_EDC1, 852422d9a3SSantosh Rastapur MEM_MC, 862422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 872422d9a3SSantosh Rastapur MEM_MC1 88f7917c00SJeff Kirsher }; 89f7917c00SJeff Kirsher 903069ee9bSVipul Pandya enum { 913eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 923eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 933069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 943069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 952422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 963eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 973eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 980abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 990abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1003069ee9bSVipul Pandya }; 1013069ee9bSVipul Pandya 102f7917c00SJeff Kirsher enum dev_master { 103f7917c00SJeff Kirsher MASTER_CANT, 104f7917c00SJeff Kirsher MASTER_MAY, 105f7917c00SJeff Kirsher MASTER_MUST 106f7917c00SJeff Kirsher }; 107f7917c00SJeff Kirsher 108f7917c00SJeff Kirsher enum dev_state { 109f7917c00SJeff Kirsher DEV_STATE_UNINIT, 110f7917c00SJeff Kirsher DEV_STATE_INIT, 111f7917c00SJeff Kirsher DEV_STATE_ERR 112f7917c00SJeff Kirsher }; 113f7917c00SJeff Kirsher 114c3168cabSGanesh Goudar enum cc_pause { 115f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 116f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 117f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 118f7917c00SJeff Kirsher }; 119f7917c00SJeff Kirsher 120c3168cabSGanesh Goudar enum cc_fec { 1213bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1223bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1233bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1243bb4858fSGanesh Goudar }; 1253bb4858fSGanesh Goudar 126f7917c00SJeff Kirsher struct port_stats { 127f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 128f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 129f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 130f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 131f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 132f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 133f7917c00SJeff Kirsher 134f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 135f7917c00SJeff Kirsher u64 tx_frames_65_127; 136f7917c00SJeff Kirsher u64 tx_frames_128_255; 137f7917c00SJeff Kirsher u64 tx_frames_256_511; 138f7917c00SJeff Kirsher u64 tx_frames_512_1023; 139f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 140f7917c00SJeff Kirsher u64 tx_frames_1519_max; 141f7917c00SJeff Kirsher 142f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 143f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 144f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 145f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 146f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 147f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 148f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 149f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 150f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 151f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 152f7917c00SJeff Kirsher 153f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 154f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 155f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 156f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 157f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 158f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 159f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 160f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 161f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 162f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 163f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 164f7917c00SJeff Kirsher 165f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 166f7917c00SJeff Kirsher u64 rx_frames_65_127; 167f7917c00SJeff Kirsher u64 rx_frames_128_255; 168f7917c00SJeff Kirsher u64 rx_frames_256_511; 169f7917c00SJeff Kirsher u64 rx_frames_512_1023; 170f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 171f7917c00SJeff Kirsher u64 rx_frames_1519_max; 172f7917c00SJeff Kirsher 173f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 174f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 175f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 176f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 177f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 178f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 179f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 180f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 181f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 182f7917c00SJeff Kirsher 183f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 184f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 185f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 186f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 187f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 188f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 189f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 190f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 191f7917c00SJeff Kirsher }; 192f7917c00SJeff Kirsher 193f7917c00SJeff Kirsher struct lb_port_stats { 194f7917c00SJeff Kirsher u64 octets; 195f7917c00SJeff Kirsher u64 frames; 196f7917c00SJeff Kirsher u64 bcast_frames; 197f7917c00SJeff Kirsher u64 mcast_frames; 198f7917c00SJeff Kirsher u64 ucast_frames; 199f7917c00SJeff Kirsher u64 error_frames; 200f7917c00SJeff Kirsher 201f7917c00SJeff Kirsher u64 frames_64; 202f7917c00SJeff Kirsher u64 frames_65_127; 203f7917c00SJeff Kirsher u64 frames_128_255; 204f7917c00SJeff Kirsher u64 frames_256_511; 205f7917c00SJeff Kirsher u64 frames_512_1023; 206f7917c00SJeff Kirsher u64 frames_1024_1518; 207f7917c00SJeff Kirsher u64 frames_1519_max; 208f7917c00SJeff Kirsher 209f7917c00SJeff Kirsher u64 drop; 210f7917c00SJeff Kirsher 211f7917c00SJeff Kirsher u64 ovflow0; 212f7917c00SJeff Kirsher u64 ovflow1; 213f7917c00SJeff Kirsher u64 ovflow2; 214f7917c00SJeff Kirsher u64 ovflow3; 215f7917c00SJeff Kirsher u64 trunc0; 216f7917c00SJeff Kirsher u64 trunc1; 217f7917c00SJeff Kirsher u64 trunc2; 218f7917c00SJeff Kirsher u64 trunc3; 219f7917c00SJeff Kirsher }; 220f7917c00SJeff Kirsher 221f7917c00SJeff Kirsher struct tp_tcp_stats { 222a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 223a4cfd929SHariprasad Shenai u64 tcp_in_segs; 224a4cfd929SHariprasad Shenai u64 tcp_out_segs; 225a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 226a4cfd929SHariprasad Shenai }; 227a4cfd929SHariprasad Shenai 228a4cfd929SHariprasad Shenai struct tp_usm_stats { 229a4cfd929SHariprasad Shenai u32 frames; 230a4cfd929SHariprasad Shenai u32 drops; 231a4cfd929SHariprasad Shenai u64 octets; 232f7917c00SJeff Kirsher }; 233f7917c00SJeff Kirsher 234a6222975SHariprasad Shenai struct tp_fcoe_stats { 235a6222975SHariprasad Shenai u32 frames_ddp; 236a6222975SHariprasad Shenai u32 frames_drop; 237a6222975SHariprasad Shenai u64 octets_ddp; 238f7917c00SJeff Kirsher }; 239f7917c00SJeff Kirsher 240f7917c00SJeff Kirsher struct tp_err_stats { 241a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 242a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 243a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 244a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 245a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 246a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 247a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 248a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 249a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 250a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 251a4cfd929SHariprasad Shenai }; 252a4cfd929SHariprasad Shenai 253a6222975SHariprasad Shenai struct tp_cpl_stats { 254a6222975SHariprasad Shenai u32 req[4]; 255a6222975SHariprasad Shenai u32 rsp[4]; 256a6222975SHariprasad Shenai }; 257a6222975SHariprasad Shenai 258a4cfd929SHariprasad Shenai struct tp_rdma_stats { 259a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 260a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 261f7917c00SJeff Kirsher }; 262f7917c00SJeff Kirsher 263e85c9a7aSHariprasad Shenai struct sge_params { 264e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 265e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 266e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 267e85c9a7aSHariprasad Shenai }; 268e85c9a7aSHariprasad Shenai 269f7917c00SJeff Kirsher struct tp_params { 270f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2712d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 272dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 273dca4faebSVipul Pandya /* channel map */ 274636f9d37SVipul Pandya 275636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 276636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 277dcf7b6f5SKumar Sanghvi 278dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 279dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 280dcf7b6f5SKumar Sanghvi 2818eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2828eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2838eb9f2f9SArjun V */ 2848eb9f2f9SArjun V int rx_pkt_encap; 2858eb9f2f9SArjun V 286dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 287dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 288dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 289dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 290dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 291dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 292dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 293dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 294dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 295dcf7b6f5SKumar Sanghvi * present. 296dcf7b6f5SKumar Sanghvi */ 2970ba9a3b6SKumar Sanghvi int fcoe_shift; 298dcf7b6f5SKumar Sanghvi int port_shift; 2990ba9a3b6SKumar Sanghvi int vnic_shift; 3000ba9a3b6SKumar Sanghvi int vlan_shift; 3010ba9a3b6SKumar Sanghvi int tos_shift; 302dcf7b6f5SKumar Sanghvi int protocol_shift; 3030ba9a3b6SKumar Sanghvi int ethertype_shift; 3040ba9a3b6SKumar Sanghvi int macmatch_shift; 3050ba9a3b6SKumar Sanghvi int matchtype_shift; 3060ba9a3b6SKumar Sanghvi int frag_shift; 3070ba9a3b6SKumar Sanghvi 3080ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 309f7917c00SJeff Kirsher }; 310f7917c00SJeff Kirsher 311f7917c00SJeff Kirsher struct vpd_params { 312f7917c00SJeff Kirsher unsigned int cclk; 313f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 314f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 315f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 316a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 317098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 318f7917c00SJeff Kirsher }; 319f7917c00SJeff Kirsher 320f7917c00SJeff Kirsher struct pci_params { 321f7917c00SJeff Kirsher unsigned char speed; 322f7917c00SJeff Kirsher unsigned char width; 323f7917c00SJeff Kirsher }; 324f7917c00SJeff Kirsher 32549aa284fSHariprasad Shenai struct devlog_params { 32649aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 32749aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 32849aa284fSHariprasad Shenai u32 size; /* size of log */ 32949aa284fSHariprasad Shenai }; 33049aa284fSHariprasad Shenai 3313ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3323ccc6cf7SHariprasad Shenai struct arch_specific_params { 3333ccc6cf7SHariprasad Shenai u8 nchan; 33444588560SHariprasad Shenai u8 pm_stats_cnt; 3352216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3363ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3373ccc6cf7SHariprasad Shenai u16 vfcount; 3383ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3393ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3403ccc6cf7SHariprasad Shenai }; 3413ccc6cf7SHariprasad Shenai 342f7917c00SJeff Kirsher struct adapter_params { 343e85c9a7aSHariprasad Shenai struct sge_params sge; 344f7917c00SJeff Kirsher struct tp_params tp; 345f7917c00SJeff Kirsher struct vpd_params vpd; 346f7917c00SJeff Kirsher struct pci_params pci; 34749aa284fSHariprasad Shenai struct devlog_params devlog; 34849aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 349f7917c00SJeff Kirsher 350f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 351f1ff24aaSHariprasad Shenai 352f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 353f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 354f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 355f7917c00SJeff Kirsher 356760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3570de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 358760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3590de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 360760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 361760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 362f7917c00SJeff Kirsher u8 api_vers[7]; 363f7917c00SJeff Kirsher 364f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 365f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 366f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 367f7917c00SJeff Kirsher 368f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 369f7917c00SJeff Kirsher unsigned char portvec; 370d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3713ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 372f7917c00SJeff Kirsher unsigned char offload; 37394cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 374f7917c00SJeff Kirsher 3759a4da2cdSVipul Pandya unsigned char bypass; 3765c31254eSKumar Sanghvi unsigned char hash_filter; 3779a4da2cdSVipul Pandya 378f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3791ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3804c2c5763SHariprasad Shenai 381b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 3824c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3834c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 384086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 385c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 3860ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 3878f46d467SArjun Vynipadath 3888f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 3898f46d467SArjun Vynipadath * used by the Port 3908f46d467SArjun Vynipadath */ 3918f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 392f7917c00SJeff Kirsher }; 393f7917c00SJeff Kirsher 394a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 395a3bfb617SHariprasad Shenai * and possible hangs. 396a3bfb617SHariprasad Shenai */ 397a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 398a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 399a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 400a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 401a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 402a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 403a3bfb617SHariprasad Shenai }; 404a3bfb617SHariprasad Shenai 4057f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 4067f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 4077f080c3fSHariprasad Shenai * error returns. 4087f080c3fSHariprasad Shenai */ 4097f080c3fSHariprasad Shenai struct mbox_cmd { 4107f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 4117f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 4127f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 4137f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 4147f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 4157f080c3fSHariprasad Shenai }; 4167f080c3fSHariprasad Shenai 4177f080c3fSHariprasad Shenai struct mbox_cmd_log { 4187f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4197f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4207f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4217f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4227f080c3fSHariprasad Shenai }; 4237f080c3fSHariprasad Shenai 4247f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4257f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4267f080c3fSHariprasad Shenai */ 4277f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4287f080c3fSHariprasad Shenai unsigned int entry_idx) 4297f080c3fSHariprasad Shenai { 4307f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4317f080c3fSHariprasad Shenai } 4327f080c3fSHariprasad Shenai 43316e47624SHariprasad Shenai #include "t4fw_api.h" 43416e47624SHariprasad Shenai 43516e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 436b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 437b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 438b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 439b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 44016e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 44116e47624SHariprasad Shenai 44216e47624SHariprasad Shenai struct fw_info { 44316e47624SHariprasad Shenai u8 chip; 44416e47624SHariprasad Shenai char *fs_name; 44516e47624SHariprasad Shenai char *fw_mod_name; 44616e47624SHariprasad Shenai struct fw_hdr fw_hdr; 44716e47624SHariprasad Shenai }; 44816e47624SHariprasad Shenai 449f7917c00SJeff Kirsher struct trace_params { 450f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 451f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 452f7917c00SJeff Kirsher unsigned short snap_len; 453f7917c00SJeff Kirsher unsigned short min_len; 454f7917c00SJeff Kirsher unsigned char skip_ofst; 455f7917c00SJeff Kirsher unsigned char skip_len; 456f7917c00SJeff Kirsher unsigned char invert; 457f7917c00SJeff Kirsher unsigned char port; 458f7917c00SJeff Kirsher }; 459f7917c00SJeff Kirsher 460c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 461c3168cabSGanesh Goudar 462c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 463c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 464c3168cabSGanesh Goudar 465c3168cabSGanesh Goudar enum fw_caps { 466c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 467c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 468c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 469c3168cabSGanesh Goudar }; 470c3168cabSGanesh Goudar 471f7917c00SJeff Kirsher struct link_config { 472c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 473c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 474c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 475c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 476c3168cabSGanesh Goudar 477c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 478c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 479c3168cabSGanesh Goudar 480c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 481c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 482c3168cabSGanesh Goudar 483c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 484c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 485c3168cabSGanesh Goudar 486f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 487c3168cabSGanesh Goudar 488f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 489ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 490f7917c00SJeff Kirsher }; 491f7917c00SJeff Kirsher 492e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 493f7917c00SJeff Kirsher 494f7917c00SJeff Kirsher enum { 495f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 496f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 497f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 498f7917c00SJeff Kirsher }; 499f7917c00SJeff Kirsher 500f7917c00SJeff Kirsher enum { 501812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 502812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 503812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 504812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 505812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 506812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 507812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 508812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 509812034f1SHariprasad Shenai }; 510812034f1SHariprasad Shenai 511812034f1SHariprasad Shenai enum { 512cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 513cf38be6dSHariprasad Shenai /* forwarded interrupts */ 5140fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 515f7917c00SJeff Kirsher }; 516f7917c00SJeff Kirsher 517f7917c00SJeff Kirsher struct adapter; 518f7917c00SJeff Kirsher struct sge_rspq; 519f7917c00SJeff Kirsher 520688848b1SAnish Bhatt #include "cxgb4_dcb.h" 521688848b1SAnish Bhatt 52276fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 52376fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 52476fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 52576fed8a9SVarun Prakash 526f7917c00SJeff Kirsher struct port_info { 527f7917c00SJeff Kirsher struct adapter *adapter; 528f7917c00SJeff Kirsher u16 viid; 529f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 530f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 531f7917c00SJeff Kirsher s8 mdio_addr; 53240e9de4bSHariprasad Shenai enum fw_port_type port_type; 533f7917c00SJeff Kirsher u8 mod_type; 534f7917c00SJeff Kirsher u8 port_id; 535f7917c00SJeff Kirsher u8 tx_chan; 536f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 537f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 538f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 539f7917c00SJeff Kirsher u8 rss_mode; 540f7917c00SJeff Kirsher struct link_config link_cfg; 541f7917c00SJeff Kirsher u16 *rss; 542a4cfd929SHariprasad Shenai struct port_stats stats_base; 543688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 544688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 545688848b1SAnish Bhatt #endif 54676fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 54776fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 54876fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5495e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5505e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 551a4569504SAtul Gupta bool ptp_enable; 552b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 553f7917c00SJeff Kirsher }; 554f7917c00SJeff Kirsher 555f7917c00SJeff Kirsher struct dentry; 556f7917c00SJeff Kirsher struct work_struct; 557f7917c00SJeff Kirsher 558f7917c00SJeff Kirsher enum { /* adapter flags */ 559f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 560144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 561144be3d9SGavin Shan USING_MSI = (1 << 2), 562144be3d9SGavin Shan USING_MSIX = (1 << 3), 563f7917c00SJeff Kirsher FW_OK = (1 << 4), 56413ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 56552367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 56652367a76SVipul Pandya MASTER_PF = (1 << 7), 56752367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 568b0ba9d5fSCasey Leedom ROOT_NO_RELAXED_ORDERING = (1 << 10), 569e1f6198eSGanesh Goudar SHUTTING_DOWN = (1 << 11), 570f7917c00SJeff Kirsher }; 571f7917c00SJeff Kirsher 57294cdb8bbSHariprasad Shenai enum { 57394cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 574a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 57594cdb8bbSHariprasad Shenai }; 57694cdb8bbSHariprasad Shenai 577f7917c00SJeff Kirsher struct rx_sw_desc; 578f7917c00SJeff Kirsher 579f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 580f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 581f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 582f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 583f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 584f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 585f7917c00SJeff Kirsher unsigned long large_alloc_failed; 58670055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 58770055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 588f7917c00SJeff Kirsher unsigned long starving; 589f7917c00SJeff Kirsher /* RO fields */ 590f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 591f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 592f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 593f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 594f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 595df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 596df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 597f7917c00SJeff Kirsher }; 598f7917c00SJeff Kirsher 599f7917c00SJeff Kirsher /* A packet gather list */ 600f7917c00SJeff Kirsher struct pkt_gl { 6015e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 602e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 603f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 604f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 605f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 606f7917c00SJeff Kirsher }; 607f7917c00SJeff Kirsher 608f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 609f7917c00SJeff Kirsher const struct pkt_gl *gl); 6102337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 6112337ba42SVarun Prakash /* LRO related declarations for ULD */ 6122337ba42SVarun Prakash struct t4_lro_mgr { 6132337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 6142337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 6152337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 6162337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6172337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6182337ba42SVarun Prakash }; 619f7917c00SJeff Kirsher 620f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 621f7917c00SJeff Kirsher struct napi_struct napi; 622f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 623f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 624f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 625f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 626f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 627e553ec3fSHariprasad Shenai u8 adaptive_rx; 628f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 629f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 630f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 631f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 632f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 633f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 634f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 635f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 636df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 637df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 638f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 639f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 640f7917c00SJeff Kirsher struct adapter *adap; 641f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 642f7917c00SJeff Kirsher rspq_handler_t handler; 6432337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 6442337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 645f7917c00SJeff Kirsher }; 646f7917c00SJeff Kirsher 647f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 648f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 649f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 650f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 651f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 652f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 653f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 654f7917c00SJeff Kirsher }; 655f7917c00SJeff Kirsher 656f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 657f7917c00SJeff Kirsher struct sge_rspq rspq; 658f7917c00SJeff Kirsher struct sge_fl fl; 659f7917c00SJeff Kirsher struct sge_eth_stats stats; 660f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 661f7917c00SJeff Kirsher 662f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 663f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 664f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 665f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 666f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 667f7917c00SJeff Kirsher }; 668f7917c00SJeff Kirsher 669f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 670f7917c00SJeff Kirsher struct sge_rspq rspq; 671f7917c00SJeff Kirsher struct sge_fl fl; 672f7917c00SJeff Kirsher struct sge_ofld_stats stats; 673f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 674f7917c00SJeff Kirsher 675f7917c00SJeff Kirsher struct tx_desc { 676f7917c00SJeff Kirsher __be64 flit[8]; 677f7917c00SJeff Kirsher }; 678f7917c00SJeff Kirsher 679f7917c00SJeff Kirsher struct tx_sw_desc; 680f7917c00SJeff Kirsher 681f7917c00SJeff Kirsher struct sge_txq { 682f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 683ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 684f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 685f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 686f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 687f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 688f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 689f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 690f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 691f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 692f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 693f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 6943069ee9bSVipul Pandya spinlock_t db_lock; 6953069ee9bSVipul Pandya int db_disabled; 6963069ee9bSVipul Pandya unsigned short db_pidx; 69705eb2389SSteve Wise unsigned short db_pidx_inc; 698df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 699df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 700f7917c00SJeff Kirsher }; 701f7917c00SJeff Kirsher 702f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 703f7917c00SJeff Kirsher struct sge_txq q; 704f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 70510b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 70610b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 70710b00466SAnish Bhatt #endif 708f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 709f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 710f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 711f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 712f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 713f7917c00SJeff Kirsher 714ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 715f7917c00SJeff Kirsher struct sge_txq q; 716f7917c00SJeff Kirsher struct adapter *adap; 717f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 718f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 719126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 720f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 721f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 722f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 723f7917c00SJeff Kirsher 724f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 725f7917c00SJeff Kirsher struct sge_txq q; 726f7917c00SJeff Kirsher struct adapter *adap; 727f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 728f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 729f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 730f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 731f7917c00SJeff Kirsher 73294cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 73394cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 73494cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 73594cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 73694cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 73794cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 73894cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 73994cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 74094cdb8bbSHariprasad Shenai }; 74194cdb8bbSHariprasad Shenai 742ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 743ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 744ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 745ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 746ab677ff4SHariprasad Shenai }; 747ab677ff4SHariprasad Shenai 748f7917c00SJeff Kirsher struct sge { 749f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 750a4569504SAtul Gupta struct sge_eth_txq ptptxq; 751f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 752f7917c00SJeff Kirsher 753f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 754f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 75594cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 756ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 757f7917c00SJeff Kirsher 758f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 759f7917c00SJeff Kirsher spinlock_t intrq_lock; 760f7917c00SJeff Kirsher 761f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 762f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 763f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 7640fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 76594cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 766f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 767f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 76852367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 76952367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 77052367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 77152367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 77252367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 7730f4d201fSKumar Sanghvi 774a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 775f7917c00SJeff Kirsher unsigned int egr_start; 7764b8e27a8SHariprasad Shenai unsigned int egr_sz; 777f7917c00SJeff Kirsher unsigned int ingr_start; 7784b8e27a8SHariprasad Shenai unsigned int ingr_sz; 7794b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 7804b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 7814b8e27a8SHariprasad Shenai unsigned long *starving_fl; 7824b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 7835b377d11SHariprasad Shenai unsigned long *blocked_fl; 784f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 785f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 786f7917c00SJeff Kirsher }; 787f7917c00SJeff Kirsher 788f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 7890fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 790f7917c00SJeff Kirsher 791f7917c00SJeff Kirsher struct l2t_data; 792f7917c00SJeff Kirsher 7932422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 7942422d9a3SSantosh Rastapur 7957d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 7967d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 7977d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 7982422d9a3SSantosh Rastapur */ 7997d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 8002422d9a3SSantosh Rastapur 8012422d9a3SSantosh Rastapur #endif 8022422d9a3SSantosh Rastapur 803a4cfd929SHariprasad Shenai struct doorbell_stats { 804a4cfd929SHariprasad Shenai u32 db_drop; 805a4cfd929SHariprasad Shenai u32 db_empty; 806a4cfd929SHariprasad Shenai u32 db_full; 807a4cfd929SHariprasad Shenai }; 808a4cfd929SHariprasad Shenai 809fc08a01aSHariprasad Shenai struct hash_mac_addr { 810fc08a01aSHariprasad Shenai struct list_head list; 811fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 812fc08a01aSHariprasad Shenai }; 813fc08a01aSHariprasad Shenai 81494cdb8bbSHariprasad Shenai struct uld_msix_bmap { 81594cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 81694cdb8bbSHariprasad Shenai unsigned int mapsize; 81794cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 81894cdb8bbSHariprasad Shenai }; 81994cdb8bbSHariprasad Shenai 82094cdb8bbSHariprasad Shenai struct uld_msix_info { 82194cdb8bbSHariprasad Shenai unsigned short vec; 82294cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 8230fbc81b3SHariprasad Shenai unsigned int idx; 82494cdb8bbSHariprasad Shenai }; 82594cdb8bbSHariprasad Shenai 826661dbeb9SHariprasad Shenai struct vf_info { 827661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 8288ea4fae9SGanesh Goudar unsigned int tx_rate; 829661dbeb9SHariprasad Shenai bool pf_set_mac; 830661dbeb9SHariprasad Shenai }; 831661dbeb9SHariprasad Shenai 8324055ae5eSHariprasad Shenai struct mbox_list { 8334055ae5eSHariprasad Shenai struct list_head list; 8344055ae5eSHariprasad Shenai }; 8354055ae5eSHariprasad Shenai 836f7917c00SJeff Kirsher struct adapter { 837f7917c00SJeff Kirsher void __iomem *regs; 83822adfe0aSSantosh Rastapur void __iomem *bar2; 8390abfd152SHariprasad Shenai u32 t4_bar0; 840f7917c00SJeff Kirsher struct pci_dev *pdev; 841f7917c00SJeff Kirsher struct device *pdev_dev; 8420de72738SHariprasad Shenai const char *name; 8433069ee9bSVipul Pandya unsigned int mbox; 844b2612722SHariprasad Shenai unsigned int pf; 845f7917c00SJeff Kirsher unsigned int flags; 846e7b48a32SHariprasad Shenai unsigned int adap_idx; 8472422d9a3SSantosh Rastapur enum chip_type chip; 848f7917c00SJeff Kirsher 849f7917c00SJeff Kirsher int msg_enable; 850f7917c00SJeff Kirsher 851f7917c00SJeff Kirsher struct adapter_params params; 852f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 853f7917c00SJeff Kirsher unsigned int swintr; 854f7917c00SJeff Kirsher 855f7917c00SJeff Kirsher struct { 856f7917c00SJeff Kirsher unsigned short vec; 857f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 858f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 85994cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 86094cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 8610fbc81b3SHariprasad Shenai int msi_idx; 862f7917c00SJeff Kirsher 863a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 864f7917c00SJeff Kirsher struct sge sge; 865f7917c00SJeff Kirsher 866f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 867f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 868f7917c00SJeff Kirsher 869661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 870661dbeb9SHariprasad Shenai u8 num_vfs; 871661dbeb9SHariprasad Shenai 872793dad94SVipul Pandya u32 filter_mode; 873636f9d37SVipul Pandya unsigned int l2t_start; 874636f9d37SVipul Pandya unsigned int l2t_end; 875f7917c00SJeff Kirsher struct l2t_data *l2t; 876b5a02f50SAnish Bhatt unsigned int clipt_start; 877b5a02f50SAnish Bhatt unsigned int clipt_end; 878b5a02f50SAnish Bhatt struct clip_tbl *clipt; 8793bdb376eSKumar Sanghvi struct smt_data *smt; 8800fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 881f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 88294cdb8bbSHariprasad Shenai unsigned int num_uld; 8830fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 884f7917c00SJeff Kirsher struct list_head list_node; 88501bcca68SVipul Pandya struct list_head rcu_node; 886fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 887f7917c00SJeff Kirsher 8887714cb9eSVarun Prakash void *iscsi_ppm; 8897714cb9eSVarun Prakash 890f7917c00SJeff Kirsher struct tid_info tids; 891f7917c00SJeff Kirsher void **tid_release_head; 892f7917c00SJeff Kirsher spinlock_t tid_release_lock; 89329aaee65SAnish Bhatt struct workqueue_struct *workq; 894f7917c00SJeff Kirsher struct work_struct tid_release_task; 895881806bcSVipul Pandya struct work_struct db_full_task; 896881806bcSVipul Pandya struct work_struct db_drop_task; 897f7917c00SJeff Kirsher bool tid_release_task_busy; 898f7917c00SJeff Kirsher 8994055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 9004055ae5eSHariprasad Shenai spinlock_t mbox_lock; 9014055ae5eSHariprasad Shenai struct mbox_list mlist; 9024055ae5eSHariprasad Shenai 9037f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 9047f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 9057f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 9067f080c3fSHariprasad Shenai 9070fbc81b3SHariprasad Shenai struct mutex uld_mutex; 9080fbc81b3SHariprasad Shenai 909f7917c00SJeff Kirsher struct dentry *debugfs_root; 910621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 911621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 9128e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 9138e3d04fdSHariprasad Shenai * used for all 4 filters. 9148e3d04fdSHariprasad Shenai */ 915f7917c00SJeff Kirsher 916a4569504SAtul Gupta struct ptp_clock *ptp_clock; 917a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 918a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 919a4569504SAtul Gupta /* ptp lock */ 920a4569504SAtul Gupta spinlock_t ptp_lock; 921f7917c00SJeff Kirsher spinlock_t stats_lock; 922fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 923d8931847SRahul Lakkireddy 924d8931847SRahul Lakkireddy /* TC u32 offload */ 925d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 926ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 92762488e4bSKumar Sanghvi 92862488e4bSKumar Sanghvi /* TC flower offload */ 92979e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 93079e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 931e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 93279e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 933ad75b7d3SRahul Lakkireddy 934ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 935ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 936f7917c00SJeff Kirsher }; 937f7917c00SJeff Kirsher 938b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 939b72a32daSRahul Lakkireddy * programmed with various parameters. 940b72a32daSRahul Lakkireddy */ 941b72a32daSRahul Lakkireddy struct ch_sched_params { 942b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 943b72a32daSRahul Lakkireddy union { 944b72a32daSRahul Lakkireddy struct { 945b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 946b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 947b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 948b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 949b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 950b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 951b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 952b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 953b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 954b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 955b72a32daSRahul Lakkireddy } params; 956b72a32daSRahul Lakkireddy } u; 957b72a32daSRahul Lakkireddy }; 958b72a32daSRahul Lakkireddy 95910a2604eSRahul Lakkireddy enum { 96010a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 96110a2604eSRahul Lakkireddy }; 96210a2604eSRahul Lakkireddy 96310a2604eSRahul Lakkireddy enum { 96410a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 96510a2604eSRahul Lakkireddy }; 96610a2604eSRahul Lakkireddy 96710a2604eSRahul Lakkireddy enum { 96810a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 96910a2604eSRahul Lakkireddy }; 97010a2604eSRahul Lakkireddy 97110a2604eSRahul Lakkireddy enum { 97210a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 97310a2604eSRahul Lakkireddy }; 97410a2604eSRahul Lakkireddy 97510a2604eSRahul Lakkireddy enum { 97610a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 97710a2604eSRahul Lakkireddy }; 97810a2604eSRahul Lakkireddy 979a6ec572bSAtul Gupta struct tx_sw_desc { /* SW state per Tx descriptor */ 980a6ec572bSAtul Gupta struct sk_buff *skb; 981a6ec572bSAtul Gupta struct ulptx_sgl *sgl; 982a6ec572bSAtul Gupta }; 983a6ec572bSAtul Gupta 9846cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 9856cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 9866cede1f1SRahul Lakkireddy */ 9876cede1f1SRahul Lakkireddy struct ch_sched_queue { 9886cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 9896cede1f1SRahul Lakkireddy s8 class; /* class index */ 9906cede1f1SRahul Lakkireddy }; 9916cede1f1SRahul Lakkireddy 992f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 993f2b7e78dSVipul Pandya */ 994f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 995f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 996f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 997f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 998f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 999f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1000f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1001f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1002f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1003f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1004f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1005f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 1006f2b7e78dSVipul Pandya 1007f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1008f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1009f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1010f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1011f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1012f2b7e78dSVipul Pandya * matching rules are true. 1013f2b7e78dSVipul Pandya * 1014f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1015f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1016f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1017f2b7e78dSVipul Pandya * MPS match type) ... 1018f2b7e78dSVipul Pandya * 1019f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1020f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1021f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1022f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1023f2b7e78dSVipul Pandya */ 1024f2b7e78dSVipul Pandya struct ch_filter_tuple { 1025f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1026f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1027f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1028f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1029f2b7e78dSVipul Pandya * set of fields. 1030f2b7e78dSVipul Pandya */ 1031f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1032f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1033f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1034f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1035f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 1036f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1037f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1038f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1039f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1040f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1041f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1042f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1043f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1044f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1045f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1046f2b7e78dSVipul Pandya 1047f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1048f2b7e78dSVipul Pandya * available for field rules. 1049f2b7e78dSVipul Pandya */ 1050f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1051f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1052f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1053f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1054f2b7e78dSVipul Pandya }; 1055f2b7e78dSVipul Pandya 1056f2b7e78dSVipul Pandya /* A filter ioctl command. 1057f2b7e78dSVipul Pandya */ 1058f2b7e78dSVipul Pandya struct ch_filter_specification { 1059f2b7e78dSVipul Pandya /* Administrative fields for filter. 1060f2b7e78dSVipul Pandya */ 1061f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1062f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1063f2b7e78dSVipul Pandya 1064f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1065f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1066f2b7e78dSVipul Pandya */ 1067f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 106812b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1069f2b7e78dSVipul Pandya 1070f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1071f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1072f2b7e78dSVipul Pandya * out as egress packets. 1073f2b7e78dSVipul Pandya */ 1074f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1075f2b7e78dSVipul Pandya 1076f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1077f2b7e78dSVipul Pandya 1078f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1079f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1080f2b7e78dSVipul Pandya 1081f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1082f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1083f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1084f2b7e78dSVipul Pandya 1085f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1086f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1087f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1088f2b7e78dSVipul Pandya */ 1089f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1090f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1091f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1092f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 10930ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1094f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1095f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1096f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1097f2b7e78dSVipul Pandya 10980ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 10990ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 11000ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 11010ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 11020ff90994SKumar Sanghvi 11030ff90994SKumar Sanghvi /* reservation for future additions */ 11040ff90994SKumar Sanghvi u8 rsvd[24]; 11050ff90994SKumar Sanghvi 1106f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1107f2b7e78dSVipul Pandya */ 1108f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1109f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1110f2b7e78dSVipul Pandya }; 1111f2b7e78dSVipul Pandya 1112f2b7e78dSVipul Pandya enum { 1113f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1114f2b7e78dSVipul Pandya FILTER_DROP, 1115f2b7e78dSVipul Pandya FILTER_SWITCH 1116f2b7e78dSVipul Pandya }; 1117f2b7e78dSVipul Pandya 1118f2b7e78dSVipul Pandya enum { 1119f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1120f2b7e78dSVipul Pandya VLAN_REMOVE, 1121f2b7e78dSVipul Pandya VLAN_INSERT, 1122f2b7e78dSVipul Pandya VLAN_REWRITE 1123f2b7e78dSVipul Pandya }; 1124f2b7e78dSVipul Pandya 1125557ccbf9SKumar Sanghvi enum { 112612b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 112712b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 112812b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 112912b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 113012b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 113112b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 113212b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 113312b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1134557ccbf9SKumar Sanghvi }; 1135557ccbf9SKumar Sanghvi 1136d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1137d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1138d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1139d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1140d57fd6caSRahul Lakkireddy * where the filter table is large. 1141d57fd6caSRahul Lakkireddy */ 1142d57fd6caSRahul Lakkireddy struct filter_entry { 1143d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1144d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1145d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1146d57fd6caSRahul Lakkireddy 1147d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1148578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1149d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 11503bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1151578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1152578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1153d57fd6caSRahul Lakkireddy 1154d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1155d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1156d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1157d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1158d57fd6caSRahul Lakkireddy */ 1159d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1160d57fd6caSRahul Lakkireddy }; 1161d57fd6caSRahul Lakkireddy 1162a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1163a4cfd929SHariprasad Shenai { 1164a4cfd929SHariprasad Shenai return adap->params.offload; 1165a4cfd929SHariprasad Shenai } 1166a4cfd929SHariprasad Shenai 11675c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 11685c31254eSKumar Sanghvi { 11695c31254eSKumar Sanghvi return adap->params.hash_filter; 11705c31254eSKumar Sanghvi } 11715c31254eSKumar Sanghvi 117294cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 117394cdb8bbSHariprasad Shenai { 117494cdb8bbSHariprasad Shenai return adap->params.crypto; 117594cdb8bbSHariprasad Shenai } 117694cdb8bbSHariprasad Shenai 11770fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 11780fbc81b3SHariprasad Shenai { 11790fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 11800fbc81b3SHariprasad Shenai } 11810fbc81b3SHariprasad Shenai 1182f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1183f7917c00SJeff Kirsher { 1184f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1185f7917c00SJeff Kirsher } 1186f7917c00SJeff Kirsher 1187f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1188f7917c00SJeff Kirsher { 1189f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1190f7917c00SJeff Kirsher } 1191f7917c00SJeff Kirsher 1192f7917c00SJeff Kirsher #ifndef readq 1193f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1194f7917c00SJeff Kirsher { 1195f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1196f7917c00SJeff Kirsher } 1197f7917c00SJeff Kirsher 1198f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1199f7917c00SJeff Kirsher { 1200f7917c00SJeff Kirsher writel(val, addr); 1201f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1202f7917c00SJeff Kirsher } 1203f7917c00SJeff Kirsher #endif 1204f7917c00SJeff Kirsher 1205f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1206f7917c00SJeff Kirsher { 1207f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1208f7917c00SJeff Kirsher } 1209f7917c00SJeff Kirsher 1210f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1211f7917c00SJeff Kirsher { 1212f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1213f7917c00SJeff Kirsher } 1214f7917c00SJeff Kirsher 1215f7917c00SJeff Kirsher /** 1216098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1217098ef6c2SHariprasad Shenai * @adapter: the adapter 1218098ef6c2SHariprasad Shenai * @port_idx: the port index 1219098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1220098ef6c2SHariprasad Shenai * 1221098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1222098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1223098ef6c2SHariprasad Shenai */ 1224098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1225098ef6c2SHariprasad Shenai u8 hw_addr[]) 1226098ef6c2SHariprasad Shenai { 1227098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1228098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1229098ef6c2SHariprasad Shenai } 1230098ef6c2SHariprasad Shenai 1231098ef6c2SHariprasad Shenai /** 1232f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1233f7917c00SJeff Kirsher * @dev: the netdev 1234f7917c00SJeff Kirsher * 1235f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1236f7917c00SJeff Kirsher */ 1237f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1238f7917c00SJeff Kirsher { 1239f7917c00SJeff Kirsher return netdev_priv(dev); 1240f7917c00SJeff Kirsher } 1241f7917c00SJeff Kirsher 1242f7917c00SJeff Kirsher /** 1243f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1244f7917c00SJeff Kirsher * @adap: the adapter 1245f7917c00SJeff Kirsher * @idx: the port index 1246f7917c00SJeff Kirsher * 1247f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1248f7917c00SJeff Kirsher */ 1249f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1250f7917c00SJeff Kirsher { 1251f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1252f7917c00SJeff Kirsher } 1253f7917c00SJeff Kirsher 1254f7917c00SJeff Kirsher /** 1255f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1256f7917c00SJeff Kirsher * @dev: the netdev 1257f7917c00SJeff Kirsher * 1258f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1259f7917c00SJeff Kirsher */ 1260f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1261f7917c00SJeff Kirsher { 1262f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1263f7917c00SJeff Kirsher } 1264f7917c00SJeff Kirsher 1265812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1266812034f1SHariprasad Shenai * - bits 0..9: chip version 1267812034f1SHariprasad Shenai * - bits 10..15: chip revision 1268812034f1SHariprasad Shenai * - bits 16..23: register dump version 1269812034f1SHariprasad Shenai */ 1270812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1271812034f1SHariprasad Shenai { 1272812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1273812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1274812034f1SHariprasad Shenai } 1275812034f1SHariprasad Shenai 1276812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1277812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1278812034f1SHariprasad Shenai const struct sge_rspq *q) 1279812034f1SHariprasad Shenai { 1280812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1281812034f1SHariprasad Shenai 1282812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1283812034f1SHariprasad Shenai } 1284812034f1SHariprasad Shenai 1285812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1286812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1287812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1288812034f1SHariprasad Shenai 1289f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1290f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1291f7917c00SJeff Kirsher 1292f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 12935fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1294f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1295f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1296f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1297f7917c00SJeff Kirsher const struct pkt_gl *gl); 1298f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1299f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1300f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1301f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 13022337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 13032337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1304f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1305f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1306f7917c00SJeff Kirsher unsigned int iqid); 1307f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1308f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1309f7917c00SJeff Kirsher unsigned int cmplqid); 13100fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 13110fbc81b3SHariprasad Shenai unsigned int cmplqid); 1312ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1313ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1314ab677ff4SHariprasad Shenai unsigned int uld_type); 1315f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 131652367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1317f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1318f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1319812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1320812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 13213069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1322f7917c00SJeff Kirsher 1323f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1324f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1325f7917c00SJeff Kirsher 13269a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 13279a4da2cdSVipul Pandya { 13289a4da2cdSVipul Pandya return adap->params.bypass; 13299a4da2cdSVipul Pandya } 13309a4da2cdSVipul Pandya 13319a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 13329a4da2cdSVipul Pandya { 13339a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 13349a4da2cdSVipul Pandya switch (device) { 13359a4da2cdSVipul Pandya case 0x440b: 13369a4da2cdSVipul Pandya case 0x440c: 13379a4da2cdSVipul Pandya return 1; 13389a4da2cdSVipul Pandya default: 13399a4da2cdSVipul Pandya return 0; 13409a4da2cdSVipul Pandya } 13419a4da2cdSVipul Pandya } 13429a4da2cdSVipul Pandya 134301b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 134401b69614SHariprasad Shenai { 134501b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 134601b69614SHariprasad Shenai switch (device) { 134701b69614SHariprasad Shenai case 0x4409: 134801b69614SHariprasad Shenai case 0x4486: 134901b69614SHariprasad Shenai return 1; 135001b69614SHariprasad Shenai 135101b69614SHariprasad Shenai default: 135201b69614SHariprasad Shenai return 0; 135301b69614SHariprasad Shenai } 135401b69614SHariprasad Shenai } 135501b69614SHariprasad Shenai 1356f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1357f7917c00SJeff Kirsher { 1358f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1359f7917c00SJeff Kirsher } 1360f7917c00SJeff Kirsher 1361f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1362f7917c00SJeff Kirsher unsigned int us) 1363f7917c00SJeff Kirsher { 1364f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1365f7917c00SJeff Kirsher } 1366f7917c00SJeff Kirsher 136752367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 136852367a76SVipul Pandya unsigned int ticks) 136952367a76SVipul Pandya { 137052367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 137152367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 137252367a76SVipul Pandya adapter->params.vpd.cclk); 137352367a76SVipul Pandya } 137452367a76SVipul Pandya 137508c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 137608c4901bSRahul Lakkireddy unsigned int ticks) 137708c4901bSRahul Lakkireddy { 137808c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 137908c4901bSRahul Lakkireddy } 138008c4901bSRahul Lakkireddy 1381f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1382f7917c00SJeff Kirsher u32 val); 1383f7917c00SJeff Kirsher 138401b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 138501b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1386f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1387f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1388f7917c00SJeff Kirsher 138901b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 139001b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 139101b69614SHariprasad Shenai int timeout) 139201b69614SHariprasad Shenai { 139301b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 139401b69614SHariprasad Shenai timeout); 139501b69614SHariprasad Shenai } 139601b69614SHariprasad Shenai 1397f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1398f7917c00SJeff Kirsher int size, void *rpl) 1399f7917c00SJeff Kirsher { 1400f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1401f7917c00SJeff Kirsher } 1402f7917c00SJeff Kirsher 1403f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1404f7917c00SJeff Kirsher int size, void *rpl) 1405f7917c00SJeff Kirsher { 1406f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1407f7917c00SJeff Kirsher } 1408f7917c00SJeff Kirsher 1409fc08a01aSHariprasad Shenai /** 1410fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1411fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1412fc08a01aSHariprasad Shenai * 1413fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1414fc08a01aSHariprasad Shenai * (hash) address matching. 1415fc08a01aSHariprasad Shenai */ 1416fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1417fc08a01aSHariprasad Shenai { 1418fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1419fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1420fc08a01aSHariprasad Shenai 1421fc08a01aSHariprasad Shenai a ^= b; 1422fc08a01aSHariprasad Shenai a ^= (a >> 12); 1423fc08a01aSHariprasad Shenai a ^= (a >> 6); 1424fc08a01aSHariprasad Shenai return a & 0x3f; 1425fc08a01aSHariprasad Shenai } 1426fc08a01aSHariprasad Shenai 142794cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 142894cdb8bbSHariprasad Shenai unsigned int cnt); 142994cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 143094cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 143194cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 143294cdb8bbSHariprasad Shenai { 143394cdb8bbSHariprasad Shenai q->adap = adap; 143494cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 143594cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 143694cdb8bbSHariprasad Shenai q->size = size; 143794cdb8bbSHariprasad Shenai } 143894cdb8bbSHariprasad Shenai 143913ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 144013ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 144113ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1442f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1443f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1444f2b7e78dSVipul Pandya unsigned int start_idx); 14450abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1446f2b7e78dSVipul Pandya 1447f2b7e78dSVipul Pandya struct fw_filter_wr; 1448f2b7e78dSVipul Pandya 1449f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1450f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1451f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1452f7917c00SJeff Kirsher 14538203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 14544036da90SHariprasad Shenai int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1455f7917c00SJeff Kirsher struct link_config *lc); 1456f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1457fc5ab020SHariprasad Shenai 1458b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1459b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1460b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1461b562fc37SHariprasad Shenai 1462fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1463fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1464fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1465f01aa633SHariprasad Shenai void *buf, int dir); 1466fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1467fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1468fc5ab020SHariprasad Shenai { 1469fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1470fc5ab020SHariprasad Shenai } 1471fc5ab020SHariprasad Shenai 1472812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1473812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1474812034f1SHariprasad Shenai 1475940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1476f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1477098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1478098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 147949216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 148049216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1481f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 148201b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 148301b69614SHariprasad Shenai int win, spinlock_t *lock, 148401b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 148501b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 148601b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 148749216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 148822c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 148922c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1490acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1491636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1492a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 14934da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 149416e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 14950de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 149616e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1497ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1498760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1499760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1500760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1501760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 150216e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 150316e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 150416e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1505f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 15063be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1507e85c9a7aSHariprasad Shenai 1508e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1509b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1510e85c9a7aSHariprasad Shenai unsigned int qid, 1511e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 151266cf188eSHariprasad S int user, 1513e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1514e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1515e85c9a7aSHariprasad Shenai 1516dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1517dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1518ae469b68SHariprasad Shenai 1519ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1520e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 15215ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1522dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1523c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1524c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1525c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1526f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1527f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1528f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1529f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1530f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1531f7917c00SJeff Kirsher unsigned int flags); 1532c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1533c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1534688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 15355ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 15365ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 15375ccf9d04SRahul Lakkireddy bool sleep_ok); 1538688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 15395ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1540688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 15415ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 15425ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 15435ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1544688ea5feSHariprasad Shenai 1545193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1546193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1547b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1548b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1549e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1550e5f0e43bSHariprasad Shenai size_t n); 1551c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1552c778af7dSHariprasad Shenai size_t n); 1553f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1554f1ff24aaSHariprasad Shenai unsigned int *valp); 1555f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1556f1ff24aaSHariprasad Shenai const unsigned int *valp); 1557f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 155819689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 155919689609SHariprasad Shenai unsigned int *pif_req_wrptr, 156019689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 156126fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 156274b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 156372aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1564f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1565a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1566a4cfd929SHariprasad Shenai struct port_stats *stats, 1567a4cfd929SHariprasad Shenai struct port_stats *offset); 156865046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1569f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1570bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1571636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1572636f9d37SVipul Pandya unsigned int mask, unsigned int val); 15732d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 15745ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 15755ccf9d04SRahul Lakkireddy bool sleep_ok); 15765ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 15775ccf9d04SRahul Lakkireddy bool sleep_ok); 15785ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 15795ccf9d04SRahul Lakkireddy bool sleep_ok); 15805ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 15815ccf9d04SRahul Lakkireddy bool sleep_ok); 1582f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 15835ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1584a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 15855ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1586f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1587f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1588f7917c00SJeff Kirsher 1589797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1590797ff0f5SHariprasad Shenai 15917864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1592f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1593f2b7e78dSVipul Pandya 1594f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1595f7917c00SJeff Kirsher const u8 *addr); 1596f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1597f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1598f7917c00SJeff Kirsher 1599f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1600f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1601f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1602f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1603f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1604636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1605636f9d37SVipul Pandya unsigned int cache_line_size); 1606636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1607f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1608f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1609f7917c00SJeff Kirsher u32 *val); 16108f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 16118f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 16128f46d467SArjun Vynipadath u32 *val); 161301b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1614f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 16158f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 161601b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1617688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1618688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 161901b69614SHariprasad Shenai const u32 *val, int timeout); 162001b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 162101b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1622688848b1SAnish Bhatt const u32 *val); 1623f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1624f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1625f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1626f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1627f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1628f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1629f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1630f7917c00SJeff Kirsher unsigned int *rss_size); 16314f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 16324f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 16334f3a0fcfSHariprasad Shenai unsigned int viid); 1634f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1635f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1636f7917c00SJeff Kirsher bool sleep_ok); 1637f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1638f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1639f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1640fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1641fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1642fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1643f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1644f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1645f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1646f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1647688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1648688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1649f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1650f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1651f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1652f7917c00SJeff Kirsher unsigned int nblinks); 1653f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1654f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1655f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1656f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1657ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1658ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1659ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1660f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1661f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1662f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1663f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1664f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1665f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1666f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1667f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1668f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 16695d700ecbSHariprasad Shenai int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 167023853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 16712061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1672c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1673c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1674f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1675881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1676881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 16778e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 16788e3d04fdSHariprasad Shenai int filter_index, int enable); 16798e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 16808e3d04fdSHariprasad Shenai int filter_index, int *enabled); 16818caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 16828caa1e84SVipul Pandya u32 addr, u32 val); 168308c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 168408c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 168508c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 16869e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 16879e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 16889e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 16899e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 1690b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1691b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1692b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 169368bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1694a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1695a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1696a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1697a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1698a3bfb617SHariprasad Shenai int hz, int ticks); 1699858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1700858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 17015ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 17025ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 17034359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 17044359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 17055ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 17065ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 17075ccf9d04SRahul Lakkireddy 17080fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 17090fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 17100fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 17110fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 171294cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1713ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1714ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1715ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1716a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 1717a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 1718a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1719a6ec572bSAtul Gupta dma_addr_t *addr); 1720a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1721a6ec572bSAtul Gupta void *pos); 1722a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1723a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1724a6ec572bSAtul Gupta const dma_addr_t *addr); 1725a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 1726f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1727