1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 490eb71a9dSNeilBrown #include <linux/rhashtable.h> 50098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 515e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 52a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 53a4569504SAtul Gupta #include <linux/ptp_classify.h> 541dde532dSRahul Lakkireddy #include <linux/crash_dump.h> 55f7917c00SJeff Kirsher #include <asm/io.h> 5627999805SHariprasad S #include "t4_chip_type.h" 57f7917c00SJeff Kirsher #include "cxgb4_uld.h" 58f7917c00SJeff Kirsher 593069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 6094cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 6194cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 623069ee9bSVipul Pandya 63a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 64a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 65a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 66a6ec572bSAtul Gupta */ 67a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 68a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 69a6ec572bSAtul Gupta 70f7917c00SJeff Kirsher enum { 71f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 72f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 73f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 74f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 75a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 76098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 77f7917c00SJeff Kirsher }; 78f7917c00SJeff Kirsher 79f7917c00SJeff Kirsher enum { 80812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 81812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 82812034f1SHariprasad Shenai }; 83812034f1SHariprasad Shenai 84812034f1SHariprasad Shenai enum { 85f7917c00SJeff Kirsher MEM_EDC0, 86f7917c00SJeff Kirsher MEM_EDC1, 872422d9a3SSantosh Rastapur MEM_MC, 882422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 894db0401fSRahul Lakkireddy MEM_MC1, 904db0401fSRahul Lakkireddy MEM_HMA, 91f7917c00SJeff Kirsher }; 92f7917c00SJeff Kirsher 933069ee9bSVipul Pandya enum { 943eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 953eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 963069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 973069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 982422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 993eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 1003eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 1010abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 1020abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1033069ee9bSVipul Pandya }; 1043069ee9bSVipul Pandya 105f7917c00SJeff Kirsher enum dev_master { 106f7917c00SJeff Kirsher MASTER_CANT, 107f7917c00SJeff Kirsher MASTER_MAY, 108f7917c00SJeff Kirsher MASTER_MUST 109f7917c00SJeff Kirsher }; 110f7917c00SJeff Kirsher 111f7917c00SJeff Kirsher enum dev_state { 112f7917c00SJeff Kirsher DEV_STATE_UNINIT, 113f7917c00SJeff Kirsher DEV_STATE_INIT, 114f7917c00SJeff Kirsher DEV_STATE_ERR 115f7917c00SJeff Kirsher }; 116f7917c00SJeff Kirsher 117c3168cabSGanesh Goudar enum cc_pause { 118f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 119f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 120f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 121f7917c00SJeff Kirsher }; 122f7917c00SJeff Kirsher 123c3168cabSGanesh Goudar enum cc_fec { 1243bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1253bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1263bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1273bb4858fSGanesh Goudar }; 1283bb4858fSGanesh Goudar 129f7917c00SJeff Kirsher struct port_stats { 130f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 131f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 132f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 133f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 134f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 135f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 136f7917c00SJeff Kirsher 137f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 138f7917c00SJeff Kirsher u64 tx_frames_65_127; 139f7917c00SJeff Kirsher u64 tx_frames_128_255; 140f7917c00SJeff Kirsher u64 tx_frames_256_511; 141f7917c00SJeff Kirsher u64 tx_frames_512_1023; 142f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 143f7917c00SJeff Kirsher u64 tx_frames_1519_max; 144f7917c00SJeff Kirsher 145f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 146f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 147f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 148f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 149f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 150f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 151f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 152f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 153f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 154f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 155f7917c00SJeff Kirsher 156f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 157f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 158f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 159f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 160f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 161f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 162f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 163f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 164f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 165f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 166f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 167f7917c00SJeff Kirsher 168f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 169f7917c00SJeff Kirsher u64 rx_frames_65_127; 170f7917c00SJeff Kirsher u64 rx_frames_128_255; 171f7917c00SJeff Kirsher u64 rx_frames_256_511; 172f7917c00SJeff Kirsher u64 rx_frames_512_1023; 173f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 174f7917c00SJeff Kirsher u64 rx_frames_1519_max; 175f7917c00SJeff Kirsher 176f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 177f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 178f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 179f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 180f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 181f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 182f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 183f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 184f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 185f7917c00SJeff Kirsher 186f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 187f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 188f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 189f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 190f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 191f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 192f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 193f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 194f7917c00SJeff Kirsher }; 195f7917c00SJeff Kirsher 196f7917c00SJeff Kirsher struct lb_port_stats { 197f7917c00SJeff Kirsher u64 octets; 198f7917c00SJeff Kirsher u64 frames; 199f7917c00SJeff Kirsher u64 bcast_frames; 200f7917c00SJeff Kirsher u64 mcast_frames; 201f7917c00SJeff Kirsher u64 ucast_frames; 202f7917c00SJeff Kirsher u64 error_frames; 203f7917c00SJeff Kirsher 204f7917c00SJeff Kirsher u64 frames_64; 205f7917c00SJeff Kirsher u64 frames_65_127; 206f7917c00SJeff Kirsher u64 frames_128_255; 207f7917c00SJeff Kirsher u64 frames_256_511; 208f7917c00SJeff Kirsher u64 frames_512_1023; 209f7917c00SJeff Kirsher u64 frames_1024_1518; 210f7917c00SJeff Kirsher u64 frames_1519_max; 211f7917c00SJeff Kirsher 212f7917c00SJeff Kirsher u64 drop; 213f7917c00SJeff Kirsher 214f7917c00SJeff Kirsher u64 ovflow0; 215f7917c00SJeff Kirsher u64 ovflow1; 216f7917c00SJeff Kirsher u64 ovflow2; 217f7917c00SJeff Kirsher u64 ovflow3; 218f7917c00SJeff Kirsher u64 trunc0; 219f7917c00SJeff Kirsher u64 trunc1; 220f7917c00SJeff Kirsher u64 trunc2; 221f7917c00SJeff Kirsher u64 trunc3; 222f7917c00SJeff Kirsher }; 223f7917c00SJeff Kirsher 224f7917c00SJeff Kirsher struct tp_tcp_stats { 225a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 226a4cfd929SHariprasad Shenai u64 tcp_in_segs; 227a4cfd929SHariprasad Shenai u64 tcp_out_segs; 228a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 229a4cfd929SHariprasad Shenai }; 230a4cfd929SHariprasad Shenai 231a4cfd929SHariprasad Shenai struct tp_usm_stats { 232a4cfd929SHariprasad Shenai u32 frames; 233a4cfd929SHariprasad Shenai u32 drops; 234a4cfd929SHariprasad Shenai u64 octets; 235f7917c00SJeff Kirsher }; 236f7917c00SJeff Kirsher 237a6222975SHariprasad Shenai struct tp_fcoe_stats { 238a6222975SHariprasad Shenai u32 frames_ddp; 239a6222975SHariprasad Shenai u32 frames_drop; 240a6222975SHariprasad Shenai u64 octets_ddp; 241f7917c00SJeff Kirsher }; 242f7917c00SJeff Kirsher 243f7917c00SJeff Kirsher struct tp_err_stats { 244a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 245a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 246a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 247a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 248a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 249a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 250a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 251a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 252a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 253a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 254a4cfd929SHariprasad Shenai }; 255a4cfd929SHariprasad Shenai 256a6222975SHariprasad Shenai struct tp_cpl_stats { 257a6222975SHariprasad Shenai u32 req[4]; 258a6222975SHariprasad Shenai u32 rsp[4]; 259a6222975SHariprasad Shenai }; 260a6222975SHariprasad Shenai 261a4cfd929SHariprasad Shenai struct tp_rdma_stats { 262a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 263a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 264f7917c00SJeff Kirsher }; 265f7917c00SJeff Kirsher 266e85c9a7aSHariprasad Shenai struct sge_params { 267e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 268e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 269e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 270e85c9a7aSHariprasad Shenai }; 271e85c9a7aSHariprasad Shenai 272f7917c00SJeff Kirsher struct tp_params { 273f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2742d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 275dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 276dca4faebSVipul Pandya /* channel map */ 277636f9d37SVipul Pandya 278636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 279636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 280dcf7b6f5SKumar Sanghvi 281dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 282dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 283dcf7b6f5SKumar Sanghvi 2848eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2858eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2868eb9f2f9SArjun V */ 2878eb9f2f9SArjun V int rx_pkt_encap; 2888eb9f2f9SArjun V 289dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 290dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 291dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 292dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 293dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 294dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 295dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 296dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 297dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 298dcf7b6f5SKumar Sanghvi * present. 299dcf7b6f5SKumar Sanghvi */ 3000ba9a3b6SKumar Sanghvi int fcoe_shift; 301dcf7b6f5SKumar Sanghvi int port_shift; 3020ba9a3b6SKumar Sanghvi int vnic_shift; 3030ba9a3b6SKumar Sanghvi int vlan_shift; 3040ba9a3b6SKumar Sanghvi int tos_shift; 305dcf7b6f5SKumar Sanghvi int protocol_shift; 3060ba9a3b6SKumar Sanghvi int ethertype_shift; 3070ba9a3b6SKumar Sanghvi int macmatch_shift; 3080ba9a3b6SKumar Sanghvi int matchtype_shift; 3090ba9a3b6SKumar Sanghvi int frag_shift; 3100ba9a3b6SKumar Sanghvi 3110ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 312f7917c00SJeff Kirsher }; 313f7917c00SJeff Kirsher 314f7917c00SJeff Kirsher struct vpd_params { 315f7917c00SJeff Kirsher unsigned int cclk; 316f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 317f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 318f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 319a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 320098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 321f7917c00SJeff Kirsher }; 322f7917c00SJeff Kirsher 323f7917c00SJeff Kirsher struct pci_params { 324baf50868SGanesh Goudar unsigned int vpd_cap_addr; 325f7917c00SJeff Kirsher unsigned char speed; 326f7917c00SJeff Kirsher unsigned char width; 327f7917c00SJeff Kirsher }; 328f7917c00SJeff Kirsher 32949aa284fSHariprasad Shenai struct devlog_params { 33049aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 33149aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 33249aa284fSHariprasad Shenai u32 size; /* size of log */ 33349aa284fSHariprasad Shenai }; 33449aa284fSHariprasad Shenai 3353ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3363ccc6cf7SHariprasad Shenai struct arch_specific_params { 3373ccc6cf7SHariprasad Shenai u8 nchan; 33844588560SHariprasad Shenai u8 pm_stats_cnt; 3392216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3403ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3413ccc6cf7SHariprasad Shenai u16 vfcount; 3423ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3433ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3443ccc6cf7SHariprasad Shenai }; 3453ccc6cf7SHariprasad Shenai 346f7917c00SJeff Kirsher struct adapter_params { 347e85c9a7aSHariprasad Shenai struct sge_params sge; 348f7917c00SJeff Kirsher struct tp_params tp; 349f7917c00SJeff Kirsher struct vpd_params vpd; 350f7917c00SJeff Kirsher struct pci_params pci; 35149aa284fSHariprasad Shenai struct devlog_params devlog; 35249aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 353f7917c00SJeff Kirsher 354f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 355f1ff24aaSHariprasad Shenai 356f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 357f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 358f7917c00SJeff Kirsher 359760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3600de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 361760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3620de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 363760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 364760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 365f7917c00SJeff Kirsher u8 api_vers[7]; 366f7917c00SJeff Kirsher 367f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 368f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 369f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 370f7917c00SJeff Kirsher 371f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 372f7917c00SJeff Kirsher unsigned char portvec; 373d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3743ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 375f7917c00SJeff Kirsher unsigned char offload; 37694cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 377f7917c00SJeff Kirsher 3789a4da2cdSVipul Pandya unsigned char bypass; 3795c31254eSKumar Sanghvi unsigned char hash_filter; 3809a4da2cdSVipul Pandya 381f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3821ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3834c2c5763SHariprasad Shenai 384b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 3854c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3864c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 387086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 388c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 3890ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 3908f46d467SArjun Vynipadath 3918f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 3928f46d467SArjun Vynipadath * used by the Port 3938f46d467SArjun Vynipadath */ 3948f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 39543db9296SRaju Rangoju bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 396f3910c62SRaju Rangoju bool write_cmpl_support; /* FW supports WRITE_CMPL */ 397f7917c00SJeff Kirsher }; 398f7917c00SJeff Kirsher 399a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 400a3bfb617SHariprasad Shenai * and possible hangs. 401a3bfb617SHariprasad Shenai */ 402a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 403a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 404a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 405a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 406a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 407a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 408a3bfb617SHariprasad Shenai }; 409a3bfb617SHariprasad Shenai 4107f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 4117f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 4127f080c3fSHariprasad Shenai * error returns. 4137f080c3fSHariprasad Shenai */ 4147f080c3fSHariprasad Shenai struct mbox_cmd { 4157f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 4167f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 4177f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 4187f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 4197f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 4207f080c3fSHariprasad Shenai }; 4217f080c3fSHariprasad Shenai 4227f080c3fSHariprasad Shenai struct mbox_cmd_log { 4237f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4247f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4257f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4267f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4277f080c3fSHariprasad Shenai }; 4287f080c3fSHariprasad Shenai 4297f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4307f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4317f080c3fSHariprasad Shenai */ 4327f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4337f080c3fSHariprasad Shenai unsigned int entry_idx) 4347f080c3fSHariprasad Shenai { 4357f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4367f080c3fSHariprasad Shenai } 4377f080c3fSHariprasad Shenai 43816e47624SHariprasad Shenai #include "t4fw_api.h" 43916e47624SHariprasad Shenai 44016e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 441b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 442b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 443b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 444b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 44516e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 44616e47624SHariprasad Shenai 44716e47624SHariprasad Shenai struct fw_info { 44816e47624SHariprasad Shenai u8 chip; 44916e47624SHariprasad Shenai char *fs_name; 45016e47624SHariprasad Shenai char *fw_mod_name; 45116e47624SHariprasad Shenai struct fw_hdr fw_hdr; 45216e47624SHariprasad Shenai }; 45316e47624SHariprasad Shenai 454f7917c00SJeff Kirsher struct trace_params { 455f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 456f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 457f7917c00SJeff Kirsher unsigned short snap_len; 458f7917c00SJeff Kirsher unsigned short min_len; 459f7917c00SJeff Kirsher unsigned char skip_ofst; 460f7917c00SJeff Kirsher unsigned char skip_len; 461f7917c00SJeff Kirsher unsigned char invert; 462f7917c00SJeff Kirsher unsigned char port; 463f7917c00SJeff Kirsher }; 464f7917c00SJeff Kirsher 465c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 466c3168cabSGanesh Goudar 467c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 468c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 469c3168cabSGanesh Goudar 470c3168cabSGanesh Goudar enum fw_caps { 471c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 472c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 473c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 474c3168cabSGanesh Goudar }; 475c3168cabSGanesh Goudar 476f7917c00SJeff Kirsher struct link_config { 477c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 478c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 479c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 480c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 481c3168cabSGanesh Goudar 482c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 483c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 484c3168cabSGanesh Goudar 485c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 486c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 487c3168cabSGanesh Goudar 488c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 489c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 490c3168cabSGanesh Goudar 491f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 492c3168cabSGanesh Goudar 493f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 494ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 4958156b0baSGanesh Goudar 4968156b0baSGanesh Goudar bool new_module; /* ->OS Transceiver Module inserted */ 4978156b0baSGanesh Goudar bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 498f7917c00SJeff Kirsher }; 499f7917c00SJeff Kirsher 500e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 501f7917c00SJeff Kirsher 502f7917c00SJeff Kirsher enum { 503f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 504f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 505f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 506f7917c00SJeff Kirsher }; 507f7917c00SJeff Kirsher 508f7917c00SJeff Kirsher enum { 509812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 510812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 511812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 512812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 513812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 514812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 515812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 516812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 517812034f1SHariprasad Shenai }; 518812034f1SHariprasad Shenai 519812034f1SHariprasad Shenai enum { 520cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 521cf38be6dSHariprasad Shenai /* forwarded interrupts */ 5220fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 523f7917c00SJeff Kirsher }; 524f7917c00SJeff Kirsher 525f7917c00SJeff Kirsher struct adapter; 526f7917c00SJeff Kirsher struct sge_rspq; 527f7917c00SJeff Kirsher 528688848b1SAnish Bhatt #include "cxgb4_dcb.h" 529688848b1SAnish Bhatt 53076fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 53176fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 53276fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 53376fed8a9SVarun Prakash 534f7917c00SJeff Kirsher struct port_info { 535f7917c00SJeff Kirsher struct adapter *adapter; 536f7917c00SJeff Kirsher u16 viid; 537f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 538f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 539f7917c00SJeff Kirsher s8 mdio_addr; 54040e9de4bSHariprasad Shenai enum fw_port_type port_type; 541f7917c00SJeff Kirsher u8 mod_type; 542f7917c00SJeff Kirsher u8 port_id; 543f7917c00SJeff Kirsher u8 tx_chan; 544f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 545f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 546f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 547f7917c00SJeff Kirsher u8 rss_mode; 548f7917c00SJeff Kirsher struct link_config link_cfg; 549f7917c00SJeff Kirsher u16 *rss; 550a4cfd929SHariprasad Shenai struct port_stats stats_base; 551688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 552688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 553688848b1SAnish Bhatt #endif 55476fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 55576fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 55676fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5575e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5585e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 559a4569504SAtul Gupta bool ptp_enable; 560b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 561f7917c00SJeff Kirsher }; 562f7917c00SJeff Kirsher 563f7917c00SJeff Kirsher struct dentry; 564f7917c00SJeff Kirsher struct work_struct; 565f7917c00SJeff Kirsher 566f7917c00SJeff Kirsher enum { /* adapter flags */ 567f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 568144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 569144be3d9SGavin Shan USING_MSI = (1 << 2), 570144be3d9SGavin Shan USING_MSIX = (1 << 3), 571f7917c00SJeff Kirsher FW_OK = (1 << 4), 57213ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 57352367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 57452367a76SVipul Pandya MASTER_PF = (1 << 7), 57552367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 576b0ba9d5fSCasey Leedom ROOT_NO_RELAXED_ORDERING = (1 << 10), 577e1f6198eSGanesh Goudar SHUTTING_DOWN = (1 << 11), 578f7917c00SJeff Kirsher }; 579f7917c00SJeff Kirsher 58094cdb8bbSHariprasad Shenai enum { 58194cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 582a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 58394cdb8bbSHariprasad Shenai }; 58494cdb8bbSHariprasad Shenai 585f7917c00SJeff Kirsher struct rx_sw_desc; 586f7917c00SJeff Kirsher 587f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 588f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 589f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 590f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 591f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 592f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 593f7917c00SJeff Kirsher unsigned long large_alloc_failed; 59470055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 59570055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 596f7917c00SJeff Kirsher unsigned long starving; 597f7917c00SJeff Kirsher /* RO fields */ 598f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 599f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 600f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 601f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 602f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 603df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 604df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 605f7917c00SJeff Kirsher }; 606f7917c00SJeff Kirsher 607f7917c00SJeff Kirsher /* A packet gather list */ 608f7917c00SJeff Kirsher struct pkt_gl { 6095e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 610e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 611f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 612f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 613f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 614f7917c00SJeff Kirsher }; 615f7917c00SJeff Kirsher 616f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 617f7917c00SJeff Kirsher const struct pkt_gl *gl); 6182337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 6192337ba42SVarun Prakash /* LRO related declarations for ULD */ 6202337ba42SVarun Prakash struct t4_lro_mgr { 6212337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 6222337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 6232337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 6242337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6252337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6262337ba42SVarun Prakash }; 627f7917c00SJeff Kirsher 628f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 629f7917c00SJeff Kirsher struct napi_struct napi; 630f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 631f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 632f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 633f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 634f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 635e553ec3fSHariprasad Shenai u8 adaptive_rx; 636f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 637f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 638f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 639f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 640f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 641f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 642f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 643f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 644df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 645df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 646f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 647f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 648f7917c00SJeff Kirsher struct adapter *adap; 649f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 650f7917c00SJeff Kirsher rspq_handler_t handler; 6512337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 6522337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 653f7917c00SJeff Kirsher }; 654f7917c00SJeff Kirsher 655f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 656f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 657f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 658f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 659f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 660f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 661f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 662f7917c00SJeff Kirsher }; 663f7917c00SJeff Kirsher 664f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 665f7917c00SJeff Kirsher struct sge_rspq rspq; 666f7917c00SJeff Kirsher struct sge_fl fl; 667f7917c00SJeff Kirsher struct sge_eth_stats stats; 668f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 669f7917c00SJeff Kirsher 670f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 671f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 672f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 673f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 674f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 675f7917c00SJeff Kirsher }; 676f7917c00SJeff Kirsher 677f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 678f7917c00SJeff Kirsher struct sge_rspq rspq; 679f7917c00SJeff Kirsher struct sge_fl fl; 680f7917c00SJeff Kirsher struct sge_ofld_stats stats; 681f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 682f7917c00SJeff Kirsher 683f7917c00SJeff Kirsher struct tx_desc { 684f7917c00SJeff Kirsher __be64 flit[8]; 685f7917c00SJeff Kirsher }; 686f7917c00SJeff Kirsher 687f7917c00SJeff Kirsher struct tx_sw_desc; 688f7917c00SJeff Kirsher 689f7917c00SJeff Kirsher struct sge_txq { 690f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 691ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 692f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 693f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 694f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 695f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 696f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 697f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 698f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 699f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 700f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 701f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 7023069ee9bSVipul Pandya spinlock_t db_lock; 7033069ee9bSVipul Pandya int db_disabled; 7043069ee9bSVipul Pandya unsigned short db_pidx; 70505eb2389SSteve Wise unsigned short db_pidx_inc; 706df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 707df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 708f7917c00SJeff Kirsher }; 709f7917c00SJeff Kirsher 710f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 711f7917c00SJeff Kirsher struct sge_txq q; 712f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 71310b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 71410b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 71510b00466SAnish Bhatt #endif 716f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 717f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 718f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 719f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 720f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 721f7917c00SJeff Kirsher 722ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 723f7917c00SJeff Kirsher struct sge_txq q; 724f7917c00SJeff Kirsher struct adapter *adap; 725f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 726f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 727126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 728f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 729f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 730f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 731f7917c00SJeff Kirsher 732f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 733f7917c00SJeff Kirsher struct sge_txq q; 734f7917c00SJeff Kirsher struct adapter *adap; 735f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 736f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 737f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 738f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 739f7917c00SJeff Kirsher 74094cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 74194cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 74294cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 74394cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 74494cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 74594cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 74694cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 74794cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 74894cdb8bbSHariprasad Shenai }; 74994cdb8bbSHariprasad Shenai 750ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 751ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 752ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 753ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 754ab677ff4SHariprasad Shenai }; 755ab677ff4SHariprasad Shenai 756f7917c00SJeff Kirsher struct sge { 757f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 758a4569504SAtul Gupta struct sge_eth_txq ptptxq; 759f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 760f7917c00SJeff Kirsher 761f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 762f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 76394cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 764ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 765f7917c00SJeff Kirsher 766f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 767f7917c00SJeff Kirsher spinlock_t intrq_lock; 768f7917c00SJeff Kirsher 769f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 770f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 771f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 7720fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 77394cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 774f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 775f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 77652367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 77752367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 77852367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 77952367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 78052367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 7810f4d201fSKumar Sanghvi 782a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 783f7917c00SJeff Kirsher unsigned int egr_start; 7844b8e27a8SHariprasad Shenai unsigned int egr_sz; 785f7917c00SJeff Kirsher unsigned int ingr_start; 7864b8e27a8SHariprasad Shenai unsigned int ingr_sz; 7874b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 7884b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 7894b8e27a8SHariprasad Shenai unsigned long *starving_fl; 7904b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 7915b377d11SHariprasad Shenai unsigned long *blocked_fl; 792f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 793f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 794f7917c00SJeff Kirsher }; 795f7917c00SJeff Kirsher 796f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 7970fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 798f7917c00SJeff Kirsher 799f7917c00SJeff Kirsher struct l2t_data; 800f7917c00SJeff Kirsher 8012422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 8022422d9a3SSantosh Rastapur 8037d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 8047d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 8057d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 8062422d9a3SSantosh Rastapur */ 8077d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 8082422d9a3SSantosh Rastapur 8092422d9a3SSantosh Rastapur #endif 8102422d9a3SSantosh Rastapur 811a4cfd929SHariprasad Shenai struct doorbell_stats { 812a4cfd929SHariprasad Shenai u32 db_drop; 813a4cfd929SHariprasad Shenai u32 db_empty; 814a4cfd929SHariprasad Shenai u32 db_full; 815a4cfd929SHariprasad Shenai }; 816a4cfd929SHariprasad Shenai 817fc08a01aSHariprasad Shenai struct hash_mac_addr { 818fc08a01aSHariprasad Shenai struct list_head list; 819fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 820fc08a01aSHariprasad Shenai }; 821fc08a01aSHariprasad Shenai 82294cdb8bbSHariprasad Shenai struct uld_msix_bmap { 82394cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 82494cdb8bbSHariprasad Shenai unsigned int mapsize; 82594cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 82694cdb8bbSHariprasad Shenai }; 82794cdb8bbSHariprasad Shenai 82894cdb8bbSHariprasad Shenai struct uld_msix_info { 82994cdb8bbSHariprasad Shenai unsigned short vec; 83094cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 8310fbc81b3SHariprasad Shenai unsigned int idx; 83294cdb8bbSHariprasad Shenai }; 83394cdb8bbSHariprasad Shenai 834661dbeb9SHariprasad Shenai struct vf_info { 835661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 8368ea4fae9SGanesh Goudar unsigned int tx_rate; 837661dbeb9SHariprasad Shenai bool pf_set_mac; 8389d5fd927SGanesh Goudar u16 vlan; 839661dbeb9SHariprasad Shenai }; 840661dbeb9SHariprasad Shenai 8418b4e6b3cSArjun Vynipadath enum { 8428b4e6b3cSArjun Vynipadath HMA_DMA_MAPPED_FLAG = 1 8438b4e6b3cSArjun Vynipadath }; 8448b4e6b3cSArjun Vynipadath 8458b4e6b3cSArjun Vynipadath struct hma_data { 8468b4e6b3cSArjun Vynipadath unsigned char flags; 8478b4e6b3cSArjun Vynipadath struct sg_table *sgt; 8488b4e6b3cSArjun Vynipadath dma_addr_t *phy_addr; /* physical address of the page */ 8498b4e6b3cSArjun Vynipadath }; 8508b4e6b3cSArjun Vynipadath 8514055ae5eSHariprasad Shenai struct mbox_list { 8524055ae5eSHariprasad Shenai struct list_head list; 8534055ae5eSHariprasad Shenai }; 8544055ae5eSHariprasad Shenai 855846eac3fSGanesh Goudar struct mps_encap_entry { 856846eac3fSGanesh Goudar atomic_t refcnt; 857846eac3fSGanesh Goudar }; 858846eac3fSGanesh Goudar 859f7917c00SJeff Kirsher struct adapter { 860f7917c00SJeff Kirsher void __iomem *regs; 86122adfe0aSSantosh Rastapur void __iomem *bar2; 8620abfd152SHariprasad Shenai u32 t4_bar0; 863f7917c00SJeff Kirsher struct pci_dev *pdev; 864f7917c00SJeff Kirsher struct device *pdev_dev; 8650de72738SHariprasad Shenai const char *name; 8663069ee9bSVipul Pandya unsigned int mbox; 867b2612722SHariprasad Shenai unsigned int pf; 868f7917c00SJeff Kirsher unsigned int flags; 869e7b48a32SHariprasad Shenai unsigned int adap_idx; 8702422d9a3SSantosh Rastapur enum chip_type chip; 871f7917c00SJeff Kirsher 872f7917c00SJeff Kirsher int msg_enable; 873846eac3fSGanesh Goudar __be16 vxlan_port; 874846eac3fSGanesh Goudar u8 vxlan_port_cnt; 875c746fc0eSGanesh Goudar __be16 geneve_port; 876c746fc0eSGanesh Goudar u8 geneve_port_cnt; 877f7917c00SJeff Kirsher 878f7917c00SJeff Kirsher struct adapter_params params; 879f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 880f7917c00SJeff Kirsher unsigned int swintr; 881f7917c00SJeff Kirsher 882f7917c00SJeff Kirsher struct { 883f7917c00SJeff Kirsher unsigned short vec; 884f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 885f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 88694cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 88794cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 8880fbc81b3SHariprasad Shenai int msi_idx; 889f7917c00SJeff Kirsher 890a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 891f7917c00SJeff Kirsher struct sge sge; 892f7917c00SJeff Kirsher 893f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 894f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 895f7917c00SJeff Kirsher 896661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 897661dbeb9SHariprasad Shenai u8 num_vfs; 898661dbeb9SHariprasad Shenai 899793dad94SVipul Pandya u32 filter_mode; 900636f9d37SVipul Pandya unsigned int l2t_start; 901636f9d37SVipul Pandya unsigned int l2t_end; 902f7917c00SJeff Kirsher struct l2t_data *l2t; 903b5a02f50SAnish Bhatt unsigned int clipt_start; 904b5a02f50SAnish Bhatt unsigned int clipt_end; 905b5a02f50SAnish Bhatt struct clip_tbl *clipt; 906846eac3fSGanesh Goudar unsigned int rawf_start; 907846eac3fSGanesh Goudar unsigned int rawf_cnt; 9083bdb376eSKumar Sanghvi struct smt_data *smt; 909846eac3fSGanesh Goudar struct mps_encap_entry *mps_encap; 9100fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 911f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 91294cdb8bbSHariprasad Shenai unsigned int num_uld; 9130fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 914f7917c00SJeff Kirsher struct list_head list_node; 91501bcca68SVipul Pandya struct list_head rcu_node; 916fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 917f7917c00SJeff Kirsher 9187714cb9eSVarun Prakash void *iscsi_ppm; 9197714cb9eSVarun Prakash 920f7917c00SJeff Kirsher struct tid_info tids; 921f7917c00SJeff Kirsher void **tid_release_head; 922f7917c00SJeff Kirsher spinlock_t tid_release_lock; 92329aaee65SAnish Bhatt struct workqueue_struct *workq; 924f7917c00SJeff Kirsher struct work_struct tid_release_task; 925881806bcSVipul Pandya struct work_struct db_full_task; 926881806bcSVipul Pandya struct work_struct db_drop_task; 9278b7372c1SGanesh Goudar struct work_struct fatal_err_notify_task; 928f7917c00SJeff Kirsher bool tid_release_task_busy; 929f7917c00SJeff Kirsher 9304055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 9314055ae5eSHariprasad Shenai spinlock_t mbox_lock; 9324055ae5eSHariprasad Shenai struct mbox_list mlist; 9334055ae5eSHariprasad Shenai 9347f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 9357f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 9367f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 9377f080c3fSHariprasad Shenai 9380fbc81b3SHariprasad Shenai struct mutex uld_mutex; 9390fbc81b3SHariprasad Shenai 940f7917c00SJeff Kirsher struct dentry *debugfs_root; 941621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 942621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 9438e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 9448e3d04fdSHariprasad Shenai * used for all 4 filters. 9458e3d04fdSHariprasad Shenai */ 946f7917c00SJeff Kirsher 947a4569504SAtul Gupta struct ptp_clock *ptp_clock; 948a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 949a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 950a4569504SAtul Gupta /* ptp lock */ 951a4569504SAtul Gupta spinlock_t ptp_lock; 952f7917c00SJeff Kirsher spinlock_t stats_lock; 953fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 954d8931847SRahul Lakkireddy 955d8931847SRahul Lakkireddy /* TC u32 offload */ 956d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 957ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 95862488e4bSKumar Sanghvi 95962488e4bSKumar Sanghvi /* TC flower offload */ 960a081e115SCasey Leedom bool tc_flower_initialized; 96179e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 96279e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 963e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 96479e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 965ad75b7d3SRahul Lakkireddy 966ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 967ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 9688b4e6b3cSArjun Vynipadath 9698b4e6b3cSArjun Vynipadath /* HMA */ 9708b4e6b3cSArjun Vynipadath struct hma_data hma; 971e4709475SRaju Rangoju 972e4709475SRaju Rangoju struct srq_data *srq; 9731dde532dSRahul Lakkireddy 9741dde532dSRahul Lakkireddy /* Dump buffer for collecting logs in kdump kernel */ 9751dde532dSRahul Lakkireddy struct vmcoredd_data vmcoredd; 976f7917c00SJeff Kirsher }; 977f7917c00SJeff Kirsher 978b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 979b72a32daSRahul Lakkireddy * programmed with various parameters. 980b72a32daSRahul Lakkireddy */ 981b72a32daSRahul Lakkireddy struct ch_sched_params { 982b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 983b72a32daSRahul Lakkireddy union { 984b72a32daSRahul Lakkireddy struct { 985b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 986b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 987b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 988b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 989b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 990b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 991b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 992b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 993b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 994b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 995b72a32daSRahul Lakkireddy } params; 996b72a32daSRahul Lakkireddy } u; 997b72a32daSRahul Lakkireddy }; 998b72a32daSRahul Lakkireddy 99910a2604eSRahul Lakkireddy enum { 100010a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 100110a2604eSRahul Lakkireddy }; 100210a2604eSRahul Lakkireddy 100310a2604eSRahul Lakkireddy enum { 100410a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 100510a2604eSRahul Lakkireddy }; 100610a2604eSRahul Lakkireddy 100710a2604eSRahul Lakkireddy enum { 100810a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 100910a2604eSRahul Lakkireddy }; 101010a2604eSRahul Lakkireddy 101110a2604eSRahul Lakkireddy enum { 101210a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 101310a2604eSRahul Lakkireddy }; 101410a2604eSRahul Lakkireddy 101510a2604eSRahul Lakkireddy enum { 101610a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 101710a2604eSRahul Lakkireddy }; 101810a2604eSRahul Lakkireddy 1019a6ec572bSAtul Gupta struct tx_sw_desc { /* SW state per Tx descriptor */ 1020a6ec572bSAtul Gupta struct sk_buff *skb; 1021a6ec572bSAtul Gupta struct ulptx_sgl *sgl; 1022a6ec572bSAtul Gupta }; 1023a6ec572bSAtul Gupta 10246cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 10256cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 10266cede1f1SRahul Lakkireddy */ 10276cede1f1SRahul Lakkireddy struct ch_sched_queue { 10286cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 10296cede1f1SRahul Lakkireddy s8 class; /* class index */ 10306cede1f1SRahul Lakkireddy }; 10316cede1f1SRahul Lakkireddy 1032f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 1033f2b7e78dSVipul Pandya */ 1034f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 1035f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 1036f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 1037f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 1038f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 1039f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1040f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1041f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1042f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1043f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1044f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1045f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 104698f3697fSKumar Sanghvi #define ENCAP_VNI_BITWIDTH 24 1047f2b7e78dSVipul Pandya 1048f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1049f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1050f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1051f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1052f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1053f2b7e78dSVipul Pandya * matching rules are true. 1054f2b7e78dSVipul Pandya * 1055f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1056f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1057f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1058f2b7e78dSVipul Pandya * MPS match type) ... 1059f2b7e78dSVipul Pandya * 1060f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1061f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1062f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1063f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1064f2b7e78dSVipul Pandya */ 1065f2b7e78dSVipul Pandya struct ch_filter_tuple { 1066f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1067f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1068f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1069f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1070f2b7e78dSVipul Pandya * set of fields. 1071f2b7e78dSVipul Pandya */ 1072f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1073f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1074f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1075f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1076f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 107798f3697fSKumar Sanghvi uint32_t encap_vld:1; /* Encapsulation valid */ 1078f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1079f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1080f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1081f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1082f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1083f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1084f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1085f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1086f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1087f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 108898f3697fSKumar Sanghvi uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1089f2b7e78dSVipul Pandya 1090f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1091f2b7e78dSVipul Pandya * available for field rules. 1092f2b7e78dSVipul Pandya */ 1093f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1094f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1095f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1096f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1097f2b7e78dSVipul Pandya }; 1098f2b7e78dSVipul Pandya 1099f2b7e78dSVipul Pandya /* A filter ioctl command. 1100f2b7e78dSVipul Pandya */ 1101f2b7e78dSVipul Pandya struct ch_filter_specification { 1102f2b7e78dSVipul Pandya /* Administrative fields for filter. 1103f2b7e78dSVipul Pandya */ 1104f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1105f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1106f2b7e78dSVipul Pandya 1107f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1108f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1109f2b7e78dSVipul Pandya */ 1110f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 111112b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1112f2b7e78dSVipul Pandya 1113f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1114f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1115f2b7e78dSVipul Pandya * out as egress packets. 1116f2b7e78dSVipul Pandya */ 1117f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1118f2b7e78dSVipul Pandya 1119f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1120f2b7e78dSVipul Pandya 1121f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1122f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1123f2b7e78dSVipul Pandya 1124f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1125f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1126f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1127f2b7e78dSVipul Pandya 1128f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1129f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1130f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1131f2b7e78dSVipul Pandya */ 1132f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1133f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1134f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1135f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 11360ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1137f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1138f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1139f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1140f2b7e78dSVipul Pandya 11410ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 11420ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 11430ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 11440ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 11450ff90994SKumar Sanghvi 11460ff90994SKumar Sanghvi /* reservation for future additions */ 11470ff90994SKumar Sanghvi u8 rsvd[24]; 11480ff90994SKumar Sanghvi 1149f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1150f2b7e78dSVipul Pandya */ 1151f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1152f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1153f2b7e78dSVipul Pandya }; 1154f2b7e78dSVipul Pandya 1155f2b7e78dSVipul Pandya enum { 1156f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1157f2b7e78dSVipul Pandya FILTER_DROP, 1158f2b7e78dSVipul Pandya FILTER_SWITCH 1159f2b7e78dSVipul Pandya }; 1160f2b7e78dSVipul Pandya 1161f2b7e78dSVipul Pandya enum { 1162f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1163f2b7e78dSVipul Pandya VLAN_REMOVE, 1164f2b7e78dSVipul Pandya VLAN_INSERT, 1165f2b7e78dSVipul Pandya VLAN_REWRITE 1166f2b7e78dSVipul Pandya }; 1167f2b7e78dSVipul Pandya 1168557ccbf9SKumar Sanghvi enum { 116912b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 117012b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 117112b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 117212b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 117312b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 117412b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 117512b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 117612b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1177557ccbf9SKumar Sanghvi }; 1178557ccbf9SKumar Sanghvi 1179d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1180d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1181d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1182d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1183d57fd6caSRahul Lakkireddy * where the filter table is large. 1184d57fd6caSRahul Lakkireddy */ 1185d57fd6caSRahul Lakkireddy struct filter_entry { 1186d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1187d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1188d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1189d57fd6caSRahul Lakkireddy 1190d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1191578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1192d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 11933bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1194578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1195578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1196d57fd6caSRahul Lakkireddy 1197d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1198d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1199d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1200d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1201d57fd6caSRahul Lakkireddy */ 1202d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1203d57fd6caSRahul Lakkireddy }; 1204d57fd6caSRahul Lakkireddy 1205a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1206a4cfd929SHariprasad Shenai { 1207a4cfd929SHariprasad Shenai return adap->params.offload; 1208a4cfd929SHariprasad Shenai } 1209a4cfd929SHariprasad Shenai 12105c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 12115c31254eSKumar Sanghvi { 12125c31254eSKumar Sanghvi return adap->params.hash_filter; 12135c31254eSKumar Sanghvi } 12145c31254eSKumar Sanghvi 121594cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 121694cdb8bbSHariprasad Shenai { 121794cdb8bbSHariprasad Shenai return adap->params.crypto; 121894cdb8bbSHariprasad Shenai } 121994cdb8bbSHariprasad Shenai 12200fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 12210fbc81b3SHariprasad Shenai { 12220fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 12230fbc81b3SHariprasad Shenai } 12240fbc81b3SHariprasad Shenai 1225f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1226f7917c00SJeff Kirsher { 1227f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1228f7917c00SJeff Kirsher } 1229f7917c00SJeff Kirsher 1230f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1231f7917c00SJeff Kirsher { 1232f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1233f7917c00SJeff Kirsher } 1234f7917c00SJeff Kirsher 1235f7917c00SJeff Kirsher #ifndef readq 1236f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1237f7917c00SJeff Kirsher { 1238f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1239f7917c00SJeff Kirsher } 1240f7917c00SJeff Kirsher 1241f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1242f7917c00SJeff Kirsher { 1243f7917c00SJeff Kirsher writel(val, addr); 1244f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1245f7917c00SJeff Kirsher } 1246f7917c00SJeff Kirsher #endif 1247f7917c00SJeff Kirsher 1248f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1249f7917c00SJeff Kirsher { 1250f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1251f7917c00SJeff Kirsher } 1252f7917c00SJeff Kirsher 1253f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1254f7917c00SJeff Kirsher { 1255f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1256f7917c00SJeff Kirsher } 1257f7917c00SJeff Kirsher 1258f7917c00SJeff Kirsher /** 1259098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1260098ef6c2SHariprasad Shenai * @adapter: the adapter 1261098ef6c2SHariprasad Shenai * @port_idx: the port index 1262098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1263098ef6c2SHariprasad Shenai * 1264098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1265098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1266098ef6c2SHariprasad Shenai */ 1267098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1268098ef6c2SHariprasad Shenai u8 hw_addr[]) 1269098ef6c2SHariprasad Shenai { 1270098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1271098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1272098ef6c2SHariprasad Shenai } 1273098ef6c2SHariprasad Shenai 1274098ef6c2SHariprasad Shenai /** 1275f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1276f7917c00SJeff Kirsher * @dev: the netdev 1277f7917c00SJeff Kirsher * 1278f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1279f7917c00SJeff Kirsher */ 1280f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1281f7917c00SJeff Kirsher { 1282f7917c00SJeff Kirsher return netdev_priv(dev); 1283f7917c00SJeff Kirsher } 1284f7917c00SJeff Kirsher 1285f7917c00SJeff Kirsher /** 1286f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1287f7917c00SJeff Kirsher * @adap: the adapter 1288f7917c00SJeff Kirsher * @idx: the port index 1289f7917c00SJeff Kirsher * 1290f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1291f7917c00SJeff Kirsher */ 1292f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1293f7917c00SJeff Kirsher { 1294f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1295f7917c00SJeff Kirsher } 1296f7917c00SJeff Kirsher 1297f7917c00SJeff Kirsher /** 1298f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1299f7917c00SJeff Kirsher * @dev: the netdev 1300f7917c00SJeff Kirsher * 1301f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1302f7917c00SJeff Kirsher */ 1303f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1304f7917c00SJeff Kirsher { 1305f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1306f7917c00SJeff Kirsher } 1307f7917c00SJeff Kirsher 1308812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1309812034f1SHariprasad Shenai * - bits 0..9: chip version 1310812034f1SHariprasad Shenai * - bits 10..15: chip revision 1311812034f1SHariprasad Shenai * - bits 16..23: register dump version 1312812034f1SHariprasad Shenai */ 1313812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1314812034f1SHariprasad Shenai { 1315812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1316812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1317812034f1SHariprasad Shenai } 1318812034f1SHariprasad Shenai 1319812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1320812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1321812034f1SHariprasad Shenai const struct sge_rspq *q) 1322812034f1SHariprasad Shenai { 1323812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1324812034f1SHariprasad Shenai 1325812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1326812034f1SHariprasad Shenai } 1327812034f1SHariprasad Shenai 1328812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1329812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1330812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1331812034f1SHariprasad Shenai 13328156b0baSGanesh Goudar void t4_os_portmod_changed(struct adapter *adap, int port_id); 1333f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1334f7917c00SJeff Kirsher 1335f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 13365fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1337f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1338f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1339f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1340f7917c00SJeff Kirsher const struct pkt_gl *gl); 1341f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1342f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1343f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1344f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 13452337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 13462337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1347f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1348f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1349f7917c00SJeff Kirsher unsigned int iqid); 1350f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1351f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1352f7917c00SJeff Kirsher unsigned int cmplqid); 13530fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 13540fbc81b3SHariprasad Shenai unsigned int cmplqid); 1355ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1356ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1357ab677ff4SHariprasad Shenai unsigned int uld_type); 1358f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 135952367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1360f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1361f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1362812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1363812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1364d0a1299cSGanesh Goudar enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 13653069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1366f7917c00SJeff Kirsher 1367f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1368f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1369f7917c00SJeff Kirsher 13709a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 13719a4da2cdSVipul Pandya { 13729a4da2cdSVipul Pandya return adap->params.bypass; 13739a4da2cdSVipul Pandya } 13749a4da2cdSVipul Pandya 13759a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 13769a4da2cdSVipul Pandya { 13779a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 13789a4da2cdSVipul Pandya switch (device) { 13799a4da2cdSVipul Pandya case 0x440b: 13809a4da2cdSVipul Pandya case 0x440c: 13819a4da2cdSVipul Pandya return 1; 13829a4da2cdSVipul Pandya default: 13839a4da2cdSVipul Pandya return 0; 13849a4da2cdSVipul Pandya } 13859a4da2cdSVipul Pandya } 13869a4da2cdSVipul Pandya 138701b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 138801b69614SHariprasad Shenai { 138901b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 139001b69614SHariprasad Shenai switch (device) { 139101b69614SHariprasad Shenai case 0x4409: 139201b69614SHariprasad Shenai case 0x4486: 139301b69614SHariprasad Shenai return 1; 139401b69614SHariprasad Shenai 139501b69614SHariprasad Shenai default: 139601b69614SHariprasad Shenai return 0; 139701b69614SHariprasad Shenai } 139801b69614SHariprasad Shenai } 139901b69614SHariprasad Shenai 1400f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1401f7917c00SJeff Kirsher { 1402f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1403f7917c00SJeff Kirsher } 1404f7917c00SJeff Kirsher 1405f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1406f7917c00SJeff Kirsher unsigned int us) 1407f7917c00SJeff Kirsher { 1408f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1409f7917c00SJeff Kirsher } 1410f7917c00SJeff Kirsher 141152367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 141252367a76SVipul Pandya unsigned int ticks) 141352367a76SVipul Pandya { 141452367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 141552367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 141652367a76SVipul Pandya adapter->params.vpd.cclk); 141752367a76SVipul Pandya } 141852367a76SVipul Pandya 141908c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 142008c4901bSRahul Lakkireddy unsigned int ticks) 142108c4901bSRahul Lakkireddy { 142208c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 142308c4901bSRahul Lakkireddy } 142408c4901bSRahul Lakkireddy 1425f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1426f7917c00SJeff Kirsher u32 val); 1427f7917c00SJeff Kirsher 142801b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 142901b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1430f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1431f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1432f7917c00SJeff Kirsher 143301b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 143401b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 143501b69614SHariprasad Shenai int timeout) 143601b69614SHariprasad Shenai { 143701b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 143801b69614SHariprasad Shenai timeout); 143901b69614SHariprasad Shenai } 144001b69614SHariprasad Shenai 1441f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1442f7917c00SJeff Kirsher int size, void *rpl) 1443f7917c00SJeff Kirsher { 1444f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1445f7917c00SJeff Kirsher } 1446f7917c00SJeff Kirsher 1447f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1448f7917c00SJeff Kirsher int size, void *rpl) 1449f7917c00SJeff Kirsher { 1450f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1451f7917c00SJeff Kirsher } 1452f7917c00SJeff Kirsher 1453fc08a01aSHariprasad Shenai /** 1454fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1455fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1456fc08a01aSHariprasad Shenai * 1457fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1458fc08a01aSHariprasad Shenai * (hash) address matching. 1459fc08a01aSHariprasad Shenai */ 1460fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1461fc08a01aSHariprasad Shenai { 1462fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1463fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1464fc08a01aSHariprasad Shenai 1465fc08a01aSHariprasad Shenai a ^= b; 1466fc08a01aSHariprasad Shenai a ^= (a >> 12); 1467fc08a01aSHariprasad Shenai a ^= (a >> 6); 1468fc08a01aSHariprasad Shenai return a & 0x3f; 1469fc08a01aSHariprasad Shenai } 1470fc08a01aSHariprasad Shenai 147194cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 147294cdb8bbSHariprasad Shenai unsigned int cnt); 147394cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 147494cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 147594cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 147694cdb8bbSHariprasad Shenai { 147794cdb8bbSHariprasad Shenai q->adap = adap; 147894cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 147994cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 148094cdb8bbSHariprasad Shenai q->size = size; 148194cdb8bbSHariprasad Shenai } 148294cdb8bbSHariprasad Shenai 1483f56ec676SArjun Vynipadath /** 1484f56ec676SArjun Vynipadath * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1485f56ec676SArjun Vynipadath * @fw_mod_type: the Firmware Mofule Type 1486f56ec676SArjun Vynipadath * 1487f56ec676SArjun Vynipadath * Return whether the Firmware Module Type represents a real Transceiver 1488f56ec676SArjun Vynipadath * Module/Cable Module Type which has been inserted. 1489f56ec676SArjun Vynipadath */ 1490f56ec676SArjun Vynipadath static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1491f56ec676SArjun Vynipadath { 1492f56ec676SArjun Vynipadath return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1493f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1494f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1495f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1496f56ec676SArjun Vynipadath } 1497f56ec676SArjun Vynipadath 149813ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 149913ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 150013ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1501f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1502f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1503f2b7e78dSVipul Pandya unsigned int start_idx); 15040abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1505f2b7e78dSVipul Pandya 1506f2b7e78dSVipul Pandya struct fw_filter_wr; 1507f2b7e78dSVipul Pandya 1508f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1509f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1510f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1511f7917c00SJeff Kirsher 15128203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 15138156b0baSGanesh Goudar 15148156b0baSGanesh Goudar int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 15158156b0baSGanesh Goudar unsigned int port, struct link_config *lc, 15168156b0baSGanesh Goudar bool sleep_ok, int timeout); 15178156b0baSGanesh Goudar 15188156b0baSGanesh Goudar static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 15198156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 15208156b0baSGanesh Goudar { 15218156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 15228156b0baSGanesh Goudar true, FW_CMD_MAX_TIMEOUT); 15238156b0baSGanesh Goudar } 15248156b0baSGanesh Goudar 15258156b0baSGanesh Goudar static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 15268156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 15278156b0baSGanesh Goudar { 15288156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 15298156b0baSGanesh Goudar false, FW_CMD_MAX_TIMEOUT); 15308156b0baSGanesh Goudar } 15318156b0baSGanesh Goudar 1532f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1533fc5ab020SHariprasad Shenai 1534b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1535b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1536b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1537b562fc37SHariprasad Shenai 15381a4330cdSRahul Lakkireddy int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 15391a4330cdSRahul Lakkireddy u32 *mem_base, u32 *mem_aperture); 15401a4330cdSRahul Lakkireddy void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 15411a4330cdSRahul Lakkireddy void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 15421a4330cdSRahul Lakkireddy int dir); 1543fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1544fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1545fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1546f01aa633SHariprasad Shenai void *buf, int dir); 1547fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1548fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1549fc5ab020SHariprasad Shenai { 1550fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1551fc5ab020SHariprasad Shenai } 1552fc5ab020SHariprasad Shenai 1553812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1554812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1555812034f1SHariprasad Shenai 1556940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1557f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1558098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1559098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 156049216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 156149216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1562f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 156301b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 156401b69614SHariprasad Shenai int win, spinlock_t *lock, 156501b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 156601b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 156701b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 156849216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 156922c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 157022c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1571acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1572636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1573a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 15744da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 157516e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 15760de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 157716e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1578ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1579760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1580760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1581760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1582760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 158316e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 158416e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 158516e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1586f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 15873be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1588e85c9a7aSHariprasad Shenai 1589e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1590b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1591e85c9a7aSHariprasad Shenai unsigned int qid, 1592e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 159366cf188eSHariprasad S int user, 1594e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1595e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1596e85c9a7aSHariprasad Shenai 1597dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1598dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1599ae469b68SHariprasad Shenai 1600ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1601e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 16025ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1603dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1604c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1605c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1606c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1607f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1608f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1609f988008aSGanesh Goudar unsigned int t4_chip_rss_size(struct adapter *adapter); 1610f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1611f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1612f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1613f7917c00SJeff Kirsher unsigned int flags); 1614c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1615c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1616688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 16175ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 16185ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 16195ccf9d04SRahul Lakkireddy bool sleep_ok); 1620688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 16215ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1622688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 16235ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 16245ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 16255ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1626688ea5feSHariprasad Shenai 1627193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1628193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1629b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1630b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1631e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1632e5f0e43bSHariprasad Shenai size_t n); 1633c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1634c778af7dSHariprasad Shenai size_t n); 1635f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1636f1ff24aaSHariprasad Shenai unsigned int *valp); 1637f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1638f1ff24aaSHariprasad Shenai const unsigned int *valp); 1639f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 164019689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 164119689609SHariprasad Shenai unsigned int *pif_req_wrptr, 164219689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 164326fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 164474b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 164572aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1646f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1647a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1648a4cfd929SHariprasad Shenai struct port_stats *stats, 1649a4cfd929SHariprasad Shenai struct port_stats *offset); 165065046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1651f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1652bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1653636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1654636f9d37SVipul Pandya unsigned int mask, unsigned int val); 16552d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 16565ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 16575ccf9d04SRahul Lakkireddy bool sleep_ok); 16585ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 16595ccf9d04SRahul Lakkireddy bool sleep_ok); 16605ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 16615ccf9d04SRahul Lakkireddy bool sleep_ok); 16625ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 16635ccf9d04SRahul Lakkireddy bool sleep_ok); 1664f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 16655ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1666a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 16675ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1668f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1669f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1670f7917c00SJeff Kirsher 1671797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1672797ff0f5SHariprasad Shenai 16737864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1674f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1675f2b7e78dSVipul Pandya 1676f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1677f7917c00SJeff Kirsher const u8 *addr); 1678f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1679f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1680f7917c00SJeff Kirsher 1681f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1682f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1683f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1684f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1685f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1686636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1687636f9d37SVipul Pandya unsigned int cache_line_size); 1688636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1689f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1690f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1691f7917c00SJeff Kirsher u32 *val); 16928f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 16938f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 16948f46d467SArjun Vynipadath u32 *val); 169501b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1696f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 16978f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 169801b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1699688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1700688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 170101b69614SHariprasad Shenai const u32 *val, int timeout); 170201b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 170301b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1704688848b1SAnish Bhatt const u32 *val); 1705f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1706f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1707f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1708f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1709f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1710f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1711f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1712f7917c00SJeff Kirsher unsigned int *rss_size); 17134f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 17144f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 17154f3a0fcfSHariprasad Shenai unsigned int viid); 1716f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1717f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1718f7917c00SJeff Kirsher bool sleep_ok); 1719846eac3fSGanesh Goudar int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1720846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1721846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 172298f3697fSKumar Sanghvi int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 172398f3697fSKumar Sanghvi bool sleep_ok); 172498f3697fSKumar Sanghvi int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 172598f3697fSKumar Sanghvi const u8 *addr, const u8 *mask, unsigned int vni, 172698f3697fSKumar Sanghvi unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 172798f3697fSKumar Sanghvi bool sleep_ok); 1728846eac3fSGanesh Goudar int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1729846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1730846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 1731f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1732f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1733f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1734fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1735fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1736fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1737f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1738f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1739f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1740f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1741688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1742688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1743e2f4f4e9SArjun Vynipadath int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1744e2f4f4e9SArjun Vynipadath struct port_info *pi, 1745e2f4f4e9SArjun Vynipadath bool rx_en, bool tx_en, bool dcb_en); 1746f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1747f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1748f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1749f7917c00SJeff Kirsher unsigned int nblinks); 1750f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1751f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1752f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1753f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1754ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1755ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1756ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1757f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1758f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1759f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1760f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1761f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1762f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1763f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1764f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1765f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1766736c3b94SRahul Lakkireddy int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 176723853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 17682061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1769c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1770c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1771f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1772881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1773881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 17748e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 17758e3d04fdSHariprasad Shenai int filter_index, int enable); 17768e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 17778e3d04fdSHariprasad Shenai int filter_index, int *enabled); 17788caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 17798caa1e84SVipul Pandya u32 addr, u32 val); 178008c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 178108c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 178208c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 17839e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 17849e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 17859e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 17869e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 1787b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1788b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1789b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 179068bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1791a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1792a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1793a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1794a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1795a3bfb617SHariprasad Shenai int hz, int ticks); 1796858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1797858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 17985ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 17995ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 18004359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 18014359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 18025ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 18035ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 18045ccf9d04SRahul Lakkireddy 18050fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 18060fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 18070fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 18080fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 1809f56ec676SArjun Vynipadath int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1810f56ec676SArjun Vynipadath unsigned int devid, unsigned int offset, 1811f56ec676SArjun Vynipadath unsigned int len, u8 *buf); 181294cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1813ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1814ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1815ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1816a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 1817a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 1818a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1819a6ec572bSAtul Gupta dma_addr_t *addr); 1820a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1821a6ec572bSAtul Gupta void *pos); 1822a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1823a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1824a6ec572bSAtul Gupta const dma_addr_t *addr); 1825a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 18269d5fd927SGanesh Goudar int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 18279d5fd927SGanesh Goudar u16 vlan); 1828f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1829