1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 490eb71a9dSNeilBrown #include <linux/rhashtable.h> 50098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 515e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 52a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 53a4569504SAtul Gupta #include <linux/ptp_classify.h> 541dde532dSRahul Lakkireddy #include <linux/crash_dump.h> 55f7917c00SJeff Kirsher #include <asm/io.h> 5627999805SHariprasad S #include "t4_chip_type.h" 57f7917c00SJeff Kirsher #include "cxgb4_uld.h" 58f7917c00SJeff Kirsher 593069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 6094cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 6194cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 623069ee9bSVipul Pandya 63a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 64a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 65a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 66a6ec572bSAtul Gupta */ 67a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 68a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 69a6ec572bSAtul Gupta 70f7917c00SJeff Kirsher enum { 71f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 72f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 73f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 74f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 75a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 76098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 77f7917c00SJeff Kirsher }; 78f7917c00SJeff Kirsher 79f7917c00SJeff Kirsher enum { 80812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 81812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 82812034f1SHariprasad Shenai }; 83812034f1SHariprasad Shenai 84812034f1SHariprasad Shenai enum { 85f7917c00SJeff Kirsher MEM_EDC0, 86f7917c00SJeff Kirsher MEM_EDC1, 872422d9a3SSantosh Rastapur MEM_MC, 882422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 894db0401fSRahul Lakkireddy MEM_MC1, 904db0401fSRahul Lakkireddy MEM_HMA, 91f7917c00SJeff Kirsher }; 92f7917c00SJeff Kirsher 933069ee9bSVipul Pandya enum { 943eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 953eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 963069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 973069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 982422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 993eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 1003eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 1010abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 1020abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1033069ee9bSVipul Pandya }; 1043069ee9bSVipul Pandya 105f7917c00SJeff Kirsher enum dev_master { 106f7917c00SJeff Kirsher MASTER_CANT, 107f7917c00SJeff Kirsher MASTER_MAY, 108f7917c00SJeff Kirsher MASTER_MUST 109f7917c00SJeff Kirsher }; 110f7917c00SJeff Kirsher 111f7917c00SJeff Kirsher enum dev_state { 112f7917c00SJeff Kirsher DEV_STATE_UNINIT, 113f7917c00SJeff Kirsher DEV_STATE_INIT, 114f7917c00SJeff Kirsher DEV_STATE_ERR 115f7917c00SJeff Kirsher }; 116f7917c00SJeff Kirsher 117c3168cabSGanesh Goudar enum cc_pause { 118f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 119f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 120f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 121f7917c00SJeff Kirsher }; 122f7917c00SJeff Kirsher 123c3168cabSGanesh Goudar enum cc_fec { 1243bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1253bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1263bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1273bb4858fSGanesh Goudar }; 1283bb4858fSGanesh Goudar 129f7917c00SJeff Kirsher struct port_stats { 130f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 131f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 132f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 133f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 134f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 135f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 136f7917c00SJeff Kirsher 137f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 138f7917c00SJeff Kirsher u64 tx_frames_65_127; 139f7917c00SJeff Kirsher u64 tx_frames_128_255; 140f7917c00SJeff Kirsher u64 tx_frames_256_511; 141f7917c00SJeff Kirsher u64 tx_frames_512_1023; 142f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 143f7917c00SJeff Kirsher u64 tx_frames_1519_max; 144f7917c00SJeff Kirsher 145f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 146f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 147f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 148f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 149f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 150f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 151f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 152f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 153f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 154f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 155f7917c00SJeff Kirsher 156f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 157f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 158f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 159f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 160f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 161f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 162f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 163f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 164f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 165f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 166f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 167f7917c00SJeff Kirsher 168f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 169f7917c00SJeff Kirsher u64 rx_frames_65_127; 170f7917c00SJeff Kirsher u64 rx_frames_128_255; 171f7917c00SJeff Kirsher u64 rx_frames_256_511; 172f7917c00SJeff Kirsher u64 rx_frames_512_1023; 173f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 174f7917c00SJeff Kirsher u64 rx_frames_1519_max; 175f7917c00SJeff Kirsher 176f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 177f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 178f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 179f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 180f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 181f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 182f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 183f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 184f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 185f7917c00SJeff Kirsher 186f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 187f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 188f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 189f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 190f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 191f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 192f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 193f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 194f7917c00SJeff Kirsher }; 195f7917c00SJeff Kirsher 196f7917c00SJeff Kirsher struct lb_port_stats { 197f7917c00SJeff Kirsher u64 octets; 198f7917c00SJeff Kirsher u64 frames; 199f7917c00SJeff Kirsher u64 bcast_frames; 200f7917c00SJeff Kirsher u64 mcast_frames; 201f7917c00SJeff Kirsher u64 ucast_frames; 202f7917c00SJeff Kirsher u64 error_frames; 203f7917c00SJeff Kirsher 204f7917c00SJeff Kirsher u64 frames_64; 205f7917c00SJeff Kirsher u64 frames_65_127; 206f7917c00SJeff Kirsher u64 frames_128_255; 207f7917c00SJeff Kirsher u64 frames_256_511; 208f7917c00SJeff Kirsher u64 frames_512_1023; 209f7917c00SJeff Kirsher u64 frames_1024_1518; 210f7917c00SJeff Kirsher u64 frames_1519_max; 211f7917c00SJeff Kirsher 212f7917c00SJeff Kirsher u64 drop; 213f7917c00SJeff Kirsher 214f7917c00SJeff Kirsher u64 ovflow0; 215f7917c00SJeff Kirsher u64 ovflow1; 216f7917c00SJeff Kirsher u64 ovflow2; 217f7917c00SJeff Kirsher u64 ovflow3; 218f7917c00SJeff Kirsher u64 trunc0; 219f7917c00SJeff Kirsher u64 trunc1; 220f7917c00SJeff Kirsher u64 trunc2; 221f7917c00SJeff Kirsher u64 trunc3; 222f7917c00SJeff Kirsher }; 223f7917c00SJeff Kirsher 224f7917c00SJeff Kirsher struct tp_tcp_stats { 225a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 226a4cfd929SHariprasad Shenai u64 tcp_in_segs; 227a4cfd929SHariprasad Shenai u64 tcp_out_segs; 228a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 229a4cfd929SHariprasad Shenai }; 230a4cfd929SHariprasad Shenai 231a4cfd929SHariprasad Shenai struct tp_usm_stats { 232a4cfd929SHariprasad Shenai u32 frames; 233a4cfd929SHariprasad Shenai u32 drops; 234a4cfd929SHariprasad Shenai u64 octets; 235f7917c00SJeff Kirsher }; 236f7917c00SJeff Kirsher 237a6222975SHariprasad Shenai struct tp_fcoe_stats { 238a6222975SHariprasad Shenai u32 frames_ddp; 239a6222975SHariprasad Shenai u32 frames_drop; 240a6222975SHariprasad Shenai u64 octets_ddp; 241f7917c00SJeff Kirsher }; 242f7917c00SJeff Kirsher 243f7917c00SJeff Kirsher struct tp_err_stats { 244a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 245a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 246a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 247a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 248a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 249a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 250a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 251a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 252a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 253a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 254a4cfd929SHariprasad Shenai }; 255a4cfd929SHariprasad Shenai 256a6222975SHariprasad Shenai struct tp_cpl_stats { 257a6222975SHariprasad Shenai u32 req[4]; 258a6222975SHariprasad Shenai u32 rsp[4]; 259a6222975SHariprasad Shenai }; 260a6222975SHariprasad Shenai 261a4cfd929SHariprasad Shenai struct tp_rdma_stats { 262a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 263a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 264f7917c00SJeff Kirsher }; 265f7917c00SJeff Kirsher 266e85c9a7aSHariprasad Shenai struct sge_params { 267e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 268e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 269e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 270e85c9a7aSHariprasad Shenai }; 271e85c9a7aSHariprasad Shenai 272f7917c00SJeff Kirsher struct tp_params { 273f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2742d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 275dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 276dca4faebSVipul Pandya /* channel map */ 277636f9d37SVipul Pandya 278636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 279636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 280dcf7b6f5SKumar Sanghvi 281dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 282dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 283dcf7b6f5SKumar Sanghvi 2848eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2858eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2868eb9f2f9SArjun V */ 2878eb9f2f9SArjun V int rx_pkt_encap; 2888eb9f2f9SArjun V 289dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 290dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 291dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 292dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 293dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 294dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 295dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 296dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 297dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 298dcf7b6f5SKumar Sanghvi * present. 299dcf7b6f5SKumar Sanghvi */ 3000ba9a3b6SKumar Sanghvi int fcoe_shift; 301dcf7b6f5SKumar Sanghvi int port_shift; 3020ba9a3b6SKumar Sanghvi int vnic_shift; 3030ba9a3b6SKumar Sanghvi int vlan_shift; 3040ba9a3b6SKumar Sanghvi int tos_shift; 305dcf7b6f5SKumar Sanghvi int protocol_shift; 3060ba9a3b6SKumar Sanghvi int ethertype_shift; 3070ba9a3b6SKumar Sanghvi int macmatch_shift; 3080ba9a3b6SKumar Sanghvi int matchtype_shift; 3090ba9a3b6SKumar Sanghvi int frag_shift; 3100ba9a3b6SKumar Sanghvi 3110ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 312f7917c00SJeff Kirsher }; 313f7917c00SJeff Kirsher 314f7917c00SJeff Kirsher struct vpd_params { 315f7917c00SJeff Kirsher unsigned int cclk; 316f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 317f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 318f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 319a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 320098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 321f7917c00SJeff Kirsher }; 322f7917c00SJeff Kirsher 3230eaec62aSCasey Leedom /* Maximum resources provisioned for a PCI PF. 3240eaec62aSCasey Leedom */ 3250eaec62aSCasey Leedom struct pf_resources { 3260eaec62aSCasey Leedom unsigned int nvi; /* N virtual interfaces */ 3270eaec62aSCasey Leedom unsigned int neq; /* N egress Qs */ 3280eaec62aSCasey Leedom unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 3290eaec62aSCasey Leedom unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 3300eaec62aSCasey Leedom unsigned int niq; /* N ingress Qs */ 3310eaec62aSCasey Leedom unsigned int tc; /* PCI-E traffic class */ 3320eaec62aSCasey Leedom unsigned int pmask; /* port access rights mask */ 3330eaec62aSCasey Leedom unsigned int nexactf; /* N exact MPS filters */ 3340eaec62aSCasey Leedom unsigned int r_caps; /* read capabilities */ 3350eaec62aSCasey Leedom unsigned int wx_caps; /* write/execute capabilities */ 3360eaec62aSCasey Leedom }; 3370eaec62aSCasey Leedom 338f7917c00SJeff Kirsher struct pci_params { 339baf50868SGanesh Goudar unsigned int vpd_cap_addr; 340f7917c00SJeff Kirsher unsigned char speed; 341f7917c00SJeff Kirsher unsigned char width; 342f7917c00SJeff Kirsher }; 343f7917c00SJeff Kirsher 34449aa284fSHariprasad Shenai struct devlog_params { 34549aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 34649aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 34749aa284fSHariprasad Shenai u32 size; /* size of log */ 34849aa284fSHariprasad Shenai }; 34949aa284fSHariprasad Shenai 3503ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3513ccc6cf7SHariprasad Shenai struct arch_specific_params { 3523ccc6cf7SHariprasad Shenai u8 nchan; 35344588560SHariprasad Shenai u8 pm_stats_cnt; 3542216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3553ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3563ccc6cf7SHariprasad Shenai u16 vfcount; 3573ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3583ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3593ccc6cf7SHariprasad Shenai }; 3603ccc6cf7SHariprasad Shenai 361f7917c00SJeff Kirsher struct adapter_params { 362e85c9a7aSHariprasad Shenai struct sge_params sge; 363f7917c00SJeff Kirsher struct tp_params tp; 364f7917c00SJeff Kirsher struct vpd_params vpd; 3650eaec62aSCasey Leedom struct pf_resources pfres; 366f7917c00SJeff Kirsher struct pci_params pci; 36749aa284fSHariprasad Shenai struct devlog_params devlog; 36849aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 369f7917c00SJeff Kirsher 370f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 371f1ff24aaSHariprasad Shenai 372f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 373f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 374f7917c00SJeff Kirsher 375760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3760de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 377760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3780de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 379760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 380760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 381f7917c00SJeff Kirsher u8 api_vers[7]; 382f7917c00SJeff Kirsher 383f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 384f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 385f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 386f7917c00SJeff Kirsher 387f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 388f7917c00SJeff Kirsher unsigned char portvec; 389d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3903ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 391f7917c00SJeff Kirsher unsigned char offload; 39294cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 393f7917c00SJeff Kirsher 3949a4da2cdSVipul Pandya unsigned char bypass; 3955c31254eSKumar Sanghvi unsigned char hash_filter; 3969a4da2cdSVipul Pandya 397f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3981ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3994c2c5763SHariprasad Shenai 400b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 4014c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 4024c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 403086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 404c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 4050ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 4068f46d467SArjun Vynipadath 4078f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 4088f46d467SArjun Vynipadath * used by the Port 4098f46d467SArjun Vynipadath */ 4108f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 41143db9296SRaju Rangoju bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 412f3910c62SRaju Rangoju bool write_cmpl_support; /* FW supports WRITE_CMPL */ 413f7917c00SJeff Kirsher }; 414f7917c00SJeff Kirsher 415a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 416a3bfb617SHariprasad Shenai * and possible hangs. 417a3bfb617SHariprasad Shenai */ 418a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 419a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 420a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 421a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 422a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 423a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 424a3bfb617SHariprasad Shenai }; 425a3bfb617SHariprasad Shenai 4267f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 4277f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 4287f080c3fSHariprasad Shenai * error returns. 4297f080c3fSHariprasad Shenai */ 4307f080c3fSHariprasad Shenai struct mbox_cmd { 4317f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 4327f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 4337f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 4347f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 4357f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 4367f080c3fSHariprasad Shenai }; 4377f080c3fSHariprasad Shenai 4387f080c3fSHariprasad Shenai struct mbox_cmd_log { 4397f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4407f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4417f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4427f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4437f080c3fSHariprasad Shenai }; 4447f080c3fSHariprasad Shenai 4457f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4467f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4477f080c3fSHariprasad Shenai */ 4487f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4497f080c3fSHariprasad Shenai unsigned int entry_idx) 4507f080c3fSHariprasad Shenai { 4517f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4527f080c3fSHariprasad Shenai } 4537f080c3fSHariprasad Shenai 45416e47624SHariprasad Shenai #include "t4fw_api.h" 45516e47624SHariprasad Shenai 45616e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 457b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 458b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 459b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 460b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 46116e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 46216e47624SHariprasad Shenai 46316e47624SHariprasad Shenai struct fw_info { 46416e47624SHariprasad Shenai u8 chip; 46516e47624SHariprasad Shenai char *fs_name; 46616e47624SHariprasad Shenai char *fw_mod_name; 46716e47624SHariprasad Shenai struct fw_hdr fw_hdr; 46816e47624SHariprasad Shenai }; 46916e47624SHariprasad Shenai 470f7917c00SJeff Kirsher struct trace_params { 471f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 472f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 473f7917c00SJeff Kirsher unsigned short snap_len; 474f7917c00SJeff Kirsher unsigned short min_len; 475f7917c00SJeff Kirsher unsigned char skip_ofst; 476f7917c00SJeff Kirsher unsigned char skip_len; 477f7917c00SJeff Kirsher unsigned char invert; 478f7917c00SJeff Kirsher unsigned char port; 479f7917c00SJeff Kirsher }; 480f7917c00SJeff Kirsher 481c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 482c3168cabSGanesh Goudar 483c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 484c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 485c3168cabSGanesh Goudar 486c3168cabSGanesh Goudar enum fw_caps { 487c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 488c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 489c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 490c3168cabSGanesh Goudar }; 491c3168cabSGanesh Goudar 492f7917c00SJeff Kirsher struct link_config { 493c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 494c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 495c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 496c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 497c3168cabSGanesh Goudar 498c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 499c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 500c3168cabSGanesh Goudar 501c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 502c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 503c3168cabSGanesh Goudar 504c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 505c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 506c3168cabSGanesh Goudar 507f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 508c3168cabSGanesh Goudar 509f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 510ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 5118156b0baSGanesh Goudar 5128156b0baSGanesh Goudar bool new_module; /* ->OS Transceiver Module inserted */ 5138156b0baSGanesh Goudar bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 514f7917c00SJeff Kirsher }; 515f7917c00SJeff Kirsher 516e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 517f7917c00SJeff Kirsher 518f7917c00SJeff Kirsher enum { 519f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 520f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 521f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 522f7917c00SJeff Kirsher }; 523f7917c00SJeff Kirsher 524f7917c00SJeff Kirsher enum { 525812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 526812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 527812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 528812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 529812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 530812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 531812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 532812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 533812034f1SHariprasad Shenai }; 534812034f1SHariprasad Shenai 535812034f1SHariprasad Shenai enum { 53668ddc82aSRahul Lakkireddy MAX_TXQ_DESC_SIZE = 64, 53768ddc82aSRahul Lakkireddy MAX_RXQ_DESC_SIZE = 128, 53868ddc82aSRahul Lakkireddy MAX_FL_DESC_SIZE = 8, 53968ddc82aSRahul Lakkireddy MAX_CTRL_TXQ_DESC_SIZE = 64, 54068ddc82aSRahul Lakkireddy }; 54168ddc82aSRahul Lakkireddy 54268ddc82aSRahul Lakkireddy enum { 543cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 544cf38be6dSHariprasad Shenai /* forwarded interrupts */ 5450fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 546f7917c00SJeff Kirsher }; 547f7917c00SJeff Kirsher 548d5fbda61SArjun Vynipadath enum { 549d5fbda61SArjun Vynipadath PRIV_FLAG_PORT_TX_VM_BIT, 550d5fbda61SArjun Vynipadath }; 551d5fbda61SArjun Vynipadath 552d5fbda61SArjun Vynipadath #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 553d5fbda61SArjun Vynipadath 554d5fbda61SArjun Vynipadath #define PRIV_FLAGS_ADAP 0 555d5fbda61SArjun Vynipadath #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 556d5fbda61SArjun Vynipadath 557f7917c00SJeff Kirsher struct adapter; 558f7917c00SJeff Kirsher struct sge_rspq; 559f7917c00SJeff Kirsher 560688848b1SAnish Bhatt #include "cxgb4_dcb.h" 561688848b1SAnish Bhatt 56276fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 56376fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 56476fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 56576fed8a9SVarun Prakash 566f7917c00SJeff Kirsher struct port_info { 567f7917c00SJeff Kirsher struct adapter *adapter; 568f7917c00SJeff Kirsher u16 viid; 569f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 570f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 571f7917c00SJeff Kirsher s8 mdio_addr; 57240e9de4bSHariprasad Shenai enum fw_port_type port_type; 573f7917c00SJeff Kirsher u8 mod_type; 574f7917c00SJeff Kirsher u8 port_id; 575f7917c00SJeff Kirsher u8 tx_chan; 576f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 577f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 578f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 579f7917c00SJeff Kirsher u8 rss_mode; 580f7917c00SJeff Kirsher struct link_config link_cfg; 581f7917c00SJeff Kirsher u16 *rss; 582a4cfd929SHariprasad Shenai struct port_stats stats_base; 583688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 584688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 585688848b1SAnish Bhatt #endif 58676fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 58776fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 58876fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5895e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5905e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 591a4569504SAtul Gupta bool ptp_enable; 592b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 593d5fbda61SArjun Vynipadath u32 eth_flags; 594f7917c00SJeff Kirsher }; 595f7917c00SJeff Kirsher 596f7917c00SJeff Kirsher struct dentry; 597f7917c00SJeff Kirsher struct work_struct; 598f7917c00SJeff Kirsher 599f7917c00SJeff Kirsher enum { /* adapter flags */ 600f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 601144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 602144be3d9SGavin Shan USING_MSI = (1 << 2), 603144be3d9SGavin Shan USING_MSIX = (1 << 3), 604f7917c00SJeff Kirsher FW_OK = (1 << 4), 60513ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 60652367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 60752367a76SVipul Pandya MASTER_PF = (1 << 7), 60852367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 609b0ba9d5fSCasey Leedom ROOT_NO_RELAXED_ORDERING = (1 << 10), 610e1f6198eSGanesh Goudar SHUTTING_DOWN = (1 << 11), 611f7917c00SJeff Kirsher }; 612f7917c00SJeff Kirsher 61394cdb8bbSHariprasad Shenai enum { 61494cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 615a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 61694cdb8bbSHariprasad Shenai }; 61794cdb8bbSHariprasad Shenai 618f7917c00SJeff Kirsher struct rx_sw_desc; 619f7917c00SJeff Kirsher 620f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 621f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 622f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 623f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 624f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 625f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 626f7917c00SJeff Kirsher unsigned long large_alloc_failed; 62770055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 62870055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 629f7917c00SJeff Kirsher unsigned long starving; 630f7917c00SJeff Kirsher /* RO fields */ 631f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 632f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 633f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 634f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 635f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 636df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 637df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 638f7917c00SJeff Kirsher }; 639f7917c00SJeff Kirsher 640f7917c00SJeff Kirsher /* A packet gather list */ 641f7917c00SJeff Kirsher struct pkt_gl { 6425e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 643e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 644f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 645f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 646f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 647f7917c00SJeff Kirsher }; 648f7917c00SJeff Kirsher 649f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 650f7917c00SJeff Kirsher const struct pkt_gl *gl); 6512337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 6522337ba42SVarun Prakash /* LRO related declarations for ULD */ 6532337ba42SVarun Prakash struct t4_lro_mgr { 6542337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 6552337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 6562337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 6572337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6582337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6592337ba42SVarun Prakash }; 660f7917c00SJeff Kirsher 661f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 662f7917c00SJeff Kirsher struct napi_struct napi; 663f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 664f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 665f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 666f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 667f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 668e553ec3fSHariprasad Shenai u8 adaptive_rx; 669f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 670f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 671f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 672f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 673f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 674f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 675f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 676f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 677df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 678df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 679f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 680f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 681f7917c00SJeff Kirsher struct adapter *adap; 682f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 683f7917c00SJeff Kirsher rspq_handler_t handler; 6842337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 6852337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 686f7917c00SJeff Kirsher }; 687f7917c00SJeff Kirsher 688f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 689f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 690f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 691f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 692f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 693f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 694f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 695992bea8eSGanesh Goudar unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 696f7917c00SJeff Kirsher }; 697f7917c00SJeff Kirsher 698f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 699f7917c00SJeff Kirsher struct sge_rspq rspq; 700f7917c00SJeff Kirsher struct sge_fl fl; 701f7917c00SJeff Kirsher struct sge_eth_stats stats; 702f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 703f7917c00SJeff Kirsher 704f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 705f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 706f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 707f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 708f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 709f7917c00SJeff Kirsher }; 710f7917c00SJeff Kirsher 711f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 712f7917c00SJeff Kirsher struct sge_rspq rspq; 713f7917c00SJeff Kirsher struct sge_fl fl; 714f7917c00SJeff Kirsher struct sge_ofld_stats stats; 715f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 716f7917c00SJeff Kirsher 717f7917c00SJeff Kirsher struct tx_desc { 718f7917c00SJeff Kirsher __be64 flit[8]; 719f7917c00SJeff Kirsher }; 720f7917c00SJeff Kirsher 721f7917c00SJeff Kirsher struct tx_sw_desc; 722f7917c00SJeff Kirsher 723f7917c00SJeff Kirsher struct sge_txq { 724f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 725ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 726f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 727f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 728f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 729f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 730f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 731f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 732f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 733f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 734f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 735f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 7363069ee9bSVipul Pandya spinlock_t db_lock; 7373069ee9bSVipul Pandya int db_disabled; 7383069ee9bSVipul Pandya unsigned short db_pidx; 73905eb2389SSteve Wise unsigned short db_pidx_inc; 740df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 741df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 742f7917c00SJeff Kirsher }; 743f7917c00SJeff Kirsher 744f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 745f7917c00SJeff Kirsher struct sge_txq q; 746f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 74710b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 74810b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 74910b00466SAnish Bhatt #endif 750f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 751f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 752f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 753f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 754f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 755f7917c00SJeff Kirsher 756ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 757f7917c00SJeff Kirsher struct sge_txq q; 758f7917c00SJeff Kirsher struct adapter *adap; 759f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 760f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 761126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 762f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 763f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 764f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 765f7917c00SJeff Kirsher 766f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 767f7917c00SJeff Kirsher struct sge_txq q; 768f7917c00SJeff Kirsher struct adapter *adap; 769f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 770f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 771f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 772f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 773f7917c00SJeff Kirsher 77494cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 77594cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 77694cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 77794cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 77894cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 77994cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 78094cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 78194cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 78294cdb8bbSHariprasad Shenai }; 78394cdb8bbSHariprasad Shenai 784ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 785ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 786ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 787ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 788ab677ff4SHariprasad Shenai }; 789ab677ff4SHariprasad Shenai 790f7917c00SJeff Kirsher struct sge { 791f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 792a4569504SAtul Gupta struct sge_eth_txq ptptxq; 793f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 794f7917c00SJeff Kirsher 795f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 796f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 79794cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 798ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 799f7917c00SJeff Kirsher 800f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 801f7917c00SJeff Kirsher spinlock_t intrq_lock; 802f7917c00SJeff Kirsher 803f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 804f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 805f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 8060fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 80794cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 808f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 809f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 81052367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 81152367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 81252367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 81352367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 81452367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 8150f4d201fSKumar Sanghvi 816a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 817f7917c00SJeff Kirsher unsigned int egr_start; 8184b8e27a8SHariprasad Shenai unsigned int egr_sz; 819f7917c00SJeff Kirsher unsigned int ingr_start; 8204b8e27a8SHariprasad Shenai unsigned int ingr_sz; 8214b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 8224b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 8234b8e27a8SHariprasad Shenai unsigned long *starving_fl; 8244b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 8255b377d11SHariprasad Shenai unsigned long *blocked_fl; 826f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 827f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 828f7917c00SJeff Kirsher }; 829f7917c00SJeff Kirsher 830f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 8310fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 832f7917c00SJeff Kirsher 833f7917c00SJeff Kirsher struct l2t_data; 834f7917c00SJeff Kirsher 8352422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 8362422d9a3SSantosh Rastapur 8377d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 8387d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 8397d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 8402422d9a3SSantosh Rastapur */ 8417d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 8422422d9a3SSantosh Rastapur 8432422d9a3SSantosh Rastapur #endif 8442422d9a3SSantosh Rastapur 845a4cfd929SHariprasad Shenai struct doorbell_stats { 846a4cfd929SHariprasad Shenai u32 db_drop; 847a4cfd929SHariprasad Shenai u32 db_empty; 848a4cfd929SHariprasad Shenai u32 db_full; 849a4cfd929SHariprasad Shenai }; 850a4cfd929SHariprasad Shenai 851fc08a01aSHariprasad Shenai struct hash_mac_addr { 852fc08a01aSHariprasad Shenai struct list_head list; 853fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 854fc08a01aSHariprasad Shenai }; 855fc08a01aSHariprasad Shenai 85694cdb8bbSHariprasad Shenai struct uld_msix_bmap { 85794cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 85894cdb8bbSHariprasad Shenai unsigned int mapsize; 85994cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 86094cdb8bbSHariprasad Shenai }; 86194cdb8bbSHariprasad Shenai 86294cdb8bbSHariprasad Shenai struct uld_msix_info { 86394cdb8bbSHariprasad Shenai unsigned short vec; 86494cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 8650fbc81b3SHariprasad Shenai unsigned int idx; 86694cdb8bbSHariprasad Shenai }; 86794cdb8bbSHariprasad Shenai 868661dbeb9SHariprasad Shenai struct vf_info { 869661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 8708ea4fae9SGanesh Goudar unsigned int tx_rate; 871661dbeb9SHariprasad Shenai bool pf_set_mac; 8729d5fd927SGanesh Goudar u16 vlan; 873661dbeb9SHariprasad Shenai }; 874661dbeb9SHariprasad Shenai 8758b4e6b3cSArjun Vynipadath enum { 8768b4e6b3cSArjun Vynipadath HMA_DMA_MAPPED_FLAG = 1 8778b4e6b3cSArjun Vynipadath }; 8788b4e6b3cSArjun Vynipadath 8798b4e6b3cSArjun Vynipadath struct hma_data { 8808b4e6b3cSArjun Vynipadath unsigned char flags; 8818b4e6b3cSArjun Vynipadath struct sg_table *sgt; 8828b4e6b3cSArjun Vynipadath dma_addr_t *phy_addr; /* physical address of the page */ 8838b4e6b3cSArjun Vynipadath }; 8848b4e6b3cSArjun Vynipadath 8854055ae5eSHariprasad Shenai struct mbox_list { 8864055ae5eSHariprasad Shenai struct list_head list; 8874055ae5eSHariprasad Shenai }; 8884055ae5eSHariprasad Shenai 889846eac3fSGanesh Goudar struct mps_encap_entry { 890846eac3fSGanesh Goudar atomic_t refcnt; 891846eac3fSGanesh Goudar }; 892846eac3fSGanesh Goudar 893f7917c00SJeff Kirsher struct adapter { 894f7917c00SJeff Kirsher void __iomem *regs; 89522adfe0aSSantosh Rastapur void __iomem *bar2; 8960abfd152SHariprasad Shenai u32 t4_bar0; 897f7917c00SJeff Kirsher struct pci_dev *pdev; 898f7917c00SJeff Kirsher struct device *pdev_dev; 8990de72738SHariprasad Shenai const char *name; 9003069ee9bSVipul Pandya unsigned int mbox; 901b2612722SHariprasad Shenai unsigned int pf; 902f7917c00SJeff Kirsher unsigned int flags; 903e7b48a32SHariprasad Shenai unsigned int adap_idx; 9042422d9a3SSantosh Rastapur enum chip_type chip; 905d5fbda61SArjun Vynipadath u32 eth_flags; 906f7917c00SJeff Kirsher 907f7917c00SJeff Kirsher int msg_enable; 908846eac3fSGanesh Goudar __be16 vxlan_port; 909846eac3fSGanesh Goudar u8 vxlan_port_cnt; 910c746fc0eSGanesh Goudar __be16 geneve_port; 911c746fc0eSGanesh Goudar u8 geneve_port_cnt; 912f7917c00SJeff Kirsher 913f7917c00SJeff Kirsher struct adapter_params params; 914f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 915f7917c00SJeff Kirsher unsigned int swintr; 916f7917c00SJeff Kirsher 917f7917c00SJeff Kirsher struct { 918f7917c00SJeff Kirsher unsigned short vec; 919f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 920f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 92194cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 92294cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 9230fbc81b3SHariprasad Shenai int msi_idx; 924f7917c00SJeff Kirsher 925a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 926f7917c00SJeff Kirsher struct sge sge; 927f7917c00SJeff Kirsher 928f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 929f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 930f7917c00SJeff Kirsher 931661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 932661dbeb9SHariprasad Shenai u8 num_vfs; 933661dbeb9SHariprasad Shenai 934793dad94SVipul Pandya u32 filter_mode; 935636f9d37SVipul Pandya unsigned int l2t_start; 936636f9d37SVipul Pandya unsigned int l2t_end; 937f7917c00SJeff Kirsher struct l2t_data *l2t; 938b5a02f50SAnish Bhatt unsigned int clipt_start; 939b5a02f50SAnish Bhatt unsigned int clipt_end; 940b5a02f50SAnish Bhatt struct clip_tbl *clipt; 941846eac3fSGanesh Goudar unsigned int rawf_start; 942846eac3fSGanesh Goudar unsigned int rawf_cnt; 9433bdb376eSKumar Sanghvi struct smt_data *smt; 944846eac3fSGanesh Goudar struct mps_encap_entry *mps_encap; 9450fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 946f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 94794cdb8bbSHariprasad Shenai unsigned int num_uld; 9480fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 949f7917c00SJeff Kirsher struct list_head list_node; 95001bcca68SVipul Pandya struct list_head rcu_node; 951fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 952f7917c00SJeff Kirsher 9537714cb9eSVarun Prakash void *iscsi_ppm; 9547714cb9eSVarun Prakash 955f7917c00SJeff Kirsher struct tid_info tids; 956f7917c00SJeff Kirsher void **tid_release_head; 957f7917c00SJeff Kirsher spinlock_t tid_release_lock; 95829aaee65SAnish Bhatt struct workqueue_struct *workq; 959f7917c00SJeff Kirsher struct work_struct tid_release_task; 960881806bcSVipul Pandya struct work_struct db_full_task; 961881806bcSVipul Pandya struct work_struct db_drop_task; 9628b7372c1SGanesh Goudar struct work_struct fatal_err_notify_task; 963f7917c00SJeff Kirsher bool tid_release_task_busy; 964f7917c00SJeff Kirsher 9654055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 9664055ae5eSHariprasad Shenai spinlock_t mbox_lock; 9674055ae5eSHariprasad Shenai struct mbox_list mlist; 9684055ae5eSHariprasad Shenai 9697f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 9707f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 9717f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 9727f080c3fSHariprasad Shenai 9730fbc81b3SHariprasad Shenai struct mutex uld_mutex; 9740fbc81b3SHariprasad Shenai 975f7917c00SJeff Kirsher struct dentry *debugfs_root; 976621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 977621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 9788e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 9798e3d04fdSHariprasad Shenai * used for all 4 filters. 9808e3d04fdSHariprasad Shenai */ 981f7917c00SJeff Kirsher 982a4569504SAtul Gupta struct ptp_clock *ptp_clock; 983a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 984a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 985a4569504SAtul Gupta /* ptp lock */ 986a4569504SAtul Gupta spinlock_t ptp_lock; 987f7917c00SJeff Kirsher spinlock_t stats_lock; 988fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 989d8931847SRahul Lakkireddy 990d8931847SRahul Lakkireddy /* TC u32 offload */ 991d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 992ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 99362488e4bSKumar Sanghvi 99462488e4bSKumar Sanghvi /* TC flower offload */ 995a081e115SCasey Leedom bool tc_flower_initialized; 99679e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 99779e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 998e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 99979e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 1000ad75b7d3SRahul Lakkireddy 1001ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 1002ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 10038b4e6b3cSArjun Vynipadath 10048b4e6b3cSArjun Vynipadath /* HMA */ 10058b4e6b3cSArjun Vynipadath struct hma_data hma; 1006e4709475SRaju Rangoju 1007e4709475SRaju Rangoju struct srq_data *srq; 10081dde532dSRahul Lakkireddy 10091dde532dSRahul Lakkireddy /* Dump buffer for collecting logs in kdump kernel */ 10101dde532dSRahul Lakkireddy struct vmcoredd_data vmcoredd; 1011f7917c00SJeff Kirsher }; 1012f7917c00SJeff Kirsher 1013b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 1014b72a32daSRahul Lakkireddy * programmed with various parameters. 1015b72a32daSRahul Lakkireddy */ 1016b72a32daSRahul Lakkireddy struct ch_sched_params { 1017b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 1018b72a32daSRahul Lakkireddy union { 1019b72a32daSRahul Lakkireddy struct { 1020b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 1021b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 1022b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 1023b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 1024b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 1025b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 1026b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 1027b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 1028b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 1029b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 1030b72a32daSRahul Lakkireddy } params; 1031b72a32daSRahul Lakkireddy } u; 1032b72a32daSRahul Lakkireddy }; 1033b72a32daSRahul Lakkireddy 103410a2604eSRahul Lakkireddy enum { 103510a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 103610a2604eSRahul Lakkireddy }; 103710a2604eSRahul Lakkireddy 103810a2604eSRahul Lakkireddy enum { 103910a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 104010a2604eSRahul Lakkireddy }; 104110a2604eSRahul Lakkireddy 104210a2604eSRahul Lakkireddy enum { 104310a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 104410a2604eSRahul Lakkireddy }; 104510a2604eSRahul Lakkireddy 104610a2604eSRahul Lakkireddy enum { 104710a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 104810a2604eSRahul Lakkireddy }; 104910a2604eSRahul Lakkireddy 105010a2604eSRahul Lakkireddy enum { 105110a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 105210a2604eSRahul Lakkireddy }; 105310a2604eSRahul Lakkireddy 1054a6ec572bSAtul Gupta struct tx_sw_desc { /* SW state per Tx descriptor */ 1055a6ec572bSAtul Gupta struct sk_buff *skb; 1056a6ec572bSAtul Gupta struct ulptx_sgl *sgl; 1057a6ec572bSAtul Gupta }; 1058a6ec572bSAtul Gupta 10596cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 10606cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 10616cede1f1SRahul Lakkireddy */ 10626cede1f1SRahul Lakkireddy struct ch_sched_queue { 10636cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 10646cede1f1SRahul Lakkireddy s8 class; /* class index */ 10656cede1f1SRahul Lakkireddy }; 10666cede1f1SRahul Lakkireddy 1067f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 1068f2b7e78dSVipul Pandya */ 1069f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 1070f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 1071f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 1072f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 1073f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 1074f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1075f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1076f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1077f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1078f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1079f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1080f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 108198f3697fSKumar Sanghvi #define ENCAP_VNI_BITWIDTH 24 1082f2b7e78dSVipul Pandya 1083f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1084f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1085f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1086f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1087f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1088f2b7e78dSVipul Pandya * matching rules are true. 1089f2b7e78dSVipul Pandya * 1090f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1091f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1092f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1093f2b7e78dSVipul Pandya * MPS match type) ... 1094f2b7e78dSVipul Pandya * 1095f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1096f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1097f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1098f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1099f2b7e78dSVipul Pandya */ 1100f2b7e78dSVipul Pandya struct ch_filter_tuple { 1101f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1102f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1103f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1104f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1105f2b7e78dSVipul Pandya * set of fields. 1106f2b7e78dSVipul Pandya */ 1107f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1108f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1109f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1110f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1111f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 111298f3697fSKumar Sanghvi uint32_t encap_vld:1; /* Encapsulation valid */ 1113f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1114f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1115f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1116f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1117f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1118f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1119f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1120f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1121f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1122f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 112398f3697fSKumar Sanghvi uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1124f2b7e78dSVipul Pandya 1125f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1126f2b7e78dSVipul Pandya * available for field rules. 1127f2b7e78dSVipul Pandya */ 1128f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1129f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1130f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1131f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1132f2b7e78dSVipul Pandya }; 1133f2b7e78dSVipul Pandya 1134f2b7e78dSVipul Pandya /* A filter ioctl command. 1135f2b7e78dSVipul Pandya */ 1136f2b7e78dSVipul Pandya struct ch_filter_specification { 1137f2b7e78dSVipul Pandya /* Administrative fields for filter. 1138f2b7e78dSVipul Pandya */ 1139f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1140f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1141f2b7e78dSVipul Pandya 1142f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1143f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1144f2b7e78dSVipul Pandya */ 1145f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 114612b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1147f2b7e78dSVipul Pandya 1148f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1149f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1150f2b7e78dSVipul Pandya * out as egress packets. 1151f2b7e78dSVipul Pandya */ 1152f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1153f2b7e78dSVipul Pandya 1154f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1155f2b7e78dSVipul Pandya 1156f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1157f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1158f2b7e78dSVipul Pandya 1159f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1160f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1161f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1162f2b7e78dSVipul Pandya 1163f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1164f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1165f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1166f2b7e78dSVipul Pandya */ 1167f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1168f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1169f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1170f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 11710ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1172f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1173f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1174f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1175f2b7e78dSVipul Pandya 11760ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 11770ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 11780ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 11790ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 11800ff90994SKumar Sanghvi 11810ff90994SKumar Sanghvi /* reservation for future additions */ 11820ff90994SKumar Sanghvi u8 rsvd[24]; 11830ff90994SKumar Sanghvi 1184f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1185f2b7e78dSVipul Pandya */ 1186f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1187f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1188f2b7e78dSVipul Pandya }; 1189f2b7e78dSVipul Pandya 1190f2b7e78dSVipul Pandya enum { 1191f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1192f2b7e78dSVipul Pandya FILTER_DROP, 1193f2b7e78dSVipul Pandya FILTER_SWITCH 1194f2b7e78dSVipul Pandya }; 1195f2b7e78dSVipul Pandya 1196f2b7e78dSVipul Pandya enum { 1197f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1198f2b7e78dSVipul Pandya VLAN_REMOVE, 1199f2b7e78dSVipul Pandya VLAN_INSERT, 1200f2b7e78dSVipul Pandya VLAN_REWRITE 1201f2b7e78dSVipul Pandya }; 1202f2b7e78dSVipul Pandya 1203557ccbf9SKumar Sanghvi enum { 120412b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 120512b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 120612b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 120712b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 120812b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 120912b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 121012b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 121112b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1212557ccbf9SKumar Sanghvi }; 1213557ccbf9SKumar Sanghvi 1214d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1215d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1216d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1217d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1218d57fd6caSRahul Lakkireddy * where the filter table is large. 1219d57fd6caSRahul Lakkireddy */ 1220d57fd6caSRahul Lakkireddy struct filter_entry { 1221d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1222d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1223d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1224d57fd6caSRahul Lakkireddy 1225d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1226578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1227d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 12283bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1229578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1230578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1231d57fd6caSRahul Lakkireddy 1232d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1233d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1234d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1235d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1236d57fd6caSRahul Lakkireddy */ 1237d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1238d57fd6caSRahul Lakkireddy }; 1239d57fd6caSRahul Lakkireddy 1240a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1241a4cfd929SHariprasad Shenai { 1242a4cfd929SHariprasad Shenai return adap->params.offload; 1243a4cfd929SHariprasad Shenai } 1244a4cfd929SHariprasad Shenai 12455c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 12465c31254eSKumar Sanghvi { 12475c31254eSKumar Sanghvi return adap->params.hash_filter; 12485c31254eSKumar Sanghvi } 12495c31254eSKumar Sanghvi 125094cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 125194cdb8bbSHariprasad Shenai { 125294cdb8bbSHariprasad Shenai return adap->params.crypto; 125394cdb8bbSHariprasad Shenai } 125494cdb8bbSHariprasad Shenai 12550fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 12560fbc81b3SHariprasad Shenai { 12570fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 12580fbc81b3SHariprasad Shenai } 12590fbc81b3SHariprasad Shenai 1260f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1261f7917c00SJeff Kirsher { 1262f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1263f7917c00SJeff Kirsher } 1264f7917c00SJeff Kirsher 1265f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1266f7917c00SJeff Kirsher { 1267f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1268f7917c00SJeff Kirsher } 1269f7917c00SJeff Kirsher 1270f7917c00SJeff Kirsher #ifndef readq 1271f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1272f7917c00SJeff Kirsher { 1273f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1274f7917c00SJeff Kirsher } 1275f7917c00SJeff Kirsher 1276f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1277f7917c00SJeff Kirsher { 1278f7917c00SJeff Kirsher writel(val, addr); 1279f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1280f7917c00SJeff Kirsher } 1281f7917c00SJeff Kirsher #endif 1282f7917c00SJeff Kirsher 1283f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1284f7917c00SJeff Kirsher { 1285f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1286f7917c00SJeff Kirsher } 1287f7917c00SJeff Kirsher 1288f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1289f7917c00SJeff Kirsher { 1290f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1291f7917c00SJeff Kirsher } 1292f7917c00SJeff Kirsher 1293f7917c00SJeff Kirsher /** 1294098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1295098ef6c2SHariprasad Shenai * @adapter: the adapter 1296098ef6c2SHariprasad Shenai * @port_idx: the port index 1297098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1298098ef6c2SHariprasad Shenai * 1299098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1300098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1301098ef6c2SHariprasad Shenai */ 1302098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1303098ef6c2SHariprasad Shenai u8 hw_addr[]) 1304098ef6c2SHariprasad Shenai { 1305098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1306098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1307098ef6c2SHariprasad Shenai } 1308098ef6c2SHariprasad Shenai 1309098ef6c2SHariprasad Shenai /** 1310f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1311f7917c00SJeff Kirsher * @dev: the netdev 1312f7917c00SJeff Kirsher * 1313f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1314f7917c00SJeff Kirsher */ 1315f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1316f7917c00SJeff Kirsher { 1317f7917c00SJeff Kirsher return netdev_priv(dev); 1318f7917c00SJeff Kirsher } 1319f7917c00SJeff Kirsher 1320f7917c00SJeff Kirsher /** 1321f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1322f7917c00SJeff Kirsher * @adap: the adapter 1323f7917c00SJeff Kirsher * @idx: the port index 1324f7917c00SJeff Kirsher * 1325f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1326f7917c00SJeff Kirsher */ 1327f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1328f7917c00SJeff Kirsher { 1329f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1330f7917c00SJeff Kirsher } 1331f7917c00SJeff Kirsher 1332f7917c00SJeff Kirsher /** 1333f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1334f7917c00SJeff Kirsher * @dev: the netdev 1335f7917c00SJeff Kirsher * 1336f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1337f7917c00SJeff Kirsher */ 1338f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1339f7917c00SJeff Kirsher { 1340f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1341f7917c00SJeff Kirsher } 1342f7917c00SJeff Kirsher 1343812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1344812034f1SHariprasad Shenai * - bits 0..9: chip version 1345812034f1SHariprasad Shenai * - bits 10..15: chip revision 1346812034f1SHariprasad Shenai * - bits 16..23: register dump version 1347812034f1SHariprasad Shenai */ 1348812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1349812034f1SHariprasad Shenai { 1350812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1351812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1352812034f1SHariprasad Shenai } 1353812034f1SHariprasad Shenai 1354812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1355812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1356812034f1SHariprasad Shenai const struct sge_rspq *q) 1357812034f1SHariprasad Shenai { 1358812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1359812034f1SHariprasad Shenai 1360812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1361812034f1SHariprasad Shenai } 1362812034f1SHariprasad Shenai 1363812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1364812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1365812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1366812034f1SHariprasad Shenai 13678156b0baSGanesh Goudar void t4_os_portmod_changed(struct adapter *adap, int port_id); 1368f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1369f7917c00SJeff Kirsher 1370f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 13715fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1372f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1373d5fbda61SArjun Vynipadath netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1374f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1375f7917c00SJeff Kirsher const struct pkt_gl *gl); 1376f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1377f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1378f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1379f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 13802337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 13812337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1382f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1383f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1384f7917c00SJeff Kirsher unsigned int iqid); 1385f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1386f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1387f7917c00SJeff Kirsher unsigned int cmplqid); 13880fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 13890fbc81b3SHariprasad Shenai unsigned int cmplqid); 1390ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1391ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1392ab677ff4SHariprasad Shenai unsigned int uld_type); 1393f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 139452367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1395f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1396f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1397812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1398812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1399d0a1299cSGanesh Goudar enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 14003069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1401f7917c00SJeff Kirsher 1402f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1403f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1404f7917c00SJeff Kirsher 14059a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 14069a4da2cdSVipul Pandya { 14079a4da2cdSVipul Pandya return adap->params.bypass; 14089a4da2cdSVipul Pandya } 14099a4da2cdSVipul Pandya 14109a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 14119a4da2cdSVipul Pandya { 14129a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 14139a4da2cdSVipul Pandya switch (device) { 14149a4da2cdSVipul Pandya case 0x440b: 14159a4da2cdSVipul Pandya case 0x440c: 14169a4da2cdSVipul Pandya return 1; 14179a4da2cdSVipul Pandya default: 14189a4da2cdSVipul Pandya return 0; 14199a4da2cdSVipul Pandya } 14209a4da2cdSVipul Pandya } 14219a4da2cdSVipul Pandya 142201b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 142301b69614SHariprasad Shenai { 142401b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 142501b69614SHariprasad Shenai switch (device) { 142601b69614SHariprasad Shenai case 0x4409: 142701b69614SHariprasad Shenai case 0x4486: 142801b69614SHariprasad Shenai return 1; 142901b69614SHariprasad Shenai 143001b69614SHariprasad Shenai default: 143101b69614SHariprasad Shenai return 0; 143201b69614SHariprasad Shenai } 143301b69614SHariprasad Shenai } 143401b69614SHariprasad Shenai 1435f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1436f7917c00SJeff Kirsher { 1437f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1438f7917c00SJeff Kirsher } 1439f7917c00SJeff Kirsher 1440f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1441f7917c00SJeff Kirsher unsigned int us) 1442f7917c00SJeff Kirsher { 1443f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1444f7917c00SJeff Kirsher } 1445f7917c00SJeff Kirsher 144652367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 144752367a76SVipul Pandya unsigned int ticks) 144852367a76SVipul Pandya { 144952367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 145052367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 145152367a76SVipul Pandya adapter->params.vpd.cclk); 145252367a76SVipul Pandya } 145352367a76SVipul Pandya 145408c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 145508c4901bSRahul Lakkireddy unsigned int ticks) 145608c4901bSRahul Lakkireddy { 145708c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 145808c4901bSRahul Lakkireddy } 145908c4901bSRahul Lakkireddy 1460f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1461f7917c00SJeff Kirsher u32 val); 1462f7917c00SJeff Kirsher 146301b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 146401b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1465f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1466f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1467f7917c00SJeff Kirsher 146801b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 146901b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 147001b69614SHariprasad Shenai int timeout) 147101b69614SHariprasad Shenai { 147201b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 147301b69614SHariprasad Shenai timeout); 147401b69614SHariprasad Shenai } 147501b69614SHariprasad Shenai 1476f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1477f7917c00SJeff Kirsher int size, void *rpl) 1478f7917c00SJeff Kirsher { 1479f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1480f7917c00SJeff Kirsher } 1481f7917c00SJeff Kirsher 1482f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1483f7917c00SJeff Kirsher int size, void *rpl) 1484f7917c00SJeff Kirsher { 1485f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1486f7917c00SJeff Kirsher } 1487f7917c00SJeff Kirsher 1488fc08a01aSHariprasad Shenai /** 1489fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1490fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1491fc08a01aSHariprasad Shenai * 1492fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1493fc08a01aSHariprasad Shenai * (hash) address matching. 1494fc08a01aSHariprasad Shenai */ 1495fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1496fc08a01aSHariprasad Shenai { 1497fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1498fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1499fc08a01aSHariprasad Shenai 1500fc08a01aSHariprasad Shenai a ^= b; 1501fc08a01aSHariprasad Shenai a ^= (a >> 12); 1502fc08a01aSHariprasad Shenai a ^= (a >> 6); 1503fc08a01aSHariprasad Shenai return a & 0x3f; 1504fc08a01aSHariprasad Shenai } 1505fc08a01aSHariprasad Shenai 150694cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 150794cdb8bbSHariprasad Shenai unsigned int cnt); 150894cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 150994cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 151094cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 151194cdb8bbSHariprasad Shenai { 151294cdb8bbSHariprasad Shenai q->adap = adap; 151394cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 151494cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 151594cdb8bbSHariprasad Shenai q->size = size; 151694cdb8bbSHariprasad Shenai } 151794cdb8bbSHariprasad Shenai 1518f56ec676SArjun Vynipadath /** 1519f56ec676SArjun Vynipadath * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1520f56ec676SArjun Vynipadath * @fw_mod_type: the Firmware Mofule Type 1521f56ec676SArjun Vynipadath * 1522f56ec676SArjun Vynipadath * Return whether the Firmware Module Type represents a real Transceiver 1523f56ec676SArjun Vynipadath * Module/Cable Module Type which has been inserted. 1524f56ec676SArjun Vynipadath */ 1525f56ec676SArjun Vynipadath static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1526f56ec676SArjun Vynipadath { 1527f56ec676SArjun Vynipadath return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1528f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1529f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1530f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1531f56ec676SArjun Vynipadath } 1532f56ec676SArjun Vynipadath 153313ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 153413ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 153513ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1536f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1537f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1538f2b7e78dSVipul Pandya unsigned int start_idx); 15390abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1540f2b7e78dSVipul Pandya 1541f2b7e78dSVipul Pandya struct fw_filter_wr; 1542f2b7e78dSVipul Pandya 1543f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1544f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1545f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1546f7917c00SJeff Kirsher 15478203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 15488156b0baSGanesh Goudar 15498156b0baSGanesh Goudar int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 15508156b0baSGanesh Goudar unsigned int port, struct link_config *lc, 15518156b0baSGanesh Goudar bool sleep_ok, int timeout); 15528156b0baSGanesh Goudar 15538156b0baSGanesh Goudar static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 15548156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 15558156b0baSGanesh Goudar { 15568156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 15578156b0baSGanesh Goudar true, FW_CMD_MAX_TIMEOUT); 15588156b0baSGanesh Goudar } 15598156b0baSGanesh Goudar 15608156b0baSGanesh Goudar static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 15618156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 15628156b0baSGanesh Goudar { 15638156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 15648156b0baSGanesh Goudar false, FW_CMD_MAX_TIMEOUT); 15658156b0baSGanesh Goudar } 15668156b0baSGanesh Goudar 1567f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1568fc5ab020SHariprasad Shenai 1569b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1570b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1571b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1572b562fc37SHariprasad Shenai 15731a4330cdSRahul Lakkireddy int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 15741a4330cdSRahul Lakkireddy u32 *mem_base, u32 *mem_aperture); 15751a4330cdSRahul Lakkireddy void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 15761a4330cdSRahul Lakkireddy void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 15771a4330cdSRahul Lakkireddy int dir); 1578fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1579fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1580fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1581f01aa633SHariprasad Shenai void *buf, int dir); 1582fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1583fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1584fc5ab020SHariprasad Shenai { 1585fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1586fc5ab020SHariprasad Shenai } 1587fc5ab020SHariprasad Shenai 1588812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1589812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1590812034f1SHariprasad Shenai 1591940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1592f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1593098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1594098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 15950eaec62aSCasey Leedom int t4_get_pfres(struct adapter *adapter); 159649216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 159749216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1598f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 159901b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 160001b69614SHariprasad Shenai int win, spinlock_t *lock, 160101b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 160201b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 160301b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 160449216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 160522c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 160622c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1607acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1608636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1609a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 16104da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 161116e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 16120de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 161316e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1614ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1615760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1616760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1617760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1618760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 161916e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 162016e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 162116e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1622f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 16233be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1624e85c9a7aSHariprasad Shenai 1625e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1626b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1627e85c9a7aSHariprasad Shenai unsigned int qid, 1628e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 162966cf188eSHariprasad S int user, 1630e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1631e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1632e85c9a7aSHariprasad Shenai 1633dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1634dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1635ae469b68SHariprasad Shenai 1636ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1637e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 16385ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1639dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1640c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1641c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1642c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1643f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1644f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1645f988008aSGanesh Goudar unsigned int t4_chip_rss_size(struct adapter *adapter); 1646f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1647f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1648f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1649f7917c00SJeff Kirsher unsigned int flags); 1650c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1651c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1652688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 16535ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 16545ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 16555ccf9d04SRahul Lakkireddy bool sleep_ok); 1656688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 16575ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1658688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 16595ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 16605ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 16615ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1662688ea5feSHariprasad Shenai 1663193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1664193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1665b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1666b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1667e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1668e5f0e43bSHariprasad Shenai size_t n); 1669c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1670c778af7dSHariprasad Shenai size_t n); 1671f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1672f1ff24aaSHariprasad Shenai unsigned int *valp); 1673f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1674f1ff24aaSHariprasad Shenai const unsigned int *valp); 1675f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 167619689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 167719689609SHariprasad Shenai unsigned int *pif_req_wrptr, 167819689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 167926fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 168074b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 168172aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1682f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1683a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1684a4cfd929SHariprasad Shenai struct port_stats *stats, 1685a4cfd929SHariprasad Shenai struct port_stats *offset); 168665046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1687f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1688bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1689636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1690636f9d37SVipul Pandya unsigned int mask, unsigned int val); 16912d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 16925ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 16935ccf9d04SRahul Lakkireddy bool sleep_ok); 16945ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 16955ccf9d04SRahul Lakkireddy bool sleep_ok); 16965ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 16975ccf9d04SRahul Lakkireddy bool sleep_ok); 16985ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 16995ccf9d04SRahul Lakkireddy bool sleep_ok); 1700f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 17015ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1702a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 17035ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1704f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1705f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1706f7917c00SJeff Kirsher 1707797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1708797ff0f5SHariprasad Shenai 17097864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1710f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1711f2b7e78dSVipul Pandya 1712f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1713f7917c00SJeff Kirsher const u8 *addr); 1714f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1715f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1716f7917c00SJeff Kirsher 1717f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1718f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1719f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1720f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1721f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1722636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1723636f9d37SVipul Pandya unsigned int cache_line_size); 1724636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1725f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1726f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1727f7917c00SJeff Kirsher u32 *val); 17288f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 17298f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 17308f46d467SArjun Vynipadath u32 *val); 173101b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1732f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 17338f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 173401b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1735688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1736688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 173701b69614SHariprasad Shenai const u32 *val, int timeout); 173801b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 173901b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1740688848b1SAnish Bhatt const u32 *val); 1741f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1742f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1743f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1744f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1745f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1746f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1747f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1748f7917c00SJeff Kirsher unsigned int *rss_size); 17494f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 17504f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 17514f3a0fcfSHariprasad Shenai unsigned int viid); 1752f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1753f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1754f7917c00SJeff Kirsher bool sleep_ok); 1755846eac3fSGanesh Goudar int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1756846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1757846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 175898f3697fSKumar Sanghvi int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 175998f3697fSKumar Sanghvi bool sleep_ok); 176098f3697fSKumar Sanghvi int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 176198f3697fSKumar Sanghvi const u8 *addr, const u8 *mask, unsigned int vni, 176298f3697fSKumar Sanghvi unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 176398f3697fSKumar Sanghvi bool sleep_ok); 1764846eac3fSGanesh Goudar int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1765846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1766846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 1767f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1768f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1769f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1770fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1771fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1772fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1773f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1774f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1775f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1776f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1777688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1778688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1779e2f4f4e9SArjun Vynipadath int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1780e2f4f4e9SArjun Vynipadath struct port_info *pi, 1781e2f4f4e9SArjun Vynipadath bool rx_en, bool tx_en, bool dcb_en); 1782f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1783f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1784f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1785f7917c00SJeff Kirsher unsigned int nblinks); 1786f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1787f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1788f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1789f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1790ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1791ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1792ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1793f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1794f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1795f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1796f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1797f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1798f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1799f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1800f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1801f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1802736c3b94SRahul Lakkireddy int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 180323853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 18042061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1805c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1806c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1807f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1808881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1809881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 18108e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 18118e3d04fdSHariprasad Shenai int filter_index, int enable); 18128e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 18138e3d04fdSHariprasad Shenai int filter_index, int *enabled); 18148caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 18158caa1e84SVipul Pandya u32 addr, u32 val); 181608c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 181708c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 181808c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 18199e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 18209e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 18219e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 18229e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 1823b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1824b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1825b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 182668bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1827a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1828a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1829a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1830a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1831a3bfb617SHariprasad Shenai int hz, int ticks); 1832858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1833858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 18345ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 18355ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 18364359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 18374359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 18385ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 18395ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 18405ccf9d04SRahul Lakkireddy 18410fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 18420fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 18430fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 18440fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 1845f56ec676SArjun Vynipadath int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1846f56ec676SArjun Vynipadath unsigned int devid, unsigned int offset, 1847f56ec676SArjun Vynipadath unsigned int len, u8 *buf); 184894cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1849ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1850ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1851ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1852a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 1853a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 1854a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1855a6ec572bSAtul Gupta dma_addr_t *addr); 1856a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1857a6ec572bSAtul Gupta void *pos); 1858a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1859a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1860a6ec572bSAtul Gupta const dma_addr_t *addr); 1861a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 18629d5fd927SGanesh Goudar int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 18639d5fd927SGanesh Goudar u16 vlan); 1864ebddd97aSGanesh Goudar int cxgb4_dcb_enabled(const struct net_device *dev); 1865f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1866