1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 505e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 51f7917c00SJeff Kirsher #include <asm/io.h> 5227999805SHariprasad S #include "t4_chip_type.h" 53f7917c00SJeff Kirsher #include "cxgb4_uld.h" 54f7917c00SJeff Kirsher 553069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 5694cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 5794cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 583069ee9bSVipul Pandya 59f7917c00SJeff Kirsher enum { 60f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 61f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 62f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 63f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 64a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 65098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 66f7917c00SJeff Kirsher }; 67f7917c00SJeff Kirsher 68f7917c00SJeff Kirsher enum { 69812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 70812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 71812034f1SHariprasad Shenai }; 72812034f1SHariprasad Shenai 73812034f1SHariprasad Shenai enum { 74f7917c00SJeff Kirsher MEM_EDC0, 75f7917c00SJeff Kirsher MEM_EDC1, 762422d9a3SSantosh Rastapur MEM_MC, 772422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 782422d9a3SSantosh Rastapur MEM_MC1 79f7917c00SJeff Kirsher }; 80f7917c00SJeff Kirsher 813069ee9bSVipul Pandya enum { 823eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 833eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 843069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 853069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 862422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 873eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 883eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 890abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 900abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 913069ee9bSVipul Pandya }; 923069ee9bSVipul Pandya 93f7917c00SJeff Kirsher enum dev_master { 94f7917c00SJeff Kirsher MASTER_CANT, 95f7917c00SJeff Kirsher MASTER_MAY, 96f7917c00SJeff Kirsher MASTER_MUST 97f7917c00SJeff Kirsher }; 98f7917c00SJeff Kirsher 99f7917c00SJeff Kirsher enum dev_state { 100f7917c00SJeff Kirsher DEV_STATE_UNINIT, 101f7917c00SJeff Kirsher DEV_STATE_INIT, 102f7917c00SJeff Kirsher DEV_STATE_ERR 103f7917c00SJeff Kirsher }; 104f7917c00SJeff Kirsher 105f7917c00SJeff Kirsher enum { 106f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 107f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 108f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 109f7917c00SJeff Kirsher }; 110f7917c00SJeff Kirsher 1113bb4858fSGanesh Goudar enum { 1123bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1133bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1143bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1153bb4858fSGanesh Goudar }; 1163bb4858fSGanesh Goudar 117f7917c00SJeff Kirsher struct port_stats { 118f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 119f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 120f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 121f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 122f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 123f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 124f7917c00SJeff Kirsher 125f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 126f7917c00SJeff Kirsher u64 tx_frames_65_127; 127f7917c00SJeff Kirsher u64 tx_frames_128_255; 128f7917c00SJeff Kirsher u64 tx_frames_256_511; 129f7917c00SJeff Kirsher u64 tx_frames_512_1023; 130f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 131f7917c00SJeff Kirsher u64 tx_frames_1519_max; 132f7917c00SJeff Kirsher 133f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 134f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 135f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 136f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 137f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 138f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 139f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 140f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 141f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 142f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 143f7917c00SJeff Kirsher 144f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 145f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 146f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 147f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 148f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 149f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 150f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 151f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 152f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 153f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 154f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 155f7917c00SJeff Kirsher 156f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 157f7917c00SJeff Kirsher u64 rx_frames_65_127; 158f7917c00SJeff Kirsher u64 rx_frames_128_255; 159f7917c00SJeff Kirsher u64 rx_frames_256_511; 160f7917c00SJeff Kirsher u64 rx_frames_512_1023; 161f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 162f7917c00SJeff Kirsher u64 rx_frames_1519_max; 163f7917c00SJeff Kirsher 164f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 165f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 166f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 167f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 168f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 169f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 170f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 171f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 172f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 173f7917c00SJeff Kirsher 174f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 175f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 176f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 177f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 178f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 179f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 180f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 181f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 182f7917c00SJeff Kirsher }; 183f7917c00SJeff Kirsher 184f7917c00SJeff Kirsher struct lb_port_stats { 185f7917c00SJeff Kirsher u64 octets; 186f7917c00SJeff Kirsher u64 frames; 187f7917c00SJeff Kirsher u64 bcast_frames; 188f7917c00SJeff Kirsher u64 mcast_frames; 189f7917c00SJeff Kirsher u64 ucast_frames; 190f7917c00SJeff Kirsher u64 error_frames; 191f7917c00SJeff Kirsher 192f7917c00SJeff Kirsher u64 frames_64; 193f7917c00SJeff Kirsher u64 frames_65_127; 194f7917c00SJeff Kirsher u64 frames_128_255; 195f7917c00SJeff Kirsher u64 frames_256_511; 196f7917c00SJeff Kirsher u64 frames_512_1023; 197f7917c00SJeff Kirsher u64 frames_1024_1518; 198f7917c00SJeff Kirsher u64 frames_1519_max; 199f7917c00SJeff Kirsher 200f7917c00SJeff Kirsher u64 drop; 201f7917c00SJeff Kirsher 202f7917c00SJeff Kirsher u64 ovflow0; 203f7917c00SJeff Kirsher u64 ovflow1; 204f7917c00SJeff Kirsher u64 ovflow2; 205f7917c00SJeff Kirsher u64 ovflow3; 206f7917c00SJeff Kirsher u64 trunc0; 207f7917c00SJeff Kirsher u64 trunc1; 208f7917c00SJeff Kirsher u64 trunc2; 209f7917c00SJeff Kirsher u64 trunc3; 210f7917c00SJeff Kirsher }; 211f7917c00SJeff Kirsher 212f7917c00SJeff Kirsher struct tp_tcp_stats { 213a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 214a4cfd929SHariprasad Shenai u64 tcp_in_segs; 215a4cfd929SHariprasad Shenai u64 tcp_out_segs; 216a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 217a4cfd929SHariprasad Shenai }; 218a4cfd929SHariprasad Shenai 219a4cfd929SHariprasad Shenai struct tp_usm_stats { 220a4cfd929SHariprasad Shenai u32 frames; 221a4cfd929SHariprasad Shenai u32 drops; 222a4cfd929SHariprasad Shenai u64 octets; 223f7917c00SJeff Kirsher }; 224f7917c00SJeff Kirsher 225a6222975SHariprasad Shenai struct tp_fcoe_stats { 226a6222975SHariprasad Shenai u32 frames_ddp; 227a6222975SHariprasad Shenai u32 frames_drop; 228a6222975SHariprasad Shenai u64 octets_ddp; 229f7917c00SJeff Kirsher }; 230f7917c00SJeff Kirsher 231f7917c00SJeff Kirsher struct tp_err_stats { 232a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 233a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 234a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 235a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 236a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 237a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 238a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 239a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 240a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 241a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 242a4cfd929SHariprasad Shenai }; 243a4cfd929SHariprasad Shenai 244a6222975SHariprasad Shenai struct tp_cpl_stats { 245a6222975SHariprasad Shenai u32 req[4]; 246a6222975SHariprasad Shenai u32 rsp[4]; 247a6222975SHariprasad Shenai }; 248a6222975SHariprasad Shenai 249a4cfd929SHariprasad Shenai struct tp_rdma_stats { 250a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 251a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 252f7917c00SJeff Kirsher }; 253f7917c00SJeff Kirsher 254e85c9a7aSHariprasad Shenai struct sge_params { 255e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 256e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 257e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 258e85c9a7aSHariprasad Shenai }; 259e85c9a7aSHariprasad Shenai 260f7917c00SJeff Kirsher struct tp_params { 261f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2622d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 263dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 264dca4faebSVipul Pandya /* channel map */ 265636f9d37SVipul Pandya 266636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 267636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 268dcf7b6f5SKumar Sanghvi 269dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 270dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 271dcf7b6f5SKumar Sanghvi 2728eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2738eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2748eb9f2f9SArjun V */ 2758eb9f2f9SArjun V int rx_pkt_encap; 2768eb9f2f9SArjun V 277dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 278dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 279dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 280dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 281dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 282dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 283dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 284dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 285dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 286dcf7b6f5SKumar Sanghvi * present. 287dcf7b6f5SKumar Sanghvi */ 288dcf7b6f5SKumar Sanghvi int vlan_shift; 289dcf7b6f5SKumar Sanghvi int vnic_shift; 290dcf7b6f5SKumar Sanghvi int port_shift; 291dcf7b6f5SKumar Sanghvi int protocol_shift; 292f7917c00SJeff Kirsher }; 293f7917c00SJeff Kirsher 294f7917c00SJeff Kirsher struct vpd_params { 295f7917c00SJeff Kirsher unsigned int cclk; 296f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 297f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 298f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 299a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 300098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 301f7917c00SJeff Kirsher }; 302f7917c00SJeff Kirsher 303f7917c00SJeff Kirsher struct pci_params { 304f7917c00SJeff Kirsher unsigned char speed; 305f7917c00SJeff Kirsher unsigned char width; 306f7917c00SJeff Kirsher }; 307f7917c00SJeff Kirsher 30849aa284fSHariprasad Shenai struct devlog_params { 30949aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 31049aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 31149aa284fSHariprasad Shenai u32 size; /* size of log */ 31249aa284fSHariprasad Shenai }; 31349aa284fSHariprasad Shenai 3143ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3153ccc6cf7SHariprasad Shenai struct arch_specific_params { 3163ccc6cf7SHariprasad Shenai u8 nchan; 31744588560SHariprasad Shenai u8 pm_stats_cnt; 3182216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3193ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3203ccc6cf7SHariprasad Shenai u16 vfcount; 3213ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3223ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3233ccc6cf7SHariprasad Shenai }; 3243ccc6cf7SHariprasad Shenai 325f7917c00SJeff Kirsher struct adapter_params { 326e85c9a7aSHariprasad Shenai struct sge_params sge; 327f7917c00SJeff Kirsher struct tp_params tp; 328f7917c00SJeff Kirsher struct vpd_params vpd; 329f7917c00SJeff Kirsher struct pci_params pci; 33049aa284fSHariprasad Shenai struct devlog_params devlog; 33149aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 332f7917c00SJeff Kirsher 333f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 334f1ff24aaSHariprasad Shenai 335f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 336f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 337f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 338f7917c00SJeff Kirsher 339f7917c00SJeff Kirsher unsigned int fw_vers; 3400de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 341f7917c00SJeff Kirsher unsigned int tp_vers; 3420de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 343f7917c00SJeff Kirsher u8 api_vers[7]; 344f7917c00SJeff Kirsher 345f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 346f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 347f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 348f7917c00SJeff Kirsher 349f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 350f7917c00SJeff Kirsher unsigned char portvec; 351d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3523ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 353f7917c00SJeff Kirsher unsigned char offload; 35494cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 355f7917c00SJeff Kirsher 3569a4da2cdSVipul Pandya unsigned char bypass; 3579a4da2cdSVipul Pandya 358f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3591ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3604c2c5763SHariprasad Shenai 361b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 3624c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3634c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 364086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 3658f46d467SArjun Vynipadath 3668f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 3678f46d467SArjun Vynipadath * used by the Port 3688f46d467SArjun Vynipadath */ 3698f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 370f7917c00SJeff Kirsher }; 371f7917c00SJeff Kirsher 372a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 373a3bfb617SHariprasad Shenai * and possible hangs. 374a3bfb617SHariprasad Shenai */ 375a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 376a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 377a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 378a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 379a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 380a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 381a3bfb617SHariprasad Shenai }; 382a3bfb617SHariprasad Shenai 3837f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 3847f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 3857f080c3fSHariprasad Shenai * error returns. 3867f080c3fSHariprasad Shenai */ 3877f080c3fSHariprasad Shenai struct mbox_cmd { 3887f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 3897f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 3907f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 3917f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 3927f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 3937f080c3fSHariprasad Shenai }; 3947f080c3fSHariprasad Shenai 3957f080c3fSHariprasad Shenai struct mbox_cmd_log { 3967f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 3977f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 3987f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 3997f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4007f080c3fSHariprasad Shenai }; 4017f080c3fSHariprasad Shenai 4027f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4037f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4047f080c3fSHariprasad Shenai */ 4057f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4067f080c3fSHariprasad Shenai unsigned int entry_idx) 4077f080c3fSHariprasad Shenai { 4087f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4097f080c3fSHariprasad Shenai } 4107f080c3fSHariprasad Shenai 41116e47624SHariprasad Shenai #include "t4fw_api.h" 41216e47624SHariprasad Shenai 41316e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 414b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 415b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 416b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 417b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 41816e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 41916e47624SHariprasad Shenai 42016e47624SHariprasad Shenai struct fw_info { 42116e47624SHariprasad Shenai u8 chip; 42216e47624SHariprasad Shenai char *fs_name; 42316e47624SHariprasad Shenai char *fw_mod_name; 42416e47624SHariprasad Shenai struct fw_hdr fw_hdr; 42516e47624SHariprasad Shenai }; 42616e47624SHariprasad Shenai 427f7917c00SJeff Kirsher struct trace_params { 428f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 429f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 430f7917c00SJeff Kirsher unsigned short snap_len; 431f7917c00SJeff Kirsher unsigned short min_len; 432f7917c00SJeff Kirsher unsigned char skip_ofst; 433f7917c00SJeff Kirsher unsigned char skip_len; 434f7917c00SJeff Kirsher unsigned char invert; 435f7917c00SJeff Kirsher unsigned char port; 436f7917c00SJeff Kirsher }; 437f7917c00SJeff Kirsher 438f7917c00SJeff Kirsher struct link_config { 439f7917c00SJeff Kirsher unsigned short supported; /* link capabilities */ 440f7917c00SJeff Kirsher unsigned short advertising; /* advertised capabilities */ 441eb97ad99SGanesh Goudar unsigned short lp_advertising; /* peer advertised capabilities */ 4429b86a8d1SHariprasad Shenai unsigned int requested_speed; /* speed user has requested */ 4439b86a8d1SHariprasad Shenai unsigned int speed; /* actual link speed */ 444f7917c00SJeff Kirsher unsigned char requested_fc; /* flow control user has requested */ 445f7917c00SJeff Kirsher unsigned char fc; /* actual link flow control */ 4463bb4858fSGanesh Goudar unsigned char auto_fec; /* Forward Error Correction: */ 4473bb4858fSGanesh Goudar unsigned char requested_fec; /* "automatic" (IEEE 802.3), */ 4483bb4858fSGanesh Goudar unsigned char fec; /* requested, and actual in use */ 449f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 450f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 451ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 452f7917c00SJeff Kirsher }; 453f7917c00SJeff Kirsher 454e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 455f7917c00SJeff Kirsher 456f7917c00SJeff Kirsher enum { 457f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 458f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 459f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 460f7917c00SJeff Kirsher }; 461f7917c00SJeff Kirsher 462f7917c00SJeff Kirsher enum { 463812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 464812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 465812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 466812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 467812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 468812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 469812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 470812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 471812034f1SHariprasad Shenai }; 472812034f1SHariprasad Shenai 473812034f1SHariprasad Shenai enum { 474cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 475cf38be6dSHariprasad Shenai /* forwarded interrupts */ 4760fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 477f7917c00SJeff Kirsher }; 478f7917c00SJeff Kirsher 479f7917c00SJeff Kirsher struct adapter; 480f7917c00SJeff Kirsher struct sge_rspq; 481f7917c00SJeff Kirsher 482688848b1SAnish Bhatt #include "cxgb4_dcb.h" 483688848b1SAnish Bhatt 48476fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 48576fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 48676fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 48776fed8a9SVarun Prakash 488f7917c00SJeff Kirsher struct port_info { 489f7917c00SJeff Kirsher struct adapter *adapter; 490f7917c00SJeff Kirsher u16 viid; 491f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 492f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 493f7917c00SJeff Kirsher s8 mdio_addr; 49440e9de4bSHariprasad Shenai enum fw_port_type port_type; 495f7917c00SJeff Kirsher u8 mod_type; 496f7917c00SJeff Kirsher u8 port_id; 497f7917c00SJeff Kirsher u8 tx_chan; 498f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 499f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 500f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 501f7917c00SJeff Kirsher u8 rss_mode; 502f7917c00SJeff Kirsher struct link_config link_cfg; 503f7917c00SJeff Kirsher u16 *rss; 504a4cfd929SHariprasad Shenai struct port_stats stats_base; 505688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 506688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 507688848b1SAnish Bhatt #endif 50876fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 50976fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 51076fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5115e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5125e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 513b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 514f7917c00SJeff Kirsher }; 515f7917c00SJeff Kirsher 516f7917c00SJeff Kirsher struct dentry; 517f7917c00SJeff Kirsher struct work_struct; 518f7917c00SJeff Kirsher 519f7917c00SJeff Kirsher enum { /* adapter flags */ 520f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 521144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 522144be3d9SGavin Shan USING_MSI = (1 << 2), 523144be3d9SGavin Shan USING_MSIX = (1 << 3), 524f7917c00SJeff Kirsher FW_OK = (1 << 4), 52513ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 52652367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 52752367a76SVipul Pandya MASTER_PF = (1 << 7), 52852367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 529f7917c00SJeff Kirsher }; 530f7917c00SJeff Kirsher 53194cdb8bbSHariprasad Shenai enum { 53294cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 53394cdb8bbSHariprasad Shenai }; 53494cdb8bbSHariprasad Shenai 535f7917c00SJeff Kirsher struct rx_sw_desc; 536f7917c00SJeff Kirsher 537f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 538f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 539f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 540f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 541f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 542f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 543f7917c00SJeff Kirsher unsigned long large_alloc_failed; 54470055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 54570055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 546f7917c00SJeff Kirsher unsigned long starving; 547f7917c00SJeff Kirsher /* RO fields */ 548f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 549f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 550f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 551f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 552f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 553df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 554df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 555f7917c00SJeff Kirsher }; 556f7917c00SJeff Kirsher 557f7917c00SJeff Kirsher /* A packet gather list */ 558f7917c00SJeff Kirsher struct pkt_gl { 5595e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 560e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 561f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 562f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 563f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 564f7917c00SJeff Kirsher }; 565f7917c00SJeff Kirsher 566f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 567f7917c00SJeff Kirsher const struct pkt_gl *gl); 5682337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 5692337ba42SVarun Prakash /* LRO related declarations for ULD */ 5702337ba42SVarun Prakash struct t4_lro_mgr { 5712337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 5722337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 5732337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 5742337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 5752337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 5762337ba42SVarun Prakash }; 577f7917c00SJeff Kirsher 578f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 579f7917c00SJeff Kirsher struct napi_struct napi; 580f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 581f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 582f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 583f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 584f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 585e553ec3fSHariprasad Shenai u8 adaptive_rx; 586f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 587f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 588f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 589f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 590f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 591f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 592f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 593f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 594df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 595df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 596f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 597f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 598f7917c00SJeff Kirsher struct adapter *adap; 599f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 600f7917c00SJeff Kirsher rspq_handler_t handler; 6012337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 6022337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 603f7917c00SJeff Kirsher }; 604f7917c00SJeff Kirsher 605f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 606f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 607f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 608f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 609f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 610f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 611f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 612f7917c00SJeff Kirsher }; 613f7917c00SJeff Kirsher 614f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 615f7917c00SJeff Kirsher struct sge_rspq rspq; 616f7917c00SJeff Kirsher struct sge_fl fl; 617f7917c00SJeff Kirsher struct sge_eth_stats stats; 618f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 619f7917c00SJeff Kirsher 620f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 621f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 622f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 623f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 624f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 625f7917c00SJeff Kirsher }; 626f7917c00SJeff Kirsher 627f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 628f7917c00SJeff Kirsher struct sge_rspq rspq; 629f7917c00SJeff Kirsher struct sge_fl fl; 630f7917c00SJeff Kirsher struct sge_ofld_stats stats; 631f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 632f7917c00SJeff Kirsher 633f7917c00SJeff Kirsher struct tx_desc { 634f7917c00SJeff Kirsher __be64 flit[8]; 635f7917c00SJeff Kirsher }; 636f7917c00SJeff Kirsher 637f7917c00SJeff Kirsher struct tx_sw_desc; 638f7917c00SJeff Kirsher 639f7917c00SJeff Kirsher struct sge_txq { 640f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 641ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 642f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 643f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 644f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 645f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 646f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 647f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 648f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 649f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 650f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 651f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 6523069ee9bSVipul Pandya spinlock_t db_lock; 6533069ee9bSVipul Pandya int db_disabled; 6543069ee9bSVipul Pandya unsigned short db_pidx; 65505eb2389SSteve Wise unsigned short db_pidx_inc; 656df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 657df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 658f7917c00SJeff Kirsher }; 659f7917c00SJeff Kirsher 660f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 661f7917c00SJeff Kirsher struct sge_txq q; 662f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 66310b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 66410b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 66510b00466SAnish Bhatt #endif 666f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 667f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 668f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 669f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 670f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 671f7917c00SJeff Kirsher 672ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 673f7917c00SJeff Kirsher struct sge_txq q; 674f7917c00SJeff Kirsher struct adapter *adap; 675f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 676f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 677126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 678f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 679f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 680f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 681f7917c00SJeff Kirsher 682f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 683f7917c00SJeff Kirsher struct sge_txq q; 684f7917c00SJeff Kirsher struct adapter *adap; 685f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 686f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 687f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 688f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 689f7917c00SJeff Kirsher 69094cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 69194cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 69294cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 69394cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 69494cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 69594cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 69694cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 69794cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 69894cdb8bbSHariprasad Shenai }; 69994cdb8bbSHariprasad Shenai 700ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 701ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 702ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 703ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 704ab677ff4SHariprasad Shenai }; 705ab677ff4SHariprasad Shenai 706f7917c00SJeff Kirsher struct sge { 707f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 708f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 709f7917c00SJeff Kirsher 710f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 711f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 71294cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 713ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 714f7917c00SJeff Kirsher 715f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 716f7917c00SJeff Kirsher spinlock_t intrq_lock; 717f7917c00SJeff Kirsher 718f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 719f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 720f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 7210fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 72294cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 723f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 724f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 72552367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 72652367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 72752367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 72852367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 72952367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 7300f4d201fSKumar Sanghvi 731a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 732f7917c00SJeff Kirsher unsigned int egr_start; 7334b8e27a8SHariprasad Shenai unsigned int egr_sz; 734f7917c00SJeff Kirsher unsigned int ingr_start; 7354b8e27a8SHariprasad Shenai unsigned int ingr_sz; 7364b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 7374b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 7384b8e27a8SHariprasad Shenai unsigned long *starving_fl; 7394b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 7405b377d11SHariprasad Shenai unsigned long *blocked_fl; 741f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 742f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 743f7917c00SJeff Kirsher }; 744f7917c00SJeff Kirsher 745f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 7460fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 747f7917c00SJeff Kirsher 748f7917c00SJeff Kirsher struct l2t_data; 749f7917c00SJeff Kirsher 7502422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 7512422d9a3SSantosh Rastapur 7527d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 7537d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 7547d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 7552422d9a3SSantosh Rastapur */ 7567d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 7572422d9a3SSantosh Rastapur 7582422d9a3SSantosh Rastapur #endif 7592422d9a3SSantosh Rastapur 760a4cfd929SHariprasad Shenai struct doorbell_stats { 761a4cfd929SHariprasad Shenai u32 db_drop; 762a4cfd929SHariprasad Shenai u32 db_empty; 763a4cfd929SHariprasad Shenai u32 db_full; 764a4cfd929SHariprasad Shenai }; 765a4cfd929SHariprasad Shenai 766fc08a01aSHariprasad Shenai struct hash_mac_addr { 767fc08a01aSHariprasad Shenai struct list_head list; 768fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 769fc08a01aSHariprasad Shenai }; 770fc08a01aSHariprasad Shenai 77194cdb8bbSHariprasad Shenai struct uld_msix_bmap { 77294cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 77394cdb8bbSHariprasad Shenai unsigned int mapsize; 77494cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 77594cdb8bbSHariprasad Shenai }; 77694cdb8bbSHariprasad Shenai 77794cdb8bbSHariprasad Shenai struct uld_msix_info { 77894cdb8bbSHariprasad Shenai unsigned short vec; 77994cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 7800fbc81b3SHariprasad Shenai unsigned int idx; 78194cdb8bbSHariprasad Shenai }; 78294cdb8bbSHariprasad Shenai 783661dbeb9SHariprasad Shenai struct vf_info { 784661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 7858ea4fae9SGanesh Goudar unsigned int tx_rate; 786661dbeb9SHariprasad Shenai bool pf_set_mac; 787661dbeb9SHariprasad Shenai }; 788661dbeb9SHariprasad Shenai 7894055ae5eSHariprasad Shenai struct mbox_list { 7904055ae5eSHariprasad Shenai struct list_head list; 7914055ae5eSHariprasad Shenai }; 7924055ae5eSHariprasad Shenai 793f7917c00SJeff Kirsher struct adapter { 794f7917c00SJeff Kirsher void __iomem *regs; 79522adfe0aSSantosh Rastapur void __iomem *bar2; 7960abfd152SHariprasad Shenai u32 t4_bar0; 797f7917c00SJeff Kirsher struct pci_dev *pdev; 798f7917c00SJeff Kirsher struct device *pdev_dev; 7990de72738SHariprasad Shenai const char *name; 8003069ee9bSVipul Pandya unsigned int mbox; 801b2612722SHariprasad Shenai unsigned int pf; 802f7917c00SJeff Kirsher unsigned int flags; 803e7b48a32SHariprasad Shenai unsigned int adap_idx; 8042422d9a3SSantosh Rastapur enum chip_type chip; 805f7917c00SJeff Kirsher 806f7917c00SJeff Kirsher int msg_enable; 807f7917c00SJeff Kirsher 808f7917c00SJeff Kirsher struct adapter_params params; 809f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 810f7917c00SJeff Kirsher unsigned int swintr; 811f7917c00SJeff Kirsher 812f7917c00SJeff Kirsher struct { 813f7917c00SJeff Kirsher unsigned short vec; 814f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 815f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 81694cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 81794cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 8180fbc81b3SHariprasad Shenai int msi_idx; 819f7917c00SJeff Kirsher 820a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 821f7917c00SJeff Kirsher struct sge sge; 822f7917c00SJeff Kirsher 823f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 824f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 825f7917c00SJeff Kirsher 826661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 827661dbeb9SHariprasad Shenai u8 num_vfs; 828661dbeb9SHariprasad Shenai 829793dad94SVipul Pandya u32 filter_mode; 830636f9d37SVipul Pandya unsigned int l2t_start; 831636f9d37SVipul Pandya unsigned int l2t_end; 832f7917c00SJeff Kirsher struct l2t_data *l2t; 833b5a02f50SAnish Bhatt unsigned int clipt_start; 834b5a02f50SAnish Bhatt unsigned int clipt_end; 835b5a02f50SAnish Bhatt struct clip_tbl *clipt; 8360fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 837f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 83894cdb8bbSHariprasad Shenai unsigned int num_uld; 8390fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 840f7917c00SJeff Kirsher struct list_head list_node; 84101bcca68SVipul Pandya struct list_head rcu_node; 842fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 843f7917c00SJeff Kirsher 8447714cb9eSVarun Prakash void *iscsi_ppm; 8457714cb9eSVarun Prakash 846f7917c00SJeff Kirsher struct tid_info tids; 847f7917c00SJeff Kirsher void **tid_release_head; 848f7917c00SJeff Kirsher spinlock_t tid_release_lock; 84929aaee65SAnish Bhatt struct workqueue_struct *workq; 850f7917c00SJeff Kirsher struct work_struct tid_release_task; 851881806bcSVipul Pandya struct work_struct db_full_task; 852881806bcSVipul Pandya struct work_struct db_drop_task; 853f7917c00SJeff Kirsher bool tid_release_task_busy; 854f7917c00SJeff Kirsher 8554055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 8564055ae5eSHariprasad Shenai spinlock_t mbox_lock; 8574055ae5eSHariprasad Shenai struct mbox_list mlist; 8584055ae5eSHariprasad Shenai 8597f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 8607f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 8617f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 8627f080c3fSHariprasad Shenai 8630fbc81b3SHariprasad Shenai struct mutex uld_mutex; 8640fbc81b3SHariprasad Shenai 865f7917c00SJeff Kirsher struct dentry *debugfs_root; 866621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 867621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 8688e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 8698e3d04fdSHariprasad Shenai * used for all 4 filters. 8708e3d04fdSHariprasad Shenai */ 871f7917c00SJeff Kirsher 872f7917c00SJeff Kirsher spinlock_t stats_lock; 873fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 874d8931847SRahul Lakkireddy 875d8931847SRahul Lakkireddy /* TC u32 offload */ 876d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 877f7917c00SJeff Kirsher }; 878f7917c00SJeff Kirsher 879b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 880b72a32daSRahul Lakkireddy * programmed with various parameters. 881b72a32daSRahul Lakkireddy */ 882b72a32daSRahul Lakkireddy struct ch_sched_params { 883b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 884b72a32daSRahul Lakkireddy union { 885b72a32daSRahul Lakkireddy struct { 886b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 887b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 888b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 889b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 890b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 891b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 892b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 893b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 894b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 895b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 896b72a32daSRahul Lakkireddy } params; 897b72a32daSRahul Lakkireddy } u; 898b72a32daSRahul Lakkireddy }; 899b72a32daSRahul Lakkireddy 90010a2604eSRahul Lakkireddy enum { 90110a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 90210a2604eSRahul Lakkireddy }; 90310a2604eSRahul Lakkireddy 90410a2604eSRahul Lakkireddy enum { 90510a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 90610a2604eSRahul Lakkireddy }; 90710a2604eSRahul Lakkireddy 90810a2604eSRahul Lakkireddy enum { 90910a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 91010a2604eSRahul Lakkireddy }; 91110a2604eSRahul Lakkireddy 91210a2604eSRahul Lakkireddy enum { 91310a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 91410a2604eSRahul Lakkireddy }; 91510a2604eSRahul Lakkireddy 91610a2604eSRahul Lakkireddy enum { 91710a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 91810a2604eSRahul Lakkireddy }; 91910a2604eSRahul Lakkireddy 9206cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 9216cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 9226cede1f1SRahul Lakkireddy */ 9236cede1f1SRahul Lakkireddy struct ch_sched_queue { 9246cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 9256cede1f1SRahul Lakkireddy s8 class; /* class index */ 9266cede1f1SRahul Lakkireddy }; 9276cede1f1SRahul Lakkireddy 928f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 929f2b7e78dSVipul Pandya */ 930f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 931f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 932f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 933f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 934f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 935f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 936f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 937f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 938f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 939f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 940f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 941f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 942f2b7e78dSVipul Pandya 943f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 944f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 945f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 946f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 947f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 948f2b7e78dSVipul Pandya * matching rules are true. 949f2b7e78dSVipul Pandya * 950f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 951f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 952f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 953f2b7e78dSVipul Pandya * MPS match type) ... 954f2b7e78dSVipul Pandya * 955f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 956f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 957f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 958f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 959f2b7e78dSVipul Pandya */ 960f2b7e78dSVipul Pandya struct ch_filter_tuple { 961f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 962f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 963f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 964f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 965f2b7e78dSVipul Pandya * set of fields. 966f2b7e78dSVipul Pandya */ 967f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 968f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 969f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 970f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 971f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 972f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 973f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 974f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 975f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 976f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 977f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 978f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 979f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 980f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 981f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 982f2b7e78dSVipul Pandya 983f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 984f2b7e78dSVipul Pandya * available for field rules. 985f2b7e78dSVipul Pandya */ 986f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 987f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 988f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 989f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 990f2b7e78dSVipul Pandya }; 991f2b7e78dSVipul Pandya 992f2b7e78dSVipul Pandya /* A filter ioctl command. 993f2b7e78dSVipul Pandya */ 994f2b7e78dSVipul Pandya struct ch_filter_specification { 995f2b7e78dSVipul Pandya /* Administrative fields for filter. 996f2b7e78dSVipul Pandya */ 997f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 998f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 999f2b7e78dSVipul Pandya 1000f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1001f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1002f2b7e78dSVipul Pandya */ 1003f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1004f2b7e78dSVipul Pandya 1005f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1006f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1007f2b7e78dSVipul Pandya * out as egress packets. 1008f2b7e78dSVipul Pandya */ 1009f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1010f2b7e78dSVipul Pandya 1011f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1012f2b7e78dSVipul Pandya 1013f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1014f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1015f2b7e78dSVipul Pandya 1016f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1017f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1018f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1019f2b7e78dSVipul Pandya 1020f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1021f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1022f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1023f2b7e78dSVipul Pandya */ 1024f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1025f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1026f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1027f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 1028f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1029f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1030f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1031f2b7e78dSVipul Pandya 1032f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1033f2b7e78dSVipul Pandya */ 1034f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1035f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1036f2b7e78dSVipul Pandya }; 1037f2b7e78dSVipul Pandya 1038f2b7e78dSVipul Pandya enum { 1039f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1040f2b7e78dSVipul Pandya FILTER_DROP, 1041f2b7e78dSVipul Pandya FILTER_SWITCH 1042f2b7e78dSVipul Pandya }; 1043f2b7e78dSVipul Pandya 1044f2b7e78dSVipul Pandya enum { 1045f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1046f2b7e78dSVipul Pandya VLAN_REMOVE, 1047f2b7e78dSVipul Pandya VLAN_INSERT, 1048f2b7e78dSVipul Pandya VLAN_REWRITE 1049f2b7e78dSVipul Pandya }; 1050f2b7e78dSVipul Pandya 1051d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1052d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1053d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1054d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1055d57fd6caSRahul Lakkireddy * where the filter table is large. 1056d57fd6caSRahul Lakkireddy */ 1057d57fd6caSRahul Lakkireddy struct filter_entry { 1058d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1059d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1060d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1061d57fd6caSRahul Lakkireddy 1062d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1063d57fd6caSRahul Lakkireddy u32 smtidx:8; /* Source MAC Table index for smac */ 1064578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1065d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1066578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1067578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1068d57fd6caSRahul Lakkireddy 1069d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1070d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1071d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1072d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1073d57fd6caSRahul Lakkireddy */ 1074d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1075d57fd6caSRahul Lakkireddy }; 1076d57fd6caSRahul Lakkireddy 1077a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1078a4cfd929SHariprasad Shenai { 1079a4cfd929SHariprasad Shenai return adap->params.offload; 1080a4cfd929SHariprasad Shenai } 1081a4cfd929SHariprasad Shenai 108294cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 108394cdb8bbSHariprasad Shenai { 108494cdb8bbSHariprasad Shenai return adap->params.crypto; 108594cdb8bbSHariprasad Shenai } 108694cdb8bbSHariprasad Shenai 10870fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 10880fbc81b3SHariprasad Shenai { 10890fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 10900fbc81b3SHariprasad Shenai } 10910fbc81b3SHariprasad Shenai 1092f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1093f7917c00SJeff Kirsher { 1094f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1095f7917c00SJeff Kirsher } 1096f7917c00SJeff Kirsher 1097f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1098f7917c00SJeff Kirsher { 1099f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1100f7917c00SJeff Kirsher } 1101f7917c00SJeff Kirsher 1102f7917c00SJeff Kirsher #ifndef readq 1103f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1104f7917c00SJeff Kirsher { 1105f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1106f7917c00SJeff Kirsher } 1107f7917c00SJeff Kirsher 1108f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1109f7917c00SJeff Kirsher { 1110f7917c00SJeff Kirsher writel(val, addr); 1111f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1112f7917c00SJeff Kirsher } 1113f7917c00SJeff Kirsher #endif 1114f7917c00SJeff Kirsher 1115f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1116f7917c00SJeff Kirsher { 1117f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1118f7917c00SJeff Kirsher } 1119f7917c00SJeff Kirsher 1120f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1121f7917c00SJeff Kirsher { 1122f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1123f7917c00SJeff Kirsher } 1124f7917c00SJeff Kirsher 1125f7917c00SJeff Kirsher /** 1126098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1127098ef6c2SHariprasad Shenai * @adapter: the adapter 1128098ef6c2SHariprasad Shenai * @port_idx: the port index 1129098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1130098ef6c2SHariprasad Shenai * 1131098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1132098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1133098ef6c2SHariprasad Shenai */ 1134098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1135098ef6c2SHariprasad Shenai u8 hw_addr[]) 1136098ef6c2SHariprasad Shenai { 1137098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1138098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1139098ef6c2SHariprasad Shenai } 1140098ef6c2SHariprasad Shenai 1141098ef6c2SHariprasad Shenai /** 1142f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1143f7917c00SJeff Kirsher * @dev: the netdev 1144f7917c00SJeff Kirsher * 1145f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1146f7917c00SJeff Kirsher */ 1147f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1148f7917c00SJeff Kirsher { 1149f7917c00SJeff Kirsher return netdev_priv(dev); 1150f7917c00SJeff Kirsher } 1151f7917c00SJeff Kirsher 1152f7917c00SJeff Kirsher /** 1153f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1154f7917c00SJeff Kirsher * @adap: the adapter 1155f7917c00SJeff Kirsher * @idx: the port index 1156f7917c00SJeff Kirsher * 1157f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1158f7917c00SJeff Kirsher */ 1159f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1160f7917c00SJeff Kirsher { 1161f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1162f7917c00SJeff Kirsher } 1163f7917c00SJeff Kirsher 1164f7917c00SJeff Kirsher /** 1165f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1166f7917c00SJeff Kirsher * @dev: the netdev 1167f7917c00SJeff Kirsher * 1168f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1169f7917c00SJeff Kirsher */ 1170f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1171f7917c00SJeff Kirsher { 1172f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1173f7917c00SJeff Kirsher } 1174f7917c00SJeff Kirsher 1175812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1176812034f1SHariprasad Shenai * - bits 0..9: chip version 1177812034f1SHariprasad Shenai * - bits 10..15: chip revision 1178812034f1SHariprasad Shenai * - bits 16..23: register dump version 1179812034f1SHariprasad Shenai */ 1180812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1181812034f1SHariprasad Shenai { 1182812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1183812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1184812034f1SHariprasad Shenai } 1185812034f1SHariprasad Shenai 1186812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1187812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1188812034f1SHariprasad Shenai const struct sge_rspq *q) 1189812034f1SHariprasad Shenai { 1190812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1191812034f1SHariprasad Shenai 1192812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1193812034f1SHariprasad Shenai } 1194812034f1SHariprasad Shenai 1195812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1196812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1197812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1198812034f1SHariprasad Shenai 1199f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1200f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1201f7917c00SJeff Kirsher 1202f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 12035fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1204f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1205f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1206f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1207f7917c00SJeff Kirsher const struct pkt_gl *gl); 1208f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1209f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1210f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1211f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 12122337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 12132337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1214f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1215f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1216f7917c00SJeff Kirsher unsigned int iqid); 1217f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1218f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1219f7917c00SJeff Kirsher unsigned int cmplqid); 12200fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 12210fbc81b3SHariprasad Shenai unsigned int cmplqid); 1222ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1223ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1224ab677ff4SHariprasad Shenai unsigned int uld_type); 1225f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 122652367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1227f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1228f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1229812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1230812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 12313069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1232f7917c00SJeff Kirsher 1233f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1234f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1235f7917c00SJeff Kirsher 12369a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 12379a4da2cdSVipul Pandya { 12389a4da2cdSVipul Pandya return adap->params.bypass; 12399a4da2cdSVipul Pandya } 12409a4da2cdSVipul Pandya 12419a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 12429a4da2cdSVipul Pandya { 12439a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 12449a4da2cdSVipul Pandya switch (device) { 12459a4da2cdSVipul Pandya case 0x440b: 12469a4da2cdSVipul Pandya case 0x440c: 12479a4da2cdSVipul Pandya return 1; 12489a4da2cdSVipul Pandya default: 12499a4da2cdSVipul Pandya return 0; 12509a4da2cdSVipul Pandya } 12519a4da2cdSVipul Pandya } 12529a4da2cdSVipul Pandya 125301b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 125401b69614SHariprasad Shenai { 125501b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 125601b69614SHariprasad Shenai switch (device) { 125701b69614SHariprasad Shenai case 0x4409: 125801b69614SHariprasad Shenai case 0x4486: 125901b69614SHariprasad Shenai return 1; 126001b69614SHariprasad Shenai 126101b69614SHariprasad Shenai default: 126201b69614SHariprasad Shenai return 0; 126301b69614SHariprasad Shenai } 126401b69614SHariprasad Shenai } 126501b69614SHariprasad Shenai 1266f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1267f7917c00SJeff Kirsher { 1268f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1269f7917c00SJeff Kirsher } 1270f7917c00SJeff Kirsher 1271f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1272f7917c00SJeff Kirsher unsigned int us) 1273f7917c00SJeff Kirsher { 1274f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1275f7917c00SJeff Kirsher } 1276f7917c00SJeff Kirsher 127752367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 127852367a76SVipul Pandya unsigned int ticks) 127952367a76SVipul Pandya { 128052367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 128152367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 128252367a76SVipul Pandya adapter->params.vpd.cclk); 128352367a76SVipul Pandya } 128452367a76SVipul Pandya 1285f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1286f7917c00SJeff Kirsher u32 val); 1287f7917c00SJeff Kirsher 128801b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 128901b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1290f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1291f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1292f7917c00SJeff Kirsher 129301b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 129401b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 129501b69614SHariprasad Shenai int timeout) 129601b69614SHariprasad Shenai { 129701b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 129801b69614SHariprasad Shenai timeout); 129901b69614SHariprasad Shenai } 130001b69614SHariprasad Shenai 1301f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1302f7917c00SJeff Kirsher int size, void *rpl) 1303f7917c00SJeff Kirsher { 1304f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1305f7917c00SJeff Kirsher } 1306f7917c00SJeff Kirsher 1307f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1308f7917c00SJeff Kirsher int size, void *rpl) 1309f7917c00SJeff Kirsher { 1310f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1311f7917c00SJeff Kirsher } 1312f7917c00SJeff Kirsher 1313fc08a01aSHariprasad Shenai /** 1314fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1315fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1316fc08a01aSHariprasad Shenai * 1317fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1318fc08a01aSHariprasad Shenai * (hash) address matching. 1319fc08a01aSHariprasad Shenai */ 1320fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1321fc08a01aSHariprasad Shenai { 1322fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1323fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1324fc08a01aSHariprasad Shenai 1325fc08a01aSHariprasad Shenai a ^= b; 1326fc08a01aSHariprasad Shenai a ^= (a >> 12); 1327fc08a01aSHariprasad Shenai a ^= (a >> 6); 1328fc08a01aSHariprasad Shenai return a & 0x3f; 1329fc08a01aSHariprasad Shenai } 1330fc08a01aSHariprasad Shenai 133194cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 133294cdb8bbSHariprasad Shenai unsigned int cnt); 133394cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 133494cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 133594cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 133694cdb8bbSHariprasad Shenai { 133794cdb8bbSHariprasad Shenai q->adap = adap; 133894cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 133994cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 134094cdb8bbSHariprasad Shenai q->size = size; 134194cdb8bbSHariprasad Shenai } 134294cdb8bbSHariprasad Shenai 134313ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 134413ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 134513ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1346f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1347f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1348f2b7e78dSVipul Pandya unsigned int start_idx); 13490abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1350f2b7e78dSVipul Pandya 1351f2b7e78dSVipul Pandya struct fw_filter_wr; 1352f2b7e78dSVipul Pandya 1353f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1354f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1355f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1356f7917c00SJeff Kirsher 13578203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 13584036da90SHariprasad Shenai int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1359f7917c00SJeff Kirsher struct link_config *lc); 1360f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1361fc5ab020SHariprasad Shenai 1362b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1363b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1364b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1365b562fc37SHariprasad Shenai 1366fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1367fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1368fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1369f01aa633SHariprasad Shenai void *buf, int dir); 1370fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1371fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1372fc5ab020SHariprasad Shenai { 1373fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1374fc5ab020SHariprasad Shenai } 1375fc5ab020SHariprasad Shenai 1376812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1377812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1378812034f1SHariprasad Shenai 1379f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1380098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1381098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 138249216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 138349216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1384f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 138501b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 138601b69614SHariprasad Shenai int win, spinlock_t *lock, 138701b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 138801b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 138901b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 139049216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 139122c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 139222c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1393acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1394636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1395a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 139616e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 13970de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 139816e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1399ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 140016e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 140116e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 140216e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1403f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 14043be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1405e85c9a7aSHariprasad Shenai 1406e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1407b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1408e85c9a7aSHariprasad Shenai unsigned int qid, 1409e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 141066cf188eSHariprasad S int user, 1411e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1412e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1413e85c9a7aSHariprasad Shenai 1414dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1415dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1416ae469b68SHariprasad Shenai 1417ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1418e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 1419dcf7b6f5SKumar Sanghvi int t4_init_tp_params(struct adapter *adap); 1420dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1421c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1422c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1423c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1424f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1425f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1426f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1427f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1428f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1429f7917c00SJeff Kirsher unsigned int flags); 1430c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1431c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1432688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 1433688ea5feSHariprasad Shenai void t4_read_rss_key(struct adapter *adapter, u32 *key); 1434688ea5feSHariprasad Shenai void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1435688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1436688ea5feSHariprasad Shenai u32 *valp); 1437688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1438688ea5feSHariprasad Shenai u32 *vfl, u32 *vfh); 1439688ea5feSHariprasad Shenai u32 t4_read_rss_pf_map(struct adapter *adapter); 1440688ea5feSHariprasad Shenai u32 t4_read_rss_pf_mask(struct adapter *adapter); 1441688ea5feSHariprasad Shenai 1442193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1443193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1444b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1445b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1446e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1447e5f0e43bSHariprasad Shenai size_t n); 1448c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1449c778af7dSHariprasad Shenai size_t n); 1450f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1451f1ff24aaSHariprasad Shenai unsigned int *valp); 1452f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1453f1ff24aaSHariprasad Shenai const unsigned int *valp); 1454f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 145519689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 145619689609SHariprasad Shenai unsigned int *pif_req_wrptr, 145719689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 145826fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 145974b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 146072aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1461f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1462a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1463a4cfd929SHariprasad Shenai struct port_stats *stats, 1464a4cfd929SHariprasad Shenai struct port_stats *offset); 146565046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1466f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1467bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1468636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1469636f9d37SVipul Pandya unsigned int mask, unsigned int val); 14702d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1471a4cfd929SHariprasad Shenai void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1472a6222975SHariprasad Shenai void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1473a4cfd929SHariprasad Shenai void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1474a4cfd929SHariprasad Shenai void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1475f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1476f7917c00SJeff Kirsher struct tp_tcp_stats *v6); 1477a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1478a6222975SHariprasad Shenai struct tp_fcoe_stats *st); 1479f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1480f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1481f7917c00SJeff Kirsher 1482797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1483797ff0f5SHariprasad Shenai 14847864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1485f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1486f2b7e78dSVipul Pandya 1487f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1488f7917c00SJeff Kirsher const u8 *addr); 1489f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1490f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1491f7917c00SJeff Kirsher 1492f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1493f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1494f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1495f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1496f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1497636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1498636f9d37SVipul Pandya unsigned int cache_line_size); 1499636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1500f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1501f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1502f7917c00SJeff Kirsher u32 *val); 15038f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 15048f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 15058f46d467SArjun Vynipadath u32 *val); 150601b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1507f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 15088f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 150901b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1510688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1511688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 151201b69614SHariprasad Shenai const u32 *val, int timeout); 151301b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 151401b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1515688848b1SAnish Bhatt const u32 *val); 1516f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1517f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1518f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1519f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1520f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1521f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1522f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1523f7917c00SJeff Kirsher unsigned int *rss_size); 15244f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 15254f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 15264f3a0fcfSHariprasad Shenai unsigned int viid); 1527f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1528f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1529f7917c00SJeff Kirsher bool sleep_ok); 1530f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1531f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1532f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1533fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1534fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1535fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1536f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1537f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1538f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1539f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1540688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1541688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1542f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1543f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1544f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1545f7917c00SJeff Kirsher unsigned int nblinks); 1546f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1547f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1548f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1549f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1550ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1551ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1552ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1553f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1554f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1555f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1556f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1557f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1558f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1559f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1560f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1561f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 15625d700ecbSHariprasad Shenai int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 156323853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 15642061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1565f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1566881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1567881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 15688e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 15698e3d04fdSHariprasad Shenai int filter_index, int enable); 15708e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 15718e3d04fdSHariprasad Shenai int filter_index, int *enabled); 15728caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 15738caa1e84SVipul Pandya u32 addr, u32 val); 1574b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1575b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1576b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 157768bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1578a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1579a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1580a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1581a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1582a3bfb617SHariprasad Shenai int hz, int ticks); 1583858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1584858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 15850fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 15860fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 15870fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 15880fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 158994cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1590ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1591ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1592ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1593f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1594