1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 505e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 51a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 52a4569504SAtul Gupta #include <linux/ptp_classify.h> 53f7917c00SJeff Kirsher #include <asm/io.h> 5427999805SHariprasad S #include "t4_chip_type.h" 55f7917c00SJeff Kirsher #include "cxgb4_uld.h" 56f7917c00SJeff Kirsher 573069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 5894cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 5994cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 603069ee9bSVipul Pandya 61a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 62a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 63a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 64a6ec572bSAtul Gupta */ 65a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 66a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 67a6ec572bSAtul Gupta 68f7917c00SJeff Kirsher enum { 69f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 70f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 71f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 72f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 73a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 74098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 75f7917c00SJeff Kirsher }; 76f7917c00SJeff Kirsher 77f7917c00SJeff Kirsher enum { 78812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 79812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 80812034f1SHariprasad Shenai }; 81812034f1SHariprasad Shenai 82812034f1SHariprasad Shenai enum { 83f7917c00SJeff Kirsher MEM_EDC0, 84f7917c00SJeff Kirsher MEM_EDC1, 852422d9a3SSantosh Rastapur MEM_MC, 862422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 874db0401fSRahul Lakkireddy MEM_MC1, 884db0401fSRahul Lakkireddy MEM_HMA, 89f7917c00SJeff Kirsher }; 90f7917c00SJeff Kirsher 913069ee9bSVipul Pandya enum { 923eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 933eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 943069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 953069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 962422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 973eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 983eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 990abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 1000abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1013069ee9bSVipul Pandya }; 1023069ee9bSVipul Pandya 103f7917c00SJeff Kirsher enum dev_master { 104f7917c00SJeff Kirsher MASTER_CANT, 105f7917c00SJeff Kirsher MASTER_MAY, 106f7917c00SJeff Kirsher MASTER_MUST 107f7917c00SJeff Kirsher }; 108f7917c00SJeff Kirsher 109f7917c00SJeff Kirsher enum dev_state { 110f7917c00SJeff Kirsher DEV_STATE_UNINIT, 111f7917c00SJeff Kirsher DEV_STATE_INIT, 112f7917c00SJeff Kirsher DEV_STATE_ERR 113f7917c00SJeff Kirsher }; 114f7917c00SJeff Kirsher 115c3168cabSGanesh Goudar enum cc_pause { 116f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 117f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 118f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 119f7917c00SJeff Kirsher }; 120f7917c00SJeff Kirsher 121c3168cabSGanesh Goudar enum cc_fec { 1223bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1233bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1243bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1253bb4858fSGanesh Goudar }; 1263bb4858fSGanesh Goudar 127f7917c00SJeff Kirsher struct port_stats { 128f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 129f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 130f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 131f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 132f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 133f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 134f7917c00SJeff Kirsher 135f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 136f7917c00SJeff Kirsher u64 tx_frames_65_127; 137f7917c00SJeff Kirsher u64 tx_frames_128_255; 138f7917c00SJeff Kirsher u64 tx_frames_256_511; 139f7917c00SJeff Kirsher u64 tx_frames_512_1023; 140f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 141f7917c00SJeff Kirsher u64 tx_frames_1519_max; 142f7917c00SJeff Kirsher 143f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 144f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 145f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 146f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 147f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 148f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 149f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 150f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 151f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 152f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 153f7917c00SJeff Kirsher 154f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 155f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 156f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 157f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 158f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 159f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 160f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 161f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 162f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 163f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 164f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 165f7917c00SJeff Kirsher 166f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 167f7917c00SJeff Kirsher u64 rx_frames_65_127; 168f7917c00SJeff Kirsher u64 rx_frames_128_255; 169f7917c00SJeff Kirsher u64 rx_frames_256_511; 170f7917c00SJeff Kirsher u64 rx_frames_512_1023; 171f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 172f7917c00SJeff Kirsher u64 rx_frames_1519_max; 173f7917c00SJeff Kirsher 174f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 175f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 176f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 177f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 178f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 179f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 180f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 181f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 182f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 183f7917c00SJeff Kirsher 184f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 185f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 186f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 187f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 188f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 189f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 190f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 191f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 192f7917c00SJeff Kirsher }; 193f7917c00SJeff Kirsher 194f7917c00SJeff Kirsher struct lb_port_stats { 195f7917c00SJeff Kirsher u64 octets; 196f7917c00SJeff Kirsher u64 frames; 197f7917c00SJeff Kirsher u64 bcast_frames; 198f7917c00SJeff Kirsher u64 mcast_frames; 199f7917c00SJeff Kirsher u64 ucast_frames; 200f7917c00SJeff Kirsher u64 error_frames; 201f7917c00SJeff Kirsher 202f7917c00SJeff Kirsher u64 frames_64; 203f7917c00SJeff Kirsher u64 frames_65_127; 204f7917c00SJeff Kirsher u64 frames_128_255; 205f7917c00SJeff Kirsher u64 frames_256_511; 206f7917c00SJeff Kirsher u64 frames_512_1023; 207f7917c00SJeff Kirsher u64 frames_1024_1518; 208f7917c00SJeff Kirsher u64 frames_1519_max; 209f7917c00SJeff Kirsher 210f7917c00SJeff Kirsher u64 drop; 211f7917c00SJeff Kirsher 212f7917c00SJeff Kirsher u64 ovflow0; 213f7917c00SJeff Kirsher u64 ovflow1; 214f7917c00SJeff Kirsher u64 ovflow2; 215f7917c00SJeff Kirsher u64 ovflow3; 216f7917c00SJeff Kirsher u64 trunc0; 217f7917c00SJeff Kirsher u64 trunc1; 218f7917c00SJeff Kirsher u64 trunc2; 219f7917c00SJeff Kirsher u64 trunc3; 220f7917c00SJeff Kirsher }; 221f7917c00SJeff Kirsher 222f7917c00SJeff Kirsher struct tp_tcp_stats { 223a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 224a4cfd929SHariprasad Shenai u64 tcp_in_segs; 225a4cfd929SHariprasad Shenai u64 tcp_out_segs; 226a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 227a4cfd929SHariprasad Shenai }; 228a4cfd929SHariprasad Shenai 229a4cfd929SHariprasad Shenai struct tp_usm_stats { 230a4cfd929SHariprasad Shenai u32 frames; 231a4cfd929SHariprasad Shenai u32 drops; 232a4cfd929SHariprasad Shenai u64 octets; 233f7917c00SJeff Kirsher }; 234f7917c00SJeff Kirsher 235a6222975SHariprasad Shenai struct tp_fcoe_stats { 236a6222975SHariprasad Shenai u32 frames_ddp; 237a6222975SHariprasad Shenai u32 frames_drop; 238a6222975SHariprasad Shenai u64 octets_ddp; 239f7917c00SJeff Kirsher }; 240f7917c00SJeff Kirsher 241f7917c00SJeff Kirsher struct tp_err_stats { 242a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 243a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 244a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 245a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 246a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 247a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 248a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 249a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 250a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 251a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 252a4cfd929SHariprasad Shenai }; 253a4cfd929SHariprasad Shenai 254a6222975SHariprasad Shenai struct tp_cpl_stats { 255a6222975SHariprasad Shenai u32 req[4]; 256a6222975SHariprasad Shenai u32 rsp[4]; 257a6222975SHariprasad Shenai }; 258a6222975SHariprasad Shenai 259a4cfd929SHariprasad Shenai struct tp_rdma_stats { 260a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 261a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 262f7917c00SJeff Kirsher }; 263f7917c00SJeff Kirsher 264e85c9a7aSHariprasad Shenai struct sge_params { 265e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 266e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 267e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 268e85c9a7aSHariprasad Shenai }; 269e85c9a7aSHariprasad Shenai 270f7917c00SJeff Kirsher struct tp_params { 271f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2722d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 273dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 274dca4faebSVipul Pandya /* channel map */ 275636f9d37SVipul Pandya 276636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 277636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 278dcf7b6f5SKumar Sanghvi 279dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 280dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 281dcf7b6f5SKumar Sanghvi 2828eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2838eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2848eb9f2f9SArjun V */ 2858eb9f2f9SArjun V int rx_pkt_encap; 2868eb9f2f9SArjun V 287dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 288dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 289dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 290dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 291dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 292dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 293dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 294dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 295dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 296dcf7b6f5SKumar Sanghvi * present. 297dcf7b6f5SKumar Sanghvi */ 2980ba9a3b6SKumar Sanghvi int fcoe_shift; 299dcf7b6f5SKumar Sanghvi int port_shift; 3000ba9a3b6SKumar Sanghvi int vnic_shift; 3010ba9a3b6SKumar Sanghvi int vlan_shift; 3020ba9a3b6SKumar Sanghvi int tos_shift; 303dcf7b6f5SKumar Sanghvi int protocol_shift; 3040ba9a3b6SKumar Sanghvi int ethertype_shift; 3050ba9a3b6SKumar Sanghvi int macmatch_shift; 3060ba9a3b6SKumar Sanghvi int matchtype_shift; 3070ba9a3b6SKumar Sanghvi int frag_shift; 3080ba9a3b6SKumar Sanghvi 3090ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 310f7917c00SJeff Kirsher }; 311f7917c00SJeff Kirsher 312f7917c00SJeff Kirsher struct vpd_params { 313f7917c00SJeff Kirsher unsigned int cclk; 314f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 315f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 316f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 317a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 318098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 319f7917c00SJeff Kirsher }; 320f7917c00SJeff Kirsher 321f7917c00SJeff Kirsher struct pci_params { 322baf50868SGanesh Goudar unsigned int vpd_cap_addr; 323f7917c00SJeff Kirsher unsigned char speed; 324f7917c00SJeff Kirsher unsigned char width; 325f7917c00SJeff Kirsher }; 326f7917c00SJeff Kirsher 32749aa284fSHariprasad Shenai struct devlog_params { 32849aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 32949aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 33049aa284fSHariprasad Shenai u32 size; /* size of log */ 33149aa284fSHariprasad Shenai }; 33249aa284fSHariprasad Shenai 3333ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3343ccc6cf7SHariprasad Shenai struct arch_specific_params { 3353ccc6cf7SHariprasad Shenai u8 nchan; 33644588560SHariprasad Shenai u8 pm_stats_cnt; 3372216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3383ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3393ccc6cf7SHariprasad Shenai u16 vfcount; 3403ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3413ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3423ccc6cf7SHariprasad Shenai }; 3433ccc6cf7SHariprasad Shenai 344f7917c00SJeff Kirsher struct adapter_params { 345e85c9a7aSHariprasad Shenai struct sge_params sge; 346f7917c00SJeff Kirsher struct tp_params tp; 347f7917c00SJeff Kirsher struct vpd_params vpd; 348f7917c00SJeff Kirsher struct pci_params pci; 34949aa284fSHariprasad Shenai struct devlog_params devlog; 35049aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 351f7917c00SJeff Kirsher 352f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 353f1ff24aaSHariprasad Shenai 354f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 355f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 356f7917c00SJeff Kirsher 357760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3580de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 359760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3600de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 361760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 362760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 363f7917c00SJeff Kirsher u8 api_vers[7]; 364f7917c00SJeff Kirsher 365f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 366f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 367f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 368f7917c00SJeff Kirsher 369f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 370f7917c00SJeff Kirsher unsigned char portvec; 371d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3723ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 373f7917c00SJeff Kirsher unsigned char offload; 37494cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 375f7917c00SJeff Kirsher 3769a4da2cdSVipul Pandya unsigned char bypass; 3775c31254eSKumar Sanghvi unsigned char hash_filter; 3789a4da2cdSVipul Pandya 379f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3801ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3814c2c5763SHariprasad Shenai 382b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 3834c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3844c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 385086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 386c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 3870ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 3888f46d467SArjun Vynipadath 3898f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 3908f46d467SArjun Vynipadath * used by the Port 3918f46d467SArjun Vynipadath */ 3928f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 393f7917c00SJeff Kirsher }; 394f7917c00SJeff Kirsher 395a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 396a3bfb617SHariprasad Shenai * and possible hangs. 397a3bfb617SHariprasad Shenai */ 398a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 399a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 400a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 401a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 402a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 403a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 404a3bfb617SHariprasad Shenai }; 405a3bfb617SHariprasad Shenai 4067f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 4077f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 4087f080c3fSHariprasad Shenai * error returns. 4097f080c3fSHariprasad Shenai */ 4107f080c3fSHariprasad Shenai struct mbox_cmd { 4117f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 4127f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 4137f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 4147f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 4157f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 4167f080c3fSHariprasad Shenai }; 4177f080c3fSHariprasad Shenai 4187f080c3fSHariprasad Shenai struct mbox_cmd_log { 4197f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4207f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4217f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4227f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4237f080c3fSHariprasad Shenai }; 4247f080c3fSHariprasad Shenai 4257f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4267f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4277f080c3fSHariprasad Shenai */ 4287f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4297f080c3fSHariprasad Shenai unsigned int entry_idx) 4307f080c3fSHariprasad Shenai { 4317f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4327f080c3fSHariprasad Shenai } 4337f080c3fSHariprasad Shenai 43416e47624SHariprasad Shenai #include "t4fw_api.h" 43516e47624SHariprasad Shenai 43616e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 437b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 438b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 439b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 440b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 44116e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 44216e47624SHariprasad Shenai 44316e47624SHariprasad Shenai struct fw_info { 44416e47624SHariprasad Shenai u8 chip; 44516e47624SHariprasad Shenai char *fs_name; 44616e47624SHariprasad Shenai char *fw_mod_name; 44716e47624SHariprasad Shenai struct fw_hdr fw_hdr; 44816e47624SHariprasad Shenai }; 44916e47624SHariprasad Shenai 450f7917c00SJeff Kirsher struct trace_params { 451f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 452f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 453f7917c00SJeff Kirsher unsigned short snap_len; 454f7917c00SJeff Kirsher unsigned short min_len; 455f7917c00SJeff Kirsher unsigned char skip_ofst; 456f7917c00SJeff Kirsher unsigned char skip_len; 457f7917c00SJeff Kirsher unsigned char invert; 458f7917c00SJeff Kirsher unsigned char port; 459f7917c00SJeff Kirsher }; 460f7917c00SJeff Kirsher 461c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 462c3168cabSGanesh Goudar 463c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 464c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 465c3168cabSGanesh Goudar 466c3168cabSGanesh Goudar enum fw_caps { 467c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 468c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 469c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 470c3168cabSGanesh Goudar }; 471c3168cabSGanesh Goudar 472f7917c00SJeff Kirsher struct link_config { 473c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 474c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 475c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 476c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 477c3168cabSGanesh Goudar 478c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 479c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 480c3168cabSGanesh Goudar 481c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 482c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 483c3168cabSGanesh Goudar 484c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 485c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 486c3168cabSGanesh Goudar 487f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 488c3168cabSGanesh Goudar 489f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 490ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 491f7917c00SJeff Kirsher }; 492f7917c00SJeff Kirsher 493e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 494f7917c00SJeff Kirsher 495f7917c00SJeff Kirsher enum { 496f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 497f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 498f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 499f7917c00SJeff Kirsher }; 500f7917c00SJeff Kirsher 501f7917c00SJeff Kirsher enum { 502812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 503812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 504812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 505812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 506812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 507812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 508812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 509812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 510812034f1SHariprasad Shenai }; 511812034f1SHariprasad Shenai 512812034f1SHariprasad Shenai enum { 513cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 514cf38be6dSHariprasad Shenai /* forwarded interrupts */ 5150fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 516f7917c00SJeff Kirsher }; 517f7917c00SJeff Kirsher 518f7917c00SJeff Kirsher struct adapter; 519f7917c00SJeff Kirsher struct sge_rspq; 520f7917c00SJeff Kirsher 521688848b1SAnish Bhatt #include "cxgb4_dcb.h" 522688848b1SAnish Bhatt 52376fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 52476fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 52576fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 52676fed8a9SVarun Prakash 527f7917c00SJeff Kirsher struct port_info { 528f7917c00SJeff Kirsher struct adapter *adapter; 529f7917c00SJeff Kirsher u16 viid; 530f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 531f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 532f7917c00SJeff Kirsher s8 mdio_addr; 53340e9de4bSHariprasad Shenai enum fw_port_type port_type; 534f7917c00SJeff Kirsher u8 mod_type; 535f7917c00SJeff Kirsher u8 port_id; 536f7917c00SJeff Kirsher u8 tx_chan; 537f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 538f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 539f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 540f7917c00SJeff Kirsher u8 rss_mode; 541f7917c00SJeff Kirsher struct link_config link_cfg; 542f7917c00SJeff Kirsher u16 *rss; 543a4cfd929SHariprasad Shenai struct port_stats stats_base; 544688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 545688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 546688848b1SAnish Bhatt #endif 54776fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 54876fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 54976fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5505e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5515e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 552a4569504SAtul Gupta bool ptp_enable; 553b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 554f7917c00SJeff Kirsher }; 555f7917c00SJeff Kirsher 556f7917c00SJeff Kirsher struct dentry; 557f7917c00SJeff Kirsher struct work_struct; 558f7917c00SJeff Kirsher 559f7917c00SJeff Kirsher enum { /* adapter flags */ 560f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 561144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 562144be3d9SGavin Shan USING_MSI = (1 << 2), 563144be3d9SGavin Shan USING_MSIX = (1 << 3), 564f7917c00SJeff Kirsher FW_OK = (1 << 4), 56513ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 56652367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 56752367a76SVipul Pandya MASTER_PF = (1 << 7), 56852367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 569b0ba9d5fSCasey Leedom ROOT_NO_RELAXED_ORDERING = (1 << 10), 570e1f6198eSGanesh Goudar SHUTTING_DOWN = (1 << 11), 571f7917c00SJeff Kirsher }; 572f7917c00SJeff Kirsher 57394cdb8bbSHariprasad Shenai enum { 57494cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 575a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 57694cdb8bbSHariprasad Shenai }; 57794cdb8bbSHariprasad Shenai 578f7917c00SJeff Kirsher struct rx_sw_desc; 579f7917c00SJeff Kirsher 580f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 581f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 582f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 583f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 584f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 585f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 586f7917c00SJeff Kirsher unsigned long large_alloc_failed; 58770055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 58870055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 589f7917c00SJeff Kirsher unsigned long starving; 590f7917c00SJeff Kirsher /* RO fields */ 591f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 592f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 593f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 594f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 595f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 596df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 597df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 598f7917c00SJeff Kirsher }; 599f7917c00SJeff Kirsher 600f7917c00SJeff Kirsher /* A packet gather list */ 601f7917c00SJeff Kirsher struct pkt_gl { 6025e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 603e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 604f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 605f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 606f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 607f7917c00SJeff Kirsher }; 608f7917c00SJeff Kirsher 609f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 610f7917c00SJeff Kirsher const struct pkt_gl *gl); 6112337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 6122337ba42SVarun Prakash /* LRO related declarations for ULD */ 6132337ba42SVarun Prakash struct t4_lro_mgr { 6142337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 6152337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 6162337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 6172337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6182337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6192337ba42SVarun Prakash }; 620f7917c00SJeff Kirsher 621f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 622f7917c00SJeff Kirsher struct napi_struct napi; 623f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 624f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 625f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 626f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 627f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 628e553ec3fSHariprasad Shenai u8 adaptive_rx; 629f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 630f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 631f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 632f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 633f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 634f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 635f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 636f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 637df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 638df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 639f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 640f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 641f7917c00SJeff Kirsher struct adapter *adap; 642f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 643f7917c00SJeff Kirsher rspq_handler_t handler; 6442337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 6452337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 646f7917c00SJeff Kirsher }; 647f7917c00SJeff Kirsher 648f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 649f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 650f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 651f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 652f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 653f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 654f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 655f7917c00SJeff Kirsher }; 656f7917c00SJeff Kirsher 657f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 658f7917c00SJeff Kirsher struct sge_rspq rspq; 659f7917c00SJeff Kirsher struct sge_fl fl; 660f7917c00SJeff Kirsher struct sge_eth_stats stats; 661f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 662f7917c00SJeff Kirsher 663f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 664f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 665f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 666f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 667f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 668f7917c00SJeff Kirsher }; 669f7917c00SJeff Kirsher 670f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 671f7917c00SJeff Kirsher struct sge_rspq rspq; 672f7917c00SJeff Kirsher struct sge_fl fl; 673f7917c00SJeff Kirsher struct sge_ofld_stats stats; 674f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 675f7917c00SJeff Kirsher 676f7917c00SJeff Kirsher struct tx_desc { 677f7917c00SJeff Kirsher __be64 flit[8]; 678f7917c00SJeff Kirsher }; 679f7917c00SJeff Kirsher 680f7917c00SJeff Kirsher struct tx_sw_desc; 681f7917c00SJeff Kirsher 682f7917c00SJeff Kirsher struct sge_txq { 683f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 684ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 685f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 686f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 687f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 688f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 689f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 690f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 691f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 692f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 693f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 694f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 6953069ee9bSVipul Pandya spinlock_t db_lock; 6963069ee9bSVipul Pandya int db_disabled; 6973069ee9bSVipul Pandya unsigned short db_pidx; 69805eb2389SSteve Wise unsigned short db_pidx_inc; 699df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 700df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 701f7917c00SJeff Kirsher }; 702f7917c00SJeff Kirsher 703f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 704f7917c00SJeff Kirsher struct sge_txq q; 705f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 70610b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 70710b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 70810b00466SAnish Bhatt #endif 709f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 710f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 711f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 712f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 713f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 714f7917c00SJeff Kirsher 715ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 716f7917c00SJeff Kirsher struct sge_txq q; 717f7917c00SJeff Kirsher struct adapter *adap; 718f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 719f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 720126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 721f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 722f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 723f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 724f7917c00SJeff Kirsher 725f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 726f7917c00SJeff Kirsher struct sge_txq q; 727f7917c00SJeff Kirsher struct adapter *adap; 728f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 729f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 730f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 731f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 732f7917c00SJeff Kirsher 73394cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 73494cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 73594cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 73694cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 73794cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 73894cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 73994cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 74094cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 74194cdb8bbSHariprasad Shenai }; 74294cdb8bbSHariprasad Shenai 743ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 744ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 745ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 746ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 747ab677ff4SHariprasad Shenai }; 748ab677ff4SHariprasad Shenai 749f7917c00SJeff Kirsher struct sge { 750f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 751a4569504SAtul Gupta struct sge_eth_txq ptptxq; 752f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 753f7917c00SJeff Kirsher 754f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 755f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 75694cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 757ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 758f7917c00SJeff Kirsher 759f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 760f7917c00SJeff Kirsher spinlock_t intrq_lock; 761f7917c00SJeff Kirsher 762f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 763f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 764f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 7650fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 76694cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 767f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 768f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 76952367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 77052367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 77152367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 77252367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 77352367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 7740f4d201fSKumar Sanghvi 775a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 776f7917c00SJeff Kirsher unsigned int egr_start; 7774b8e27a8SHariprasad Shenai unsigned int egr_sz; 778f7917c00SJeff Kirsher unsigned int ingr_start; 7794b8e27a8SHariprasad Shenai unsigned int ingr_sz; 7804b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 7814b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 7824b8e27a8SHariprasad Shenai unsigned long *starving_fl; 7834b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 7845b377d11SHariprasad Shenai unsigned long *blocked_fl; 785f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 786f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 787f7917c00SJeff Kirsher }; 788f7917c00SJeff Kirsher 789f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 7900fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 791f7917c00SJeff Kirsher 792f7917c00SJeff Kirsher struct l2t_data; 793f7917c00SJeff Kirsher 7942422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 7952422d9a3SSantosh Rastapur 7967d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 7977d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 7987d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 7992422d9a3SSantosh Rastapur */ 8007d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 8012422d9a3SSantosh Rastapur 8022422d9a3SSantosh Rastapur #endif 8032422d9a3SSantosh Rastapur 804a4cfd929SHariprasad Shenai struct doorbell_stats { 805a4cfd929SHariprasad Shenai u32 db_drop; 806a4cfd929SHariprasad Shenai u32 db_empty; 807a4cfd929SHariprasad Shenai u32 db_full; 808a4cfd929SHariprasad Shenai }; 809a4cfd929SHariprasad Shenai 810fc08a01aSHariprasad Shenai struct hash_mac_addr { 811fc08a01aSHariprasad Shenai struct list_head list; 812fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 813fc08a01aSHariprasad Shenai }; 814fc08a01aSHariprasad Shenai 81594cdb8bbSHariprasad Shenai struct uld_msix_bmap { 81694cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 81794cdb8bbSHariprasad Shenai unsigned int mapsize; 81894cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 81994cdb8bbSHariprasad Shenai }; 82094cdb8bbSHariprasad Shenai 82194cdb8bbSHariprasad Shenai struct uld_msix_info { 82294cdb8bbSHariprasad Shenai unsigned short vec; 82394cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 8240fbc81b3SHariprasad Shenai unsigned int idx; 82594cdb8bbSHariprasad Shenai }; 82694cdb8bbSHariprasad Shenai 827661dbeb9SHariprasad Shenai struct vf_info { 828661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 8298ea4fae9SGanesh Goudar unsigned int tx_rate; 830661dbeb9SHariprasad Shenai bool pf_set_mac; 8319d5fd927SGanesh Goudar u16 vlan; 832661dbeb9SHariprasad Shenai }; 833661dbeb9SHariprasad Shenai 8348b4e6b3cSArjun Vynipadath enum { 8358b4e6b3cSArjun Vynipadath HMA_DMA_MAPPED_FLAG = 1 8368b4e6b3cSArjun Vynipadath }; 8378b4e6b3cSArjun Vynipadath 8388b4e6b3cSArjun Vynipadath struct hma_data { 8398b4e6b3cSArjun Vynipadath unsigned char flags; 8408b4e6b3cSArjun Vynipadath struct sg_table *sgt; 8418b4e6b3cSArjun Vynipadath dma_addr_t *phy_addr; /* physical address of the page */ 8428b4e6b3cSArjun Vynipadath }; 8438b4e6b3cSArjun Vynipadath 8444055ae5eSHariprasad Shenai struct mbox_list { 8454055ae5eSHariprasad Shenai struct list_head list; 8464055ae5eSHariprasad Shenai }; 8474055ae5eSHariprasad Shenai 848846eac3fSGanesh Goudar struct mps_encap_entry { 849846eac3fSGanesh Goudar atomic_t refcnt; 850846eac3fSGanesh Goudar }; 851846eac3fSGanesh Goudar 852f7917c00SJeff Kirsher struct adapter { 853f7917c00SJeff Kirsher void __iomem *regs; 85422adfe0aSSantosh Rastapur void __iomem *bar2; 8550abfd152SHariprasad Shenai u32 t4_bar0; 856f7917c00SJeff Kirsher struct pci_dev *pdev; 857f7917c00SJeff Kirsher struct device *pdev_dev; 8580de72738SHariprasad Shenai const char *name; 8593069ee9bSVipul Pandya unsigned int mbox; 860b2612722SHariprasad Shenai unsigned int pf; 861f7917c00SJeff Kirsher unsigned int flags; 862e7b48a32SHariprasad Shenai unsigned int adap_idx; 8632422d9a3SSantosh Rastapur enum chip_type chip; 864f7917c00SJeff Kirsher 865f7917c00SJeff Kirsher int msg_enable; 866846eac3fSGanesh Goudar __be16 vxlan_port; 867846eac3fSGanesh Goudar u8 vxlan_port_cnt; 868c746fc0eSGanesh Goudar __be16 geneve_port; 869c746fc0eSGanesh Goudar u8 geneve_port_cnt; 870f7917c00SJeff Kirsher 871f7917c00SJeff Kirsher struct adapter_params params; 872f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 873f7917c00SJeff Kirsher unsigned int swintr; 874f7917c00SJeff Kirsher 875f7917c00SJeff Kirsher struct { 876f7917c00SJeff Kirsher unsigned short vec; 877f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 878f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 87994cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 88094cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 8810fbc81b3SHariprasad Shenai int msi_idx; 882f7917c00SJeff Kirsher 883a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 884f7917c00SJeff Kirsher struct sge sge; 885f7917c00SJeff Kirsher 886f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 887f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 888f7917c00SJeff Kirsher 889661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 890661dbeb9SHariprasad Shenai u8 num_vfs; 891661dbeb9SHariprasad Shenai 892793dad94SVipul Pandya u32 filter_mode; 893636f9d37SVipul Pandya unsigned int l2t_start; 894636f9d37SVipul Pandya unsigned int l2t_end; 895f7917c00SJeff Kirsher struct l2t_data *l2t; 896b5a02f50SAnish Bhatt unsigned int clipt_start; 897b5a02f50SAnish Bhatt unsigned int clipt_end; 898b5a02f50SAnish Bhatt struct clip_tbl *clipt; 899846eac3fSGanesh Goudar unsigned int rawf_start; 900846eac3fSGanesh Goudar unsigned int rawf_cnt; 9013bdb376eSKumar Sanghvi struct smt_data *smt; 902846eac3fSGanesh Goudar struct mps_encap_entry *mps_encap; 9030fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 904f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 90594cdb8bbSHariprasad Shenai unsigned int num_uld; 9060fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 907f7917c00SJeff Kirsher struct list_head list_node; 90801bcca68SVipul Pandya struct list_head rcu_node; 909fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 910f7917c00SJeff Kirsher 9117714cb9eSVarun Prakash void *iscsi_ppm; 9127714cb9eSVarun Prakash 913f7917c00SJeff Kirsher struct tid_info tids; 914f7917c00SJeff Kirsher void **tid_release_head; 915f7917c00SJeff Kirsher spinlock_t tid_release_lock; 91629aaee65SAnish Bhatt struct workqueue_struct *workq; 917f7917c00SJeff Kirsher struct work_struct tid_release_task; 918881806bcSVipul Pandya struct work_struct db_full_task; 919881806bcSVipul Pandya struct work_struct db_drop_task; 920f7917c00SJeff Kirsher bool tid_release_task_busy; 921f7917c00SJeff Kirsher 9224055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 9234055ae5eSHariprasad Shenai spinlock_t mbox_lock; 9244055ae5eSHariprasad Shenai struct mbox_list mlist; 9254055ae5eSHariprasad Shenai 9267f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 9277f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 9287f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 9297f080c3fSHariprasad Shenai 9300fbc81b3SHariprasad Shenai struct mutex uld_mutex; 9310fbc81b3SHariprasad Shenai 932f7917c00SJeff Kirsher struct dentry *debugfs_root; 933621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 934621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 9358e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 9368e3d04fdSHariprasad Shenai * used for all 4 filters. 9378e3d04fdSHariprasad Shenai */ 938f7917c00SJeff Kirsher 939a4569504SAtul Gupta struct ptp_clock *ptp_clock; 940a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 941a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 942a4569504SAtul Gupta /* ptp lock */ 943a4569504SAtul Gupta spinlock_t ptp_lock; 944f7917c00SJeff Kirsher spinlock_t stats_lock; 945fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 946d8931847SRahul Lakkireddy 947d8931847SRahul Lakkireddy /* TC u32 offload */ 948d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 949ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 95062488e4bSKumar Sanghvi 95162488e4bSKumar Sanghvi /* TC flower offload */ 95279e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 95379e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 954e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 95579e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 956ad75b7d3SRahul Lakkireddy 957ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 958ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 9598b4e6b3cSArjun Vynipadath 9608b4e6b3cSArjun Vynipadath /* HMA */ 9618b4e6b3cSArjun Vynipadath struct hma_data hma; 962f7917c00SJeff Kirsher }; 963f7917c00SJeff Kirsher 964b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 965b72a32daSRahul Lakkireddy * programmed with various parameters. 966b72a32daSRahul Lakkireddy */ 967b72a32daSRahul Lakkireddy struct ch_sched_params { 968b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 969b72a32daSRahul Lakkireddy union { 970b72a32daSRahul Lakkireddy struct { 971b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 972b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 973b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 974b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 975b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 976b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 977b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 978b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 979b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 980b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 981b72a32daSRahul Lakkireddy } params; 982b72a32daSRahul Lakkireddy } u; 983b72a32daSRahul Lakkireddy }; 984b72a32daSRahul Lakkireddy 98510a2604eSRahul Lakkireddy enum { 98610a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 98710a2604eSRahul Lakkireddy }; 98810a2604eSRahul Lakkireddy 98910a2604eSRahul Lakkireddy enum { 99010a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 99110a2604eSRahul Lakkireddy }; 99210a2604eSRahul Lakkireddy 99310a2604eSRahul Lakkireddy enum { 99410a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 99510a2604eSRahul Lakkireddy }; 99610a2604eSRahul Lakkireddy 99710a2604eSRahul Lakkireddy enum { 99810a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 99910a2604eSRahul Lakkireddy }; 100010a2604eSRahul Lakkireddy 100110a2604eSRahul Lakkireddy enum { 100210a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 100310a2604eSRahul Lakkireddy }; 100410a2604eSRahul Lakkireddy 1005a6ec572bSAtul Gupta struct tx_sw_desc { /* SW state per Tx descriptor */ 1006a6ec572bSAtul Gupta struct sk_buff *skb; 1007a6ec572bSAtul Gupta struct ulptx_sgl *sgl; 1008a6ec572bSAtul Gupta }; 1009a6ec572bSAtul Gupta 10106cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 10116cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 10126cede1f1SRahul Lakkireddy */ 10136cede1f1SRahul Lakkireddy struct ch_sched_queue { 10146cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 10156cede1f1SRahul Lakkireddy s8 class; /* class index */ 10166cede1f1SRahul Lakkireddy }; 10176cede1f1SRahul Lakkireddy 1018f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 1019f2b7e78dSVipul Pandya */ 1020f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 1021f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 1022f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 1023f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 1024f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 1025f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1026f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1027f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1028f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1029f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1030f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1031f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 1032f2b7e78dSVipul Pandya 1033f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1034f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1035f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1036f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1037f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1038f2b7e78dSVipul Pandya * matching rules are true. 1039f2b7e78dSVipul Pandya * 1040f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1041f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1042f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1043f2b7e78dSVipul Pandya * MPS match type) ... 1044f2b7e78dSVipul Pandya * 1045f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1046f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1047f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1048f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1049f2b7e78dSVipul Pandya */ 1050f2b7e78dSVipul Pandya struct ch_filter_tuple { 1051f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1052f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1053f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1054f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1055f2b7e78dSVipul Pandya * set of fields. 1056f2b7e78dSVipul Pandya */ 1057f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1058f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1059f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1060f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1061f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 1062f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1063f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1064f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1065f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1066f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1067f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1068f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1069f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1070f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1071f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1072f2b7e78dSVipul Pandya 1073f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1074f2b7e78dSVipul Pandya * available for field rules. 1075f2b7e78dSVipul Pandya */ 1076f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1077f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1078f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1079f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1080f2b7e78dSVipul Pandya }; 1081f2b7e78dSVipul Pandya 1082f2b7e78dSVipul Pandya /* A filter ioctl command. 1083f2b7e78dSVipul Pandya */ 1084f2b7e78dSVipul Pandya struct ch_filter_specification { 1085f2b7e78dSVipul Pandya /* Administrative fields for filter. 1086f2b7e78dSVipul Pandya */ 1087f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1088f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1089f2b7e78dSVipul Pandya 1090f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1091f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1092f2b7e78dSVipul Pandya */ 1093f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 109412b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1095f2b7e78dSVipul Pandya 1096f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1097f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1098f2b7e78dSVipul Pandya * out as egress packets. 1099f2b7e78dSVipul Pandya */ 1100f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1101f2b7e78dSVipul Pandya 1102f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1103f2b7e78dSVipul Pandya 1104f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1105f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1106f2b7e78dSVipul Pandya 1107f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1108f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1109f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1110f2b7e78dSVipul Pandya 1111f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1112f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1113f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1114f2b7e78dSVipul Pandya */ 1115f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1116f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1117f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1118f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 11190ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1120f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1121f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1122f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1123f2b7e78dSVipul Pandya 11240ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 11250ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 11260ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 11270ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 11280ff90994SKumar Sanghvi 11290ff90994SKumar Sanghvi /* reservation for future additions */ 11300ff90994SKumar Sanghvi u8 rsvd[24]; 11310ff90994SKumar Sanghvi 1132f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1133f2b7e78dSVipul Pandya */ 1134f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1135f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1136f2b7e78dSVipul Pandya }; 1137f2b7e78dSVipul Pandya 1138f2b7e78dSVipul Pandya enum { 1139f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1140f2b7e78dSVipul Pandya FILTER_DROP, 1141f2b7e78dSVipul Pandya FILTER_SWITCH 1142f2b7e78dSVipul Pandya }; 1143f2b7e78dSVipul Pandya 1144f2b7e78dSVipul Pandya enum { 1145f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1146f2b7e78dSVipul Pandya VLAN_REMOVE, 1147f2b7e78dSVipul Pandya VLAN_INSERT, 1148f2b7e78dSVipul Pandya VLAN_REWRITE 1149f2b7e78dSVipul Pandya }; 1150f2b7e78dSVipul Pandya 1151557ccbf9SKumar Sanghvi enum { 115212b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 115312b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 115412b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 115512b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 115612b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 115712b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 115812b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 115912b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1160557ccbf9SKumar Sanghvi }; 1161557ccbf9SKumar Sanghvi 1162d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1163d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1164d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1165d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1166d57fd6caSRahul Lakkireddy * where the filter table is large. 1167d57fd6caSRahul Lakkireddy */ 1168d57fd6caSRahul Lakkireddy struct filter_entry { 1169d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1170d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1171d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1172d57fd6caSRahul Lakkireddy 1173d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1174578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1175d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 11763bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1177578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1178578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1179d57fd6caSRahul Lakkireddy 1180d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1181d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1182d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1183d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1184d57fd6caSRahul Lakkireddy */ 1185d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1186d57fd6caSRahul Lakkireddy }; 1187d57fd6caSRahul Lakkireddy 1188a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1189a4cfd929SHariprasad Shenai { 1190a4cfd929SHariprasad Shenai return adap->params.offload; 1191a4cfd929SHariprasad Shenai } 1192a4cfd929SHariprasad Shenai 11935c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 11945c31254eSKumar Sanghvi { 11955c31254eSKumar Sanghvi return adap->params.hash_filter; 11965c31254eSKumar Sanghvi } 11975c31254eSKumar Sanghvi 119894cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 119994cdb8bbSHariprasad Shenai { 120094cdb8bbSHariprasad Shenai return adap->params.crypto; 120194cdb8bbSHariprasad Shenai } 120294cdb8bbSHariprasad Shenai 12030fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 12040fbc81b3SHariprasad Shenai { 12050fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 12060fbc81b3SHariprasad Shenai } 12070fbc81b3SHariprasad Shenai 1208f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1209f7917c00SJeff Kirsher { 1210f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1211f7917c00SJeff Kirsher } 1212f7917c00SJeff Kirsher 1213f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1214f7917c00SJeff Kirsher { 1215f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1216f7917c00SJeff Kirsher } 1217f7917c00SJeff Kirsher 1218f7917c00SJeff Kirsher #ifndef readq 1219f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1220f7917c00SJeff Kirsher { 1221f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1222f7917c00SJeff Kirsher } 1223f7917c00SJeff Kirsher 1224f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1225f7917c00SJeff Kirsher { 1226f7917c00SJeff Kirsher writel(val, addr); 1227f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1228f7917c00SJeff Kirsher } 1229f7917c00SJeff Kirsher #endif 1230f7917c00SJeff Kirsher 1231f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1232f7917c00SJeff Kirsher { 1233f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1234f7917c00SJeff Kirsher } 1235f7917c00SJeff Kirsher 1236f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1237f7917c00SJeff Kirsher { 1238f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1239f7917c00SJeff Kirsher } 1240f7917c00SJeff Kirsher 1241f7917c00SJeff Kirsher /** 1242098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1243098ef6c2SHariprasad Shenai * @adapter: the adapter 1244098ef6c2SHariprasad Shenai * @port_idx: the port index 1245098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1246098ef6c2SHariprasad Shenai * 1247098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1248098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1249098ef6c2SHariprasad Shenai */ 1250098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1251098ef6c2SHariprasad Shenai u8 hw_addr[]) 1252098ef6c2SHariprasad Shenai { 1253098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1254098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1255098ef6c2SHariprasad Shenai } 1256098ef6c2SHariprasad Shenai 1257098ef6c2SHariprasad Shenai /** 1258f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1259f7917c00SJeff Kirsher * @dev: the netdev 1260f7917c00SJeff Kirsher * 1261f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1262f7917c00SJeff Kirsher */ 1263f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1264f7917c00SJeff Kirsher { 1265f7917c00SJeff Kirsher return netdev_priv(dev); 1266f7917c00SJeff Kirsher } 1267f7917c00SJeff Kirsher 1268f7917c00SJeff Kirsher /** 1269f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1270f7917c00SJeff Kirsher * @adap: the adapter 1271f7917c00SJeff Kirsher * @idx: the port index 1272f7917c00SJeff Kirsher * 1273f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1274f7917c00SJeff Kirsher */ 1275f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1276f7917c00SJeff Kirsher { 1277f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1278f7917c00SJeff Kirsher } 1279f7917c00SJeff Kirsher 1280f7917c00SJeff Kirsher /** 1281f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1282f7917c00SJeff Kirsher * @dev: the netdev 1283f7917c00SJeff Kirsher * 1284f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1285f7917c00SJeff Kirsher */ 1286f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1287f7917c00SJeff Kirsher { 1288f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1289f7917c00SJeff Kirsher } 1290f7917c00SJeff Kirsher 1291812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1292812034f1SHariprasad Shenai * - bits 0..9: chip version 1293812034f1SHariprasad Shenai * - bits 10..15: chip revision 1294812034f1SHariprasad Shenai * - bits 16..23: register dump version 1295812034f1SHariprasad Shenai */ 1296812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1297812034f1SHariprasad Shenai { 1298812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1299812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1300812034f1SHariprasad Shenai } 1301812034f1SHariprasad Shenai 1302812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1303812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1304812034f1SHariprasad Shenai const struct sge_rspq *q) 1305812034f1SHariprasad Shenai { 1306812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1307812034f1SHariprasad Shenai 1308812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1309812034f1SHariprasad Shenai } 1310812034f1SHariprasad Shenai 1311812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1312812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1313812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1314812034f1SHariprasad Shenai 1315f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1316f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1317f7917c00SJeff Kirsher 1318f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 13195fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1320f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1321f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1322f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1323f7917c00SJeff Kirsher const struct pkt_gl *gl); 1324f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1325f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1326f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1327f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 13282337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 13292337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1330f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1331f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1332f7917c00SJeff Kirsher unsigned int iqid); 1333f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1334f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1335f7917c00SJeff Kirsher unsigned int cmplqid); 13360fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 13370fbc81b3SHariprasad Shenai unsigned int cmplqid); 1338ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1339ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1340ab677ff4SHariprasad Shenai unsigned int uld_type); 1341f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 134252367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1343f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1344f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1345812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1346812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1347d0a1299cSGanesh Goudar enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 13483069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1349f7917c00SJeff Kirsher 1350f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1351f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1352f7917c00SJeff Kirsher 13539a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 13549a4da2cdSVipul Pandya { 13559a4da2cdSVipul Pandya return adap->params.bypass; 13569a4da2cdSVipul Pandya } 13579a4da2cdSVipul Pandya 13589a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 13599a4da2cdSVipul Pandya { 13609a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 13619a4da2cdSVipul Pandya switch (device) { 13629a4da2cdSVipul Pandya case 0x440b: 13639a4da2cdSVipul Pandya case 0x440c: 13649a4da2cdSVipul Pandya return 1; 13659a4da2cdSVipul Pandya default: 13669a4da2cdSVipul Pandya return 0; 13679a4da2cdSVipul Pandya } 13689a4da2cdSVipul Pandya } 13699a4da2cdSVipul Pandya 137001b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 137101b69614SHariprasad Shenai { 137201b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 137301b69614SHariprasad Shenai switch (device) { 137401b69614SHariprasad Shenai case 0x4409: 137501b69614SHariprasad Shenai case 0x4486: 137601b69614SHariprasad Shenai return 1; 137701b69614SHariprasad Shenai 137801b69614SHariprasad Shenai default: 137901b69614SHariprasad Shenai return 0; 138001b69614SHariprasad Shenai } 138101b69614SHariprasad Shenai } 138201b69614SHariprasad Shenai 1383f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1384f7917c00SJeff Kirsher { 1385f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1386f7917c00SJeff Kirsher } 1387f7917c00SJeff Kirsher 1388f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1389f7917c00SJeff Kirsher unsigned int us) 1390f7917c00SJeff Kirsher { 1391f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1392f7917c00SJeff Kirsher } 1393f7917c00SJeff Kirsher 139452367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 139552367a76SVipul Pandya unsigned int ticks) 139652367a76SVipul Pandya { 139752367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 139852367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 139952367a76SVipul Pandya adapter->params.vpd.cclk); 140052367a76SVipul Pandya } 140152367a76SVipul Pandya 140208c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 140308c4901bSRahul Lakkireddy unsigned int ticks) 140408c4901bSRahul Lakkireddy { 140508c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 140608c4901bSRahul Lakkireddy } 140708c4901bSRahul Lakkireddy 1408f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1409f7917c00SJeff Kirsher u32 val); 1410f7917c00SJeff Kirsher 141101b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 141201b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1413f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1414f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1415f7917c00SJeff Kirsher 141601b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 141701b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 141801b69614SHariprasad Shenai int timeout) 141901b69614SHariprasad Shenai { 142001b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 142101b69614SHariprasad Shenai timeout); 142201b69614SHariprasad Shenai } 142301b69614SHariprasad Shenai 1424f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1425f7917c00SJeff Kirsher int size, void *rpl) 1426f7917c00SJeff Kirsher { 1427f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1428f7917c00SJeff Kirsher } 1429f7917c00SJeff Kirsher 1430f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1431f7917c00SJeff Kirsher int size, void *rpl) 1432f7917c00SJeff Kirsher { 1433f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1434f7917c00SJeff Kirsher } 1435f7917c00SJeff Kirsher 1436fc08a01aSHariprasad Shenai /** 1437fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1438fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1439fc08a01aSHariprasad Shenai * 1440fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1441fc08a01aSHariprasad Shenai * (hash) address matching. 1442fc08a01aSHariprasad Shenai */ 1443fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1444fc08a01aSHariprasad Shenai { 1445fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1446fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1447fc08a01aSHariprasad Shenai 1448fc08a01aSHariprasad Shenai a ^= b; 1449fc08a01aSHariprasad Shenai a ^= (a >> 12); 1450fc08a01aSHariprasad Shenai a ^= (a >> 6); 1451fc08a01aSHariprasad Shenai return a & 0x3f; 1452fc08a01aSHariprasad Shenai } 1453fc08a01aSHariprasad Shenai 145494cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 145594cdb8bbSHariprasad Shenai unsigned int cnt); 145694cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 145794cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 145894cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 145994cdb8bbSHariprasad Shenai { 146094cdb8bbSHariprasad Shenai q->adap = adap; 146194cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 146294cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 146394cdb8bbSHariprasad Shenai q->size = size; 146494cdb8bbSHariprasad Shenai } 146594cdb8bbSHariprasad Shenai 1466f56ec676SArjun Vynipadath /** 1467f56ec676SArjun Vynipadath * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1468f56ec676SArjun Vynipadath * @fw_mod_type: the Firmware Mofule Type 1469f56ec676SArjun Vynipadath * 1470f56ec676SArjun Vynipadath * Return whether the Firmware Module Type represents a real Transceiver 1471f56ec676SArjun Vynipadath * Module/Cable Module Type which has been inserted. 1472f56ec676SArjun Vynipadath */ 1473f56ec676SArjun Vynipadath static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1474f56ec676SArjun Vynipadath { 1475f56ec676SArjun Vynipadath return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1476f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1477f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1478f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1479f56ec676SArjun Vynipadath } 1480f56ec676SArjun Vynipadath 148113ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 148213ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 148313ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1484f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1485f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1486f2b7e78dSVipul Pandya unsigned int start_idx); 14870abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1488f2b7e78dSVipul Pandya 1489f2b7e78dSVipul Pandya struct fw_filter_wr; 1490f2b7e78dSVipul Pandya 1491f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1492f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1493f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1494f7917c00SJeff Kirsher 14958203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 14964036da90SHariprasad Shenai int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1497f7917c00SJeff Kirsher struct link_config *lc); 1498f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1499fc5ab020SHariprasad Shenai 1500b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1501b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1502b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1503b562fc37SHariprasad Shenai 15041a4330cdSRahul Lakkireddy int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 15051a4330cdSRahul Lakkireddy u32 *mem_base, u32 *mem_aperture); 15061a4330cdSRahul Lakkireddy void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 15071a4330cdSRahul Lakkireddy void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 15081a4330cdSRahul Lakkireddy int dir); 1509fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1510fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1511fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1512f01aa633SHariprasad Shenai void *buf, int dir); 1513fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1514fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1515fc5ab020SHariprasad Shenai { 1516fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1517fc5ab020SHariprasad Shenai } 1518fc5ab020SHariprasad Shenai 1519812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1520812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1521812034f1SHariprasad Shenai 1522940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1523f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1524098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1525098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 152649216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 152749216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1528f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 152901b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 153001b69614SHariprasad Shenai int win, spinlock_t *lock, 153101b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 153201b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 153301b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 153449216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 153522c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 153622c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1537acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1538636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1539a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 15404da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 154116e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 15420de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 154316e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1544ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1545760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1546760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1547760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1548760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 154916e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 155016e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 155116e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1552f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 15533be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1554e85c9a7aSHariprasad Shenai 1555e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1556b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1557e85c9a7aSHariprasad Shenai unsigned int qid, 1558e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 155966cf188eSHariprasad S int user, 1560e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1561e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1562e85c9a7aSHariprasad Shenai 1563dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1564dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1565ae469b68SHariprasad Shenai 1566ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1567e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 15685ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1569dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1570c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1571c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1572c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1573f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1574f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1575f988008aSGanesh Goudar unsigned int t4_chip_rss_size(struct adapter *adapter); 1576f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1577f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1578f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1579f7917c00SJeff Kirsher unsigned int flags); 1580c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1581c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1582688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 15835ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 15845ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 15855ccf9d04SRahul Lakkireddy bool sleep_ok); 1586688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 15875ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1588688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 15895ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 15905ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 15915ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1592688ea5feSHariprasad Shenai 1593193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1594193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1595b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1596b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1597e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1598e5f0e43bSHariprasad Shenai size_t n); 1599c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1600c778af7dSHariprasad Shenai size_t n); 1601f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1602f1ff24aaSHariprasad Shenai unsigned int *valp); 1603f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1604f1ff24aaSHariprasad Shenai const unsigned int *valp); 1605f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 160619689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 160719689609SHariprasad Shenai unsigned int *pif_req_wrptr, 160819689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 160926fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 161074b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 161172aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1612f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1613a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1614a4cfd929SHariprasad Shenai struct port_stats *stats, 1615a4cfd929SHariprasad Shenai struct port_stats *offset); 161665046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1617f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1618bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1619636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1620636f9d37SVipul Pandya unsigned int mask, unsigned int val); 16212d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 16225ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 16235ccf9d04SRahul Lakkireddy bool sleep_ok); 16245ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 16255ccf9d04SRahul Lakkireddy bool sleep_ok); 16265ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 16275ccf9d04SRahul Lakkireddy bool sleep_ok); 16285ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 16295ccf9d04SRahul Lakkireddy bool sleep_ok); 1630f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 16315ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1632a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 16335ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1634f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1635f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1636f7917c00SJeff Kirsher 1637797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1638797ff0f5SHariprasad Shenai 16397864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1640f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1641f2b7e78dSVipul Pandya 1642f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1643f7917c00SJeff Kirsher const u8 *addr); 1644f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1645f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1646f7917c00SJeff Kirsher 1647f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1648f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1649f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1650f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1651f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1652636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1653636f9d37SVipul Pandya unsigned int cache_line_size); 1654636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1655f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1656f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1657f7917c00SJeff Kirsher u32 *val); 16588f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 16598f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 16608f46d467SArjun Vynipadath u32 *val); 166101b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1662f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 16638f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 166401b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1665688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1666688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 166701b69614SHariprasad Shenai const u32 *val, int timeout); 166801b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 166901b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1670688848b1SAnish Bhatt const u32 *val); 1671f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1672f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1673f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1674f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1675f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1676f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1677f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1678f7917c00SJeff Kirsher unsigned int *rss_size); 16794f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 16804f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 16814f3a0fcfSHariprasad Shenai unsigned int viid); 1682f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1683f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1684f7917c00SJeff Kirsher bool sleep_ok); 1685846eac3fSGanesh Goudar int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1686846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1687846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 1688846eac3fSGanesh Goudar int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1689846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1690846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 1691f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1692f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1693f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1694fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1695fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1696fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1697f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1698f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1699f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1700f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1701688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1702688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1703f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1704f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1705f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1706f7917c00SJeff Kirsher unsigned int nblinks); 1707f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1708f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1709f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1710f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1711ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1712ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1713ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1714f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1715f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1716f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1717f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1718f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1719f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1720f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1721f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1722f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1723736c3b94SRahul Lakkireddy int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 172423853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 17252061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1726c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1727c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1728f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1729881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1730881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 17318e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 17328e3d04fdSHariprasad Shenai int filter_index, int enable); 17338e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 17348e3d04fdSHariprasad Shenai int filter_index, int *enabled); 17358caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 17368caa1e84SVipul Pandya u32 addr, u32 val); 173708c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 173808c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 173908c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 17409e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 17419e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 17429e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 17439e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 1744b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1745b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1746b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 174768bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1748a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1749a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1750a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1751a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1752a3bfb617SHariprasad Shenai int hz, int ticks); 1753858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1754858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 17555ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 17565ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 17574359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 17584359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 17595ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 17605ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 17615ccf9d04SRahul Lakkireddy 17620fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 17630fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 17640fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 17650fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 1766f56ec676SArjun Vynipadath int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1767f56ec676SArjun Vynipadath unsigned int devid, unsigned int offset, 1768f56ec676SArjun Vynipadath unsigned int len, u8 *buf); 176994cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1770ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1771ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1772ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1773a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 1774a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 1775a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1776a6ec572bSAtul Gupta dma_addr_t *addr); 1777a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1778a6ec572bSAtul Gupta void *pos); 1779a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1780a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1781a6ec572bSAtul Gupta const dma_addr_t *addr); 1782a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 17839d5fd927SGanesh Goudar int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 17849d5fd927SGanesh Goudar u16 vlan); 1785f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1786