1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 505e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 51f7917c00SJeff Kirsher #include <asm/io.h> 5227999805SHariprasad S #include "t4_chip_type.h" 53f7917c00SJeff Kirsher #include "cxgb4_uld.h" 54f7917c00SJeff Kirsher 553069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 5694cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 5794cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 583069ee9bSVipul Pandya 59f7917c00SJeff Kirsher enum { 60f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 61f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 62f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 63f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 64a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 65098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 66f7917c00SJeff Kirsher }; 67f7917c00SJeff Kirsher 68f7917c00SJeff Kirsher enum { 69812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 70812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 71812034f1SHariprasad Shenai }; 72812034f1SHariprasad Shenai 73812034f1SHariprasad Shenai enum { 74f7917c00SJeff Kirsher MEM_EDC0, 75f7917c00SJeff Kirsher MEM_EDC1, 762422d9a3SSantosh Rastapur MEM_MC, 772422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 782422d9a3SSantosh Rastapur MEM_MC1 79f7917c00SJeff Kirsher }; 80f7917c00SJeff Kirsher 813069ee9bSVipul Pandya enum { 823eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 833eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 843069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 853069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 862422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 873eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 883eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 890abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 900abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 913069ee9bSVipul Pandya }; 923069ee9bSVipul Pandya 93f7917c00SJeff Kirsher enum dev_master { 94f7917c00SJeff Kirsher MASTER_CANT, 95f7917c00SJeff Kirsher MASTER_MAY, 96f7917c00SJeff Kirsher MASTER_MUST 97f7917c00SJeff Kirsher }; 98f7917c00SJeff Kirsher 99f7917c00SJeff Kirsher enum dev_state { 100f7917c00SJeff Kirsher DEV_STATE_UNINIT, 101f7917c00SJeff Kirsher DEV_STATE_INIT, 102f7917c00SJeff Kirsher DEV_STATE_ERR 103f7917c00SJeff Kirsher }; 104f7917c00SJeff Kirsher 105f7917c00SJeff Kirsher enum { 106f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 107f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 108f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 109f7917c00SJeff Kirsher }; 110f7917c00SJeff Kirsher 111f7917c00SJeff Kirsher struct port_stats { 112f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 113f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 114f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 115f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 116f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 117f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 118f7917c00SJeff Kirsher 119f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 120f7917c00SJeff Kirsher u64 tx_frames_65_127; 121f7917c00SJeff Kirsher u64 tx_frames_128_255; 122f7917c00SJeff Kirsher u64 tx_frames_256_511; 123f7917c00SJeff Kirsher u64 tx_frames_512_1023; 124f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 125f7917c00SJeff Kirsher u64 tx_frames_1519_max; 126f7917c00SJeff Kirsher 127f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 128f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 129f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 130f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 131f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 132f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 133f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 134f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 135f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 136f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 137f7917c00SJeff Kirsher 138f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 139f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 140f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 141f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 142f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 143f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 144f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 145f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 146f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 147f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 148f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 149f7917c00SJeff Kirsher 150f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 151f7917c00SJeff Kirsher u64 rx_frames_65_127; 152f7917c00SJeff Kirsher u64 rx_frames_128_255; 153f7917c00SJeff Kirsher u64 rx_frames_256_511; 154f7917c00SJeff Kirsher u64 rx_frames_512_1023; 155f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 156f7917c00SJeff Kirsher u64 rx_frames_1519_max; 157f7917c00SJeff Kirsher 158f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 159f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 160f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 161f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 162f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 163f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 164f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 165f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 166f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 167f7917c00SJeff Kirsher 168f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 169f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 170f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 171f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 172f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 173f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 174f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 175f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 176f7917c00SJeff Kirsher }; 177f7917c00SJeff Kirsher 178f7917c00SJeff Kirsher struct lb_port_stats { 179f7917c00SJeff Kirsher u64 octets; 180f7917c00SJeff Kirsher u64 frames; 181f7917c00SJeff Kirsher u64 bcast_frames; 182f7917c00SJeff Kirsher u64 mcast_frames; 183f7917c00SJeff Kirsher u64 ucast_frames; 184f7917c00SJeff Kirsher u64 error_frames; 185f7917c00SJeff Kirsher 186f7917c00SJeff Kirsher u64 frames_64; 187f7917c00SJeff Kirsher u64 frames_65_127; 188f7917c00SJeff Kirsher u64 frames_128_255; 189f7917c00SJeff Kirsher u64 frames_256_511; 190f7917c00SJeff Kirsher u64 frames_512_1023; 191f7917c00SJeff Kirsher u64 frames_1024_1518; 192f7917c00SJeff Kirsher u64 frames_1519_max; 193f7917c00SJeff Kirsher 194f7917c00SJeff Kirsher u64 drop; 195f7917c00SJeff Kirsher 196f7917c00SJeff Kirsher u64 ovflow0; 197f7917c00SJeff Kirsher u64 ovflow1; 198f7917c00SJeff Kirsher u64 ovflow2; 199f7917c00SJeff Kirsher u64 ovflow3; 200f7917c00SJeff Kirsher u64 trunc0; 201f7917c00SJeff Kirsher u64 trunc1; 202f7917c00SJeff Kirsher u64 trunc2; 203f7917c00SJeff Kirsher u64 trunc3; 204f7917c00SJeff Kirsher }; 205f7917c00SJeff Kirsher 206f7917c00SJeff Kirsher struct tp_tcp_stats { 207a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 208a4cfd929SHariprasad Shenai u64 tcp_in_segs; 209a4cfd929SHariprasad Shenai u64 tcp_out_segs; 210a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 211a4cfd929SHariprasad Shenai }; 212a4cfd929SHariprasad Shenai 213a4cfd929SHariprasad Shenai struct tp_usm_stats { 214a4cfd929SHariprasad Shenai u32 frames; 215a4cfd929SHariprasad Shenai u32 drops; 216a4cfd929SHariprasad Shenai u64 octets; 217f7917c00SJeff Kirsher }; 218f7917c00SJeff Kirsher 219a6222975SHariprasad Shenai struct tp_fcoe_stats { 220a6222975SHariprasad Shenai u32 frames_ddp; 221a6222975SHariprasad Shenai u32 frames_drop; 222a6222975SHariprasad Shenai u64 octets_ddp; 223f7917c00SJeff Kirsher }; 224f7917c00SJeff Kirsher 225f7917c00SJeff Kirsher struct tp_err_stats { 226a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 227a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 228a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 229a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 230a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 231a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 232a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 233a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 234a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 235a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 236a4cfd929SHariprasad Shenai }; 237a4cfd929SHariprasad Shenai 238a6222975SHariprasad Shenai struct tp_cpl_stats { 239a6222975SHariprasad Shenai u32 req[4]; 240a6222975SHariprasad Shenai u32 rsp[4]; 241a6222975SHariprasad Shenai }; 242a6222975SHariprasad Shenai 243a4cfd929SHariprasad Shenai struct tp_rdma_stats { 244a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 245a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 246f7917c00SJeff Kirsher }; 247f7917c00SJeff Kirsher 248e85c9a7aSHariprasad Shenai struct sge_params { 249e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 250e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 251e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 252e85c9a7aSHariprasad Shenai }; 253e85c9a7aSHariprasad Shenai 254f7917c00SJeff Kirsher struct tp_params { 255f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2562d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 257dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 258dca4faebSVipul Pandya /* channel map */ 259636f9d37SVipul Pandya 260636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 261636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 262dcf7b6f5SKumar Sanghvi 263dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 264dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 265dcf7b6f5SKumar Sanghvi 266dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 267dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 268dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 269dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 270dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 271dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 272dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 273dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 274dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 275dcf7b6f5SKumar Sanghvi * present. 276dcf7b6f5SKumar Sanghvi */ 277dcf7b6f5SKumar Sanghvi int vlan_shift; 278dcf7b6f5SKumar Sanghvi int vnic_shift; 279dcf7b6f5SKumar Sanghvi int port_shift; 280dcf7b6f5SKumar Sanghvi int protocol_shift; 281f7917c00SJeff Kirsher }; 282f7917c00SJeff Kirsher 283f7917c00SJeff Kirsher struct vpd_params { 284f7917c00SJeff Kirsher unsigned int cclk; 285f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 286f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 287f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 288a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 289098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 290f7917c00SJeff Kirsher }; 291f7917c00SJeff Kirsher 292f7917c00SJeff Kirsher struct pci_params { 293f7917c00SJeff Kirsher unsigned char speed; 294f7917c00SJeff Kirsher unsigned char width; 295f7917c00SJeff Kirsher }; 296f7917c00SJeff Kirsher 29749aa284fSHariprasad Shenai struct devlog_params { 29849aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 29949aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 30049aa284fSHariprasad Shenai u32 size; /* size of log */ 30149aa284fSHariprasad Shenai }; 30249aa284fSHariprasad Shenai 3033ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3043ccc6cf7SHariprasad Shenai struct arch_specific_params { 3053ccc6cf7SHariprasad Shenai u8 nchan; 30644588560SHariprasad Shenai u8 pm_stats_cnt; 3072216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3083ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3093ccc6cf7SHariprasad Shenai u16 vfcount; 3103ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3113ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3123ccc6cf7SHariprasad Shenai }; 3133ccc6cf7SHariprasad Shenai 314f7917c00SJeff Kirsher struct adapter_params { 315e85c9a7aSHariprasad Shenai struct sge_params sge; 316f7917c00SJeff Kirsher struct tp_params tp; 317f7917c00SJeff Kirsher struct vpd_params vpd; 318f7917c00SJeff Kirsher struct pci_params pci; 31949aa284fSHariprasad Shenai struct devlog_params devlog; 32049aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 321f7917c00SJeff Kirsher 322f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 323f1ff24aaSHariprasad Shenai 324f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 325f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 326f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 327f7917c00SJeff Kirsher 328f7917c00SJeff Kirsher unsigned int fw_vers; 3290de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 330f7917c00SJeff Kirsher unsigned int tp_vers; 3310de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 332f7917c00SJeff Kirsher u8 api_vers[7]; 333f7917c00SJeff Kirsher 334f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 335f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 336f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 337f7917c00SJeff Kirsher 338f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 339f7917c00SJeff Kirsher unsigned char portvec; 340d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3413ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 342f7917c00SJeff Kirsher unsigned char offload; 34394cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 344f7917c00SJeff Kirsher 3459a4da2cdSVipul Pandya unsigned char bypass; 3469a4da2cdSVipul Pandya 347f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3481ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3494c2c5763SHariprasad Shenai 350b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 3514c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3524c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 353f7917c00SJeff Kirsher }; 354f7917c00SJeff Kirsher 355a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 356a3bfb617SHariprasad Shenai * and possible hangs. 357a3bfb617SHariprasad Shenai */ 358a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 359a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 360a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 361a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 362a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 363a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 364a3bfb617SHariprasad Shenai }; 365a3bfb617SHariprasad Shenai 3667f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 3677f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 3687f080c3fSHariprasad Shenai * error returns. 3697f080c3fSHariprasad Shenai */ 3707f080c3fSHariprasad Shenai struct mbox_cmd { 3717f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 3727f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 3737f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 3747f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 3757f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 3767f080c3fSHariprasad Shenai }; 3777f080c3fSHariprasad Shenai 3787f080c3fSHariprasad Shenai struct mbox_cmd_log { 3797f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 3807f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 3817f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 3827f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 3837f080c3fSHariprasad Shenai }; 3847f080c3fSHariprasad Shenai 3857f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 3867f080c3fSHariprasad Shenai * return a pointer to the specified entry. 3877f080c3fSHariprasad Shenai */ 3887f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 3897f080c3fSHariprasad Shenai unsigned int entry_idx) 3907f080c3fSHariprasad Shenai { 3917f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 3927f080c3fSHariprasad Shenai } 3937f080c3fSHariprasad Shenai 39416e47624SHariprasad Shenai #include "t4fw_api.h" 39516e47624SHariprasad Shenai 39616e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 397b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 398b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 399b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 400b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 40116e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 40216e47624SHariprasad Shenai 40316e47624SHariprasad Shenai struct fw_info { 40416e47624SHariprasad Shenai u8 chip; 40516e47624SHariprasad Shenai char *fs_name; 40616e47624SHariprasad Shenai char *fw_mod_name; 40716e47624SHariprasad Shenai struct fw_hdr fw_hdr; 40816e47624SHariprasad Shenai }; 40916e47624SHariprasad Shenai 410f7917c00SJeff Kirsher struct trace_params { 411f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 412f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 413f7917c00SJeff Kirsher unsigned short snap_len; 414f7917c00SJeff Kirsher unsigned short min_len; 415f7917c00SJeff Kirsher unsigned char skip_ofst; 416f7917c00SJeff Kirsher unsigned char skip_len; 417f7917c00SJeff Kirsher unsigned char invert; 418f7917c00SJeff Kirsher unsigned char port; 419f7917c00SJeff Kirsher }; 420f7917c00SJeff Kirsher 421f7917c00SJeff Kirsher struct link_config { 422f7917c00SJeff Kirsher unsigned short supported; /* link capabilities */ 423f7917c00SJeff Kirsher unsigned short advertising; /* advertised capabilities */ 424eb97ad99SGanesh Goudar unsigned short lp_advertising; /* peer advertised capabilities */ 425f7917c00SJeff Kirsher unsigned short requested_speed; /* speed user has requested */ 426f7917c00SJeff Kirsher unsigned short speed; /* actual link speed */ 427f7917c00SJeff Kirsher unsigned char requested_fc; /* flow control user has requested */ 428f7917c00SJeff Kirsher unsigned char fc; /* actual link flow control */ 429f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 430f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 431ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 432f7917c00SJeff Kirsher }; 433f7917c00SJeff Kirsher 434e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 435f7917c00SJeff Kirsher 436f7917c00SJeff Kirsher enum { 437f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 438f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 439f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 440f7917c00SJeff Kirsher MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 441f36e58e5SHariprasad Shenai MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ 442f2692d16SVarun Prakash 443f2692d16SVarun Prakash /* # of streaming iSCSIT Rx queues */ 444f2692d16SVarun Prakash MAX_ISCSIT_QUEUES = MAX_OFLD_QSETS, 445f7917c00SJeff Kirsher }; 446f7917c00SJeff Kirsher 447f7917c00SJeff Kirsher enum { 448812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 449812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 450812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 451812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 452812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 453812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 454812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 455812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 456812034f1SHariprasad Shenai }; 457812034f1SHariprasad Shenai 458812034f1SHariprasad Shenai enum { 459cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 460cf38be6dSHariprasad Shenai /* forwarded interrupts */ 461f2692d16SVarun Prakash MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES + 462f2692d16SVarun Prakash MAX_RDMA_CIQS + MAX_ISCSIT_QUEUES + INGQ_EXTRAS, 463f7917c00SJeff Kirsher }; 464f7917c00SJeff Kirsher 465f7917c00SJeff Kirsher struct adapter; 466f7917c00SJeff Kirsher struct sge_rspq; 467f7917c00SJeff Kirsher 468688848b1SAnish Bhatt #include "cxgb4_dcb.h" 469688848b1SAnish Bhatt 47076fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 47176fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 47276fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 47376fed8a9SVarun Prakash 474f7917c00SJeff Kirsher struct port_info { 475f7917c00SJeff Kirsher struct adapter *adapter; 476f7917c00SJeff Kirsher u16 viid; 477f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 478f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 479f7917c00SJeff Kirsher s8 mdio_addr; 48040e9de4bSHariprasad Shenai enum fw_port_type port_type; 481f7917c00SJeff Kirsher u8 mod_type; 482f7917c00SJeff Kirsher u8 port_id; 483f7917c00SJeff Kirsher u8 tx_chan; 484f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 485f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 486f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 487f7917c00SJeff Kirsher u8 rss_mode; 488f7917c00SJeff Kirsher struct link_config link_cfg; 489f7917c00SJeff Kirsher u16 *rss; 490a4cfd929SHariprasad Shenai struct port_stats stats_base; 491688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 492688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 493688848b1SAnish Bhatt #endif 49476fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 49576fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 49676fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 4975e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 4985e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 499b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 500f7917c00SJeff Kirsher }; 501f7917c00SJeff Kirsher 502f7917c00SJeff Kirsher struct dentry; 503f7917c00SJeff Kirsher struct work_struct; 504f7917c00SJeff Kirsher 505f7917c00SJeff Kirsher enum { /* adapter flags */ 506f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 507144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 508144be3d9SGavin Shan USING_MSI = (1 << 2), 509144be3d9SGavin Shan USING_MSIX = (1 << 3), 510f7917c00SJeff Kirsher FW_OK = (1 << 4), 51113ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 51252367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 51352367a76SVipul Pandya MASTER_PF = (1 << 7), 51452367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 515f7917c00SJeff Kirsher }; 516f7917c00SJeff Kirsher 51794cdb8bbSHariprasad Shenai enum { 51894cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 51994cdb8bbSHariprasad Shenai }; 52094cdb8bbSHariprasad Shenai 521f7917c00SJeff Kirsher struct rx_sw_desc; 522f7917c00SJeff Kirsher 523f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 524f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 525f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 526f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 527f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 528f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 529f7917c00SJeff Kirsher unsigned long large_alloc_failed; 53070055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 53170055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 532f7917c00SJeff Kirsher unsigned long starving; 533f7917c00SJeff Kirsher /* RO fields */ 534f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 535f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 536f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 537f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 538f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 539df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 540df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 541f7917c00SJeff Kirsher }; 542f7917c00SJeff Kirsher 543f7917c00SJeff Kirsher /* A packet gather list */ 544f7917c00SJeff Kirsher struct pkt_gl { 5455e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 546e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 547f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 548f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 549f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 550f7917c00SJeff Kirsher }; 551f7917c00SJeff Kirsher 552f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 553f7917c00SJeff Kirsher const struct pkt_gl *gl); 5542337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 5552337ba42SVarun Prakash /* LRO related declarations for ULD */ 5562337ba42SVarun Prakash struct t4_lro_mgr { 5572337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 5582337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 5592337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 5602337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 5612337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 5622337ba42SVarun Prakash }; 563f7917c00SJeff Kirsher 564f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 565f7917c00SJeff Kirsher struct napi_struct napi; 566f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 567f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 568f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 569f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 570f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 571e553ec3fSHariprasad Shenai u8 adaptive_rx; 572f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 573f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 574f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 575f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 576f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 577f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 578f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 579f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 580df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 581df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 582f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 583f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 584f7917c00SJeff Kirsher struct adapter *adap; 585f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 586f7917c00SJeff Kirsher rspq_handler_t handler; 5872337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 5882337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 5893a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 5903a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_IDLE 0 5913a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 5923a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 5933a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 5943a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 5953a336cb1SHariprasad Shenai #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 5963a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5973a336cb1SHariprasad Shenai #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 5983a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL) 5993a336cb1SHariprasad Shenai #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 6003a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 6013a336cb1SHariprasad Shenai unsigned int bpoll_state; 6023a336cb1SHariprasad Shenai spinlock_t bpoll_lock; /* lock for busy poll */ 6033a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 6043a336cb1SHariprasad Shenai 605f7917c00SJeff Kirsher }; 606f7917c00SJeff Kirsher 607f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 608f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 609f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 610f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 611f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 612f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 613f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 614f7917c00SJeff Kirsher }; 615f7917c00SJeff Kirsher 616f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 617f7917c00SJeff Kirsher struct sge_rspq rspq; 618f7917c00SJeff Kirsher struct sge_fl fl; 619f7917c00SJeff Kirsher struct sge_eth_stats stats; 620f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 621f7917c00SJeff Kirsher 622f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 623f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 624f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 625f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 626f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 627f7917c00SJeff Kirsher }; 628f7917c00SJeff Kirsher 629f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 630f7917c00SJeff Kirsher struct sge_rspq rspq; 631f7917c00SJeff Kirsher struct sge_fl fl; 632f7917c00SJeff Kirsher struct sge_ofld_stats stats; 633f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 634f7917c00SJeff Kirsher 635f7917c00SJeff Kirsher struct tx_desc { 636f7917c00SJeff Kirsher __be64 flit[8]; 637f7917c00SJeff Kirsher }; 638f7917c00SJeff Kirsher 639f7917c00SJeff Kirsher struct tx_sw_desc; 640f7917c00SJeff Kirsher 641f7917c00SJeff Kirsher struct sge_txq { 642f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 643f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 644f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 645f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 646f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 647f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 648f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 649f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 650f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 651f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 652f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 6533069ee9bSVipul Pandya spinlock_t db_lock; 6543069ee9bSVipul Pandya int db_disabled; 6553069ee9bSVipul Pandya unsigned short db_pidx; 65605eb2389SSteve Wise unsigned short db_pidx_inc; 657df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 658df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 659f7917c00SJeff Kirsher }; 660f7917c00SJeff Kirsher 661f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 662f7917c00SJeff Kirsher struct sge_txq q; 663f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 66410b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 66510b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 66610b00466SAnish Bhatt #endif 667f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 668f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 669f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 670f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 671f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 672f7917c00SJeff Kirsher 673f7917c00SJeff Kirsher struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 674f7917c00SJeff Kirsher struct sge_txq q; 675f7917c00SJeff Kirsher struct adapter *adap; 676f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 677f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 678126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 679f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 680f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 681f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 682f7917c00SJeff Kirsher 683f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 684f7917c00SJeff Kirsher struct sge_txq q; 685f7917c00SJeff Kirsher struct adapter *adap; 686f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 687f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 688f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 689f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 690f7917c00SJeff Kirsher 69194cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 69294cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 69394cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 69494cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 69594cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 69694cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 69794cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 69894cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 69994cdb8bbSHariprasad Shenai }; 70094cdb8bbSHariprasad Shenai 701f7917c00SJeff Kirsher struct sge { 702f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 703f7917c00SJeff Kirsher struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 704f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 705f7917c00SJeff Kirsher 706f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 707f90ce561SHariprasad Shenai struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS]; 708f2692d16SVarun Prakash struct sge_ofld_rxq iscsitrxq[MAX_ISCSIT_QUEUES]; 709f7917c00SJeff Kirsher struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 710cf38be6dSHariprasad Shenai struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 711f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 71294cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 713f7917c00SJeff Kirsher 714f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 715f7917c00SJeff Kirsher spinlock_t intrq_lock; 716f7917c00SJeff Kirsher 717f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 718f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 719f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 720f90ce561SHariprasad Shenai u16 iscsiqsets; /* # of active iSCSI queue sets */ 721f2692d16SVarun Prakash u16 niscsitq; /* # of available iSCST Rx queues */ 722f7917c00SJeff Kirsher u16 rdmaqs; /* # of available RDMA Rx queues */ 723cf38be6dSHariprasad Shenai u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 72494cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 725f90ce561SHariprasad Shenai u16 iscsi_rxq[MAX_OFLD_QSETS]; 726f2692d16SVarun Prakash u16 iscsit_rxq[MAX_ISCSIT_QUEUES]; 727f36e58e5SHariprasad Shenai u16 rdma_rxq[MAX_RDMA_QUEUES]; 728f36e58e5SHariprasad Shenai u16 rdma_ciq[MAX_RDMA_CIQS]; 729f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 730f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 73152367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 73252367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 73352367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 73452367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 73552367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 7360f4d201fSKumar Sanghvi 737a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 738f7917c00SJeff Kirsher unsigned int egr_start; 7394b8e27a8SHariprasad Shenai unsigned int egr_sz; 740f7917c00SJeff Kirsher unsigned int ingr_start; 7414b8e27a8SHariprasad Shenai unsigned int ingr_sz; 7424b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 7434b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 7444b8e27a8SHariprasad Shenai unsigned long *starving_fl; 7454b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 7465b377d11SHariprasad Shenai unsigned long *blocked_fl; 747f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 748f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 749f7917c00SJeff Kirsher }; 750f7917c00SJeff Kirsher 751f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 752f90ce561SHariprasad Shenai #define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++) 753f2692d16SVarun Prakash #define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++) 754f7917c00SJeff Kirsher #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 755cf38be6dSHariprasad Shenai #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 756f7917c00SJeff Kirsher 757f7917c00SJeff Kirsher struct l2t_data; 758f7917c00SJeff Kirsher 7592422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 7602422d9a3SSantosh Rastapur 7617d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 7627d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 7637d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 7642422d9a3SSantosh Rastapur */ 7657d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 7662422d9a3SSantosh Rastapur 7672422d9a3SSantosh Rastapur #endif 7682422d9a3SSantosh Rastapur 769a4cfd929SHariprasad Shenai struct doorbell_stats { 770a4cfd929SHariprasad Shenai u32 db_drop; 771a4cfd929SHariprasad Shenai u32 db_empty; 772a4cfd929SHariprasad Shenai u32 db_full; 773a4cfd929SHariprasad Shenai }; 774a4cfd929SHariprasad Shenai 775fc08a01aSHariprasad Shenai struct hash_mac_addr { 776fc08a01aSHariprasad Shenai struct list_head list; 777fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 778fc08a01aSHariprasad Shenai }; 779fc08a01aSHariprasad Shenai 78094cdb8bbSHariprasad Shenai struct uld_msix_bmap { 78194cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 78294cdb8bbSHariprasad Shenai unsigned int mapsize; 78394cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 78494cdb8bbSHariprasad Shenai }; 78594cdb8bbSHariprasad Shenai 78694cdb8bbSHariprasad Shenai struct uld_msix_info { 78794cdb8bbSHariprasad Shenai unsigned short vec; 78894cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 78994cdb8bbSHariprasad Shenai }; 79094cdb8bbSHariprasad Shenai 791f7917c00SJeff Kirsher struct adapter { 792f7917c00SJeff Kirsher void __iomem *regs; 79322adfe0aSSantosh Rastapur void __iomem *bar2; 7940abfd152SHariprasad Shenai u32 t4_bar0; 795f7917c00SJeff Kirsher struct pci_dev *pdev; 796f7917c00SJeff Kirsher struct device *pdev_dev; 7970de72738SHariprasad Shenai const char *name; 7983069ee9bSVipul Pandya unsigned int mbox; 799b2612722SHariprasad Shenai unsigned int pf; 800f7917c00SJeff Kirsher unsigned int flags; 8012422d9a3SSantosh Rastapur enum chip_type chip; 802f7917c00SJeff Kirsher 803f7917c00SJeff Kirsher int msg_enable; 804f7917c00SJeff Kirsher 805f7917c00SJeff Kirsher struct adapter_params params; 806f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 807f7917c00SJeff Kirsher unsigned int swintr; 808f7917c00SJeff Kirsher 809f7917c00SJeff Kirsher struct { 810f7917c00SJeff Kirsher unsigned short vec; 811f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 812f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 81394cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 81494cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 81594cdb8bbSHariprasad Shenai unsigned int msi_idx; 816f7917c00SJeff Kirsher 817a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 818f7917c00SJeff Kirsher struct sge sge; 819f7917c00SJeff Kirsher 820f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 821f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 822f7917c00SJeff Kirsher 823793dad94SVipul Pandya u32 filter_mode; 824636f9d37SVipul Pandya unsigned int l2t_start; 825636f9d37SVipul Pandya unsigned int l2t_end; 826f7917c00SJeff Kirsher struct l2t_data *l2t; 827b5a02f50SAnish Bhatt unsigned int clipt_start; 828b5a02f50SAnish Bhatt unsigned int clipt_end; 829b5a02f50SAnish Bhatt struct clip_tbl *clipt; 83094cdb8bbSHariprasad Shenai struct cxgb4_pci_uld_info *uld; 831f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 83294cdb8bbSHariprasad Shenai unsigned int num_uld; 833f7917c00SJeff Kirsher struct list_head list_node; 83401bcca68SVipul Pandya struct list_head rcu_node; 835fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 836f7917c00SJeff Kirsher 8377714cb9eSVarun Prakash void *iscsi_ppm; 8387714cb9eSVarun Prakash 839f7917c00SJeff Kirsher struct tid_info tids; 840f7917c00SJeff Kirsher void **tid_release_head; 841f7917c00SJeff Kirsher spinlock_t tid_release_lock; 84229aaee65SAnish Bhatt struct workqueue_struct *workq; 843f7917c00SJeff Kirsher struct work_struct tid_release_task; 844881806bcSVipul Pandya struct work_struct db_full_task; 845881806bcSVipul Pandya struct work_struct db_drop_task; 846f7917c00SJeff Kirsher bool tid_release_task_busy; 847f7917c00SJeff Kirsher 8487f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 8497f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 8507f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 8517f080c3fSHariprasad Shenai 852f7917c00SJeff Kirsher struct dentry *debugfs_root; 853621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 854621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 8558e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 8568e3d04fdSHariprasad Shenai * used for all 4 filters. 8578e3d04fdSHariprasad Shenai */ 858f7917c00SJeff Kirsher 859f7917c00SJeff Kirsher spinlock_t stats_lock; 860fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 861f7917c00SJeff Kirsher }; 862f7917c00SJeff Kirsher 863b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 864b72a32daSRahul Lakkireddy * programmed with various parameters. 865b72a32daSRahul Lakkireddy */ 866b72a32daSRahul Lakkireddy struct ch_sched_params { 867b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 868b72a32daSRahul Lakkireddy union { 869b72a32daSRahul Lakkireddy struct { 870b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 871b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 872b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 873b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 874b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 875b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 876b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 877b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 878b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 879b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 880b72a32daSRahul Lakkireddy } params; 881b72a32daSRahul Lakkireddy } u; 882b72a32daSRahul Lakkireddy }; 883b72a32daSRahul Lakkireddy 8846cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 8856cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 8866cede1f1SRahul Lakkireddy */ 8876cede1f1SRahul Lakkireddy struct ch_sched_queue { 8886cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 8896cede1f1SRahul Lakkireddy s8 class; /* class index */ 8906cede1f1SRahul Lakkireddy }; 8916cede1f1SRahul Lakkireddy 892f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 893f2b7e78dSVipul Pandya */ 894f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 895f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 896f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 897f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 898f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 899f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 900f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 901f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 902f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 903f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 904f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 905f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 906f2b7e78dSVipul Pandya 907f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 908f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 909f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 910f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 911f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 912f2b7e78dSVipul Pandya * matching rules are true. 913f2b7e78dSVipul Pandya * 914f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 915f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 916f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 917f2b7e78dSVipul Pandya * MPS match type) ... 918f2b7e78dSVipul Pandya * 919f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 920f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 921f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 922f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 923f2b7e78dSVipul Pandya */ 924f2b7e78dSVipul Pandya struct ch_filter_tuple { 925f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 926f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 927f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 928f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 929f2b7e78dSVipul Pandya * set of fields. 930f2b7e78dSVipul Pandya */ 931f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 932f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 933f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 934f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 935f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 936f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 937f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 938f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 939f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 940f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 941f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 942f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 943f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 944f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 945f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 946f2b7e78dSVipul Pandya 947f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 948f2b7e78dSVipul Pandya * available for field rules. 949f2b7e78dSVipul Pandya */ 950f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 951f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 952f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 953f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 954f2b7e78dSVipul Pandya }; 955f2b7e78dSVipul Pandya 956f2b7e78dSVipul Pandya /* A filter ioctl command. 957f2b7e78dSVipul Pandya */ 958f2b7e78dSVipul Pandya struct ch_filter_specification { 959f2b7e78dSVipul Pandya /* Administrative fields for filter. 960f2b7e78dSVipul Pandya */ 961f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 962f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 963f2b7e78dSVipul Pandya 964f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 965f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 966f2b7e78dSVipul Pandya */ 967f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 968f2b7e78dSVipul Pandya 969f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 970f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 971f2b7e78dSVipul Pandya * out as egress packets. 972f2b7e78dSVipul Pandya */ 973f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 974f2b7e78dSVipul Pandya 975f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 976f2b7e78dSVipul Pandya 977f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 978f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 979f2b7e78dSVipul Pandya 980f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 981f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 982f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 983f2b7e78dSVipul Pandya 984f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 985f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 986f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 987f2b7e78dSVipul Pandya */ 988f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 989f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 990f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 991f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 992f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 993f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 994f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 995f2b7e78dSVipul Pandya 996f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 997f2b7e78dSVipul Pandya */ 998f2b7e78dSVipul Pandya struct ch_filter_tuple val; 999f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1000f2b7e78dSVipul Pandya }; 1001f2b7e78dSVipul Pandya 1002f2b7e78dSVipul Pandya enum { 1003f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1004f2b7e78dSVipul Pandya FILTER_DROP, 1005f2b7e78dSVipul Pandya FILTER_SWITCH 1006f2b7e78dSVipul Pandya }; 1007f2b7e78dSVipul Pandya 1008f2b7e78dSVipul Pandya enum { 1009f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1010f2b7e78dSVipul Pandya VLAN_REMOVE, 1011f2b7e78dSVipul Pandya VLAN_INSERT, 1012f2b7e78dSVipul Pandya VLAN_REWRITE 1013f2b7e78dSVipul Pandya }; 1014f2b7e78dSVipul Pandya 1015a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1016a4cfd929SHariprasad Shenai { 1017a4cfd929SHariprasad Shenai return adap->params.offload; 1018a4cfd929SHariprasad Shenai } 1019a4cfd929SHariprasad Shenai 102094cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 102194cdb8bbSHariprasad Shenai { 102294cdb8bbSHariprasad Shenai return adap->params.crypto; 102394cdb8bbSHariprasad Shenai } 102494cdb8bbSHariprasad Shenai 1025f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1026f7917c00SJeff Kirsher { 1027f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1028f7917c00SJeff Kirsher } 1029f7917c00SJeff Kirsher 1030f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1031f7917c00SJeff Kirsher { 1032f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1033f7917c00SJeff Kirsher } 1034f7917c00SJeff Kirsher 1035f7917c00SJeff Kirsher #ifndef readq 1036f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1037f7917c00SJeff Kirsher { 1038f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1039f7917c00SJeff Kirsher } 1040f7917c00SJeff Kirsher 1041f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1042f7917c00SJeff Kirsher { 1043f7917c00SJeff Kirsher writel(val, addr); 1044f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1045f7917c00SJeff Kirsher } 1046f7917c00SJeff Kirsher #endif 1047f7917c00SJeff Kirsher 1048f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1049f7917c00SJeff Kirsher { 1050f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1051f7917c00SJeff Kirsher } 1052f7917c00SJeff Kirsher 1053f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1054f7917c00SJeff Kirsher { 1055f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1056f7917c00SJeff Kirsher } 1057f7917c00SJeff Kirsher 1058f7917c00SJeff Kirsher /** 1059098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1060098ef6c2SHariprasad Shenai * @adapter: the adapter 1061098ef6c2SHariprasad Shenai * @port_idx: the port index 1062098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1063098ef6c2SHariprasad Shenai * 1064098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1065098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1066098ef6c2SHariprasad Shenai */ 1067098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1068098ef6c2SHariprasad Shenai u8 hw_addr[]) 1069098ef6c2SHariprasad Shenai { 1070098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1071098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1072098ef6c2SHariprasad Shenai } 1073098ef6c2SHariprasad Shenai 1074098ef6c2SHariprasad Shenai /** 1075f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1076f7917c00SJeff Kirsher * @dev: the netdev 1077f7917c00SJeff Kirsher * 1078f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1079f7917c00SJeff Kirsher */ 1080f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1081f7917c00SJeff Kirsher { 1082f7917c00SJeff Kirsher return netdev_priv(dev); 1083f7917c00SJeff Kirsher } 1084f7917c00SJeff Kirsher 1085f7917c00SJeff Kirsher /** 1086f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1087f7917c00SJeff Kirsher * @adap: the adapter 1088f7917c00SJeff Kirsher * @idx: the port index 1089f7917c00SJeff Kirsher * 1090f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1091f7917c00SJeff Kirsher */ 1092f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1093f7917c00SJeff Kirsher { 1094f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1095f7917c00SJeff Kirsher } 1096f7917c00SJeff Kirsher 1097f7917c00SJeff Kirsher /** 1098f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1099f7917c00SJeff Kirsher * @dev: the netdev 1100f7917c00SJeff Kirsher * 1101f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1102f7917c00SJeff Kirsher */ 1103f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1104f7917c00SJeff Kirsher { 1105f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1106f7917c00SJeff Kirsher } 1107f7917c00SJeff Kirsher 11083a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 11093a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 11103a336cb1SHariprasad Shenai { 11113a336cb1SHariprasad Shenai spin_lock_init(&q->bpoll_lock); 11123a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 11133a336cb1SHariprasad Shenai } 11143a336cb1SHariprasad Shenai 11153a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 11163a336cb1SHariprasad Shenai { 11173a336cb1SHariprasad Shenai bool rc = true; 11183a336cb1SHariprasad Shenai 11193a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 11203a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 11213a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 11223a336cb1SHariprasad Shenai rc = false; 11233a336cb1SHariprasad Shenai } else { 11243a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_NAPI; 11253a336cb1SHariprasad Shenai } 11263a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 11273a336cb1SHariprasad Shenai return rc; 11283a336cb1SHariprasad Shenai } 11293a336cb1SHariprasad Shenai 11303a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 11313a336cb1SHariprasad Shenai { 11323a336cb1SHariprasad Shenai bool rc = false; 11333a336cb1SHariprasad Shenai 11343a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 11353a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 11363a336cb1SHariprasad Shenai rc = true; 11373a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 11383a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 11393a336cb1SHariprasad Shenai return rc; 11403a336cb1SHariprasad Shenai } 11413a336cb1SHariprasad Shenai 11423a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 11433a336cb1SHariprasad Shenai { 11443a336cb1SHariprasad Shenai bool rc = true; 11453a336cb1SHariprasad Shenai 11463a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 11473a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 11483a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 11493a336cb1SHariprasad Shenai rc = false; 11503a336cb1SHariprasad Shenai } else { 11513a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL; 11523a336cb1SHariprasad Shenai } 11533a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 11543a336cb1SHariprasad Shenai return rc; 11553a336cb1SHariprasad Shenai } 11563a336cb1SHariprasad Shenai 11573a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 11583a336cb1SHariprasad Shenai { 11593a336cb1SHariprasad Shenai bool rc = false; 11603a336cb1SHariprasad Shenai 11613a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 11623a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 11633a336cb1SHariprasad Shenai rc = true; 11643a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 11653a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 11663a336cb1SHariprasad Shenai return rc; 11673a336cb1SHariprasad Shenai } 11683a336cb1SHariprasad Shenai 11693a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 11703a336cb1SHariprasad Shenai { 11713a336cb1SHariprasad Shenai return q->bpoll_state & CXGB_POLL_USER_PEND; 11723a336cb1SHariprasad Shenai } 11733a336cb1SHariprasad Shenai #else 11743a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 11753a336cb1SHariprasad Shenai { 11763a336cb1SHariprasad Shenai } 11773a336cb1SHariprasad Shenai 11783a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 11793a336cb1SHariprasad Shenai { 11803a336cb1SHariprasad Shenai return true; 11813a336cb1SHariprasad Shenai } 11823a336cb1SHariprasad Shenai 11833a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 11843a336cb1SHariprasad Shenai { 11853a336cb1SHariprasad Shenai return false; 11863a336cb1SHariprasad Shenai } 11873a336cb1SHariprasad Shenai 11883a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 11893a336cb1SHariprasad Shenai { 11903a336cb1SHariprasad Shenai return false; 11913a336cb1SHariprasad Shenai } 11923a336cb1SHariprasad Shenai 11933a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 11943a336cb1SHariprasad Shenai { 11953a336cb1SHariprasad Shenai return false; 11963a336cb1SHariprasad Shenai } 11973a336cb1SHariprasad Shenai 11983a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 11993a336cb1SHariprasad Shenai { 12003a336cb1SHariprasad Shenai return false; 12013a336cb1SHariprasad Shenai } 12023a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 12033a336cb1SHariprasad Shenai 1204812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1205812034f1SHariprasad Shenai * - bits 0..9: chip version 1206812034f1SHariprasad Shenai * - bits 10..15: chip revision 1207812034f1SHariprasad Shenai * - bits 16..23: register dump version 1208812034f1SHariprasad Shenai */ 1209812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1210812034f1SHariprasad Shenai { 1211812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1212812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1213812034f1SHariprasad Shenai } 1214812034f1SHariprasad Shenai 1215812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1216812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1217812034f1SHariprasad Shenai const struct sge_rspq *q) 1218812034f1SHariprasad Shenai { 1219812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1220812034f1SHariprasad Shenai 1221812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1222812034f1SHariprasad Shenai } 1223812034f1SHariprasad Shenai 1224812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1225812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1226812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1227812034f1SHariprasad Shenai 1228f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1229f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1230f7917c00SJeff Kirsher 1231f7917c00SJeff Kirsher void *t4_alloc_mem(size_t size); 1232f7917c00SJeff Kirsher 1233f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 12345fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1235f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1236f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1237f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1238f7917c00SJeff Kirsher const struct pkt_gl *gl); 1239f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1240f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1241f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1242f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 12432337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 12442337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1245f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1246f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1247f7917c00SJeff Kirsher unsigned int iqid); 1248f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1249f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1250f7917c00SJeff Kirsher unsigned int cmplqid); 1251f7917c00SJeff Kirsher int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1252f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid); 1253f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 125452367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1255f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1256f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 12573a336cb1SHariprasad Shenai int cxgb_busy_poll(struct napi_struct *napi); 1258812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1259812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 12603069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1261f7917c00SJeff Kirsher 1262f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1263f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1264f7917c00SJeff Kirsher 12659a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 12669a4da2cdSVipul Pandya { 12679a4da2cdSVipul Pandya return adap->params.bypass; 12689a4da2cdSVipul Pandya } 12699a4da2cdSVipul Pandya 12709a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 12719a4da2cdSVipul Pandya { 12729a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 12739a4da2cdSVipul Pandya switch (device) { 12749a4da2cdSVipul Pandya case 0x440b: 12759a4da2cdSVipul Pandya case 0x440c: 12769a4da2cdSVipul Pandya return 1; 12779a4da2cdSVipul Pandya default: 12789a4da2cdSVipul Pandya return 0; 12799a4da2cdSVipul Pandya } 12809a4da2cdSVipul Pandya } 12819a4da2cdSVipul Pandya 128201b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 128301b69614SHariprasad Shenai { 128401b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 128501b69614SHariprasad Shenai switch (device) { 128601b69614SHariprasad Shenai case 0x4409: 128701b69614SHariprasad Shenai case 0x4486: 128801b69614SHariprasad Shenai return 1; 128901b69614SHariprasad Shenai 129001b69614SHariprasad Shenai default: 129101b69614SHariprasad Shenai return 0; 129201b69614SHariprasad Shenai } 129301b69614SHariprasad Shenai } 129401b69614SHariprasad Shenai 1295f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1296f7917c00SJeff Kirsher { 1297f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1298f7917c00SJeff Kirsher } 1299f7917c00SJeff Kirsher 1300f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1301f7917c00SJeff Kirsher unsigned int us) 1302f7917c00SJeff Kirsher { 1303f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1304f7917c00SJeff Kirsher } 1305f7917c00SJeff Kirsher 130652367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 130752367a76SVipul Pandya unsigned int ticks) 130852367a76SVipul Pandya { 130952367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 131052367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 131152367a76SVipul Pandya adapter->params.vpd.cclk); 131252367a76SVipul Pandya } 131352367a76SVipul Pandya 1314f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1315f7917c00SJeff Kirsher u32 val); 1316f7917c00SJeff Kirsher 131701b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 131801b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1319f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1320f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1321f7917c00SJeff Kirsher 132201b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 132301b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 132401b69614SHariprasad Shenai int timeout) 132501b69614SHariprasad Shenai { 132601b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 132701b69614SHariprasad Shenai timeout); 132801b69614SHariprasad Shenai } 132901b69614SHariprasad Shenai 1330f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1331f7917c00SJeff Kirsher int size, void *rpl) 1332f7917c00SJeff Kirsher { 1333f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1334f7917c00SJeff Kirsher } 1335f7917c00SJeff Kirsher 1336f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1337f7917c00SJeff Kirsher int size, void *rpl) 1338f7917c00SJeff Kirsher { 1339f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1340f7917c00SJeff Kirsher } 1341f7917c00SJeff Kirsher 1342fc08a01aSHariprasad Shenai /** 1343fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1344fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1345fc08a01aSHariprasad Shenai * 1346fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1347fc08a01aSHariprasad Shenai * (hash) address matching. 1348fc08a01aSHariprasad Shenai */ 1349fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1350fc08a01aSHariprasad Shenai { 1351fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1352fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1353fc08a01aSHariprasad Shenai 1354fc08a01aSHariprasad Shenai a ^= b; 1355fc08a01aSHariprasad Shenai a ^= (a >> 12); 1356fc08a01aSHariprasad Shenai a ^= (a >> 6); 1357fc08a01aSHariprasad Shenai return a & 0x3f; 1358fc08a01aSHariprasad Shenai } 1359fc08a01aSHariprasad Shenai 136094cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 136194cdb8bbSHariprasad Shenai unsigned int cnt); 136294cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 136394cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 136494cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 136594cdb8bbSHariprasad Shenai { 136694cdb8bbSHariprasad Shenai q->adap = adap; 136794cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 136894cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 136994cdb8bbSHariprasad Shenai q->size = size; 137094cdb8bbSHariprasad Shenai } 137194cdb8bbSHariprasad Shenai 137213ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 137313ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 137413ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1375f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1376f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1377f2b7e78dSVipul Pandya unsigned int start_idx); 13780abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1379f2b7e78dSVipul Pandya 1380f2b7e78dSVipul Pandya struct fw_filter_wr; 1381f2b7e78dSVipul Pandya 1382f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1383f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1384f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1385f7917c00SJeff Kirsher 13868203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 13874036da90SHariprasad Shenai int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1388f7917c00SJeff Kirsher struct link_config *lc); 1389f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1390fc5ab020SHariprasad Shenai 1391b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1392b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1393b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1394b562fc37SHariprasad Shenai 1395fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1396fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1397fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1398f01aa633SHariprasad Shenai void *buf, int dir); 1399fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1400fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1401fc5ab020SHariprasad Shenai { 1402fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1403fc5ab020SHariprasad Shenai } 1404fc5ab020SHariprasad Shenai 1405812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1406812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1407812034f1SHariprasad Shenai 1408f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1409098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1410098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 141149216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 141249216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1413f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 141401b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 141501b69614SHariprasad Shenai int win, spinlock_t *lock, 141601b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 141701b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 141801b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 141949216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 142022c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 142122c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1422acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1423636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1424a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 142516e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 14260de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 142716e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1428ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 142916e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 143016e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 143116e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1432f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 1433e85c9a7aSHariprasad Shenai 1434e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1435b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1436e85c9a7aSHariprasad Shenai unsigned int qid, 1437e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 143866cf188eSHariprasad S int user, 1439e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1440e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1441e85c9a7aSHariprasad Shenai 1442dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1443dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1444ae469b68SHariprasad Shenai 1445ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1446e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 1447dcf7b6f5SKumar Sanghvi int t4_init_tp_params(struct adapter *adap); 1448dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1449c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1450c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1451c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1452f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1453f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1454f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1455f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1456f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1457f7917c00SJeff Kirsher unsigned int flags); 1458c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1459c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1460688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 1461688ea5feSHariprasad Shenai void t4_read_rss_key(struct adapter *adapter, u32 *key); 1462688ea5feSHariprasad Shenai void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1463688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1464688ea5feSHariprasad Shenai u32 *valp); 1465688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1466688ea5feSHariprasad Shenai u32 *vfl, u32 *vfh); 1467688ea5feSHariprasad Shenai u32 t4_read_rss_pf_map(struct adapter *adapter); 1468688ea5feSHariprasad Shenai u32 t4_read_rss_pf_mask(struct adapter *adapter); 1469688ea5feSHariprasad Shenai 1470145ef8a5SHariprasad Shenai unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1471b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1472b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1473e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1474e5f0e43bSHariprasad Shenai size_t n); 1475c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1476c778af7dSHariprasad Shenai size_t n); 1477f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1478f1ff24aaSHariprasad Shenai unsigned int *valp); 1479f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1480f1ff24aaSHariprasad Shenai const unsigned int *valp); 1481f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 148219689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 148319689609SHariprasad Shenai unsigned int *pif_req_wrptr, 148419689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 148526fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 148674b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 148772aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1488f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1489a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1490a4cfd929SHariprasad Shenai struct port_stats *stats, 1491a4cfd929SHariprasad Shenai struct port_stats *offset); 149265046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1493f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1494bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1495636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1496636f9d37SVipul Pandya unsigned int mask, unsigned int val); 14972d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1498a4cfd929SHariprasad Shenai void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1499a6222975SHariprasad Shenai void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1500a4cfd929SHariprasad Shenai void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1501a4cfd929SHariprasad Shenai void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1502f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1503f7917c00SJeff Kirsher struct tp_tcp_stats *v6); 1504a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1505a6222975SHariprasad Shenai struct tp_fcoe_stats *st); 1506f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1507f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1508f7917c00SJeff Kirsher 1509797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1510797ff0f5SHariprasad Shenai 15117864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1512f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1513f2b7e78dSVipul Pandya 1514f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1515f7917c00SJeff Kirsher const u8 *addr); 1516f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1517f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1518f7917c00SJeff Kirsher 1519f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1520f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1521f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1522f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1523f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1524636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1525636f9d37SVipul Pandya unsigned int cache_line_size); 1526636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1527f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1528f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1529f7917c00SJeff Kirsher u32 *val); 153001b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1531f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 153201b69614SHariprasad Shenai u32 *val, int rw); 153301b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1534688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1535688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 153601b69614SHariprasad Shenai const u32 *val, int timeout); 153701b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 153801b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1539688848b1SAnish Bhatt const u32 *val); 1540f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1541f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1542f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1543f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1544f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1545f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1546f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1547f7917c00SJeff Kirsher unsigned int *rss_size); 15484f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 15494f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 15504f3a0fcfSHariprasad Shenai unsigned int viid); 1551f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1552f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1553f7917c00SJeff Kirsher bool sleep_ok); 1554f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1555f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1556f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1557fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1558fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1559fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1560f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1561f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1562f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1563f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1564688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1565688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1566f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1567f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1568f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1569f7917c00SJeff Kirsher unsigned int nblinks); 1570f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1571f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1572f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1573f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1574ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1575ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1576ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1577f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1578f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1579f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1580f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1581f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1582f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1583f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1584f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1585f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 15865d700ecbSHariprasad Shenai int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 158723853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1588f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1589881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1590881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 15918e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 15928e3d04fdSHariprasad Shenai int filter_index, int enable); 15938e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 15948e3d04fdSHariprasad Shenai int filter_index, int *enabled); 15958caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 15968caa1e84SVipul Pandya u32 addr, u32 val); 1597b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1598b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1599b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 160068bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1601fd88b31aSHariprasad Shenai void t4_free_mem(void *addr); 1602a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1603a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1604a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1605a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1606a3bfb617SHariprasad Shenai int hz, int ticks); 1607858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1608858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 160994cdb8bbSHariprasad Shenai void uld_mem_free(struct adapter *adap); 161094cdb8bbSHariprasad Shenai int uld_mem_alloc(struct adapter *adap); 161194cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1612f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1613