1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4ce100b8bSAnish Bhatt * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49f7917c00SJeff Kirsher #include <asm/io.h> 50f7917c00SJeff Kirsher #include "cxgb4_uld.h" 51f7917c00SJeff Kirsher 523069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 533069ee9bSVipul Pandya 54f7917c00SJeff Kirsher enum { 55f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 56f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 57f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 58f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 59a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 60f7917c00SJeff Kirsher }; 61f7917c00SJeff Kirsher 62f7917c00SJeff Kirsher enum { 63812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 64812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 65812034f1SHariprasad Shenai }; 66812034f1SHariprasad Shenai 67812034f1SHariprasad Shenai enum { 68f7917c00SJeff Kirsher MEM_EDC0, 69f7917c00SJeff Kirsher MEM_EDC1, 702422d9a3SSantosh Rastapur MEM_MC, 712422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 722422d9a3SSantosh Rastapur MEM_MC1 73f7917c00SJeff Kirsher }; 74f7917c00SJeff Kirsher 753069ee9bSVipul Pandya enum { 763eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 773eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 783069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 793069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 802422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 813eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 823eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 830abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 840abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 853069ee9bSVipul Pandya }; 863069ee9bSVipul Pandya 87f7917c00SJeff Kirsher enum dev_master { 88f7917c00SJeff Kirsher MASTER_CANT, 89f7917c00SJeff Kirsher MASTER_MAY, 90f7917c00SJeff Kirsher MASTER_MUST 91f7917c00SJeff Kirsher }; 92f7917c00SJeff Kirsher 93f7917c00SJeff Kirsher enum dev_state { 94f7917c00SJeff Kirsher DEV_STATE_UNINIT, 95f7917c00SJeff Kirsher DEV_STATE_INIT, 96f7917c00SJeff Kirsher DEV_STATE_ERR 97f7917c00SJeff Kirsher }; 98f7917c00SJeff Kirsher 99f7917c00SJeff Kirsher enum { 100f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 101f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 102f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 103f7917c00SJeff Kirsher }; 104f7917c00SJeff Kirsher 105f7917c00SJeff Kirsher struct port_stats { 106f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 107f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 108f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 109f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 110f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 111f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 112f7917c00SJeff Kirsher 113f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 114f7917c00SJeff Kirsher u64 tx_frames_65_127; 115f7917c00SJeff Kirsher u64 tx_frames_128_255; 116f7917c00SJeff Kirsher u64 tx_frames_256_511; 117f7917c00SJeff Kirsher u64 tx_frames_512_1023; 118f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 119f7917c00SJeff Kirsher u64 tx_frames_1519_max; 120f7917c00SJeff Kirsher 121f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 122f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 123f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 124f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 125f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 126f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 127f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 128f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 129f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 130f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 131f7917c00SJeff Kirsher 132f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 133f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 134f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 135f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 136f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 137f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 138f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 139f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 140f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 141f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 142f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 143f7917c00SJeff Kirsher 144f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 145f7917c00SJeff Kirsher u64 rx_frames_65_127; 146f7917c00SJeff Kirsher u64 rx_frames_128_255; 147f7917c00SJeff Kirsher u64 rx_frames_256_511; 148f7917c00SJeff Kirsher u64 rx_frames_512_1023; 149f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 150f7917c00SJeff Kirsher u64 rx_frames_1519_max; 151f7917c00SJeff Kirsher 152f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 153f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 154f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 155f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 156f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 157f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 158f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 159f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 160f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 161f7917c00SJeff Kirsher 162f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 163f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 164f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 165f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 166f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 167f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 168f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 169f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 170f7917c00SJeff Kirsher }; 171f7917c00SJeff Kirsher 172f7917c00SJeff Kirsher struct lb_port_stats { 173f7917c00SJeff Kirsher u64 octets; 174f7917c00SJeff Kirsher u64 frames; 175f7917c00SJeff Kirsher u64 bcast_frames; 176f7917c00SJeff Kirsher u64 mcast_frames; 177f7917c00SJeff Kirsher u64 ucast_frames; 178f7917c00SJeff Kirsher u64 error_frames; 179f7917c00SJeff Kirsher 180f7917c00SJeff Kirsher u64 frames_64; 181f7917c00SJeff Kirsher u64 frames_65_127; 182f7917c00SJeff Kirsher u64 frames_128_255; 183f7917c00SJeff Kirsher u64 frames_256_511; 184f7917c00SJeff Kirsher u64 frames_512_1023; 185f7917c00SJeff Kirsher u64 frames_1024_1518; 186f7917c00SJeff Kirsher u64 frames_1519_max; 187f7917c00SJeff Kirsher 188f7917c00SJeff Kirsher u64 drop; 189f7917c00SJeff Kirsher 190f7917c00SJeff Kirsher u64 ovflow0; 191f7917c00SJeff Kirsher u64 ovflow1; 192f7917c00SJeff Kirsher u64 ovflow2; 193f7917c00SJeff Kirsher u64 ovflow3; 194f7917c00SJeff Kirsher u64 trunc0; 195f7917c00SJeff Kirsher u64 trunc1; 196f7917c00SJeff Kirsher u64 trunc2; 197f7917c00SJeff Kirsher u64 trunc3; 198f7917c00SJeff Kirsher }; 199f7917c00SJeff Kirsher 200f7917c00SJeff Kirsher struct tp_tcp_stats { 201a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 202a4cfd929SHariprasad Shenai u64 tcp_in_segs; 203a4cfd929SHariprasad Shenai u64 tcp_out_segs; 204a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 205a4cfd929SHariprasad Shenai }; 206a4cfd929SHariprasad Shenai 207a4cfd929SHariprasad Shenai struct tp_usm_stats { 208a4cfd929SHariprasad Shenai u32 frames; 209a4cfd929SHariprasad Shenai u32 drops; 210a4cfd929SHariprasad Shenai u64 octets; 211f7917c00SJeff Kirsher }; 212f7917c00SJeff Kirsher 213a6222975SHariprasad Shenai struct tp_fcoe_stats { 214a6222975SHariprasad Shenai u32 frames_ddp; 215a6222975SHariprasad Shenai u32 frames_drop; 216a6222975SHariprasad Shenai u64 octets_ddp; 217a6222975SHariprasad Shenai }; 218a6222975SHariprasad Shenai 219f7917c00SJeff Kirsher struct tp_err_stats { 220a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 221a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 222a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 223a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 224a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 225a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 226a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 227a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 228a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 229a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 230a4cfd929SHariprasad Shenai }; 231a4cfd929SHariprasad Shenai 232a6222975SHariprasad Shenai struct tp_cpl_stats { 233a6222975SHariprasad Shenai u32 req[4]; 234a6222975SHariprasad Shenai u32 rsp[4]; 235a6222975SHariprasad Shenai }; 236a6222975SHariprasad Shenai 237a4cfd929SHariprasad Shenai struct tp_rdma_stats { 238a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 239a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 240f7917c00SJeff Kirsher }; 241f7917c00SJeff Kirsher 242e85c9a7aSHariprasad Shenai struct sge_params { 243e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 244e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 245e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 246e85c9a7aSHariprasad Shenai }; 247e85c9a7aSHariprasad Shenai 248f7917c00SJeff Kirsher struct tp_params { 249f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2502d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 251dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 252dca4faebSVipul Pandya /* channel map */ 253636f9d37SVipul Pandya 254636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 255636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 256dcf7b6f5SKumar Sanghvi 257dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 258dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 259dcf7b6f5SKumar Sanghvi 260dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 261dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 262dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 263dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 264dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 265dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 266dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 267dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 268dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 269dcf7b6f5SKumar Sanghvi * present. 270dcf7b6f5SKumar Sanghvi */ 271dcf7b6f5SKumar Sanghvi int vlan_shift; 272dcf7b6f5SKumar Sanghvi int vnic_shift; 273dcf7b6f5SKumar Sanghvi int port_shift; 274dcf7b6f5SKumar Sanghvi int protocol_shift; 275f7917c00SJeff Kirsher }; 276f7917c00SJeff Kirsher 277f7917c00SJeff Kirsher struct vpd_params { 278f7917c00SJeff Kirsher unsigned int cclk; 279f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 280f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 281f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 282a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 283f7917c00SJeff Kirsher }; 284f7917c00SJeff Kirsher 285f7917c00SJeff Kirsher struct pci_params { 286f7917c00SJeff Kirsher unsigned char speed; 287f7917c00SJeff Kirsher unsigned char width; 288f7917c00SJeff Kirsher }; 289f7917c00SJeff Kirsher 290d14807ddSHariprasad Shenai #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) 291d14807ddSHariprasad Shenai #define CHELSIO_CHIP_FPGA 0x100 292d14807ddSHariprasad Shenai #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) 293d14807ddSHariprasad Shenai #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) 294d14807ddSHariprasad Shenai 295d14807ddSHariprasad Shenai #define CHELSIO_T4 0x4 296d14807ddSHariprasad Shenai #define CHELSIO_T5 0x5 297ab4b583bSHariprasad Shenai #define CHELSIO_T6 0x6 298d14807ddSHariprasad Shenai 299d14807ddSHariprasad Shenai enum chip_type { 300d14807ddSHariprasad Shenai T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 301d14807ddSHariprasad Shenai T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), 302d14807ddSHariprasad Shenai T4_FIRST_REV = T4_A1, 303d14807ddSHariprasad Shenai T4_LAST_REV = T4_A2, 304d14807ddSHariprasad Shenai 305d14807ddSHariprasad Shenai T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 306d14807ddSHariprasad Shenai T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), 307d14807ddSHariprasad Shenai T5_FIRST_REV = T5_A0, 308d14807ddSHariprasad Shenai T5_LAST_REV = T5_A1, 309ab4b583bSHariprasad Shenai 310ab4b583bSHariprasad Shenai T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0), 311ab4b583bSHariprasad Shenai T6_FIRST_REV = T6_A0, 312ab4b583bSHariprasad Shenai T6_LAST_REV = T6_A0, 313d14807ddSHariprasad Shenai }; 314d14807ddSHariprasad Shenai 31549aa284fSHariprasad Shenai struct devlog_params { 31649aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 31749aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 31849aa284fSHariprasad Shenai u32 size; /* size of log */ 31949aa284fSHariprasad Shenai }; 32049aa284fSHariprasad Shenai 3213ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3223ccc6cf7SHariprasad Shenai struct arch_specific_params { 3233ccc6cf7SHariprasad Shenai u8 nchan; 3243ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3253ccc6cf7SHariprasad Shenai u16 vfcount; 3263ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3273ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3283ccc6cf7SHariprasad Shenai }; 3293ccc6cf7SHariprasad Shenai 330f7917c00SJeff Kirsher struct adapter_params { 331e85c9a7aSHariprasad Shenai struct sge_params sge; 332f7917c00SJeff Kirsher struct tp_params tp; 333f7917c00SJeff Kirsher struct vpd_params vpd; 334f7917c00SJeff Kirsher struct pci_params pci; 33549aa284fSHariprasad Shenai struct devlog_params devlog; 33649aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 337f7917c00SJeff Kirsher 338f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 339f1ff24aaSHariprasad Shenai 340f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 341f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 342f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 343f7917c00SJeff Kirsher 344f7917c00SJeff Kirsher unsigned int fw_vers; 345f7917c00SJeff Kirsher unsigned int tp_vers; 346f7917c00SJeff Kirsher u8 api_vers[7]; 347f7917c00SJeff Kirsher 348f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 349f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 350f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 351f7917c00SJeff Kirsher 352f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 353f7917c00SJeff Kirsher unsigned char portvec; 354d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3553ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 356f7917c00SJeff Kirsher unsigned char offload; 357f7917c00SJeff Kirsher 3589a4da2cdSVipul Pandya unsigned char bypass; 3599a4da2cdSVipul Pandya 360f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3611ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3624c2c5763SHariprasad Shenai 3634c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3644c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 365f7917c00SJeff Kirsher }; 366f7917c00SJeff Kirsher 367a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 368a3bfb617SHariprasad Shenai * and possible hangs. 369a3bfb617SHariprasad Shenai */ 370a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 371a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 372a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 373a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 374a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 375a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 376a3bfb617SHariprasad Shenai }; 377a3bfb617SHariprasad Shenai 37816e47624SHariprasad Shenai #include "t4fw_api.h" 37916e47624SHariprasad Shenai 38016e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 381b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 382b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 383b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 384b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 38516e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 38616e47624SHariprasad Shenai 38716e47624SHariprasad Shenai struct fw_info { 38816e47624SHariprasad Shenai u8 chip; 38916e47624SHariprasad Shenai char *fs_name; 39016e47624SHariprasad Shenai char *fw_mod_name; 39116e47624SHariprasad Shenai struct fw_hdr fw_hdr; 39216e47624SHariprasad Shenai }; 39316e47624SHariprasad Shenai 39416e47624SHariprasad Shenai 395f7917c00SJeff Kirsher struct trace_params { 396f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 397f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 398f7917c00SJeff Kirsher unsigned short snap_len; 399f7917c00SJeff Kirsher unsigned short min_len; 400f7917c00SJeff Kirsher unsigned char skip_ofst; 401f7917c00SJeff Kirsher unsigned char skip_len; 402f7917c00SJeff Kirsher unsigned char invert; 403f7917c00SJeff Kirsher unsigned char port; 404f7917c00SJeff Kirsher }; 405f7917c00SJeff Kirsher 406f7917c00SJeff Kirsher struct link_config { 407f7917c00SJeff Kirsher unsigned short supported; /* link capabilities */ 408f7917c00SJeff Kirsher unsigned short advertising; /* advertised capabilities */ 409f7917c00SJeff Kirsher unsigned short requested_speed; /* speed user has requested */ 410f7917c00SJeff Kirsher unsigned short speed; /* actual link speed */ 411f7917c00SJeff Kirsher unsigned char requested_fc; /* flow control user has requested */ 412f7917c00SJeff Kirsher unsigned char fc; /* actual link flow control */ 413f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 414f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 415f7917c00SJeff Kirsher }; 416f7917c00SJeff Kirsher 417e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 418f7917c00SJeff Kirsher 419f7917c00SJeff Kirsher enum { 420f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 421f7917c00SJeff Kirsher MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 422f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 423f7917c00SJeff Kirsher MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 424f36e58e5SHariprasad Shenai MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ 425cf38be6dSHariprasad Shenai MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */ 426f7917c00SJeff Kirsher }; 427f7917c00SJeff Kirsher 428f7917c00SJeff Kirsher enum { 429812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 430812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 431812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 432812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 433812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 434812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 435812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 436812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 437812034f1SHariprasad Shenai }; 438812034f1SHariprasad Shenai 439812034f1SHariprasad Shenai enum { 440cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 441cf38be6dSHariprasad Shenai /* forwarded interrupts */ 442cf38be6dSHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES 443cf38be6dSHariprasad Shenai + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS, 444f7917c00SJeff Kirsher }; 445f7917c00SJeff Kirsher 446f7917c00SJeff Kirsher struct adapter; 447f7917c00SJeff Kirsher struct sge_rspq; 448f7917c00SJeff Kirsher 449688848b1SAnish Bhatt #include "cxgb4_dcb.h" 450688848b1SAnish Bhatt 45176fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 45276fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 45376fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 45476fed8a9SVarun Prakash 455f7917c00SJeff Kirsher struct port_info { 456f7917c00SJeff Kirsher struct adapter *adapter; 457f7917c00SJeff Kirsher u16 viid; 458f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 459f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 460f7917c00SJeff Kirsher s8 mdio_addr; 46140e9de4bSHariprasad Shenai enum fw_port_type port_type; 462f7917c00SJeff Kirsher u8 mod_type; 463f7917c00SJeff Kirsher u8 port_id; 464f7917c00SJeff Kirsher u8 tx_chan; 465f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 466f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 467f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 468f7917c00SJeff Kirsher u8 rss_mode; 469f7917c00SJeff Kirsher struct link_config link_cfg; 470f7917c00SJeff Kirsher u16 *rss; 471a4cfd929SHariprasad Shenai struct port_stats stats_base; 472688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 473688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 474688848b1SAnish Bhatt #endif 47576fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 47676fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 47776fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 478f7917c00SJeff Kirsher }; 479f7917c00SJeff Kirsher 480f7917c00SJeff Kirsher struct dentry; 481f7917c00SJeff Kirsher struct work_struct; 482f7917c00SJeff Kirsher 483f7917c00SJeff Kirsher enum { /* adapter flags */ 484f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 485144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 486144be3d9SGavin Shan USING_MSI = (1 << 2), 487144be3d9SGavin Shan USING_MSIX = (1 << 3), 488f7917c00SJeff Kirsher FW_OK = (1 << 4), 48913ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 49052367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 49152367a76SVipul Pandya MASTER_PF = (1 << 7), 49252367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 493f7917c00SJeff Kirsher }; 494f7917c00SJeff Kirsher 495f7917c00SJeff Kirsher struct rx_sw_desc; 496f7917c00SJeff Kirsher 497f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 498f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 499f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 500f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 501f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 502f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 503f7917c00SJeff Kirsher unsigned long large_alloc_failed; 504f7917c00SJeff Kirsher unsigned long starving; 505f7917c00SJeff Kirsher /* RO fields */ 506f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 507f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 508f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 509f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 510f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 511df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 512df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 513f7917c00SJeff Kirsher }; 514f7917c00SJeff Kirsher 515f7917c00SJeff Kirsher /* A packet gather list */ 516f7917c00SJeff Kirsher struct pkt_gl { 517e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 518f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 519f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 520f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 521f7917c00SJeff Kirsher }; 522f7917c00SJeff Kirsher 523f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 524f7917c00SJeff Kirsher const struct pkt_gl *gl); 525f7917c00SJeff Kirsher 526f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 527f7917c00SJeff Kirsher struct napi_struct napi; 528f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 529f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 530f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 531f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 532f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 533e553ec3fSHariprasad Shenai u8 adaptive_rx; 534f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 535f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 536f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 537f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 538f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 539f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 540f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 541f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 542df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 543df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 544f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 545f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 546f7917c00SJeff Kirsher struct adapter *adap; 547f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 548f7917c00SJeff Kirsher rspq_handler_t handler; 5493a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 5503a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_IDLE 0 5513a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 5523a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 5533a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 5543a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 5553a336cb1SHariprasad Shenai #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 5563a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5573a336cb1SHariprasad Shenai #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 5583a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL) 5593a336cb1SHariprasad Shenai #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 5603a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5613a336cb1SHariprasad Shenai unsigned int bpoll_state; 5623a336cb1SHariprasad Shenai spinlock_t bpoll_lock; /* lock for busy poll */ 5633a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 5643a336cb1SHariprasad Shenai 565f7917c00SJeff Kirsher }; 566f7917c00SJeff Kirsher 567f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 568f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 569f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 570f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 571f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 572f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 573f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 574f7917c00SJeff Kirsher }; 575f7917c00SJeff Kirsher 576f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 577f7917c00SJeff Kirsher struct sge_rspq rspq; 578f7917c00SJeff Kirsher struct sge_fl fl; 579f7917c00SJeff Kirsher struct sge_eth_stats stats; 580f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 581f7917c00SJeff Kirsher 582f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 583f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 584f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 585f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 586f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 587f7917c00SJeff Kirsher }; 588f7917c00SJeff Kirsher 589f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 590f7917c00SJeff Kirsher struct sge_rspq rspq; 591f7917c00SJeff Kirsher struct sge_fl fl; 592f7917c00SJeff Kirsher struct sge_ofld_stats stats; 593f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 594f7917c00SJeff Kirsher 595f7917c00SJeff Kirsher struct tx_desc { 596f7917c00SJeff Kirsher __be64 flit[8]; 597f7917c00SJeff Kirsher }; 598f7917c00SJeff Kirsher 599f7917c00SJeff Kirsher struct tx_sw_desc; 600f7917c00SJeff Kirsher 601f7917c00SJeff Kirsher struct sge_txq { 602f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 603f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 604f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 605f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 606f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 607f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 608f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 609f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 610f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 611f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 612f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 6133069ee9bSVipul Pandya spinlock_t db_lock; 6143069ee9bSVipul Pandya int db_disabled; 6153069ee9bSVipul Pandya unsigned short db_pidx; 61605eb2389SSteve Wise unsigned short db_pidx_inc; 617df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 618df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 619f7917c00SJeff Kirsher }; 620f7917c00SJeff Kirsher 621f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 622f7917c00SJeff Kirsher struct sge_txq q; 623f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 62410b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 62510b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 62610b00466SAnish Bhatt #endif 627f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 628f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 629f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 630f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 631f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 632f7917c00SJeff Kirsher 633f7917c00SJeff Kirsher struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 634f7917c00SJeff Kirsher struct sge_txq q; 635f7917c00SJeff Kirsher struct adapter *adap; 636f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 637f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 638f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 639f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 640f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 641f7917c00SJeff Kirsher 642f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 643f7917c00SJeff Kirsher struct sge_txq q; 644f7917c00SJeff Kirsher struct adapter *adap; 645f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 646f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 647f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 648f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 649f7917c00SJeff Kirsher 650f7917c00SJeff Kirsher struct sge { 651f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 652f7917c00SJeff Kirsher struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 653f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 654f7917c00SJeff Kirsher 655f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 656f7917c00SJeff Kirsher struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 657f7917c00SJeff Kirsher struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 658cf38be6dSHariprasad Shenai struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 659f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 660f7917c00SJeff Kirsher 661f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 662f7917c00SJeff Kirsher spinlock_t intrq_lock; 663f7917c00SJeff Kirsher 664f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 665f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 666f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 667f7917c00SJeff Kirsher u16 ofldqsets; /* # of active offload queue sets */ 668f7917c00SJeff Kirsher u16 rdmaqs; /* # of available RDMA Rx queues */ 669cf38be6dSHariprasad Shenai u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 670f7917c00SJeff Kirsher u16 ofld_rxq[MAX_OFLD_QSETS]; 671f36e58e5SHariprasad Shenai u16 rdma_rxq[MAX_RDMA_QUEUES]; 672f36e58e5SHariprasad Shenai u16 rdma_ciq[MAX_RDMA_CIQS]; 673f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 674f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 67552367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 67652367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 67752367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 67852367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 67952367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 6800f4d201fSKumar Sanghvi 681a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 682f7917c00SJeff Kirsher unsigned int egr_start; 6834b8e27a8SHariprasad Shenai unsigned int egr_sz; 684f7917c00SJeff Kirsher unsigned int ingr_start; 6854b8e27a8SHariprasad Shenai unsigned int ingr_sz; 6864b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 6874b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 6884b8e27a8SHariprasad Shenai unsigned long *starving_fl; 6894b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 6905b377d11SHariprasad Shenai unsigned long *blocked_fl; 691f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 692f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 693f7917c00SJeff Kirsher }; 694f7917c00SJeff Kirsher 695f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 696f7917c00SJeff Kirsher #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 697f7917c00SJeff Kirsher #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 698cf38be6dSHariprasad Shenai #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 699f7917c00SJeff Kirsher 700f7917c00SJeff Kirsher struct l2t_data; 701f7917c00SJeff Kirsher 7022422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 7032422d9a3SSantosh Rastapur 7047d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 7057d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 7067d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 7072422d9a3SSantosh Rastapur */ 7087d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 7092422d9a3SSantosh Rastapur 7102422d9a3SSantosh Rastapur #endif 7112422d9a3SSantosh Rastapur 712a4cfd929SHariprasad Shenai struct doorbell_stats { 713a4cfd929SHariprasad Shenai u32 db_drop; 714a4cfd929SHariprasad Shenai u32 db_empty; 715a4cfd929SHariprasad Shenai u32 db_full; 716a4cfd929SHariprasad Shenai }; 717a4cfd929SHariprasad Shenai 718f7917c00SJeff Kirsher struct adapter { 719f7917c00SJeff Kirsher void __iomem *regs; 72022adfe0aSSantosh Rastapur void __iomem *bar2; 7210abfd152SHariprasad Shenai u32 t4_bar0; 722f7917c00SJeff Kirsher struct pci_dev *pdev; 723f7917c00SJeff Kirsher struct device *pdev_dev; 7243069ee9bSVipul Pandya unsigned int mbox; 725b2612722SHariprasad Shenai unsigned int pf; 726f7917c00SJeff Kirsher unsigned int flags; 7272422d9a3SSantosh Rastapur enum chip_type chip; 728f7917c00SJeff Kirsher 729f7917c00SJeff Kirsher int msg_enable; 730f7917c00SJeff Kirsher 731f7917c00SJeff Kirsher struct adapter_params params; 732f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 733f7917c00SJeff Kirsher unsigned int swintr; 734f7917c00SJeff Kirsher 735f7917c00SJeff Kirsher struct { 736f7917c00SJeff Kirsher unsigned short vec; 737f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 738f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 739f7917c00SJeff Kirsher 740a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 741f7917c00SJeff Kirsher struct sge sge; 742f7917c00SJeff Kirsher 743f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 744f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 745f7917c00SJeff Kirsher 746793dad94SVipul Pandya u32 filter_mode; 747636f9d37SVipul Pandya unsigned int l2t_start; 748636f9d37SVipul Pandya unsigned int l2t_end; 749f7917c00SJeff Kirsher struct l2t_data *l2t; 750b5a02f50SAnish Bhatt unsigned int clipt_start; 751b5a02f50SAnish Bhatt unsigned int clipt_end; 752b5a02f50SAnish Bhatt struct clip_tbl *clipt; 753f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 754f7917c00SJeff Kirsher struct list_head list_node; 75501bcca68SVipul Pandya struct list_head rcu_node; 756f7917c00SJeff Kirsher 757f7917c00SJeff Kirsher struct tid_info tids; 758f7917c00SJeff Kirsher void **tid_release_head; 759f7917c00SJeff Kirsher spinlock_t tid_release_lock; 76029aaee65SAnish Bhatt struct workqueue_struct *workq; 761f7917c00SJeff Kirsher struct work_struct tid_release_task; 762881806bcSVipul Pandya struct work_struct db_full_task; 763881806bcSVipul Pandya struct work_struct db_drop_task; 764f7917c00SJeff Kirsher bool tid_release_task_busy; 765f7917c00SJeff Kirsher 766f7917c00SJeff Kirsher struct dentry *debugfs_root; 767f7917c00SJeff Kirsher 768f7917c00SJeff Kirsher spinlock_t stats_lock; 769fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 770f7917c00SJeff Kirsher }; 771f7917c00SJeff Kirsher 772f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 773f2b7e78dSVipul Pandya */ 774f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 775f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 776f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 777f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 778f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 779f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 780f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 781f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 782f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 783f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 784f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 785f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 786f2b7e78dSVipul Pandya 787f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 788f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 789f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 790f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 791f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 792f2b7e78dSVipul Pandya * matching rules are true. 793f2b7e78dSVipul Pandya * 794f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 795f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 796f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 797f2b7e78dSVipul Pandya * MPS match type) ... 798f2b7e78dSVipul Pandya * 799f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 800f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 801f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 802f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 803f2b7e78dSVipul Pandya */ 804f2b7e78dSVipul Pandya struct ch_filter_tuple { 805f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 806f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 807f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 808f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 809f2b7e78dSVipul Pandya * set of fields. 810f2b7e78dSVipul Pandya */ 811f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 812f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 813f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 814f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 815f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 816f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 817f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 818f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 819f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 820f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 821f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 822f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 823f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 824f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 825f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 826f2b7e78dSVipul Pandya 827f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 828f2b7e78dSVipul Pandya * available for field rules. 829f2b7e78dSVipul Pandya */ 830f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 831f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 832f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 833f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 834f2b7e78dSVipul Pandya }; 835f2b7e78dSVipul Pandya 836f2b7e78dSVipul Pandya /* A filter ioctl command. 837f2b7e78dSVipul Pandya */ 838f2b7e78dSVipul Pandya struct ch_filter_specification { 839f2b7e78dSVipul Pandya /* Administrative fields for filter. 840f2b7e78dSVipul Pandya */ 841f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 842f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 843f2b7e78dSVipul Pandya 844f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 845f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 846f2b7e78dSVipul Pandya */ 847f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 848f2b7e78dSVipul Pandya 849f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 850f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 851f2b7e78dSVipul Pandya * out as egress packets. 852f2b7e78dSVipul Pandya */ 853f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 854f2b7e78dSVipul Pandya 855f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 856f2b7e78dSVipul Pandya 857f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 858f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 859f2b7e78dSVipul Pandya 860f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 861f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 862f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 863f2b7e78dSVipul Pandya 864f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 865f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 866f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 867f2b7e78dSVipul Pandya */ 868f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 869f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 870f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 871f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 872f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 873f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 874f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 875f2b7e78dSVipul Pandya 876f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 877f2b7e78dSVipul Pandya */ 878f2b7e78dSVipul Pandya struct ch_filter_tuple val; 879f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 880f2b7e78dSVipul Pandya }; 881f2b7e78dSVipul Pandya 882f2b7e78dSVipul Pandya enum { 883f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 884f2b7e78dSVipul Pandya FILTER_DROP, 885f2b7e78dSVipul Pandya FILTER_SWITCH 886f2b7e78dSVipul Pandya }; 887f2b7e78dSVipul Pandya 888f2b7e78dSVipul Pandya enum { 889f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 890f2b7e78dSVipul Pandya VLAN_REMOVE, 891f2b7e78dSVipul Pandya VLAN_INSERT, 892f2b7e78dSVipul Pandya VLAN_REWRITE 893f2b7e78dSVipul Pandya }; 894f2b7e78dSVipul Pandya 895a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 896a4cfd929SHariprasad Shenai { 897a4cfd929SHariprasad Shenai return adap->params.offload; 898a4cfd929SHariprasad Shenai } 899a4cfd929SHariprasad Shenai 900ab4b583bSHariprasad Shenai static inline int is_t6(enum chip_type chip) 901ab4b583bSHariprasad Shenai { 902ab4b583bSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6; 903ab4b583bSHariprasad Shenai } 904ab4b583bSHariprasad Shenai 9052422d9a3SSantosh Rastapur static inline int is_t5(enum chip_type chip) 9062422d9a3SSantosh Rastapur { 907d14807ddSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5; 9082422d9a3SSantosh Rastapur } 9092422d9a3SSantosh Rastapur 9102422d9a3SSantosh Rastapur static inline int is_t4(enum chip_type chip) 9112422d9a3SSantosh Rastapur { 912d14807ddSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; 9132422d9a3SSantosh Rastapur } 9142422d9a3SSantosh Rastapur 915f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 916f7917c00SJeff Kirsher { 917f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 918f7917c00SJeff Kirsher } 919f7917c00SJeff Kirsher 920f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 921f7917c00SJeff Kirsher { 922f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 923f7917c00SJeff Kirsher } 924f7917c00SJeff Kirsher 925f7917c00SJeff Kirsher #ifndef readq 926f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 927f7917c00SJeff Kirsher { 928f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 929f7917c00SJeff Kirsher } 930f7917c00SJeff Kirsher 931f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 932f7917c00SJeff Kirsher { 933f7917c00SJeff Kirsher writel(val, addr); 934f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 935f7917c00SJeff Kirsher } 936f7917c00SJeff Kirsher #endif 937f7917c00SJeff Kirsher 938f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 939f7917c00SJeff Kirsher { 940f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 941f7917c00SJeff Kirsher } 942f7917c00SJeff Kirsher 943f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 944f7917c00SJeff Kirsher { 945f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 946f7917c00SJeff Kirsher } 947f7917c00SJeff Kirsher 948f7917c00SJeff Kirsher /** 949f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 950f7917c00SJeff Kirsher * @dev: the netdev 951f7917c00SJeff Kirsher * 952f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 953f7917c00SJeff Kirsher */ 954f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 955f7917c00SJeff Kirsher { 956f7917c00SJeff Kirsher return netdev_priv(dev); 957f7917c00SJeff Kirsher } 958f7917c00SJeff Kirsher 959f7917c00SJeff Kirsher /** 960f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 961f7917c00SJeff Kirsher * @adap: the adapter 962f7917c00SJeff Kirsher * @idx: the port index 963f7917c00SJeff Kirsher * 964f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 965f7917c00SJeff Kirsher */ 966f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 967f7917c00SJeff Kirsher { 968f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 969f7917c00SJeff Kirsher } 970f7917c00SJeff Kirsher 971f7917c00SJeff Kirsher /** 972f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 973f7917c00SJeff Kirsher * @dev: the netdev 974f7917c00SJeff Kirsher * 975f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 976f7917c00SJeff Kirsher */ 977f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 978f7917c00SJeff Kirsher { 979f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 980f7917c00SJeff Kirsher } 981f7917c00SJeff Kirsher 9823a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 9833a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 9843a336cb1SHariprasad Shenai { 9853a336cb1SHariprasad Shenai spin_lock_init(&q->bpoll_lock); 9863a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 9873a336cb1SHariprasad Shenai } 9883a336cb1SHariprasad Shenai 9893a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 9903a336cb1SHariprasad Shenai { 9913a336cb1SHariprasad Shenai bool rc = true; 9923a336cb1SHariprasad Shenai 9933a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 9943a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 9953a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 9963a336cb1SHariprasad Shenai rc = false; 9973a336cb1SHariprasad Shenai } else { 9983a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_NAPI; 9993a336cb1SHariprasad Shenai } 10003a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 10013a336cb1SHariprasad Shenai return rc; 10023a336cb1SHariprasad Shenai } 10033a336cb1SHariprasad Shenai 10043a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 10053a336cb1SHariprasad Shenai { 10063a336cb1SHariprasad Shenai bool rc = false; 10073a336cb1SHariprasad Shenai 10083a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 10093a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 10103a336cb1SHariprasad Shenai rc = true; 10113a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 10123a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 10133a336cb1SHariprasad Shenai return rc; 10143a336cb1SHariprasad Shenai } 10153a336cb1SHariprasad Shenai 10163a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 10173a336cb1SHariprasad Shenai { 10183a336cb1SHariprasad Shenai bool rc = true; 10193a336cb1SHariprasad Shenai 10203a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 10213a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 10223a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 10233a336cb1SHariprasad Shenai rc = false; 10243a336cb1SHariprasad Shenai } else { 10253a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL; 10263a336cb1SHariprasad Shenai } 10273a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 10283a336cb1SHariprasad Shenai return rc; 10293a336cb1SHariprasad Shenai } 10303a336cb1SHariprasad Shenai 10313a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 10323a336cb1SHariprasad Shenai { 10333a336cb1SHariprasad Shenai bool rc = false; 10343a336cb1SHariprasad Shenai 10353a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 10363a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 10373a336cb1SHariprasad Shenai rc = true; 10383a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 10393a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 10403a336cb1SHariprasad Shenai return rc; 10413a336cb1SHariprasad Shenai } 10423a336cb1SHariprasad Shenai 10433a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 10443a336cb1SHariprasad Shenai { 10453a336cb1SHariprasad Shenai return q->bpoll_state & CXGB_POLL_USER_PEND; 10463a336cb1SHariprasad Shenai } 10473a336cb1SHariprasad Shenai #else 10483a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 10493a336cb1SHariprasad Shenai { 10503a336cb1SHariprasad Shenai } 10513a336cb1SHariprasad Shenai 10523a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 10533a336cb1SHariprasad Shenai { 10543a336cb1SHariprasad Shenai return true; 10553a336cb1SHariprasad Shenai } 10563a336cb1SHariprasad Shenai 10573a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 10583a336cb1SHariprasad Shenai { 10593a336cb1SHariprasad Shenai return false; 10603a336cb1SHariprasad Shenai } 10613a336cb1SHariprasad Shenai 10623a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 10633a336cb1SHariprasad Shenai { 10643a336cb1SHariprasad Shenai return false; 10653a336cb1SHariprasad Shenai } 10663a336cb1SHariprasad Shenai 10673a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 10683a336cb1SHariprasad Shenai { 10693a336cb1SHariprasad Shenai return false; 10703a336cb1SHariprasad Shenai } 10713a336cb1SHariprasad Shenai 10723a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 10733a336cb1SHariprasad Shenai { 10743a336cb1SHariprasad Shenai return false; 10753a336cb1SHariprasad Shenai } 10763a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 10773a336cb1SHariprasad Shenai 1078812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1079812034f1SHariprasad Shenai * - bits 0..9: chip version 1080812034f1SHariprasad Shenai * - bits 10..15: chip revision 1081812034f1SHariprasad Shenai * - bits 16..23: register dump version 1082812034f1SHariprasad Shenai */ 1083812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1084812034f1SHariprasad Shenai { 1085812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1086812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1087812034f1SHariprasad Shenai } 1088812034f1SHariprasad Shenai 1089812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1090812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1091812034f1SHariprasad Shenai const struct sge_rspq *q) 1092812034f1SHariprasad Shenai { 1093812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1094812034f1SHariprasad Shenai 1095812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1096812034f1SHariprasad Shenai } 1097812034f1SHariprasad Shenai 1098812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1099812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1100812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1101812034f1SHariprasad Shenai 1102f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1103f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1104f7917c00SJeff Kirsher 1105f7917c00SJeff Kirsher void *t4_alloc_mem(size_t size); 1106f7917c00SJeff Kirsher 1107f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 11085fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1109f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1110f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1111f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1112f7917c00SJeff Kirsher const struct pkt_gl *gl); 1113f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1114f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1115f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1116f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 1117145ef8a5SHariprasad Shenai struct sge_fl *fl, rspq_handler_t hnd, int cong); 1118f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1119f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1120f7917c00SJeff Kirsher unsigned int iqid); 1121f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1122f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1123f7917c00SJeff Kirsher unsigned int cmplqid); 1124f7917c00SJeff Kirsher int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1125f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid); 1126f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 112752367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1128f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1129f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 11303a336cb1SHariprasad Shenai int cxgb_busy_poll(struct napi_struct *napi); 1131812034f1SHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1132812034f1SHariprasad Shenai unsigned int cnt); 1133812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1134812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 11353069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1136f7917c00SJeff Kirsher 1137f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1138f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1139f7917c00SJeff Kirsher 11409a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 11419a4da2cdSVipul Pandya { 11429a4da2cdSVipul Pandya return adap->params.bypass; 11439a4da2cdSVipul Pandya } 11449a4da2cdSVipul Pandya 11459a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 11469a4da2cdSVipul Pandya { 11479a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 11489a4da2cdSVipul Pandya switch (device) { 11499a4da2cdSVipul Pandya case 0x440b: 11509a4da2cdSVipul Pandya case 0x440c: 11519a4da2cdSVipul Pandya return 1; 11529a4da2cdSVipul Pandya default: 11539a4da2cdSVipul Pandya return 0; 11549a4da2cdSVipul Pandya } 11559a4da2cdSVipul Pandya } 11569a4da2cdSVipul Pandya 115701b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 115801b69614SHariprasad Shenai { 115901b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 116001b69614SHariprasad Shenai switch (device) { 116101b69614SHariprasad Shenai case 0x4409: 116201b69614SHariprasad Shenai case 0x4486: 116301b69614SHariprasad Shenai return 1; 116401b69614SHariprasad Shenai 116501b69614SHariprasad Shenai default: 116601b69614SHariprasad Shenai return 0; 116701b69614SHariprasad Shenai } 116801b69614SHariprasad Shenai } 116901b69614SHariprasad Shenai 1170f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1171f7917c00SJeff Kirsher { 1172f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1173f7917c00SJeff Kirsher } 1174f7917c00SJeff Kirsher 1175f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1176f7917c00SJeff Kirsher unsigned int us) 1177f7917c00SJeff Kirsher { 1178f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1179f7917c00SJeff Kirsher } 1180f7917c00SJeff Kirsher 118152367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 118252367a76SVipul Pandya unsigned int ticks) 118352367a76SVipul Pandya { 118452367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 118552367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 118652367a76SVipul Pandya adapter->params.vpd.cclk); 118752367a76SVipul Pandya } 118852367a76SVipul Pandya 1189f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1190f7917c00SJeff Kirsher u32 val); 1191f7917c00SJeff Kirsher 119201b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 119301b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1194f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1195f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1196f7917c00SJeff Kirsher 119701b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 119801b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 119901b69614SHariprasad Shenai int timeout) 120001b69614SHariprasad Shenai { 120101b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 120201b69614SHariprasad Shenai timeout); 120301b69614SHariprasad Shenai } 120401b69614SHariprasad Shenai 1205f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1206f7917c00SJeff Kirsher int size, void *rpl) 1207f7917c00SJeff Kirsher { 1208f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1209f7917c00SJeff Kirsher } 1210f7917c00SJeff Kirsher 1211f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1212f7917c00SJeff Kirsher int size, void *rpl) 1213f7917c00SJeff Kirsher { 1214f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1215f7917c00SJeff Kirsher } 1216f7917c00SJeff Kirsher 121713ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 121813ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 121913ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1220f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1221f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1222f2b7e78dSVipul Pandya unsigned int start_idx); 12230abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1224f2b7e78dSVipul Pandya 1225f2b7e78dSVipul Pandya struct fw_filter_wr; 1226f2b7e78dSVipul Pandya 1227f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1228f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1229f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1230f7917c00SJeff Kirsher 12318203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 1232f7917c00SJeff Kirsher int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 1233f7917c00SJeff Kirsher struct link_config *lc); 1234f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1235fc5ab020SHariprasad Shenai 1236b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1237b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1238b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1239b562fc37SHariprasad Shenai 1240fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1241fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1242fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1243f01aa633SHariprasad Shenai void *buf, int dir); 1244fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1245fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1246fc5ab020SHariprasad Shenai { 1247fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1248fc5ab020SHariprasad Shenai } 1249fc5ab020SHariprasad Shenai 1250812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1251812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1252812034f1SHariprasad Shenai 1253f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1254636f9d37SVipul Pandya int get_vpd_params(struct adapter *adapter, struct vpd_params *p); 125549216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 125649216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1257f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 125801b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 125901b69614SHariprasad Shenai int win, spinlock_t *lock, 126001b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 126101b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 126201b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 126349216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 126422c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 126522c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1266636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 126716e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 126816e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1269ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 127016e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 127116e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 127216e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1273f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 1274e85c9a7aSHariprasad Shenai 1275e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1276b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1277e85c9a7aSHariprasad Shenai unsigned int qid, 1278e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 1279e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1280e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1281e85c9a7aSHariprasad Shenai 1282dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1283dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1284ae469b68SHariprasad Shenai 1285ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1286e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 1287dcf7b6f5SKumar Sanghvi int t4_init_tp_params(struct adapter *adap); 1288dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1289c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1290f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1291f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1292f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1293f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1294f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1295f7917c00SJeff Kirsher unsigned int flags); 1296c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1297c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1298688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 1299688ea5feSHariprasad Shenai void t4_read_rss_key(struct adapter *adapter, u32 *key); 1300688ea5feSHariprasad Shenai void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1301688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1302688ea5feSHariprasad Shenai u32 *valp); 1303688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1304688ea5feSHariprasad Shenai u32 *vfl, u32 *vfh); 1305688ea5feSHariprasad Shenai u32 t4_read_rss_pf_map(struct adapter *adapter); 1306688ea5feSHariprasad Shenai u32 t4_read_rss_pf_mask(struct adapter *adapter); 1307688ea5feSHariprasad Shenai 1308145ef8a5SHariprasad Shenai unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1309b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1310b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1311e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1312e5f0e43bSHariprasad Shenai size_t n); 1313c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1314c778af7dSHariprasad Shenai size_t n); 1315f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1316f1ff24aaSHariprasad Shenai unsigned int *valp); 1317f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1318f1ff24aaSHariprasad Shenai const unsigned int *valp); 1319f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 132074b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 132172aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1322f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1323a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1324a4cfd929SHariprasad Shenai struct port_stats *stats, 1325a4cfd929SHariprasad Shenai struct port_stats *offset); 132665046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1327f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1328bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1329636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1330636f9d37SVipul Pandya unsigned int mask, unsigned int val); 13312d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1332a4cfd929SHariprasad Shenai void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1333a6222975SHariprasad Shenai void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1334a4cfd929SHariprasad Shenai void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1335a4cfd929SHariprasad Shenai void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1336f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1337f7917c00SJeff Kirsher struct tp_tcp_stats *v6); 1338a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1339a6222975SHariprasad Shenai struct tp_fcoe_stats *st); 1340f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1341f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1342f7917c00SJeff Kirsher 1343797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1344797ff0f5SHariprasad Shenai 1345f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1346f2b7e78dSVipul Pandya 1347f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1348f7917c00SJeff Kirsher const u8 *addr); 1349f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1350f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1351f7917c00SJeff Kirsher 1352f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1353f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1354f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1355f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1356f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1357636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1358636f9d37SVipul Pandya unsigned int cache_line_size); 1359636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1360f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1361f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1362f7917c00SJeff Kirsher u32 *val); 136301b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1364f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 136501b69614SHariprasad Shenai u32 *val, int rw); 136601b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1367688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1368688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 136901b69614SHariprasad Shenai const u32 *val, int timeout); 137001b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 137101b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1372688848b1SAnish Bhatt const u32 *val); 1373f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1374f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1375f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1376f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1377f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1378f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1379f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1380f7917c00SJeff Kirsher unsigned int *rss_size); 13814f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 13824f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 13834f3a0fcfSHariprasad Shenai unsigned int viid); 1384f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1385f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1386f7917c00SJeff Kirsher bool sleep_ok); 1387f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1388f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1389f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1390f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1391f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1392f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1393f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1394688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1395688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1396f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1397f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1398f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1399f7917c00SJeff Kirsher unsigned int nblinks); 1400f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1401f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1402f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1403f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1404f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1405f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1406f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1407f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1408f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1409f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1410f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1411f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1412f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 14135d700ecbSHariprasad Shenai int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 1414f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1415881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1416881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 14178caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 14188caa1e84SVipul Pandya u32 addr, u32 val); 141968bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1420fd88b31aSHariprasad Shenai void t4_free_mem(void *addr); 1421a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1422a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1423a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1424a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1425a3bfb617SHariprasad Shenai int hz, int ticks); 1426f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1427