1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 505e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 51f7917c00SJeff Kirsher #include <asm/io.h> 5227999805SHariprasad S #include "t4_chip_type.h" 53f7917c00SJeff Kirsher #include "cxgb4_uld.h" 54f7917c00SJeff Kirsher 553069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 5694cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 5794cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 583069ee9bSVipul Pandya 59f7917c00SJeff Kirsher enum { 60f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 61f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 62f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 63f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 64a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 65098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 66f7917c00SJeff Kirsher }; 67f7917c00SJeff Kirsher 68f7917c00SJeff Kirsher enum { 69812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 70812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 71812034f1SHariprasad Shenai }; 72812034f1SHariprasad Shenai 73812034f1SHariprasad Shenai enum { 74f7917c00SJeff Kirsher MEM_EDC0, 75f7917c00SJeff Kirsher MEM_EDC1, 762422d9a3SSantosh Rastapur MEM_MC, 772422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 782422d9a3SSantosh Rastapur MEM_MC1 79f7917c00SJeff Kirsher }; 80f7917c00SJeff Kirsher 813069ee9bSVipul Pandya enum { 823eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 833eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 843069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 853069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 862422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 873eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 883eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 890abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 900abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 913069ee9bSVipul Pandya }; 923069ee9bSVipul Pandya 93f7917c00SJeff Kirsher enum dev_master { 94f7917c00SJeff Kirsher MASTER_CANT, 95f7917c00SJeff Kirsher MASTER_MAY, 96f7917c00SJeff Kirsher MASTER_MUST 97f7917c00SJeff Kirsher }; 98f7917c00SJeff Kirsher 99f7917c00SJeff Kirsher enum dev_state { 100f7917c00SJeff Kirsher DEV_STATE_UNINIT, 101f7917c00SJeff Kirsher DEV_STATE_INIT, 102f7917c00SJeff Kirsher DEV_STATE_ERR 103f7917c00SJeff Kirsher }; 104f7917c00SJeff Kirsher 105f7917c00SJeff Kirsher enum { 106f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 107f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 108f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 109f7917c00SJeff Kirsher }; 110f7917c00SJeff Kirsher 111f7917c00SJeff Kirsher struct port_stats { 112f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 113f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 114f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 115f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 116f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 117f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 118f7917c00SJeff Kirsher 119f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 120f7917c00SJeff Kirsher u64 tx_frames_65_127; 121f7917c00SJeff Kirsher u64 tx_frames_128_255; 122f7917c00SJeff Kirsher u64 tx_frames_256_511; 123f7917c00SJeff Kirsher u64 tx_frames_512_1023; 124f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 125f7917c00SJeff Kirsher u64 tx_frames_1519_max; 126f7917c00SJeff Kirsher 127f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 128f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 129f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 130f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 131f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 132f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 133f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 134f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 135f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 136f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 137f7917c00SJeff Kirsher 138f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 139f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 140f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 141f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 142f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 143f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 144f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 145f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 146f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 147f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 148f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 149f7917c00SJeff Kirsher 150f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 151f7917c00SJeff Kirsher u64 rx_frames_65_127; 152f7917c00SJeff Kirsher u64 rx_frames_128_255; 153f7917c00SJeff Kirsher u64 rx_frames_256_511; 154f7917c00SJeff Kirsher u64 rx_frames_512_1023; 155f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 156f7917c00SJeff Kirsher u64 rx_frames_1519_max; 157f7917c00SJeff Kirsher 158f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 159f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 160f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 161f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 162f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 163f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 164f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 165f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 166f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 167f7917c00SJeff Kirsher 168f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 169f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 170f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 171f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 172f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 173f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 174f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 175f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 176f7917c00SJeff Kirsher }; 177f7917c00SJeff Kirsher 178f7917c00SJeff Kirsher struct lb_port_stats { 179f7917c00SJeff Kirsher u64 octets; 180f7917c00SJeff Kirsher u64 frames; 181f7917c00SJeff Kirsher u64 bcast_frames; 182f7917c00SJeff Kirsher u64 mcast_frames; 183f7917c00SJeff Kirsher u64 ucast_frames; 184f7917c00SJeff Kirsher u64 error_frames; 185f7917c00SJeff Kirsher 186f7917c00SJeff Kirsher u64 frames_64; 187f7917c00SJeff Kirsher u64 frames_65_127; 188f7917c00SJeff Kirsher u64 frames_128_255; 189f7917c00SJeff Kirsher u64 frames_256_511; 190f7917c00SJeff Kirsher u64 frames_512_1023; 191f7917c00SJeff Kirsher u64 frames_1024_1518; 192f7917c00SJeff Kirsher u64 frames_1519_max; 193f7917c00SJeff Kirsher 194f7917c00SJeff Kirsher u64 drop; 195f7917c00SJeff Kirsher 196f7917c00SJeff Kirsher u64 ovflow0; 197f7917c00SJeff Kirsher u64 ovflow1; 198f7917c00SJeff Kirsher u64 ovflow2; 199f7917c00SJeff Kirsher u64 ovflow3; 200f7917c00SJeff Kirsher u64 trunc0; 201f7917c00SJeff Kirsher u64 trunc1; 202f7917c00SJeff Kirsher u64 trunc2; 203f7917c00SJeff Kirsher u64 trunc3; 204f7917c00SJeff Kirsher }; 205f7917c00SJeff Kirsher 206f7917c00SJeff Kirsher struct tp_tcp_stats { 207a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 208a4cfd929SHariprasad Shenai u64 tcp_in_segs; 209a4cfd929SHariprasad Shenai u64 tcp_out_segs; 210a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 211a4cfd929SHariprasad Shenai }; 212a4cfd929SHariprasad Shenai 213a4cfd929SHariprasad Shenai struct tp_usm_stats { 214a4cfd929SHariprasad Shenai u32 frames; 215a4cfd929SHariprasad Shenai u32 drops; 216a4cfd929SHariprasad Shenai u64 octets; 217f7917c00SJeff Kirsher }; 218f7917c00SJeff Kirsher 219a6222975SHariprasad Shenai struct tp_fcoe_stats { 220a6222975SHariprasad Shenai u32 frames_ddp; 221a6222975SHariprasad Shenai u32 frames_drop; 222a6222975SHariprasad Shenai u64 octets_ddp; 223f7917c00SJeff Kirsher }; 224f7917c00SJeff Kirsher 225f7917c00SJeff Kirsher struct tp_err_stats { 226a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 227a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 228a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 229a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 230a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 231a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 232a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 233a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 234a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 235a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 236a4cfd929SHariprasad Shenai }; 237a4cfd929SHariprasad Shenai 238a6222975SHariprasad Shenai struct tp_cpl_stats { 239a6222975SHariprasad Shenai u32 req[4]; 240a6222975SHariprasad Shenai u32 rsp[4]; 241a6222975SHariprasad Shenai }; 242a6222975SHariprasad Shenai 243a4cfd929SHariprasad Shenai struct tp_rdma_stats { 244a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 245a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 246f7917c00SJeff Kirsher }; 247f7917c00SJeff Kirsher 248e85c9a7aSHariprasad Shenai struct sge_params { 249e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 250e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 251e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 252e85c9a7aSHariprasad Shenai }; 253e85c9a7aSHariprasad Shenai 254f7917c00SJeff Kirsher struct tp_params { 255f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2562d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 257dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 258dca4faebSVipul Pandya /* channel map */ 259636f9d37SVipul Pandya 260636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 261636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 262dcf7b6f5SKumar Sanghvi 263dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 264dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 265dcf7b6f5SKumar Sanghvi 266dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 267dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 268dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 269dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 270dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 271dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 272dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 273dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 274dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 275dcf7b6f5SKumar Sanghvi * present. 276dcf7b6f5SKumar Sanghvi */ 277dcf7b6f5SKumar Sanghvi int vlan_shift; 278dcf7b6f5SKumar Sanghvi int vnic_shift; 279dcf7b6f5SKumar Sanghvi int port_shift; 280dcf7b6f5SKumar Sanghvi int protocol_shift; 281f7917c00SJeff Kirsher }; 282f7917c00SJeff Kirsher 283f7917c00SJeff Kirsher struct vpd_params { 284f7917c00SJeff Kirsher unsigned int cclk; 285f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 286f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 287f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 288a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 289098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 290f7917c00SJeff Kirsher }; 291f7917c00SJeff Kirsher 292f7917c00SJeff Kirsher struct pci_params { 293f7917c00SJeff Kirsher unsigned char speed; 294f7917c00SJeff Kirsher unsigned char width; 295f7917c00SJeff Kirsher }; 296f7917c00SJeff Kirsher 29749aa284fSHariprasad Shenai struct devlog_params { 29849aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 29949aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 30049aa284fSHariprasad Shenai u32 size; /* size of log */ 30149aa284fSHariprasad Shenai }; 30249aa284fSHariprasad Shenai 3033ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3043ccc6cf7SHariprasad Shenai struct arch_specific_params { 3053ccc6cf7SHariprasad Shenai u8 nchan; 30644588560SHariprasad Shenai u8 pm_stats_cnt; 3072216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3083ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3093ccc6cf7SHariprasad Shenai u16 vfcount; 3103ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3113ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3123ccc6cf7SHariprasad Shenai }; 3133ccc6cf7SHariprasad Shenai 314f7917c00SJeff Kirsher struct adapter_params { 315e85c9a7aSHariprasad Shenai struct sge_params sge; 316f7917c00SJeff Kirsher struct tp_params tp; 317f7917c00SJeff Kirsher struct vpd_params vpd; 318f7917c00SJeff Kirsher struct pci_params pci; 31949aa284fSHariprasad Shenai struct devlog_params devlog; 32049aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 321f7917c00SJeff Kirsher 322f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 323f1ff24aaSHariprasad Shenai 324f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 325f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 326f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 327f7917c00SJeff Kirsher 328f7917c00SJeff Kirsher unsigned int fw_vers; 3290de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 330f7917c00SJeff Kirsher unsigned int tp_vers; 3310de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 332f7917c00SJeff Kirsher u8 api_vers[7]; 333f7917c00SJeff Kirsher 334f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 335f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 336f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 337f7917c00SJeff Kirsher 338f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 339f7917c00SJeff Kirsher unsigned char portvec; 340d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3413ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 342f7917c00SJeff Kirsher unsigned char offload; 34394cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 344f7917c00SJeff Kirsher 3459a4da2cdSVipul Pandya unsigned char bypass; 3469a4da2cdSVipul Pandya 347f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3481ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3494c2c5763SHariprasad Shenai 350b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 3514c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3524c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 353f7917c00SJeff Kirsher }; 354f7917c00SJeff Kirsher 355a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 356a3bfb617SHariprasad Shenai * and possible hangs. 357a3bfb617SHariprasad Shenai */ 358a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 359a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 360a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 361a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 362a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 363a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 364a3bfb617SHariprasad Shenai }; 365a3bfb617SHariprasad Shenai 3667f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 3677f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 3687f080c3fSHariprasad Shenai * error returns. 3697f080c3fSHariprasad Shenai */ 3707f080c3fSHariprasad Shenai struct mbox_cmd { 3717f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 3727f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 3737f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 3747f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 3757f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 3767f080c3fSHariprasad Shenai }; 3777f080c3fSHariprasad Shenai 3787f080c3fSHariprasad Shenai struct mbox_cmd_log { 3797f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 3807f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 3817f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 3827f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 3837f080c3fSHariprasad Shenai }; 3847f080c3fSHariprasad Shenai 3857f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 3867f080c3fSHariprasad Shenai * return a pointer to the specified entry. 3877f080c3fSHariprasad Shenai */ 3887f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 3897f080c3fSHariprasad Shenai unsigned int entry_idx) 3907f080c3fSHariprasad Shenai { 3917f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 3927f080c3fSHariprasad Shenai } 3937f080c3fSHariprasad Shenai 39416e47624SHariprasad Shenai #include "t4fw_api.h" 39516e47624SHariprasad Shenai 39616e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 397b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 398b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 399b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 400b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 40116e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 40216e47624SHariprasad Shenai 40316e47624SHariprasad Shenai struct fw_info { 40416e47624SHariprasad Shenai u8 chip; 40516e47624SHariprasad Shenai char *fs_name; 40616e47624SHariprasad Shenai char *fw_mod_name; 40716e47624SHariprasad Shenai struct fw_hdr fw_hdr; 40816e47624SHariprasad Shenai }; 40916e47624SHariprasad Shenai 410f7917c00SJeff Kirsher struct trace_params { 411f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 412f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 413f7917c00SJeff Kirsher unsigned short snap_len; 414f7917c00SJeff Kirsher unsigned short min_len; 415f7917c00SJeff Kirsher unsigned char skip_ofst; 416f7917c00SJeff Kirsher unsigned char skip_len; 417f7917c00SJeff Kirsher unsigned char invert; 418f7917c00SJeff Kirsher unsigned char port; 419f7917c00SJeff Kirsher }; 420f7917c00SJeff Kirsher 421f7917c00SJeff Kirsher struct link_config { 422f7917c00SJeff Kirsher unsigned short supported; /* link capabilities */ 423f7917c00SJeff Kirsher unsigned short advertising; /* advertised capabilities */ 424eb97ad99SGanesh Goudar unsigned short lp_advertising; /* peer advertised capabilities */ 425f7917c00SJeff Kirsher unsigned short requested_speed; /* speed user has requested */ 426f7917c00SJeff Kirsher unsigned short speed; /* actual link speed */ 427f7917c00SJeff Kirsher unsigned char requested_fc; /* flow control user has requested */ 428f7917c00SJeff Kirsher unsigned char fc; /* actual link flow control */ 429f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 430f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 431ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 432f7917c00SJeff Kirsher }; 433f7917c00SJeff Kirsher 434e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 435f7917c00SJeff Kirsher 436f7917c00SJeff Kirsher enum { 437f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 438f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 439f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 440f7917c00SJeff Kirsher }; 441f7917c00SJeff Kirsher 442f7917c00SJeff Kirsher enum { 443812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 444812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 445812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 446812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 447812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 448812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 449812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 450812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 451812034f1SHariprasad Shenai }; 452812034f1SHariprasad Shenai 453812034f1SHariprasad Shenai enum { 454cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 455cf38be6dSHariprasad Shenai /* forwarded interrupts */ 4560fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 457f7917c00SJeff Kirsher }; 458f7917c00SJeff Kirsher 459f7917c00SJeff Kirsher struct adapter; 460f7917c00SJeff Kirsher struct sge_rspq; 461f7917c00SJeff Kirsher 462688848b1SAnish Bhatt #include "cxgb4_dcb.h" 463688848b1SAnish Bhatt 46476fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 46576fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 46676fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 46776fed8a9SVarun Prakash 468f7917c00SJeff Kirsher struct port_info { 469f7917c00SJeff Kirsher struct adapter *adapter; 470f7917c00SJeff Kirsher u16 viid; 471f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 472f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 473f7917c00SJeff Kirsher s8 mdio_addr; 47440e9de4bSHariprasad Shenai enum fw_port_type port_type; 475f7917c00SJeff Kirsher u8 mod_type; 476f7917c00SJeff Kirsher u8 port_id; 477f7917c00SJeff Kirsher u8 tx_chan; 478f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 479f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 480f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 481f7917c00SJeff Kirsher u8 rss_mode; 482f7917c00SJeff Kirsher struct link_config link_cfg; 483f7917c00SJeff Kirsher u16 *rss; 484a4cfd929SHariprasad Shenai struct port_stats stats_base; 485688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 486688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 487688848b1SAnish Bhatt #endif 48876fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 48976fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 49076fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 4915e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 4925e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 493b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 494f7917c00SJeff Kirsher }; 495f7917c00SJeff Kirsher 496f7917c00SJeff Kirsher struct dentry; 497f7917c00SJeff Kirsher struct work_struct; 498f7917c00SJeff Kirsher 499f7917c00SJeff Kirsher enum { /* adapter flags */ 500f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 501144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 502144be3d9SGavin Shan USING_MSI = (1 << 2), 503144be3d9SGavin Shan USING_MSIX = (1 << 3), 504f7917c00SJeff Kirsher FW_OK = (1 << 4), 50513ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 50652367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 50752367a76SVipul Pandya MASTER_PF = (1 << 7), 50852367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 509f7917c00SJeff Kirsher }; 510f7917c00SJeff Kirsher 51194cdb8bbSHariprasad Shenai enum { 51294cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 51394cdb8bbSHariprasad Shenai }; 51494cdb8bbSHariprasad Shenai 515f7917c00SJeff Kirsher struct rx_sw_desc; 516f7917c00SJeff Kirsher 517f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 518f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 519f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 520f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 521f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 522f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 523f7917c00SJeff Kirsher unsigned long large_alloc_failed; 52470055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 52570055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 526f7917c00SJeff Kirsher unsigned long starving; 527f7917c00SJeff Kirsher /* RO fields */ 528f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 529f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 530f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 531f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 532f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 533df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 534df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 535f7917c00SJeff Kirsher }; 536f7917c00SJeff Kirsher 537f7917c00SJeff Kirsher /* A packet gather list */ 538f7917c00SJeff Kirsher struct pkt_gl { 5395e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 540e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 541f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 542f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 543f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 544f7917c00SJeff Kirsher }; 545f7917c00SJeff Kirsher 546f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 547f7917c00SJeff Kirsher const struct pkt_gl *gl); 5482337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 5492337ba42SVarun Prakash /* LRO related declarations for ULD */ 5502337ba42SVarun Prakash struct t4_lro_mgr { 5512337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 5522337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 5532337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 5542337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 5552337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 5562337ba42SVarun Prakash }; 557f7917c00SJeff Kirsher 558f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 559f7917c00SJeff Kirsher struct napi_struct napi; 560f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 561f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 562f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 563f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 564f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 565e553ec3fSHariprasad Shenai u8 adaptive_rx; 566f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 567f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 568f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 569f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 570f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 571f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 572f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 573f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 574df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 575df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 576f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 577f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 578f7917c00SJeff Kirsher struct adapter *adap; 579f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 580f7917c00SJeff Kirsher rspq_handler_t handler; 5812337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 5822337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 5833a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 5843a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_IDLE 0 5853a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 5863a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 5873a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 5883a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 5893a336cb1SHariprasad Shenai #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 5903a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5913a336cb1SHariprasad Shenai #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 5923a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL) 5933a336cb1SHariprasad Shenai #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 5943a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5953a336cb1SHariprasad Shenai unsigned int bpoll_state; 5963a336cb1SHariprasad Shenai spinlock_t bpoll_lock; /* lock for busy poll */ 5973a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 5983a336cb1SHariprasad Shenai 599f7917c00SJeff Kirsher }; 600f7917c00SJeff Kirsher 601f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 602f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 603f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 604f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 605f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 606f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 607f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 608f7917c00SJeff Kirsher }; 609f7917c00SJeff Kirsher 610f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 611f7917c00SJeff Kirsher struct sge_rspq rspq; 612f7917c00SJeff Kirsher struct sge_fl fl; 613f7917c00SJeff Kirsher struct sge_eth_stats stats; 614f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 615f7917c00SJeff Kirsher 616f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 617f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 618f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 619f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 620f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 621f7917c00SJeff Kirsher }; 622f7917c00SJeff Kirsher 623f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 624f7917c00SJeff Kirsher struct sge_rspq rspq; 625f7917c00SJeff Kirsher struct sge_fl fl; 626f7917c00SJeff Kirsher struct sge_ofld_stats stats; 627f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 628f7917c00SJeff Kirsher 629f7917c00SJeff Kirsher struct tx_desc { 630f7917c00SJeff Kirsher __be64 flit[8]; 631f7917c00SJeff Kirsher }; 632f7917c00SJeff Kirsher 633f7917c00SJeff Kirsher struct tx_sw_desc; 634f7917c00SJeff Kirsher 635f7917c00SJeff Kirsher struct sge_txq { 636f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 637f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 638f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 639f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 640f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 641f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 642f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 643f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 644f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 645f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 646f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 6473069ee9bSVipul Pandya spinlock_t db_lock; 6483069ee9bSVipul Pandya int db_disabled; 6493069ee9bSVipul Pandya unsigned short db_pidx; 65005eb2389SSteve Wise unsigned short db_pidx_inc; 651df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 652df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 653f7917c00SJeff Kirsher }; 654f7917c00SJeff Kirsher 655f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 656f7917c00SJeff Kirsher struct sge_txq q; 657f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 65810b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 65910b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 66010b00466SAnish Bhatt #endif 661f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 662f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 663f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 664f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 665f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 666f7917c00SJeff Kirsher 667f7917c00SJeff Kirsher struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 668f7917c00SJeff Kirsher struct sge_txq q; 669f7917c00SJeff Kirsher struct adapter *adap; 670f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 671f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 672126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 673f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 674f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 675f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 676f7917c00SJeff Kirsher 677f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 678f7917c00SJeff Kirsher struct sge_txq q; 679f7917c00SJeff Kirsher struct adapter *adap; 680f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 681f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 682f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 683f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 684f7917c00SJeff Kirsher 68594cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 68694cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 68794cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 68894cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 68994cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 69094cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 69194cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 69294cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 69394cdb8bbSHariprasad Shenai }; 69494cdb8bbSHariprasad Shenai 695f7917c00SJeff Kirsher struct sge { 696f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 697f7917c00SJeff Kirsher struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 698f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 699f7917c00SJeff Kirsher 700f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 701f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 70294cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 703f7917c00SJeff Kirsher 704f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 705f7917c00SJeff Kirsher spinlock_t intrq_lock; 706f7917c00SJeff Kirsher 707f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 708f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 709f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 7100fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 71194cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 712f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 713f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 71452367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 71552367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 71652367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 71752367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 71852367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 7190f4d201fSKumar Sanghvi 720a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 721f7917c00SJeff Kirsher unsigned int egr_start; 7224b8e27a8SHariprasad Shenai unsigned int egr_sz; 723f7917c00SJeff Kirsher unsigned int ingr_start; 7244b8e27a8SHariprasad Shenai unsigned int ingr_sz; 7254b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 7264b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 7274b8e27a8SHariprasad Shenai unsigned long *starving_fl; 7284b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 7295b377d11SHariprasad Shenai unsigned long *blocked_fl; 730f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 731f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 732f7917c00SJeff Kirsher }; 733f7917c00SJeff Kirsher 734f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 7350fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 736f7917c00SJeff Kirsher 737f7917c00SJeff Kirsher struct l2t_data; 738f7917c00SJeff Kirsher 7392422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 7402422d9a3SSantosh Rastapur 7417d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 7427d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 7437d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 7442422d9a3SSantosh Rastapur */ 7457d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 7462422d9a3SSantosh Rastapur 7472422d9a3SSantosh Rastapur #endif 7482422d9a3SSantosh Rastapur 749a4cfd929SHariprasad Shenai struct doorbell_stats { 750a4cfd929SHariprasad Shenai u32 db_drop; 751a4cfd929SHariprasad Shenai u32 db_empty; 752a4cfd929SHariprasad Shenai u32 db_full; 753a4cfd929SHariprasad Shenai }; 754a4cfd929SHariprasad Shenai 755fc08a01aSHariprasad Shenai struct hash_mac_addr { 756fc08a01aSHariprasad Shenai struct list_head list; 757fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 758fc08a01aSHariprasad Shenai }; 759fc08a01aSHariprasad Shenai 76094cdb8bbSHariprasad Shenai struct uld_msix_bmap { 76194cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 76294cdb8bbSHariprasad Shenai unsigned int mapsize; 76394cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 76494cdb8bbSHariprasad Shenai }; 76594cdb8bbSHariprasad Shenai 76694cdb8bbSHariprasad Shenai struct uld_msix_info { 76794cdb8bbSHariprasad Shenai unsigned short vec; 76894cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 7690fbc81b3SHariprasad Shenai unsigned int idx; 77094cdb8bbSHariprasad Shenai }; 77194cdb8bbSHariprasad Shenai 772661dbeb9SHariprasad Shenai struct vf_info { 773661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 774661dbeb9SHariprasad Shenai bool pf_set_mac; 775661dbeb9SHariprasad Shenai }; 776661dbeb9SHariprasad Shenai 777f7917c00SJeff Kirsher struct adapter { 778f7917c00SJeff Kirsher void __iomem *regs; 77922adfe0aSSantosh Rastapur void __iomem *bar2; 7800abfd152SHariprasad Shenai u32 t4_bar0; 781f7917c00SJeff Kirsher struct pci_dev *pdev; 782f7917c00SJeff Kirsher struct device *pdev_dev; 7830de72738SHariprasad Shenai const char *name; 7843069ee9bSVipul Pandya unsigned int mbox; 785b2612722SHariprasad Shenai unsigned int pf; 786f7917c00SJeff Kirsher unsigned int flags; 787e7b48a32SHariprasad Shenai unsigned int adap_idx; 7882422d9a3SSantosh Rastapur enum chip_type chip; 789f7917c00SJeff Kirsher 790f7917c00SJeff Kirsher int msg_enable; 791f7917c00SJeff Kirsher 792f7917c00SJeff Kirsher struct adapter_params params; 793f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 794f7917c00SJeff Kirsher unsigned int swintr; 795f7917c00SJeff Kirsher 796f7917c00SJeff Kirsher struct { 797f7917c00SJeff Kirsher unsigned short vec; 798f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 799f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 80094cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 80194cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 8020fbc81b3SHariprasad Shenai int msi_idx; 803f7917c00SJeff Kirsher 804a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 805f7917c00SJeff Kirsher struct sge sge; 806f7917c00SJeff Kirsher 807f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 808f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 809f7917c00SJeff Kirsher 810661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 811661dbeb9SHariprasad Shenai u8 num_vfs; 812661dbeb9SHariprasad Shenai 813793dad94SVipul Pandya u32 filter_mode; 814636f9d37SVipul Pandya unsigned int l2t_start; 815636f9d37SVipul Pandya unsigned int l2t_end; 816f7917c00SJeff Kirsher struct l2t_data *l2t; 817b5a02f50SAnish Bhatt unsigned int clipt_start; 818b5a02f50SAnish Bhatt unsigned int clipt_end; 819b5a02f50SAnish Bhatt struct clip_tbl *clipt; 8200fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 821f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 82294cdb8bbSHariprasad Shenai unsigned int num_uld; 8230fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 824f7917c00SJeff Kirsher struct list_head list_node; 82501bcca68SVipul Pandya struct list_head rcu_node; 826fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 827f7917c00SJeff Kirsher 8287714cb9eSVarun Prakash void *iscsi_ppm; 8297714cb9eSVarun Prakash 830f7917c00SJeff Kirsher struct tid_info tids; 831f7917c00SJeff Kirsher void **tid_release_head; 832f7917c00SJeff Kirsher spinlock_t tid_release_lock; 83329aaee65SAnish Bhatt struct workqueue_struct *workq; 834f7917c00SJeff Kirsher struct work_struct tid_release_task; 835881806bcSVipul Pandya struct work_struct db_full_task; 836881806bcSVipul Pandya struct work_struct db_drop_task; 837f7917c00SJeff Kirsher bool tid_release_task_busy; 838f7917c00SJeff Kirsher 8397f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 8407f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 8417f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 8427f080c3fSHariprasad Shenai 8430fbc81b3SHariprasad Shenai struct mutex uld_mutex; 8440fbc81b3SHariprasad Shenai 845f7917c00SJeff Kirsher struct dentry *debugfs_root; 846621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 847621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 8488e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 8498e3d04fdSHariprasad Shenai * used for all 4 filters. 8508e3d04fdSHariprasad Shenai */ 851f7917c00SJeff Kirsher 852f7917c00SJeff Kirsher spinlock_t stats_lock; 853fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 854f7917c00SJeff Kirsher }; 855f7917c00SJeff Kirsher 856b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 857b72a32daSRahul Lakkireddy * programmed with various parameters. 858b72a32daSRahul Lakkireddy */ 859b72a32daSRahul Lakkireddy struct ch_sched_params { 860b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 861b72a32daSRahul Lakkireddy union { 862b72a32daSRahul Lakkireddy struct { 863b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 864b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 865b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 866b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 867b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 868b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 869b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 870b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 871b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 872b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 873b72a32daSRahul Lakkireddy } params; 874b72a32daSRahul Lakkireddy } u; 875b72a32daSRahul Lakkireddy }; 876b72a32daSRahul Lakkireddy 87710a2604eSRahul Lakkireddy enum { 87810a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 87910a2604eSRahul Lakkireddy }; 88010a2604eSRahul Lakkireddy 88110a2604eSRahul Lakkireddy enum { 88210a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 88310a2604eSRahul Lakkireddy }; 88410a2604eSRahul Lakkireddy 88510a2604eSRahul Lakkireddy enum { 88610a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 88710a2604eSRahul Lakkireddy }; 88810a2604eSRahul Lakkireddy 88910a2604eSRahul Lakkireddy enum { 89010a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 89110a2604eSRahul Lakkireddy }; 89210a2604eSRahul Lakkireddy 89310a2604eSRahul Lakkireddy enum { 89410a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 89510a2604eSRahul Lakkireddy }; 89610a2604eSRahul Lakkireddy 8976cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 8986cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 8996cede1f1SRahul Lakkireddy */ 9006cede1f1SRahul Lakkireddy struct ch_sched_queue { 9016cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 9026cede1f1SRahul Lakkireddy s8 class; /* class index */ 9036cede1f1SRahul Lakkireddy }; 9046cede1f1SRahul Lakkireddy 905f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 906f2b7e78dSVipul Pandya */ 907f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 908f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 909f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 910f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 911f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 912f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 913f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 914f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 915f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 916f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 917f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 918f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 919f2b7e78dSVipul Pandya 920f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 921f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 922f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 923f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 924f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 925f2b7e78dSVipul Pandya * matching rules are true. 926f2b7e78dSVipul Pandya * 927f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 928f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 929f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 930f2b7e78dSVipul Pandya * MPS match type) ... 931f2b7e78dSVipul Pandya * 932f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 933f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 934f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 935f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 936f2b7e78dSVipul Pandya */ 937f2b7e78dSVipul Pandya struct ch_filter_tuple { 938f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 939f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 940f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 941f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 942f2b7e78dSVipul Pandya * set of fields. 943f2b7e78dSVipul Pandya */ 944f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 945f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 946f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 947f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 948f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 949f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 950f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 951f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 952f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 953f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 954f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 955f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 956f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 957f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 958f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 959f2b7e78dSVipul Pandya 960f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 961f2b7e78dSVipul Pandya * available for field rules. 962f2b7e78dSVipul Pandya */ 963f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 964f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 965f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 966f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 967f2b7e78dSVipul Pandya }; 968f2b7e78dSVipul Pandya 969f2b7e78dSVipul Pandya /* A filter ioctl command. 970f2b7e78dSVipul Pandya */ 971f2b7e78dSVipul Pandya struct ch_filter_specification { 972f2b7e78dSVipul Pandya /* Administrative fields for filter. 973f2b7e78dSVipul Pandya */ 974f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 975f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 976f2b7e78dSVipul Pandya 977f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 978f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 979f2b7e78dSVipul Pandya */ 980f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 981f2b7e78dSVipul Pandya 982f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 983f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 984f2b7e78dSVipul Pandya * out as egress packets. 985f2b7e78dSVipul Pandya */ 986f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 987f2b7e78dSVipul Pandya 988f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 989f2b7e78dSVipul Pandya 990f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 991f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 992f2b7e78dSVipul Pandya 993f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 994f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 995f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 996f2b7e78dSVipul Pandya 997f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 998f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 999f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1000f2b7e78dSVipul Pandya */ 1001f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1002f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1003f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1004f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 1005f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1006f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1007f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1008f2b7e78dSVipul Pandya 1009f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1010f2b7e78dSVipul Pandya */ 1011f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1012f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1013f2b7e78dSVipul Pandya }; 1014f2b7e78dSVipul Pandya 1015f2b7e78dSVipul Pandya enum { 1016f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1017f2b7e78dSVipul Pandya FILTER_DROP, 1018f2b7e78dSVipul Pandya FILTER_SWITCH 1019f2b7e78dSVipul Pandya }; 1020f2b7e78dSVipul Pandya 1021f2b7e78dSVipul Pandya enum { 1022f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1023f2b7e78dSVipul Pandya VLAN_REMOVE, 1024f2b7e78dSVipul Pandya VLAN_INSERT, 1025f2b7e78dSVipul Pandya VLAN_REWRITE 1026f2b7e78dSVipul Pandya }; 1027f2b7e78dSVipul Pandya 1028d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1029d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1030d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1031d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1032d57fd6caSRahul Lakkireddy * where the filter table is large. 1033d57fd6caSRahul Lakkireddy */ 1034d57fd6caSRahul Lakkireddy struct filter_entry { 1035d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1036d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1037d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1038d57fd6caSRahul Lakkireddy 1039d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1040d57fd6caSRahul Lakkireddy u32 smtidx:8; /* Source MAC Table index for smac */ 1041578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1042d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 1043578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1044578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1045d57fd6caSRahul Lakkireddy 1046d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1047d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1048d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1049d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1050d57fd6caSRahul Lakkireddy */ 1051d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1052d57fd6caSRahul Lakkireddy }; 1053d57fd6caSRahul Lakkireddy 1054a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1055a4cfd929SHariprasad Shenai { 1056a4cfd929SHariprasad Shenai return adap->params.offload; 1057a4cfd929SHariprasad Shenai } 1058a4cfd929SHariprasad Shenai 105994cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 106094cdb8bbSHariprasad Shenai { 106194cdb8bbSHariprasad Shenai return adap->params.crypto; 106294cdb8bbSHariprasad Shenai } 106394cdb8bbSHariprasad Shenai 10640fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 10650fbc81b3SHariprasad Shenai { 10660fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 10670fbc81b3SHariprasad Shenai } 10680fbc81b3SHariprasad Shenai 1069f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1070f7917c00SJeff Kirsher { 1071f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1072f7917c00SJeff Kirsher } 1073f7917c00SJeff Kirsher 1074f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1075f7917c00SJeff Kirsher { 1076f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1077f7917c00SJeff Kirsher } 1078f7917c00SJeff Kirsher 1079f7917c00SJeff Kirsher #ifndef readq 1080f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1081f7917c00SJeff Kirsher { 1082f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1083f7917c00SJeff Kirsher } 1084f7917c00SJeff Kirsher 1085f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1086f7917c00SJeff Kirsher { 1087f7917c00SJeff Kirsher writel(val, addr); 1088f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1089f7917c00SJeff Kirsher } 1090f7917c00SJeff Kirsher #endif 1091f7917c00SJeff Kirsher 1092f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1093f7917c00SJeff Kirsher { 1094f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1095f7917c00SJeff Kirsher } 1096f7917c00SJeff Kirsher 1097f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1098f7917c00SJeff Kirsher { 1099f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1100f7917c00SJeff Kirsher } 1101f7917c00SJeff Kirsher 1102f7917c00SJeff Kirsher /** 1103098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1104098ef6c2SHariprasad Shenai * @adapter: the adapter 1105098ef6c2SHariprasad Shenai * @port_idx: the port index 1106098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1107098ef6c2SHariprasad Shenai * 1108098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1109098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1110098ef6c2SHariprasad Shenai */ 1111098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1112098ef6c2SHariprasad Shenai u8 hw_addr[]) 1113098ef6c2SHariprasad Shenai { 1114098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1115098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1116098ef6c2SHariprasad Shenai } 1117098ef6c2SHariprasad Shenai 1118098ef6c2SHariprasad Shenai /** 1119f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1120f7917c00SJeff Kirsher * @dev: the netdev 1121f7917c00SJeff Kirsher * 1122f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1123f7917c00SJeff Kirsher */ 1124f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1125f7917c00SJeff Kirsher { 1126f7917c00SJeff Kirsher return netdev_priv(dev); 1127f7917c00SJeff Kirsher } 1128f7917c00SJeff Kirsher 1129f7917c00SJeff Kirsher /** 1130f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1131f7917c00SJeff Kirsher * @adap: the adapter 1132f7917c00SJeff Kirsher * @idx: the port index 1133f7917c00SJeff Kirsher * 1134f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1135f7917c00SJeff Kirsher */ 1136f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1137f7917c00SJeff Kirsher { 1138f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1139f7917c00SJeff Kirsher } 1140f7917c00SJeff Kirsher 1141f7917c00SJeff Kirsher /** 1142f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1143f7917c00SJeff Kirsher * @dev: the netdev 1144f7917c00SJeff Kirsher * 1145f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1146f7917c00SJeff Kirsher */ 1147f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1148f7917c00SJeff Kirsher { 1149f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1150f7917c00SJeff Kirsher } 1151f7917c00SJeff Kirsher 11523a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 11533a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 11543a336cb1SHariprasad Shenai { 11553a336cb1SHariprasad Shenai spin_lock_init(&q->bpoll_lock); 11563a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 11573a336cb1SHariprasad Shenai } 11583a336cb1SHariprasad Shenai 11593a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 11603a336cb1SHariprasad Shenai { 11613a336cb1SHariprasad Shenai bool rc = true; 11623a336cb1SHariprasad Shenai 11633a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 11643a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 11653a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 11663a336cb1SHariprasad Shenai rc = false; 11673a336cb1SHariprasad Shenai } else { 11683a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_NAPI; 11693a336cb1SHariprasad Shenai } 11703a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 11713a336cb1SHariprasad Shenai return rc; 11723a336cb1SHariprasad Shenai } 11733a336cb1SHariprasad Shenai 11743a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 11753a336cb1SHariprasad Shenai { 11763a336cb1SHariprasad Shenai bool rc = false; 11773a336cb1SHariprasad Shenai 11783a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 11793a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 11803a336cb1SHariprasad Shenai rc = true; 11813a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 11823a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 11833a336cb1SHariprasad Shenai return rc; 11843a336cb1SHariprasad Shenai } 11853a336cb1SHariprasad Shenai 11863a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 11873a336cb1SHariprasad Shenai { 11883a336cb1SHariprasad Shenai bool rc = true; 11893a336cb1SHariprasad Shenai 11903a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 11913a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 11923a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 11933a336cb1SHariprasad Shenai rc = false; 11943a336cb1SHariprasad Shenai } else { 11953a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL; 11963a336cb1SHariprasad Shenai } 11973a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 11983a336cb1SHariprasad Shenai return rc; 11993a336cb1SHariprasad Shenai } 12003a336cb1SHariprasad Shenai 12013a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 12023a336cb1SHariprasad Shenai { 12033a336cb1SHariprasad Shenai bool rc = false; 12043a336cb1SHariprasad Shenai 12053a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 12063a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 12073a336cb1SHariprasad Shenai rc = true; 12083a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 12093a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 12103a336cb1SHariprasad Shenai return rc; 12113a336cb1SHariprasad Shenai } 12123a336cb1SHariprasad Shenai 12133a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 12143a336cb1SHariprasad Shenai { 12153a336cb1SHariprasad Shenai return q->bpoll_state & CXGB_POLL_USER_PEND; 12163a336cb1SHariprasad Shenai } 12173a336cb1SHariprasad Shenai #else 12183a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 12193a336cb1SHariprasad Shenai { 12203a336cb1SHariprasad Shenai } 12213a336cb1SHariprasad Shenai 12223a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 12233a336cb1SHariprasad Shenai { 12243a336cb1SHariprasad Shenai return true; 12253a336cb1SHariprasad Shenai } 12263a336cb1SHariprasad Shenai 12273a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 12283a336cb1SHariprasad Shenai { 12293a336cb1SHariprasad Shenai return false; 12303a336cb1SHariprasad Shenai } 12313a336cb1SHariprasad Shenai 12323a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 12333a336cb1SHariprasad Shenai { 12343a336cb1SHariprasad Shenai return false; 12353a336cb1SHariprasad Shenai } 12363a336cb1SHariprasad Shenai 12373a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 12383a336cb1SHariprasad Shenai { 12393a336cb1SHariprasad Shenai return false; 12403a336cb1SHariprasad Shenai } 12413a336cb1SHariprasad Shenai 12423a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 12433a336cb1SHariprasad Shenai { 12443a336cb1SHariprasad Shenai return false; 12453a336cb1SHariprasad Shenai } 12463a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 12473a336cb1SHariprasad Shenai 1248812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1249812034f1SHariprasad Shenai * - bits 0..9: chip version 1250812034f1SHariprasad Shenai * - bits 10..15: chip revision 1251812034f1SHariprasad Shenai * - bits 16..23: register dump version 1252812034f1SHariprasad Shenai */ 1253812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1254812034f1SHariprasad Shenai { 1255812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1256812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1257812034f1SHariprasad Shenai } 1258812034f1SHariprasad Shenai 1259812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1260812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1261812034f1SHariprasad Shenai const struct sge_rspq *q) 1262812034f1SHariprasad Shenai { 1263812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1264812034f1SHariprasad Shenai 1265812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1266812034f1SHariprasad Shenai } 1267812034f1SHariprasad Shenai 1268812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1269812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1270812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1271812034f1SHariprasad Shenai 1272f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1273f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1274f7917c00SJeff Kirsher 1275f7917c00SJeff Kirsher void *t4_alloc_mem(size_t size); 1276f7917c00SJeff Kirsher 1277f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 12785fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1279f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1280f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1281f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1282f7917c00SJeff Kirsher const struct pkt_gl *gl); 1283f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1284f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1285f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1286f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 12872337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 12882337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1289f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1290f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1291f7917c00SJeff Kirsher unsigned int iqid); 1292f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1293f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1294f7917c00SJeff Kirsher unsigned int cmplqid); 12950fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 12960fbc81b3SHariprasad Shenai unsigned int cmplqid); 1297f7917c00SJeff Kirsher int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1298f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid); 1299f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 130052367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1301f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1302f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 13033a336cb1SHariprasad Shenai int cxgb_busy_poll(struct napi_struct *napi); 1304812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1305812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 13063069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1307f7917c00SJeff Kirsher 1308f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1309f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1310f7917c00SJeff Kirsher 13119a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 13129a4da2cdSVipul Pandya { 13139a4da2cdSVipul Pandya return adap->params.bypass; 13149a4da2cdSVipul Pandya } 13159a4da2cdSVipul Pandya 13169a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 13179a4da2cdSVipul Pandya { 13189a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 13199a4da2cdSVipul Pandya switch (device) { 13209a4da2cdSVipul Pandya case 0x440b: 13219a4da2cdSVipul Pandya case 0x440c: 13229a4da2cdSVipul Pandya return 1; 13239a4da2cdSVipul Pandya default: 13249a4da2cdSVipul Pandya return 0; 13259a4da2cdSVipul Pandya } 13269a4da2cdSVipul Pandya } 13279a4da2cdSVipul Pandya 132801b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 132901b69614SHariprasad Shenai { 133001b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 133101b69614SHariprasad Shenai switch (device) { 133201b69614SHariprasad Shenai case 0x4409: 133301b69614SHariprasad Shenai case 0x4486: 133401b69614SHariprasad Shenai return 1; 133501b69614SHariprasad Shenai 133601b69614SHariprasad Shenai default: 133701b69614SHariprasad Shenai return 0; 133801b69614SHariprasad Shenai } 133901b69614SHariprasad Shenai } 134001b69614SHariprasad Shenai 1341f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1342f7917c00SJeff Kirsher { 1343f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1344f7917c00SJeff Kirsher } 1345f7917c00SJeff Kirsher 1346f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1347f7917c00SJeff Kirsher unsigned int us) 1348f7917c00SJeff Kirsher { 1349f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1350f7917c00SJeff Kirsher } 1351f7917c00SJeff Kirsher 135252367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 135352367a76SVipul Pandya unsigned int ticks) 135452367a76SVipul Pandya { 135552367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 135652367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 135752367a76SVipul Pandya adapter->params.vpd.cclk); 135852367a76SVipul Pandya } 135952367a76SVipul Pandya 1360f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1361f7917c00SJeff Kirsher u32 val); 1362f7917c00SJeff Kirsher 136301b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 136401b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1365f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1366f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1367f7917c00SJeff Kirsher 136801b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 136901b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 137001b69614SHariprasad Shenai int timeout) 137101b69614SHariprasad Shenai { 137201b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 137301b69614SHariprasad Shenai timeout); 137401b69614SHariprasad Shenai } 137501b69614SHariprasad Shenai 1376f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1377f7917c00SJeff Kirsher int size, void *rpl) 1378f7917c00SJeff Kirsher { 1379f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1380f7917c00SJeff Kirsher } 1381f7917c00SJeff Kirsher 1382f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1383f7917c00SJeff Kirsher int size, void *rpl) 1384f7917c00SJeff Kirsher { 1385f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1386f7917c00SJeff Kirsher } 1387f7917c00SJeff Kirsher 1388fc08a01aSHariprasad Shenai /** 1389fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1390fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1391fc08a01aSHariprasad Shenai * 1392fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1393fc08a01aSHariprasad Shenai * (hash) address matching. 1394fc08a01aSHariprasad Shenai */ 1395fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1396fc08a01aSHariprasad Shenai { 1397fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1398fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1399fc08a01aSHariprasad Shenai 1400fc08a01aSHariprasad Shenai a ^= b; 1401fc08a01aSHariprasad Shenai a ^= (a >> 12); 1402fc08a01aSHariprasad Shenai a ^= (a >> 6); 1403fc08a01aSHariprasad Shenai return a & 0x3f; 1404fc08a01aSHariprasad Shenai } 1405fc08a01aSHariprasad Shenai 140694cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 140794cdb8bbSHariprasad Shenai unsigned int cnt); 140894cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 140994cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 141094cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 141194cdb8bbSHariprasad Shenai { 141294cdb8bbSHariprasad Shenai q->adap = adap; 141394cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 141494cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 141594cdb8bbSHariprasad Shenai q->size = size; 141694cdb8bbSHariprasad Shenai } 141794cdb8bbSHariprasad Shenai 141813ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 141913ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 142013ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1421f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1422f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1423f2b7e78dSVipul Pandya unsigned int start_idx); 14240abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1425f2b7e78dSVipul Pandya 1426f2b7e78dSVipul Pandya struct fw_filter_wr; 1427f2b7e78dSVipul Pandya 1428f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1429f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1430f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1431f7917c00SJeff Kirsher 14328203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 14334036da90SHariprasad Shenai int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1434f7917c00SJeff Kirsher struct link_config *lc); 1435f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1436fc5ab020SHariprasad Shenai 1437b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1438b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1439b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1440b562fc37SHariprasad Shenai 1441fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1442fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1443fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1444f01aa633SHariprasad Shenai void *buf, int dir); 1445fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1446fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1447fc5ab020SHariprasad Shenai { 1448fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1449fc5ab020SHariprasad Shenai } 1450fc5ab020SHariprasad Shenai 1451812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1452812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1453812034f1SHariprasad Shenai 1454f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1455098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1456098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 145749216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 145849216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1459f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 146001b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 146101b69614SHariprasad Shenai int win, spinlock_t *lock, 146201b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 146301b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 146401b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 146549216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 146622c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 146722c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1468acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1469636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1470a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 147116e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 14720de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 147316e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1474ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 147516e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 147616e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 147716e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1478f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 1479e85c9a7aSHariprasad Shenai 1480e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1481b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1482e85c9a7aSHariprasad Shenai unsigned int qid, 1483e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 148466cf188eSHariprasad S int user, 1485e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1486e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1487e85c9a7aSHariprasad Shenai 1488dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1489dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1490ae469b68SHariprasad Shenai 1491ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1492e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 1493dcf7b6f5SKumar Sanghvi int t4_init_tp_params(struct adapter *adap); 1494dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1495c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1496c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1497c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1498f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1499f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1500f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1501f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1502f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1503f7917c00SJeff Kirsher unsigned int flags); 1504c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1505c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1506688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 1507688ea5feSHariprasad Shenai void t4_read_rss_key(struct adapter *adapter, u32 *key); 1508688ea5feSHariprasad Shenai void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1509688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1510688ea5feSHariprasad Shenai u32 *valp); 1511688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1512688ea5feSHariprasad Shenai u32 *vfl, u32 *vfh); 1513688ea5feSHariprasad Shenai u32 t4_read_rss_pf_map(struct adapter *adapter); 1514688ea5feSHariprasad Shenai u32 t4_read_rss_pf_mask(struct adapter *adapter); 1515688ea5feSHariprasad Shenai 1516145ef8a5SHariprasad Shenai unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1517b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1518b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1519e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1520e5f0e43bSHariprasad Shenai size_t n); 1521c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1522c778af7dSHariprasad Shenai size_t n); 1523f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1524f1ff24aaSHariprasad Shenai unsigned int *valp); 1525f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1526f1ff24aaSHariprasad Shenai const unsigned int *valp); 1527f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 152819689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 152919689609SHariprasad Shenai unsigned int *pif_req_wrptr, 153019689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 153126fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 153274b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 153372aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1534f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1535a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1536a4cfd929SHariprasad Shenai struct port_stats *stats, 1537a4cfd929SHariprasad Shenai struct port_stats *offset); 153865046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1539f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1540bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1541636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1542636f9d37SVipul Pandya unsigned int mask, unsigned int val); 15432d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1544a4cfd929SHariprasad Shenai void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 1545a6222975SHariprasad Shenai void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 1546a4cfd929SHariprasad Shenai void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 1547a4cfd929SHariprasad Shenai void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 1548f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1549f7917c00SJeff Kirsher struct tp_tcp_stats *v6); 1550a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 1551a6222975SHariprasad Shenai struct tp_fcoe_stats *st); 1552f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1553f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1554f7917c00SJeff Kirsher 1555797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1556797ff0f5SHariprasad Shenai 15577864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1558f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1559f2b7e78dSVipul Pandya 1560f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1561f7917c00SJeff Kirsher const u8 *addr); 1562f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1563f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1564f7917c00SJeff Kirsher 1565f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1566f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1567f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1568f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1569f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1570636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1571636f9d37SVipul Pandya unsigned int cache_line_size); 1572636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1573f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1574f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1575f7917c00SJeff Kirsher u32 *val); 157601b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1577f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 157801b69614SHariprasad Shenai u32 *val, int rw); 157901b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1580688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1581688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 158201b69614SHariprasad Shenai const u32 *val, int timeout); 158301b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 158401b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1585688848b1SAnish Bhatt const u32 *val); 1586f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1587f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1588f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1589f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1590f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1591f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1592f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1593f7917c00SJeff Kirsher unsigned int *rss_size); 15944f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 15954f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 15964f3a0fcfSHariprasad Shenai unsigned int viid); 1597f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1598f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1599f7917c00SJeff Kirsher bool sleep_ok); 1600f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1601f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1602f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1603fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1604fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1605fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1606f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1607f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1608f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1609f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1610688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1611688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1612f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1613f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1614f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1615f7917c00SJeff Kirsher unsigned int nblinks); 1616f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1617f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1618f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1619f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1620ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1621ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1622ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1623f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1624f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1625f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1626f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1627f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1628f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1629f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1630f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1631f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 16325d700ecbSHariprasad Shenai int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 163323853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 1634f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1635881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1636881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 16378e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 16388e3d04fdSHariprasad Shenai int filter_index, int enable); 16398e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 16408e3d04fdSHariprasad Shenai int filter_index, int *enabled); 16418caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 16428caa1e84SVipul Pandya u32 addr, u32 val); 1643b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1644b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1645b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 164668bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1647fd88b31aSHariprasad Shenai void t4_free_mem(void *addr); 1648a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1649a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1650a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1651a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1652a3bfb617SHariprasad Shenai int hz, int ticks); 1653858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1654858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 16550fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 16560fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 16570fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 16580fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 165994cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1660f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1661