1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 505e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 51a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 52a4569504SAtul Gupta #include <linux/ptp_classify.h> 53f7917c00SJeff Kirsher #include <asm/io.h> 5427999805SHariprasad S #include "t4_chip_type.h" 55f7917c00SJeff Kirsher #include "cxgb4_uld.h" 56f7917c00SJeff Kirsher 573069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 5894cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 5994cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 603069ee9bSVipul Pandya 61f7917c00SJeff Kirsher enum { 62f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 63f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 64f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 65f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 66a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 67098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 68f7917c00SJeff Kirsher }; 69f7917c00SJeff Kirsher 70f7917c00SJeff Kirsher enum { 71812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 72812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 73812034f1SHariprasad Shenai }; 74812034f1SHariprasad Shenai 75812034f1SHariprasad Shenai enum { 76f7917c00SJeff Kirsher MEM_EDC0, 77f7917c00SJeff Kirsher MEM_EDC1, 782422d9a3SSantosh Rastapur MEM_MC, 792422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 802422d9a3SSantosh Rastapur MEM_MC1 81f7917c00SJeff Kirsher }; 82f7917c00SJeff Kirsher 833069ee9bSVipul Pandya enum { 843eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 853eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 863069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 873069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 882422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 893eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 903eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 910abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 920abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 933069ee9bSVipul Pandya }; 943069ee9bSVipul Pandya 95f7917c00SJeff Kirsher enum dev_master { 96f7917c00SJeff Kirsher MASTER_CANT, 97f7917c00SJeff Kirsher MASTER_MAY, 98f7917c00SJeff Kirsher MASTER_MUST 99f7917c00SJeff Kirsher }; 100f7917c00SJeff Kirsher 101f7917c00SJeff Kirsher enum dev_state { 102f7917c00SJeff Kirsher DEV_STATE_UNINIT, 103f7917c00SJeff Kirsher DEV_STATE_INIT, 104f7917c00SJeff Kirsher DEV_STATE_ERR 105f7917c00SJeff Kirsher }; 106f7917c00SJeff Kirsher 107c3168cabSGanesh Goudar enum cc_pause { 108f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 109f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 110f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 111f7917c00SJeff Kirsher }; 112f7917c00SJeff Kirsher 113c3168cabSGanesh Goudar enum cc_fec { 1143bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1153bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1163bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1173bb4858fSGanesh Goudar }; 1183bb4858fSGanesh Goudar 119f7917c00SJeff Kirsher struct port_stats { 120f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 121f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 122f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 123f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 124f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 125f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 126f7917c00SJeff Kirsher 127f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 128f7917c00SJeff Kirsher u64 tx_frames_65_127; 129f7917c00SJeff Kirsher u64 tx_frames_128_255; 130f7917c00SJeff Kirsher u64 tx_frames_256_511; 131f7917c00SJeff Kirsher u64 tx_frames_512_1023; 132f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 133f7917c00SJeff Kirsher u64 tx_frames_1519_max; 134f7917c00SJeff Kirsher 135f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 136f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 137f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 138f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 139f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 140f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 141f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 142f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 143f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 144f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 145f7917c00SJeff Kirsher 146f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 147f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 148f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 149f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 150f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 151f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 152f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 153f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 154f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 155f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 156f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 157f7917c00SJeff Kirsher 158f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 159f7917c00SJeff Kirsher u64 rx_frames_65_127; 160f7917c00SJeff Kirsher u64 rx_frames_128_255; 161f7917c00SJeff Kirsher u64 rx_frames_256_511; 162f7917c00SJeff Kirsher u64 rx_frames_512_1023; 163f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 164f7917c00SJeff Kirsher u64 rx_frames_1519_max; 165f7917c00SJeff Kirsher 166f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 167f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 168f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 169f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 170f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 171f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 172f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 173f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 174f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 175f7917c00SJeff Kirsher 176f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 177f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 178f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 179f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 180f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 181f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 182f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 183f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 184f7917c00SJeff Kirsher }; 185f7917c00SJeff Kirsher 186f7917c00SJeff Kirsher struct lb_port_stats { 187f7917c00SJeff Kirsher u64 octets; 188f7917c00SJeff Kirsher u64 frames; 189f7917c00SJeff Kirsher u64 bcast_frames; 190f7917c00SJeff Kirsher u64 mcast_frames; 191f7917c00SJeff Kirsher u64 ucast_frames; 192f7917c00SJeff Kirsher u64 error_frames; 193f7917c00SJeff Kirsher 194f7917c00SJeff Kirsher u64 frames_64; 195f7917c00SJeff Kirsher u64 frames_65_127; 196f7917c00SJeff Kirsher u64 frames_128_255; 197f7917c00SJeff Kirsher u64 frames_256_511; 198f7917c00SJeff Kirsher u64 frames_512_1023; 199f7917c00SJeff Kirsher u64 frames_1024_1518; 200f7917c00SJeff Kirsher u64 frames_1519_max; 201f7917c00SJeff Kirsher 202f7917c00SJeff Kirsher u64 drop; 203f7917c00SJeff Kirsher 204f7917c00SJeff Kirsher u64 ovflow0; 205f7917c00SJeff Kirsher u64 ovflow1; 206f7917c00SJeff Kirsher u64 ovflow2; 207f7917c00SJeff Kirsher u64 ovflow3; 208f7917c00SJeff Kirsher u64 trunc0; 209f7917c00SJeff Kirsher u64 trunc1; 210f7917c00SJeff Kirsher u64 trunc2; 211f7917c00SJeff Kirsher u64 trunc3; 212f7917c00SJeff Kirsher }; 213f7917c00SJeff Kirsher 214f7917c00SJeff Kirsher struct tp_tcp_stats { 215a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 216a4cfd929SHariprasad Shenai u64 tcp_in_segs; 217a4cfd929SHariprasad Shenai u64 tcp_out_segs; 218a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 219a4cfd929SHariprasad Shenai }; 220a4cfd929SHariprasad Shenai 221a4cfd929SHariprasad Shenai struct tp_usm_stats { 222a4cfd929SHariprasad Shenai u32 frames; 223a4cfd929SHariprasad Shenai u32 drops; 224a4cfd929SHariprasad Shenai u64 octets; 225f7917c00SJeff Kirsher }; 226f7917c00SJeff Kirsher 227a6222975SHariprasad Shenai struct tp_fcoe_stats { 228a6222975SHariprasad Shenai u32 frames_ddp; 229a6222975SHariprasad Shenai u32 frames_drop; 230a6222975SHariprasad Shenai u64 octets_ddp; 231f7917c00SJeff Kirsher }; 232f7917c00SJeff Kirsher 233f7917c00SJeff Kirsher struct tp_err_stats { 234a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 235a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 236a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 237a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 238a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 239a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 240a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 241a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 242a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 243a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 244a4cfd929SHariprasad Shenai }; 245a4cfd929SHariprasad Shenai 246a6222975SHariprasad Shenai struct tp_cpl_stats { 247a6222975SHariprasad Shenai u32 req[4]; 248a6222975SHariprasad Shenai u32 rsp[4]; 249a6222975SHariprasad Shenai }; 250a6222975SHariprasad Shenai 251a4cfd929SHariprasad Shenai struct tp_rdma_stats { 252a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 253a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 254f7917c00SJeff Kirsher }; 255f7917c00SJeff Kirsher 256e85c9a7aSHariprasad Shenai struct sge_params { 257e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 258e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 259e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 260e85c9a7aSHariprasad Shenai }; 261e85c9a7aSHariprasad Shenai 262f7917c00SJeff Kirsher struct tp_params { 263f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2642d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 265dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 266dca4faebSVipul Pandya /* channel map */ 267636f9d37SVipul Pandya 268636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 269636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 270dcf7b6f5SKumar Sanghvi 271dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 272dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 273dcf7b6f5SKumar Sanghvi 2748eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2758eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2768eb9f2f9SArjun V */ 2778eb9f2f9SArjun V int rx_pkt_encap; 2788eb9f2f9SArjun V 279dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 280dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 281dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 282dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 283dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 284dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 285dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 286dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 287dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 288dcf7b6f5SKumar Sanghvi * present. 289dcf7b6f5SKumar Sanghvi */ 290dcf7b6f5SKumar Sanghvi int vlan_shift; 291dcf7b6f5SKumar Sanghvi int vnic_shift; 292dcf7b6f5SKumar Sanghvi int port_shift; 293dcf7b6f5SKumar Sanghvi int protocol_shift; 294f7917c00SJeff Kirsher }; 295f7917c00SJeff Kirsher 296f7917c00SJeff Kirsher struct vpd_params { 297f7917c00SJeff Kirsher unsigned int cclk; 298f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 299f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 300f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 301a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 302098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 303f7917c00SJeff Kirsher }; 304f7917c00SJeff Kirsher 305f7917c00SJeff Kirsher struct pci_params { 306f7917c00SJeff Kirsher unsigned char speed; 307f7917c00SJeff Kirsher unsigned char width; 308f7917c00SJeff Kirsher }; 309f7917c00SJeff Kirsher 31049aa284fSHariprasad Shenai struct devlog_params { 31149aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 31249aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 31349aa284fSHariprasad Shenai u32 size; /* size of log */ 31449aa284fSHariprasad Shenai }; 31549aa284fSHariprasad Shenai 3163ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3173ccc6cf7SHariprasad Shenai struct arch_specific_params { 3183ccc6cf7SHariprasad Shenai u8 nchan; 31944588560SHariprasad Shenai u8 pm_stats_cnt; 3202216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3213ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3223ccc6cf7SHariprasad Shenai u16 vfcount; 3233ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3243ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3253ccc6cf7SHariprasad Shenai }; 3263ccc6cf7SHariprasad Shenai 327f7917c00SJeff Kirsher struct adapter_params { 328e85c9a7aSHariprasad Shenai struct sge_params sge; 329f7917c00SJeff Kirsher struct tp_params tp; 330f7917c00SJeff Kirsher struct vpd_params vpd; 331f7917c00SJeff Kirsher struct pci_params pci; 33249aa284fSHariprasad Shenai struct devlog_params devlog; 33349aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 334f7917c00SJeff Kirsher 335f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 336f1ff24aaSHariprasad Shenai 337f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 338f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 339f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 340f7917c00SJeff Kirsher 341760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3420de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 343760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3440de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 345760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 346760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 347f7917c00SJeff Kirsher u8 api_vers[7]; 348f7917c00SJeff Kirsher 349f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 350f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 351f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 352f7917c00SJeff Kirsher 353f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 354f7917c00SJeff Kirsher unsigned char portvec; 355d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3563ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 357f7917c00SJeff Kirsher unsigned char offload; 35894cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 359f7917c00SJeff Kirsher 3609a4da2cdSVipul Pandya unsigned char bypass; 3619a4da2cdSVipul Pandya 362f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3631ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3644c2c5763SHariprasad Shenai 365b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 3664c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3674c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 368086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 369c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 3700ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 3718f46d467SArjun Vynipadath 3728f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 3738f46d467SArjun Vynipadath * used by the Port 3748f46d467SArjun Vynipadath */ 3758f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 376f7917c00SJeff Kirsher }; 377f7917c00SJeff Kirsher 378a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 379a3bfb617SHariprasad Shenai * and possible hangs. 380a3bfb617SHariprasad Shenai */ 381a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 382a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 383a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 384a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 385a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 386a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 387a3bfb617SHariprasad Shenai }; 388a3bfb617SHariprasad Shenai 3897f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 3907f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 3917f080c3fSHariprasad Shenai * error returns. 3927f080c3fSHariprasad Shenai */ 3937f080c3fSHariprasad Shenai struct mbox_cmd { 3947f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 3957f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 3967f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 3977f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 3987f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 3997f080c3fSHariprasad Shenai }; 4007f080c3fSHariprasad Shenai 4017f080c3fSHariprasad Shenai struct mbox_cmd_log { 4027f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4037f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4047f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4057f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4067f080c3fSHariprasad Shenai }; 4077f080c3fSHariprasad Shenai 4087f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4097f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4107f080c3fSHariprasad Shenai */ 4117f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4127f080c3fSHariprasad Shenai unsigned int entry_idx) 4137f080c3fSHariprasad Shenai { 4147f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4157f080c3fSHariprasad Shenai } 4167f080c3fSHariprasad Shenai 41716e47624SHariprasad Shenai #include "t4fw_api.h" 41816e47624SHariprasad Shenai 41916e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 420b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 421b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 422b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 423b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 42416e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 42516e47624SHariprasad Shenai 42616e47624SHariprasad Shenai struct fw_info { 42716e47624SHariprasad Shenai u8 chip; 42816e47624SHariprasad Shenai char *fs_name; 42916e47624SHariprasad Shenai char *fw_mod_name; 43016e47624SHariprasad Shenai struct fw_hdr fw_hdr; 43116e47624SHariprasad Shenai }; 43216e47624SHariprasad Shenai 433f7917c00SJeff Kirsher struct trace_params { 434f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 435f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 436f7917c00SJeff Kirsher unsigned short snap_len; 437f7917c00SJeff Kirsher unsigned short min_len; 438f7917c00SJeff Kirsher unsigned char skip_ofst; 439f7917c00SJeff Kirsher unsigned char skip_len; 440f7917c00SJeff Kirsher unsigned char invert; 441f7917c00SJeff Kirsher unsigned char port; 442f7917c00SJeff Kirsher }; 443f7917c00SJeff Kirsher 444c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 445c3168cabSGanesh Goudar 446c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 447c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 448c3168cabSGanesh Goudar 449c3168cabSGanesh Goudar enum fw_caps { 450c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 451c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 452c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 453c3168cabSGanesh Goudar }; 454c3168cabSGanesh Goudar 455f7917c00SJeff Kirsher struct link_config { 456c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 457c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 458c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 459c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 460c3168cabSGanesh Goudar 461c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 462c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 463c3168cabSGanesh Goudar 464c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 465c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 466c3168cabSGanesh Goudar 467c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 468c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 469c3168cabSGanesh Goudar 470f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 471c3168cabSGanesh Goudar 472f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 473ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 474f7917c00SJeff Kirsher }; 475f7917c00SJeff Kirsher 476e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 477f7917c00SJeff Kirsher 478f7917c00SJeff Kirsher enum { 479f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 480f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 481f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 482f7917c00SJeff Kirsher }; 483f7917c00SJeff Kirsher 484f7917c00SJeff Kirsher enum { 485812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 486812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 487812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 488812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 489812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 490812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 491812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 492812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 493812034f1SHariprasad Shenai }; 494812034f1SHariprasad Shenai 495812034f1SHariprasad Shenai enum { 496cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 497cf38be6dSHariprasad Shenai /* forwarded interrupts */ 4980fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 499f7917c00SJeff Kirsher }; 500f7917c00SJeff Kirsher 501f7917c00SJeff Kirsher struct adapter; 502f7917c00SJeff Kirsher struct sge_rspq; 503f7917c00SJeff Kirsher 504688848b1SAnish Bhatt #include "cxgb4_dcb.h" 505688848b1SAnish Bhatt 50676fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 50776fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 50876fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 50976fed8a9SVarun Prakash 510f7917c00SJeff Kirsher struct port_info { 511f7917c00SJeff Kirsher struct adapter *adapter; 512f7917c00SJeff Kirsher u16 viid; 513f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 514f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 515f7917c00SJeff Kirsher s8 mdio_addr; 51640e9de4bSHariprasad Shenai enum fw_port_type port_type; 517f7917c00SJeff Kirsher u8 mod_type; 518f7917c00SJeff Kirsher u8 port_id; 519f7917c00SJeff Kirsher u8 tx_chan; 520f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 521f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 522f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 523f7917c00SJeff Kirsher u8 rss_mode; 524f7917c00SJeff Kirsher struct link_config link_cfg; 525f7917c00SJeff Kirsher u16 *rss; 526a4cfd929SHariprasad Shenai struct port_stats stats_base; 527688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 528688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 529688848b1SAnish Bhatt #endif 53076fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 53176fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 53276fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5335e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5345e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 535a4569504SAtul Gupta bool ptp_enable; 536b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 537f7917c00SJeff Kirsher }; 538f7917c00SJeff Kirsher 539f7917c00SJeff Kirsher struct dentry; 540f7917c00SJeff Kirsher struct work_struct; 541f7917c00SJeff Kirsher 542f7917c00SJeff Kirsher enum { /* adapter flags */ 543f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 544144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 545144be3d9SGavin Shan USING_MSI = (1 << 2), 546144be3d9SGavin Shan USING_MSIX = (1 << 3), 547f7917c00SJeff Kirsher FW_OK = (1 << 4), 54813ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 54952367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 55052367a76SVipul Pandya MASTER_PF = (1 << 7), 55152367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 552b0ba9d5fSCasey Leedom ROOT_NO_RELAXED_ORDERING = (1 << 10), 553e1f6198eSGanesh Goudar SHUTTING_DOWN = (1 << 11), 554f7917c00SJeff Kirsher }; 555f7917c00SJeff Kirsher 55694cdb8bbSHariprasad Shenai enum { 55794cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 55894cdb8bbSHariprasad Shenai }; 55994cdb8bbSHariprasad Shenai 560f7917c00SJeff Kirsher struct rx_sw_desc; 561f7917c00SJeff Kirsher 562f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 563f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 564f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 565f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 566f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 567f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 568f7917c00SJeff Kirsher unsigned long large_alloc_failed; 56970055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 57070055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 571f7917c00SJeff Kirsher unsigned long starving; 572f7917c00SJeff Kirsher /* RO fields */ 573f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 574f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 575f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 576f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 577f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 578df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 579df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 580f7917c00SJeff Kirsher }; 581f7917c00SJeff Kirsher 582f7917c00SJeff Kirsher /* A packet gather list */ 583f7917c00SJeff Kirsher struct pkt_gl { 5845e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 585e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 586f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 587f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 588f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 589f7917c00SJeff Kirsher }; 590f7917c00SJeff Kirsher 591f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 592f7917c00SJeff Kirsher const struct pkt_gl *gl); 5932337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 5942337ba42SVarun Prakash /* LRO related declarations for ULD */ 5952337ba42SVarun Prakash struct t4_lro_mgr { 5962337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 5972337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 5982337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 5992337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6002337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6012337ba42SVarun Prakash }; 602f7917c00SJeff Kirsher 603f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 604f7917c00SJeff Kirsher struct napi_struct napi; 605f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 606f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 607f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 608f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 609f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 610e553ec3fSHariprasad Shenai u8 adaptive_rx; 611f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 612f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 613f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 614f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 615f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 616f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 617f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 618f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 619df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 620df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 621f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 622f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 623f7917c00SJeff Kirsher struct adapter *adap; 624f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 625f7917c00SJeff Kirsher rspq_handler_t handler; 6262337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 6272337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 628f7917c00SJeff Kirsher }; 629f7917c00SJeff Kirsher 630f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 631f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 632f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 633f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 634f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 635f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 636f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 637f7917c00SJeff Kirsher }; 638f7917c00SJeff Kirsher 639f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 640f7917c00SJeff Kirsher struct sge_rspq rspq; 641f7917c00SJeff Kirsher struct sge_fl fl; 642f7917c00SJeff Kirsher struct sge_eth_stats stats; 643f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 644f7917c00SJeff Kirsher 645f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 646f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 647f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 648f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 649f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 650f7917c00SJeff Kirsher }; 651f7917c00SJeff Kirsher 652f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 653f7917c00SJeff Kirsher struct sge_rspq rspq; 654f7917c00SJeff Kirsher struct sge_fl fl; 655f7917c00SJeff Kirsher struct sge_ofld_stats stats; 656f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 657f7917c00SJeff Kirsher 658f7917c00SJeff Kirsher struct tx_desc { 659f7917c00SJeff Kirsher __be64 flit[8]; 660f7917c00SJeff Kirsher }; 661f7917c00SJeff Kirsher 662f7917c00SJeff Kirsher struct tx_sw_desc; 663f7917c00SJeff Kirsher 664f7917c00SJeff Kirsher struct sge_txq { 665f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 666ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 667f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 668f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 669f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 670f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 671f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 672f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 673f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 674f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 675f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 676f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 6773069ee9bSVipul Pandya spinlock_t db_lock; 6783069ee9bSVipul Pandya int db_disabled; 6793069ee9bSVipul Pandya unsigned short db_pidx; 68005eb2389SSteve Wise unsigned short db_pidx_inc; 681df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 682df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 683f7917c00SJeff Kirsher }; 684f7917c00SJeff Kirsher 685f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 686f7917c00SJeff Kirsher struct sge_txq q; 687f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 68810b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 68910b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 69010b00466SAnish Bhatt #endif 691f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 692f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 693f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 694f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 695f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 696f7917c00SJeff Kirsher 697ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 698f7917c00SJeff Kirsher struct sge_txq q; 699f7917c00SJeff Kirsher struct adapter *adap; 700f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 701f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 702126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 703f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 704f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 705f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 706f7917c00SJeff Kirsher 707f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 708f7917c00SJeff Kirsher struct sge_txq q; 709f7917c00SJeff Kirsher struct adapter *adap; 710f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 711f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 712f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 713f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 714f7917c00SJeff Kirsher 71594cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 71694cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 71794cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 71894cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 71994cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 72094cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 72194cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 72294cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 72394cdb8bbSHariprasad Shenai }; 72494cdb8bbSHariprasad Shenai 725ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 726ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 727ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 728ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 729ab677ff4SHariprasad Shenai }; 730ab677ff4SHariprasad Shenai 731f7917c00SJeff Kirsher struct sge { 732f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 733a4569504SAtul Gupta struct sge_eth_txq ptptxq; 734f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 735f7917c00SJeff Kirsher 736f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 737f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 73894cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 739ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 740f7917c00SJeff Kirsher 741f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 742f7917c00SJeff Kirsher spinlock_t intrq_lock; 743f7917c00SJeff Kirsher 744f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 745f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 746f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 7470fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 74894cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 749f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 750f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 75152367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 75252367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 75352367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 75452367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 75552367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 7560f4d201fSKumar Sanghvi 757a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 758f7917c00SJeff Kirsher unsigned int egr_start; 7594b8e27a8SHariprasad Shenai unsigned int egr_sz; 760f7917c00SJeff Kirsher unsigned int ingr_start; 7614b8e27a8SHariprasad Shenai unsigned int ingr_sz; 7624b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 7634b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 7644b8e27a8SHariprasad Shenai unsigned long *starving_fl; 7654b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 7665b377d11SHariprasad Shenai unsigned long *blocked_fl; 767f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 768f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 769f7917c00SJeff Kirsher }; 770f7917c00SJeff Kirsher 771f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 7720fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 773f7917c00SJeff Kirsher 774f7917c00SJeff Kirsher struct l2t_data; 775f7917c00SJeff Kirsher 7762422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 7772422d9a3SSantosh Rastapur 7787d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 7797d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 7807d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 7812422d9a3SSantosh Rastapur */ 7827d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 7832422d9a3SSantosh Rastapur 7842422d9a3SSantosh Rastapur #endif 7852422d9a3SSantosh Rastapur 786a4cfd929SHariprasad Shenai struct doorbell_stats { 787a4cfd929SHariprasad Shenai u32 db_drop; 788a4cfd929SHariprasad Shenai u32 db_empty; 789a4cfd929SHariprasad Shenai u32 db_full; 790a4cfd929SHariprasad Shenai }; 791a4cfd929SHariprasad Shenai 792fc08a01aSHariprasad Shenai struct hash_mac_addr { 793fc08a01aSHariprasad Shenai struct list_head list; 794fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 795fc08a01aSHariprasad Shenai }; 796fc08a01aSHariprasad Shenai 79794cdb8bbSHariprasad Shenai struct uld_msix_bmap { 79894cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 79994cdb8bbSHariprasad Shenai unsigned int mapsize; 80094cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 80194cdb8bbSHariprasad Shenai }; 80294cdb8bbSHariprasad Shenai 80394cdb8bbSHariprasad Shenai struct uld_msix_info { 80494cdb8bbSHariprasad Shenai unsigned short vec; 80594cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 8060fbc81b3SHariprasad Shenai unsigned int idx; 80794cdb8bbSHariprasad Shenai }; 80894cdb8bbSHariprasad Shenai 809661dbeb9SHariprasad Shenai struct vf_info { 810661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 8118ea4fae9SGanesh Goudar unsigned int tx_rate; 812661dbeb9SHariprasad Shenai bool pf_set_mac; 813661dbeb9SHariprasad Shenai }; 814661dbeb9SHariprasad Shenai 8154055ae5eSHariprasad Shenai struct mbox_list { 8164055ae5eSHariprasad Shenai struct list_head list; 8174055ae5eSHariprasad Shenai }; 8184055ae5eSHariprasad Shenai 819f7917c00SJeff Kirsher struct adapter { 820f7917c00SJeff Kirsher void __iomem *regs; 82122adfe0aSSantosh Rastapur void __iomem *bar2; 8220abfd152SHariprasad Shenai u32 t4_bar0; 823f7917c00SJeff Kirsher struct pci_dev *pdev; 824f7917c00SJeff Kirsher struct device *pdev_dev; 8250de72738SHariprasad Shenai const char *name; 8263069ee9bSVipul Pandya unsigned int mbox; 827b2612722SHariprasad Shenai unsigned int pf; 828f7917c00SJeff Kirsher unsigned int flags; 829e7b48a32SHariprasad Shenai unsigned int adap_idx; 8302422d9a3SSantosh Rastapur enum chip_type chip; 831f7917c00SJeff Kirsher 832f7917c00SJeff Kirsher int msg_enable; 833f7917c00SJeff Kirsher 834f7917c00SJeff Kirsher struct adapter_params params; 835f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 836f7917c00SJeff Kirsher unsigned int swintr; 837f7917c00SJeff Kirsher 838f7917c00SJeff Kirsher struct { 839f7917c00SJeff Kirsher unsigned short vec; 840f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 841f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 84294cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 84394cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 8440fbc81b3SHariprasad Shenai int msi_idx; 845f7917c00SJeff Kirsher 846a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 847f7917c00SJeff Kirsher struct sge sge; 848f7917c00SJeff Kirsher 849f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 850f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 851f7917c00SJeff Kirsher 852661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 853661dbeb9SHariprasad Shenai u8 num_vfs; 854661dbeb9SHariprasad Shenai 855793dad94SVipul Pandya u32 filter_mode; 856636f9d37SVipul Pandya unsigned int l2t_start; 857636f9d37SVipul Pandya unsigned int l2t_end; 858f7917c00SJeff Kirsher struct l2t_data *l2t; 859b5a02f50SAnish Bhatt unsigned int clipt_start; 860b5a02f50SAnish Bhatt unsigned int clipt_end; 861b5a02f50SAnish Bhatt struct clip_tbl *clipt; 8623bdb376eSKumar Sanghvi struct smt_data *smt; 8630fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 864f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 86594cdb8bbSHariprasad Shenai unsigned int num_uld; 8660fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 867f7917c00SJeff Kirsher struct list_head list_node; 86801bcca68SVipul Pandya struct list_head rcu_node; 869fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 870f7917c00SJeff Kirsher 8717714cb9eSVarun Prakash void *iscsi_ppm; 8727714cb9eSVarun Prakash 873f7917c00SJeff Kirsher struct tid_info tids; 874f7917c00SJeff Kirsher void **tid_release_head; 875f7917c00SJeff Kirsher spinlock_t tid_release_lock; 87629aaee65SAnish Bhatt struct workqueue_struct *workq; 877f7917c00SJeff Kirsher struct work_struct tid_release_task; 878881806bcSVipul Pandya struct work_struct db_full_task; 879881806bcSVipul Pandya struct work_struct db_drop_task; 880f7917c00SJeff Kirsher bool tid_release_task_busy; 881f7917c00SJeff Kirsher 8824055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 8834055ae5eSHariprasad Shenai spinlock_t mbox_lock; 8844055ae5eSHariprasad Shenai struct mbox_list mlist; 8854055ae5eSHariprasad Shenai 8867f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 8877f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 8887f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 8897f080c3fSHariprasad Shenai 8900fbc81b3SHariprasad Shenai struct mutex uld_mutex; 8910fbc81b3SHariprasad Shenai 892f7917c00SJeff Kirsher struct dentry *debugfs_root; 893621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 894621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 8958e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 8968e3d04fdSHariprasad Shenai * used for all 4 filters. 8978e3d04fdSHariprasad Shenai */ 898f7917c00SJeff Kirsher 899a4569504SAtul Gupta struct ptp_clock *ptp_clock; 900a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 901a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 902a4569504SAtul Gupta /* ptp lock */ 903a4569504SAtul Gupta spinlock_t ptp_lock; 904f7917c00SJeff Kirsher spinlock_t stats_lock; 905fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 906d8931847SRahul Lakkireddy 907d8931847SRahul Lakkireddy /* TC u32 offload */ 908d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 909ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 91062488e4bSKumar Sanghvi 91162488e4bSKumar Sanghvi /* TC flower offload */ 91262488e4bSKumar Sanghvi DECLARE_HASHTABLE(flower_anymatch_tbl, 9); 913e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 914ad75b7d3SRahul Lakkireddy 915ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 916ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 917f7917c00SJeff Kirsher }; 918f7917c00SJeff Kirsher 919b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 920b72a32daSRahul Lakkireddy * programmed with various parameters. 921b72a32daSRahul Lakkireddy */ 922b72a32daSRahul Lakkireddy struct ch_sched_params { 923b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 924b72a32daSRahul Lakkireddy union { 925b72a32daSRahul Lakkireddy struct { 926b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 927b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 928b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 929b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 930b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 931b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 932b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 933b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 934b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 935b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 936b72a32daSRahul Lakkireddy } params; 937b72a32daSRahul Lakkireddy } u; 938b72a32daSRahul Lakkireddy }; 939b72a32daSRahul Lakkireddy 94010a2604eSRahul Lakkireddy enum { 94110a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 94210a2604eSRahul Lakkireddy }; 94310a2604eSRahul Lakkireddy 94410a2604eSRahul Lakkireddy enum { 94510a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 94610a2604eSRahul Lakkireddy }; 94710a2604eSRahul Lakkireddy 94810a2604eSRahul Lakkireddy enum { 94910a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 95010a2604eSRahul Lakkireddy }; 95110a2604eSRahul Lakkireddy 95210a2604eSRahul Lakkireddy enum { 95310a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 95410a2604eSRahul Lakkireddy }; 95510a2604eSRahul Lakkireddy 95610a2604eSRahul Lakkireddy enum { 95710a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 95810a2604eSRahul Lakkireddy }; 95910a2604eSRahul Lakkireddy 9606cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 9616cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 9626cede1f1SRahul Lakkireddy */ 9636cede1f1SRahul Lakkireddy struct ch_sched_queue { 9646cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 9656cede1f1SRahul Lakkireddy s8 class; /* class index */ 9666cede1f1SRahul Lakkireddy }; 9676cede1f1SRahul Lakkireddy 968f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 969f2b7e78dSVipul Pandya */ 970f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 971f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 972f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 973f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 974f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 975f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 976f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 977f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 978f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 979f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 980f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 981f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 982f2b7e78dSVipul Pandya 983f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 984f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 985f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 986f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 987f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 988f2b7e78dSVipul Pandya * matching rules are true. 989f2b7e78dSVipul Pandya * 990f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 991f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 992f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 993f2b7e78dSVipul Pandya * MPS match type) ... 994f2b7e78dSVipul Pandya * 995f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 996f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 997f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 998f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 999f2b7e78dSVipul Pandya */ 1000f2b7e78dSVipul Pandya struct ch_filter_tuple { 1001f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1002f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1003f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1004f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1005f2b7e78dSVipul Pandya * set of fields. 1006f2b7e78dSVipul Pandya */ 1007f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1008f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1009f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1010f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1011f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 1012f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1013f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1014f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1015f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1016f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1017f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1018f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1019f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1020f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1021f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 1022f2b7e78dSVipul Pandya 1023f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1024f2b7e78dSVipul Pandya * available for field rules. 1025f2b7e78dSVipul Pandya */ 1026f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1027f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1028f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1029f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1030f2b7e78dSVipul Pandya }; 1031f2b7e78dSVipul Pandya 1032f2b7e78dSVipul Pandya /* A filter ioctl command. 1033f2b7e78dSVipul Pandya */ 1034f2b7e78dSVipul Pandya struct ch_filter_specification { 1035f2b7e78dSVipul Pandya /* Administrative fields for filter. 1036f2b7e78dSVipul Pandya */ 1037f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1038f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1039f2b7e78dSVipul Pandya 1040f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1041f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1042f2b7e78dSVipul Pandya */ 1043f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 1044f2b7e78dSVipul Pandya 1045f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1046f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1047f2b7e78dSVipul Pandya * out as egress packets. 1048f2b7e78dSVipul Pandya */ 1049f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1050f2b7e78dSVipul Pandya 1051f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1052f2b7e78dSVipul Pandya 1053f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1054f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1055f2b7e78dSVipul Pandya 1056f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1057f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1058f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1059f2b7e78dSVipul Pandya 1060f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1061f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1062f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1063f2b7e78dSVipul Pandya */ 1064f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1065f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1066f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1067f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 10680ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1069f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1070f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1071f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1072f2b7e78dSVipul Pandya 10730ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 10740ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 10750ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 10760ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 10770ff90994SKumar Sanghvi 10780ff90994SKumar Sanghvi /* reservation for future additions */ 10790ff90994SKumar Sanghvi u8 rsvd[24]; 10800ff90994SKumar Sanghvi 1081f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1082f2b7e78dSVipul Pandya */ 1083f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1084f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1085f2b7e78dSVipul Pandya }; 1086f2b7e78dSVipul Pandya 1087f2b7e78dSVipul Pandya enum { 1088f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1089f2b7e78dSVipul Pandya FILTER_DROP, 1090f2b7e78dSVipul Pandya FILTER_SWITCH 1091f2b7e78dSVipul Pandya }; 1092f2b7e78dSVipul Pandya 1093f2b7e78dSVipul Pandya enum { 1094f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1095f2b7e78dSVipul Pandya VLAN_REMOVE, 1096f2b7e78dSVipul Pandya VLAN_INSERT, 1097f2b7e78dSVipul Pandya VLAN_REWRITE 1098f2b7e78dSVipul Pandya }; 1099f2b7e78dSVipul Pandya 1100557ccbf9SKumar Sanghvi enum { 1101557ccbf9SKumar Sanghvi NAT_MODE_ALL = 7, /* NAT on entire 4-tuple */ 1102557ccbf9SKumar Sanghvi }; 1103557ccbf9SKumar Sanghvi 1104d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1105d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1106d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1107d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1108d57fd6caSRahul Lakkireddy * where the filter table is large. 1109d57fd6caSRahul Lakkireddy */ 1110d57fd6caSRahul Lakkireddy struct filter_entry { 1111d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1112d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1113d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1114d57fd6caSRahul Lakkireddy 1115d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1116578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1117d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 11183bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1119578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1120578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1121d57fd6caSRahul Lakkireddy 1122d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1123d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1124d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1125d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1126d57fd6caSRahul Lakkireddy */ 1127d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1128d57fd6caSRahul Lakkireddy }; 1129d57fd6caSRahul Lakkireddy 1130a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1131a4cfd929SHariprasad Shenai { 1132a4cfd929SHariprasad Shenai return adap->params.offload; 1133a4cfd929SHariprasad Shenai } 1134a4cfd929SHariprasad Shenai 113594cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 113694cdb8bbSHariprasad Shenai { 113794cdb8bbSHariprasad Shenai return adap->params.crypto; 113894cdb8bbSHariprasad Shenai } 113994cdb8bbSHariprasad Shenai 11400fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 11410fbc81b3SHariprasad Shenai { 11420fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 11430fbc81b3SHariprasad Shenai } 11440fbc81b3SHariprasad Shenai 1145f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1146f7917c00SJeff Kirsher { 1147f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1148f7917c00SJeff Kirsher } 1149f7917c00SJeff Kirsher 1150f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1151f7917c00SJeff Kirsher { 1152f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1153f7917c00SJeff Kirsher } 1154f7917c00SJeff Kirsher 1155f7917c00SJeff Kirsher #ifndef readq 1156f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1157f7917c00SJeff Kirsher { 1158f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1159f7917c00SJeff Kirsher } 1160f7917c00SJeff Kirsher 1161f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1162f7917c00SJeff Kirsher { 1163f7917c00SJeff Kirsher writel(val, addr); 1164f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1165f7917c00SJeff Kirsher } 1166f7917c00SJeff Kirsher #endif 1167f7917c00SJeff Kirsher 1168f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1169f7917c00SJeff Kirsher { 1170f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1171f7917c00SJeff Kirsher } 1172f7917c00SJeff Kirsher 1173f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1174f7917c00SJeff Kirsher { 1175f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1176f7917c00SJeff Kirsher } 1177f7917c00SJeff Kirsher 1178f7917c00SJeff Kirsher /** 1179098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1180098ef6c2SHariprasad Shenai * @adapter: the adapter 1181098ef6c2SHariprasad Shenai * @port_idx: the port index 1182098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1183098ef6c2SHariprasad Shenai * 1184098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1185098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1186098ef6c2SHariprasad Shenai */ 1187098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1188098ef6c2SHariprasad Shenai u8 hw_addr[]) 1189098ef6c2SHariprasad Shenai { 1190098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1191098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1192098ef6c2SHariprasad Shenai } 1193098ef6c2SHariprasad Shenai 1194098ef6c2SHariprasad Shenai /** 1195f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1196f7917c00SJeff Kirsher * @dev: the netdev 1197f7917c00SJeff Kirsher * 1198f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1199f7917c00SJeff Kirsher */ 1200f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1201f7917c00SJeff Kirsher { 1202f7917c00SJeff Kirsher return netdev_priv(dev); 1203f7917c00SJeff Kirsher } 1204f7917c00SJeff Kirsher 1205f7917c00SJeff Kirsher /** 1206f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1207f7917c00SJeff Kirsher * @adap: the adapter 1208f7917c00SJeff Kirsher * @idx: the port index 1209f7917c00SJeff Kirsher * 1210f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1211f7917c00SJeff Kirsher */ 1212f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1213f7917c00SJeff Kirsher { 1214f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1215f7917c00SJeff Kirsher } 1216f7917c00SJeff Kirsher 1217f7917c00SJeff Kirsher /** 1218f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1219f7917c00SJeff Kirsher * @dev: the netdev 1220f7917c00SJeff Kirsher * 1221f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1222f7917c00SJeff Kirsher */ 1223f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1224f7917c00SJeff Kirsher { 1225f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1226f7917c00SJeff Kirsher } 1227f7917c00SJeff Kirsher 1228812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1229812034f1SHariprasad Shenai * - bits 0..9: chip version 1230812034f1SHariprasad Shenai * - bits 10..15: chip revision 1231812034f1SHariprasad Shenai * - bits 16..23: register dump version 1232812034f1SHariprasad Shenai */ 1233812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1234812034f1SHariprasad Shenai { 1235812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1236812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1237812034f1SHariprasad Shenai } 1238812034f1SHariprasad Shenai 1239812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1240812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1241812034f1SHariprasad Shenai const struct sge_rspq *q) 1242812034f1SHariprasad Shenai { 1243812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1244812034f1SHariprasad Shenai 1245812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1246812034f1SHariprasad Shenai } 1247812034f1SHariprasad Shenai 1248812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1249812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1250812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1251812034f1SHariprasad Shenai 1252f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1253f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1254f7917c00SJeff Kirsher 1255f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 12565fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1257f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1258f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1259f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1260f7917c00SJeff Kirsher const struct pkt_gl *gl); 1261f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1262f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1263f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1264f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 12652337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 12662337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1267f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1268f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1269f7917c00SJeff Kirsher unsigned int iqid); 1270f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1271f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1272f7917c00SJeff Kirsher unsigned int cmplqid); 12730fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 12740fbc81b3SHariprasad Shenai unsigned int cmplqid); 1275ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1276ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1277ab677ff4SHariprasad Shenai unsigned int uld_type); 1278f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 127952367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1280f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1281f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1282812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1283812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 12843069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1285f7917c00SJeff Kirsher 1286f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1287f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1288f7917c00SJeff Kirsher 12899a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 12909a4da2cdSVipul Pandya { 12919a4da2cdSVipul Pandya return adap->params.bypass; 12929a4da2cdSVipul Pandya } 12939a4da2cdSVipul Pandya 12949a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 12959a4da2cdSVipul Pandya { 12969a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 12979a4da2cdSVipul Pandya switch (device) { 12989a4da2cdSVipul Pandya case 0x440b: 12999a4da2cdSVipul Pandya case 0x440c: 13009a4da2cdSVipul Pandya return 1; 13019a4da2cdSVipul Pandya default: 13029a4da2cdSVipul Pandya return 0; 13039a4da2cdSVipul Pandya } 13049a4da2cdSVipul Pandya } 13059a4da2cdSVipul Pandya 130601b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 130701b69614SHariprasad Shenai { 130801b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 130901b69614SHariprasad Shenai switch (device) { 131001b69614SHariprasad Shenai case 0x4409: 131101b69614SHariprasad Shenai case 0x4486: 131201b69614SHariprasad Shenai return 1; 131301b69614SHariprasad Shenai 131401b69614SHariprasad Shenai default: 131501b69614SHariprasad Shenai return 0; 131601b69614SHariprasad Shenai } 131701b69614SHariprasad Shenai } 131801b69614SHariprasad Shenai 1319f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1320f7917c00SJeff Kirsher { 1321f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1322f7917c00SJeff Kirsher } 1323f7917c00SJeff Kirsher 1324f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1325f7917c00SJeff Kirsher unsigned int us) 1326f7917c00SJeff Kirsher { 1327f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1328f7917c00SJeff Kirsher } 1329f7917c00SJeff Kirsher 133052367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 133152367a76SVipul Pandya unsigned int ticks) 133252367a76SVipul Pandya { 133352367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 133452367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 133552367a76SVipul Pandya adapter->params.vpd.cclk); 133652367a76SVipul Pandya } 133752367a76SVipul Pandya 1338f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1339f7917c00SJeff Kirsher u32 val); 1340f7917c00SJeff Kirsher 134101b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 134201b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1343f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1344f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1345f7917c00SJeff Kirsher 134601b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 134701b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 134801b69614SHariprasad Shenai int timeout) 134901b69614SHariprasad Shenai { 135001b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 135101b69614SHariprasad Shenai timeout); 135201b69614SHariprasad Shenai } 135301b69614SHariprasad Shenai 1354f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1355f7917c00SJeff Kirsher int size, void *rpl) 1356f7917c00SJeff Kirsher { 1357f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1358f7917c00SJeff Kirsher } 1359f7917c00SJeff Kirsher 1360f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1361f7917c00SJeff Kirsher int size, void *rpl) 1362f7917c00SJeff Kirsher { 1363f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1364f7917c00SJeff Kirsher } 1365f7917c00SJeff Kirsher 1366fc08a01aSHariprasad Shenai /** 1367fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1368fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1369fc08a01aSHariprasad Shenai * 1370fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1371fc08a01aSHariprasad Shenai * (hash) address matching. 1372fc08a01aSHariprasad Shenai */ 1373fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1374fc08a01aSHariprasad Shenai { 1375fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1376fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1377fc08a01aSHariprasad Shenai 1378fc08a01aSHariprasad Shenai a ^= b; 1379fc08a01aSHariprasad Shenai a ^= (a >> 12); 1380fc08a01aSHariprasad Shenai a ^= (a >> 6); 1381fc08a01aSHariprasad Shenai return a & 0x3f; 1382fc08a01aSHariprasad Shenai } 1383fc08a01aSHariprasad Shenai 138494cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 138594cdb8bbSHariprasad Shenai unsigned int cnt); 138694cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 138794cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 138894cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 138994cdb8bbSHariprasad Shenai { 139094cdb8bbSHariprasad Shenai q->adap = adap; 139194cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 139294cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 139394cdb8bbSHariprasad Shenai q->size = size; 139494cdb8bbSHariprasad Shenai } 139594cdb8bbSHariprasad Shenai 139613ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 139713ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 139813ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1399f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1400f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1401f2b7e78dSVipul Pandya unsigned int start_idx); 14020abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1403f2b7e78dSVipul Pandya 1404f2b7e78dSVipul Pandya struct fw_filter_wr; 1405f2b7e78dSVipul Pandya 1406f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1407f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1408f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1409f7917c00SJeff Kirsher 14108203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 14114036da90SHariprasad Shenai int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 1412f7917c00SJeff Kirsher struct link_config *lc); 1413f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1414fc5ab020SHariprasad Shenai 1415b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1416b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1417b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1418b562fc37SHariprasad Shenai 1419fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1420fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1421fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1422f01aa633SHariprasad Shenai void *buf, int dir); 1423fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1424fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1425fc5ab020SHariprasad Shenai { 1426fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1427fc5ab020SHariprasad Shenai } 1428fc5ab020SHariprasad Shenai 1429812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1430812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1431812034f1SHariprasad Shenai 1432f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1433098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1434098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 143549216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 143649216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1437f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 143801b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 143901b69614SHariprasad Shenai int win, spinlock_t *lock, 144001b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 144101b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 144201b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 144349216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 144422c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 144522c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1446acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1447636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1448a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 14494da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 145016e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 14510de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 145216e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1453ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1454760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1455760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1456760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1457760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 145816e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 145916e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 146016e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1461f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 14623be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1463e85c9a7aSHariprasad Shenai 1464e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1465b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1466e85c9a7aSHariprasad Shenai unsigned int qid, 1467e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 146866cf188eSHariprasad S int user, 1469e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1470e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1471e85c9a7aSHariprasad Shenai 1472dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1473dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1474ae469b68SHariprasad Shenai 1475ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1476e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 14775ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1478dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1479c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1480c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1481c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1482f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1483f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1484f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1485f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1486f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1487f7917c00SJeff Kirsher unsigned int flags); 1488c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1489c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1490688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 14915ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 14925ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 14935ccf9d04SRahul Lakkireddy bool sleep_ok); 1494688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 14955ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1496688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 14975ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 14985ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 14995ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1500688ea5feSHariprasad Shenai 1501193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1502193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1503b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1504b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1505e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1506e5f0e43bSHariprasad Shenai size_t n); 1507c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1508c778af7dSHariprasad Shenai size_t n); 1509f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1510f1ff24aaSHariprasad Shenai unsigned int *valp); 1511f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1512f1ff24aaSHariprasad Shenai const unsigned int *valp); 1513f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 151419689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 151519689609SHariprasad Shenai unsigned int *pif_req_wrptr, 151619689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 151726fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 151874b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 151972aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1520f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1521a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1522a4cfd929SHariprasad Shenai struct port_stats *stats, 1523a4cfd929SHariprasad Shenai struct port_stats *offset); 152465046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1525f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1526bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1527636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1528636f9d37SVipul Pandya unsigned int mask, unsigned int val); 15292d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 15305ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 15315ccf9d04SRahul Lakkireddy bool sleep_ok); 15325ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 15335ccf9d04SRahul Lakkireddy bool sleep_ok); 15345ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 15355ccf9d04SRahul Lakkireddy bool sleep_ok); 15365ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 15375ccf9d04SRahul Lakkireddy bool sleep_ok); 1538f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 15395ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1540a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 15415ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1542f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1543f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1544f7917c00SJeff Kirsher 1545797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1546797ff0f5SHariprasad Shenai 15477864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1548f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1549f2b7e78dSVipul Pandya 1550f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1551f7917c00SJeff Kirsher const u8 *addr); 1552f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1553f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1554f7917c00SJeff Kirsher 1555f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1556f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1557f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1558f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1559f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1560636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1561636f9d37SVipul Pandya unsigned int cache_line_size); 1562636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1563f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1564f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1565f7917c00SJeff Kirsher u32 *val); 15668f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 15678f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 15688f46d467SArjun Vynipadath u32 *val); 156901b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1570f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 15718f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 157201b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1573688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1574688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 157501b69614SHariprasad Shenai const u32 *val, int timeout); 157601b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 157701b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1578688848b1SAnish Bhatt const u32 *val); 1579f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1580f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1581f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1582f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1583f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1584f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1585f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1586f7917c00SJeff Kirsher unsigned int *rss_size); 15874f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 15884f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 15894f3a0fcfSHariprasad Shenai unsigned int viid); 1590f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1591f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1592f7917c00SJeff Kirsher bool sleep_ok); 1593f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1594f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1595f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1596fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1597fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1598fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1599f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1600f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1601f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1602f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1603688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1604688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1605f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1606f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1607f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1608f7917c00SJeff Kirsher unsigned int nblinks); 1609f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1610f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1611f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1612f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1613ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1614ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1615ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1616f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1617f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1618f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1619f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1620f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1621f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1622f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1623f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1624f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 16255d700ecbSHariprasad Shenai int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 162623853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 16272061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1628c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1629c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1630f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1631881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1632881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 16338e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 16348e3d04fdSHariprasad Shenai int filter_index, int enable); 16358e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 16368e3d04fdSHariprasad Shenai int filter_index, int *enabled); 16378caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 16388caa1e84SVipul Pandya u32 addr, u32 val); 1639b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1640b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1641b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 164268bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1643a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1644a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1645a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1646a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1647a3bfb617SHariprasad Shenai int hz, int ticks); 1648858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1649858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 16505ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 16515ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 16524359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 16534359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 16545ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 16555ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 16565ccf9d04SRahul Lakkireddy 16570fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 16580fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 16590fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 16600fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 166194cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1662ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1663ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1664ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1665f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1666