1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 490eb71a9dSNeilBrown #include <linux/rhashtable.h> 50098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 515e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 52a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 53a4569504SAtul Gupta #include <linux/ptp_classify.h> 541dde532dSRahul Lakkireddy #include <linux/crash_dump.h> 55b1871915SGanesh Goudar #include <linux/thermal.h> 56f7917c00SJeff Kirsher #include <asm/io.h> 5727999805SHariprasad S #include "t4_chip_type.h" 58f7917c00SJeff Kirsher #include "cxgb4_uld.h" 59f7917c00SJeff Kirsher 603069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 6194cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 6294cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 633069ee9bSVipul Pandya 64a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 65a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 66a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 67a6ec572bSAtul Gupta */ 68a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 69a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 70a6ec572bSAtul Gupta 71f7917c00SJeff Kirsher enum { 72f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 73f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 74f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 75f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 76a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 77098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 78f7917c00SJeff Kirsher }; 79f7917c00SJeff Kirsher 80f7917c00SJeff Kirsher enum { 81812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 82812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 83812034f1SHariprasad Shenai }; 84812034f1SHariprasad Shenai 85812034f1SHariprasad Shenai enum { 86f7917c00SJeff Kirsher MEM_EDC0, 87f7917c00SJeff Kirsher MEM_EDC1, 882422d9a3SSantosh Rastapur MEM_MC, 892422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 904db0401fSRahul Lakkireddy MEM_MC1, 914db0401fSRahul Lakkireddy MEM_HMA, 92f7917c00SJeff Kirsher }; 93f7917c00SJeff Kirsher 943069ee9bSVipul Pandya enum { 953eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 963eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 973069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 983069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 992422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 1003eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 1013eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 1020abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 1030abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1043069ee9bSVipul Pandya }; 1053069ee9bSVipul Pandya 106f7917c00SJeff Kirsher enum dev_master { 107f7917c00SJeff Kirsher MASTER_CANT, 108f7917c00SJeff Kirsher MASTER_MAY, 109f7917c00SJeff Kirsher MASTER_MUST 110f7917c00SJeff Kirsher }; 111f7917c00SJeff Kirsher 112f7917c00SJeff Kirsher enum dev_state { 113f7917c00SJeff Kirsher DEV_STATE_UNINIT, 114f7917c00SJeff Kirsher DEV_STATE_INIT, 115f7917c00SJeff Kirsher DEV_STATE_ERR 116f7917c00SJeff Kirsher }; 117f7917c00SJeff Kirsher 118c3168cabSGanesh Goudar enum cc_pause { 119f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 120f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 121f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 122f7917c00SJeff Kirsher }; 123f7917c00SJeff Kirsher 124c3168cabSGanesh Goudar enum cc_fec { 1253bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1263bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1273bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1283bb4858fSGanesh Goudar }; 1293bb4858fSGanesh Goudar 130f7917c00SJeff Kirsher struct port_stats { 131f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 132f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 133f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 134f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 135f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 136f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 137f7917c00SJeff Kirsher 138f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 139f7917c00SJeff Kirsher u64 tx_frames_65_127; 140f7917c00SJeff Kirsher u64 tx_frames_128_255; 141f7917c00SJeff Kirsher u64 tx_frames_256_511; 142f7917c00SJeff Kirsher u64 tx_frames_512_1023; 143f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 144f7917c00SJeff Kirsher u64 tx_frames_1519_max; 145f7917c00SJeff Kirsher 146f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 147f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 148f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 149f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 150f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 151f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 152f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 153f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 154f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 155f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 156f7917c00SJeff Kirsher 157f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 158f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 159f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 160f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 161f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 162f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 163f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 164f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 165f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 166f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 167f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 168f7917c00SJeff Kirsher 169f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 170f7917c00SJeff Kirsher u64 rx_frames_65_127; 171f7917c00SJeff Kirsher u64 rx_frames_128_255; 172f7917c00SJeff Kirsher u64 rx_frames_256_511; 173f7917c00SJeff Kirsher u64 rx_frames_512_1023; 174f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 175f7917c00SJeff Kirsher u64 rx_frames_1519_max; 176f7917c00SJeff Kirsher 177f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 178f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 179f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 180f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 181f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 182f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 183f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 184f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 185f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 186f7917c00SJeff Kirsher 187f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 188f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 189f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 190f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 191f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 192f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 193f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 194f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 195f7917c00SJeff Kirsher }; 196f7917c00SJeff Kirsher 197f7917c00SJeff Kirsher struct lb_port_stats { 198f7917c00SJeff Kirsher u64 octets; 199f7917c00SJeff Kirsher u64 frames; 200f7917c00SJeff Kirsher u64 bcast_frames; 201f7917c00SJeff Kirsher u64 mcast_frames; 202f7917c00SJeff Kirsher u64 ucast_frames; 203f7917c00SJeff Kirsher u64 error_frames; 204f7917c00SJeff Kirsher 205f7917c00SJeff Kirsher u64 frames_64; 206f7917c00SJeff Kirsher u64 frames_65_127; 207f7917c00SJeff Kirsher u64 frames_128_255; 208f7917c00SJeff Kirsher u64 frames_256_511; 209f7917c00SJeff Kirsher u64 frames_512_1023; 210f7917c00SJeff Kirsher u64 frames_1024_1518; 211f7917c00SJeff Kirsher u64 frames_1519_max; 212f7917c00SJeff Kirsher 213f7917c00SJeff Kirsher u64 drop; 214f7917c00SJeff Kirsher 215f7917c00SJeff Kirsher u64 ovflow0; 216f7917c00SJeff Kirsher u64 ovflow1; 217f7917c00SJeff Kirsher u64 ovflow2; 218f7917c00SJeff Kirsher u64 ovflow3; 219f7917c00SJeff Kirsher u64 trunc0; 220f7917c00SJeff Kirsher u64 trunc1; 221f7917c00SJeff Kirsher u64 trunc2; 222f7917c00SJeff Kirsher u64 trunc3; 223f7917c00SJeff Kirsher }; 224f7917c00SJeff Kirsher 225f7917c00SJeff Kirsher struct tp_tcp_stats { 226a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 227a4cfd929SHariprasad Shenai u64 tcp_in_segs; 228a4cfd929SHariprasad Shenai u64 tcp_out_segs; 229a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 230a4cfd929SHariprasad Shenai }; 231a4cfd929SHariprasad Shenai 232a4cfd929SHariprasad Shenai struct tp_usm_stats { 233a4cfd929SHariprasad Shenai u32 frames; 234a4cfd929SHariprasad Shenai u32 drops; 235a4cfd929SHariprasad Shenai u64 octets; 236f7917c00SJeff Kirsher }; 237f7917c00SJeff Kirsher 238a6222975SHariprasad Shenai struct tp_fcoe_stats { 239a6222975SHariprasad Shenai u32 frames_ddp; 240a6222975SHariprasad Shenai u32 frames_drop; 241a6222975SHariprasad Shenai u64 octets_ddp; 242f7917c00SJeff Kirsher }; 243f7917c00SJeff Kirsher 244f7917c00SJeff Kirsher struct tp_err_stats { 245a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 246a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 247a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 248a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 249a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 250a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 251a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 252a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 253a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 254a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 255a4cfd929SHariprasad Shenai }; 256a4cfd929SHariprasad Shenai 257a6222975SHariprasad Shenai struct tp_cpl_stats { 258a6222975SHariprasad Shenai u32 req[4]; 259a6222975SHariprasad Shenai u32 rsp[4]; 260a6222975SHariprasad Shenai }; 261a6222975SHariprasad Shenai 262a4cfd929SHariprasad Shenai struct tp_rdma_stats { 263a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 264a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 265f7917c00SJeff Kirsher }; 266f7917c00SJeff Kirsher 267e85c9a7aSHariprasad Shenai struct sge_params { 268e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 269e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 270e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 271e85c9a7aSHariprasad Shenai }; 272e85c9a7aSHariprasad Shenai 273f7917c00SJeff Kirsher struct tp_params { 274f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2752d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 276dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 277dca4faebSVipul Pandya /* channel map */ 278636f9d37SVipul Pandya 279636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 280636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 281dcf7b6f5SKumar Sanghvi 282dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 283dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 284dcf7b6f5SKumar Sanghvi 2858eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 2868eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 2878eb9f2f9SArjun V */ 2888eb9f2f9SArjun V int rx_pkt_encap; 2898eb9f2f9SArjun V 290dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 291dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 292dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 293dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 294dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 295dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 296dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 297dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 298dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 299dcf7b6f5SKumar Sanghvi * present. 300dcf7b6f5SKumar Sanghvi */ 3010ba9a3b6SKumar Sanghvi int fcoe_shift; 302dcf7b6f5SKumar Sanghvi int port_shift; 3030ba9a3b6SKumar Sanghvi int vnic_shift; 3040ba9a3b6SKumar Sanghvi int vlan_shift; 3050ba9a3b6SKumar Sanghvi int tos_shift; 306dcf7b6f5SKumar Sanghvi int protocol_shift; 3070ba9a3b6SKumar Sanghvi int ethertype_shift; 3080ba9a3b6SKumar Sanghvi int macmatch_shift; 3090ba9a3b6SKumar Sanghvi int matchtype_shift; 3100ba9a3b6SKumar Sanghvi int frag_shift; 3110ba9a3b6SKumar Sanghvi 3120ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 313f7917c00SJeff Kirsher }; 314f7917c00SJeff Kirsher 315f7917c00SJeff Kirsher struct vpd_params { 316f7917c00SJeff Kirsher unsigned int cclk; 317f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 318f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 319f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 320a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 321098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 322f7917c00SJeff Kirsher }; 323f7917c00SJeff Kirsher 3240eaec62aSCasey Leedom /* Maximum resources provisioned for a PCI PF. 3250eaec62aSCasey Leedom */ 3260eaec62aSCasey Leedom struct pf_resources { 3270eaec62aSCasey Leedom unsigned int nvi; /* N virtual interfaces */ 3280eaec62aSCasey Leedom unsigned int neq; /* N egress Qs */ 3290eaec62aSCasey Leedom unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 3300eaec62aSCasey Leedom unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 3310eaec62aSCasey Leedom unsigned int niq; /* N ingress Qs */ 3320eaec62aSCasey Leedom unsigned int tc; /* PCI-E traffic class */ 3330eaec62aSCasey Leedom unsigned int pmask; /* port access rights mask */ 3340eaec62aSCasey Leedom unsigned int nexactf; /* N exact MPS filters */ 3350eaec62aSCasey Leedom unsigned int r_caps; /* read capabilities */ 3360eaec62aSCasey Leedom unsigned int wx_caps; /* write/execute capabilities */ 3370eaec62aSCasey Leedom }; 3380eaec62aSCasey Leedom 339f7917c00SJeff Kirsher struct pci_params { 340baf50868SGanesh Goudar unsigned int vpd_cap_addr; 341f7917c00SJeff Kirsher unsigned char speed; 342f7917c00SJeff Kirsher unsigned char width; 343f7917c00SJeff Kirsher }; 344f7917c00SJeff Kirsher 34549aa284fSHariprasad Shenai struct devlog_params { 34649aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 34749aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 34849aa284fSHariprasad Shenai u32 size; /* size of log */ 34949aa284fSHariprasad Shenai }; 35049aa284fSHariprasad Shenai 3513ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3523ccc6cf7SHariprasad Shenai struct arch_specific_params { 3533ccc6cf7SHariprasad Shenai u8 nchan; 35444588560SHariprasad Shenai u8 pm_stats_cnt; 3552216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3563ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3573ccc6cf7SHariprasad Shenai u16 vfcount; 3583ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3593ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3603ccc6cf7SHariprasad Shenai }; 3613ccc6cf7SHariprasad Shenai 362f7917c00SJeff Kirsher struct adapter_params { 363e85c9a7aSHariprasad Shenai struct sge_params sge; 364f7917c00SJeff Kirsher struct tp_params tp; 365f7917c00SJeff Kirsher struct vpd_params vpd; 3660eaec62aSCasey Leedom struct pf_resources pfres; 367f7917c00SJeff Kirsher struct pci_params pci; 36849aa284fSHariprasad Shenai struct devlog_params devlog; 36949aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 370f7917c00SJeff Kirsher 371f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 372f1ff24aaSHariprasad Shenai 373f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 374f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 375f7917c00SJeff Kirsher 376760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3770de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 378760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3790de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 380760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 381760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 382f7917c00SJeff Kirsher u8 api_vers[7]; 383f7917c00SJeff Kirsher 384f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 385f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 386f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 387f7917c00SJeff Kirsher 388f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 389f7917c00SJeff Kirsher unsigned char portvec; 390d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 3913ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 392f7917c00SJeff Kirsher unsigned char offload; 39394cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 394f7917c00SJeff Kirsher 3959a4da2cdSVipul Pandya unsigned char bypass; 3965c31254eSKumar Sanghvi unsigned char hash_filter; 3979a4da2cdSVipul Pandya 398f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3991ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 4004c2c5763SHariprasad Shenai 401b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 4024c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 4034c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 404086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 405c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 4060ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 40702d805dcSSantosh Rastapur unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 4088f46d467SArjun Vynipadath 4098f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 4108f46d467SArjun Vynipadath * used by the Port 4118f46d467SArjun Vynipadath */ 4128f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 41343db9296SRaju Rangoju bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 414f3910c62SRaju Rangoju bool write_cmpl_support; /* FW supports WRITE_CMPL */ 415f7917c00SJeff Kirsher }; 416f7917c00SJeff Kirsher 417a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 418a3bfb617SHariprasad Shenai * and possible hangs. 419a3bfb617SHariprasad Shenai */ 420a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 421a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 422a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 423a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 424a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 425a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 426a3bfb617SHariprasad Shenai }; 427a3bfb617SHariprasad Shenai 4287f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 4297f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 4307f080c3fSHariprasad Shenai * error returns. 4317f080c3fSHariprasad Shenai */ 4327f080c3fSHariprasad Shenai struct mbox_cmd { 4337f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 4347f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 4357f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 4367f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 4377f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 4387f080c3fSHariprasad Shenai }; 4397f080c3fSHariprasad Shenai 4407f080c3fSHariprasad Shenai struct mbox_cmd_log { 4417f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4427f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4437f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4447f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4457f080c3fSHariprasad Shenai }; 4467f080c3fSHariprasad Shenai 4477f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4487f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4497f080c3fSHariprasad Shenai */ 4507f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4517f080c3fSHariprasad Shenai unsigned int entry_idx) 4527f080c3fSHariprasad Shenai { 4537f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4547f080c3fSHariprasad Shenai } 4557f080c3fSHariprasad Shenai 45616e47624SHariprasad Shenai #include "t4fw_api.h" 45716e47624SHariprasad Shenai 45816e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 459b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 460b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 461b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 462b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 46316e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 46416e47624SHariprasad Shenai 46516e47624SHariprasad Shenai struct fw_info { 46616e47624SHariprasad Shenai u8 chip; 46716e47624SHariprasad Shenai char *fs_name; 46816e47624SHariprasad Shenai char *fw_mod_name; 46916e47624SHariprasad Shenai struct fw_hdr fw_hdr; 47016e47624SHariprasad Shenai }; 47116e47624SHariprasad Shenai 472f7917c00SJeff Kirsher struct trace_params { 473f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 474f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 475f7917c00SJeff Kirsher unsigned short snap_len; 476f7917c00SJeff Kirsher unsigned short min_len; 477f7917c00SJeff Kirsher unsigned char skip_ofst; 478f7917c00SJeff Kirsher unsigned char skip_len; 479f7917c00SJeff Kirsher unsigned char invert; 480f7917c00SJeff Kirsher unsigned char port; 481f7917c00SJeff Kirsher }; 482f7917c00SJeff Kirsher 483c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 484c3168cabSGanesh Goudar 485c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 486c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 487c3168cabSGanesh Goudar 488c3168cabSGanesh Goudar enum fw_caps { 489c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 490c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 491c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 492c3168cabSGanesh Goudar }; 493c3168cabSGanesh Goudar 494f7917c00SJeff Kirsher struct link_config { 495c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 496c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 497c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 498c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 499c3168cabSGanesh Goudar 500c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 501c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 502c3168cabSGanesh Goudar 503c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 504c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 505c3168cabSGanesh Goudar 506c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 507c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 508c3168cabSGanesh Goudar 509f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 510c3168cabSGanesh Goudar 511f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 512ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 5138156b0baSGanesh Goudar 5148156b0baSGanesh Goudar bool new_module; /* ->OS Transceiver Module inserted */ 5158156b0baSGanesh Goudar bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 516f7917c00SJeff Kirsher }; 517f7917c00SJeff Kirsher 518e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 519f7917c00SJeff Kirsher 520f7917c00SJeff Kirsher enum { 521f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 522f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 523f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 524f7917c00SJeff Kirsher }; 525f7917c00SJeff Kirsher 526f7917c00SJeff Kirsher enum { 527812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 528812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 529812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 530812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 531812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 532812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 533812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 534812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 535812034f1SHariprasad Shenai }; 536812034f1SHariprasad Shenai 537812034f1SHariprasad Shenai enum { 53868ddc82aSRahul Lakkireddy MAX_TXQ_DESC_SIZE = 64, 53968ddc82aSRahul Lakkireddy MAX_RXQ_DESC_SIZE = 128, 54068ddc82aSRahul Lakkireddy MAX_FL_DESC_SIZE = 8, 54168ddc82aSRahul Lakkireddy MAX_CTRL_TXQ_DESC_SIZE = 64, 54268ddc82aSRahul Lakkireddy }; 54368ddc82aSRahul Lakkireddy 54468ddc82aSRahul Lakkireddy enum { 545cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 546cf38be6dSHariprasad Shenai /* forwarded interrupts */ 5470fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 548f7917c00SJeff Kirsher }; 549f7917c00SJeff Kirsher 550d5fbda61SArjun Vynipadath enum { 551d5fbda61SArjun Vynipadath PRIV_FLAG_PORT_TX_VM_BIT, 552d5fbda61SArjun Vynipadath }; 553d5fbda61SArjun Vynipadath 554d5fbda61SArjun Vynipadath #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 555d5fbda61SArjun Vynipadath 556d5fbda61SArjun Vynipadath #define PRIV_FLAGS_ADAP 0 557d5fbda61SArjun Vynipadath #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 558d5fbda61SArjun Vynipadath 559f7917c00SJeff Kirsher struct adapter; 560f7917c00SJeff Kirsher struct sge_rspq; 561f7917c00SJeff Kirsher 562688848b1SAnish Bhatt #include "cxgb4_dcb.h" 563688848b1SAnish Bhatt 56476fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 56576fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 56676fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 56776fed8a9SVarun Prakash 568f7917c00SJeff Kirsher struct port_info { 569f7917c00SJeff Kirsher struct adapter *adapter; 570f7917c00SJeff Kirsher u16 viid; 5713f8cfd0dSArjun Vynipadath int xact_addr_filt; /* index of exact MAC address filter */ 572f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 573f7917c00SJeff Kirsher s8 mdio_addr; 57440e9de4bSHariprasad Shenai enum fw_port_type port_type; 575f7917c00SJeff Kirsher u8 mod_type; 576f7917c00SJeff Kirsher u8 port_id; 577f7917c00SJeff Kirsher u8 tx_chan; 578f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 579f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 580f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 581f7917c00SJeff Kirsher u8 rss_mode; 582f7917c00SJeff Kirsher struct link_config link_cfg; 583f7917c00SJeff Kirsher u16 *rss; 584a4cfd929SHariprasad Shenai struct port_stats stats_base; 585688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 586688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 587688848b1SAnish Bhatt #endif 58876fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 58976fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 59076fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 5915e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 5925e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 593a4569504SAtul Gupta bool ptp_enable; 594b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 595d5fbda61SArjun Vynipadath u32 eth_flags; 59602d805dcSSantosh Rastapur 59702d805dcSSantosh Rastapur /* viid and smt fields either returned by fw 59802d805dcSSantosh Rastapur * or decoded by parsing viid by driver. 59902d805dcSSantosh Rastapur */ 60002d805dcSSantosh Rastapur u8 vin; 60102d805dcSSantosh Rastapur u8 vivld; 60202d805dcSSantosh Rastapur u8 smt_idx; 603f7917c00SJeff Kirsher }; 604f7917c00SJeff Kirsher 605f7917c00SJeff Kirsher struct dentry; 606f7917c00SJeff Kirsher struct work_struct; 607f7917c00SJeff Kirsher 608f7917c00SJeff Kirsher enum { /* adapter flags */ 609f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 610144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 611144be3d9SGavin Shan USING_MSI = (1 << 2), 612144be3d9SGavin Shan USING_MSIX = (1 << 3), 613f7917c00SJeff Kirsher FW_OK = (1 << 4), 61413ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 61552367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 61652367a76SVipul Pandya MASTER_PF = (1 << 7), 61752367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 618b0ba9d5fSCasey Leedom ROOT_NO_RELAXED_ORDERING = (1 << 10), 619e1f6198eSGanesh Goudar SHUTTING_DOWN = (1 << 11), 620d429005fSVishal Kulkarni SGE_DBQ_TIMER = (1 << 12), 621f7917c00SJeff Kirsher }; 622f7917c00SJeff Kirsher 62394cdb8bbSHariprasad Shenai enum { 62494cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 625a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 62694cdb8bbSHariprasad Shenai }; 62794cdb8bbSHariprasad Shenai 628f7917c00SJeff Kirsher struct rx_sw_desc; 629f7917c00SJeff Kirsher 630f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 631f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 632f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 633f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 634f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 635f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 636f7917c00SJeff Kirsher unsigned long large_alloc_failed; 63770055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 63870055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 639f7917c00SJeff Kirsher unsigned long starving; 640f7917c00SJeff Kirsher /* RO fields */ 641f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 642f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 643f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 644f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 645f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 646df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 647df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 648f7917c00SJeff Kirsher }; 649f7917c00SJeff Kirsher 650f7917c00SJeff Kirsher /* A packet gather list */ 651f7917c00SJeff Kirsher struct pkt_gl { 6525e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 653e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 654f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 655f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 656f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 657f7917c00SJeff Kirsher }; 658f7917c00SJeff Kirsher 659f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 660f7917c00SJeff Kirsher const struct pkt_gl *gl); 6612337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 6622337ba42SVarun Prakash /* LRO related declarations for ULD */ 6632337ba42SVarun Prakash struct t4_lro_mgr { 6642337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 6652337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 6662337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 6672337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6682337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6692337ba42SVarun Prakash }; 670f7917c00SJeff Kirsher 671f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 672f7917c00SJeff Kirsher struct napi_struct napi; 673f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 674f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 675f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 676f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 677f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 678e553ec3fSHariprasad Shenai u8 adaptive_rx; 679f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 680f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 681f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 682f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 683f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 684f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 685f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 686f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 687df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 688df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 689f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 690f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 691f7917c00SJeff Kirsher struct adapter *adap; 692f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 693f7917c00SJeff Kirsher rspq_handler_t handler; 6942337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 6952337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 696f7917c00SJeff Kirsher }; 697f7917c00SJeff Kirsher 698f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 699f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 700f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 701f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 702f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 703f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 704f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 705992bea8eSGanesh Goudar unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 706f7917c00SJeff Kirsher }; 707f7917c00SJeff Kirsher 708f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 709f7917c00SJeff Kirsher struct sge_rspq rspq; 710f7917c00SJeff Kirsher struct sge_fl fl; 711f7917c00SJeff Kirsher struct sge_eth_stats stats; 712f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 713f7917c00SJeff Kirsher 714f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 715f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 716f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 717f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 718f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 719f7917c00SJeff Kirsher }; 720f7917c00SJeff Kirsher 721f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 722f7917c00SJeff Kirsher struct sge_rspq rspq; 723f7917c00SJeff Kirsher struct sge_fl fl; 724f7917c00SJeff Kirsher struct sge_ofld_stats stats; 725f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 726f7917c00SJeff Kirsher 727f7917c00SJeff Kirsher struct tx_desc { 728f7917c00SJeff Kirsher __be64 flit[8]; 729f7917c00SJeff Kirsher }; 730f7917c00SJeff Kirsher 731f7917c00SJeff Kirsher struct tx_sw_desc; 732f7917c00SJeff Kirsher 733f7917c00SJeff Kirsher struct sge_txq { 734f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 735ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 736f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 737f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 738f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 739f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 740f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 741f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 742f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 743f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 744f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 745f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 7463069ee9bSVipul Pandya spinlock_t db_lock; 7473069ee9bSVipul Pandya int db_disabled; 7483069ee9bSVipul Pandya unsigned short db_pidx; 74905eb2389SSteve Wise unsigned short db_pidx_inc; 750df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 751df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 752f7917c00SJeff Kirsher }; 753f7917c00SJeff Kirsher 754f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 755f7917c00SJeff Kirsher struct sge_txq q; 756f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 75710b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 75810b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 75910b00466SAnish Bhatt #endif 760d429005fSVishal Kulkarni u8 dbqt; /* SGE Doorbell Queue Timer in use */ 761d429005fSVishal Kulkarni unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 762f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 763f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 764f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 765f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 766f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 767f7917c00SJeff Kirsher 768ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 769f7917c00SJeff Kirsher struct sge_txq q; 770f7917c00SJeff Kirsher struct adapter *adap; 771f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 772f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 773126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 774f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 775f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 776f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 777f7917c00SJeff Kirsher 778f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 779f7917c00SJeff Kirsher struct sge_txq q; 780f7917c00SJeff Kirsher struct adapter *adap; 781f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 782f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 783f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 784f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 785f7917c00SJeff Kirsher 78694cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 78794cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 78894cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 78994cdb8bbSHariprasad Shenai u16 *msix_tbl; /* msix_tbl for uld */ 79094cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 79194cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 79294cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 79394cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 79494cdb8bbSHariprasad Shenai }; 79594cdb8bbSHariprasad Shenai 796ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 797ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 798ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 799ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 800ab677ff4SHariprasad Shenai }; 801ab677ff4SHariprasad Shenai 802f7917c00SJeff Kirsher struct sge { 803f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 804a4569504SAtul Gupta struct sge_eth_txq ptptxq; 805f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 806f7917c00SJeff Kirsher 807f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 808f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 80994cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 810ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 811f7917c00SJeff Kirsher 812f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 813f7917c00SJeff Kirsher spinlock_t intrq_lock; 814f7917c00SJeff Kirsher 815f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 816f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 817f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 8180fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 81994cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 820f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 821f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 822543a1b85SVishal Kulkarni u16 dbqtimer_tick; 823d429005fSVishal Kulkarni u16 dbqtimer_val[SGE_NDBQTIMERS]; 82452367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 82552367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 82652367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 82752367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 82852367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 8290f4d201fSKumar Sanghvi 830a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 831f7917c00SJeff Kirsher unsigned int egr_start; 8324b8e27a8SHariprasad Shenai unsigned int egr_sz; 833f7917c00SJeff Kirsher unsigned int ingr_start; 8344b8e27a8SHariprasad Shenai unsigned int ingr_sz; 8354b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 8364b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 8374b8e27a8SHariprasad Shenai unsigned long *starving_fl; 8384b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 8395b377d11SHariprasad Shenai unsigned long *blocked_fl; 840f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 841f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 842f7917c00SJeff Kirsher }; 843f7917c00SJeff Kirsher 844f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 8450fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 846f7917c00SJeff Kirsher 847f7917c00SJeff Kirsher struct l2t_data; 848f7917c00SJeff Kirsher 8492422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 8502422d9a3SSantosh Rastapur 8517d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 8527d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 8537d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 8542422d9a3SSantosh Rastapur */ 8557d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 8562422d9a3SSantosh Rastapur 8572422d9a3SSantosh Rastapur #endif 8582422d9a3SSantosh Rastapur 859a4cfd929SHariprasad Shenai struct doorbell_stats { 860a4cfd929SHariprasad Shenai u32 db_drop; 861a4cfd929SHariprasad Shenai u32 db_empty; 862a4cfd929SHariprasad Shenai u32 db_full; 863a4cfd929SHariprasad Shenai }; 864a4cfd929SHariprasad Shenai 865fc08a01aSHariprasad Shenai struct hash_mac_addr { 866fc08a01aSHariprasad Shenai struct list_head list; 867fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 8683f8cfd0dSArjun Vynipadath unsigned int iface_mac; 869fc08a01aSHariprasad Shenai }; 870fc08a01aSHariprasad Shenai 87194cdb8bbSHariprasad Shenai struct uld_msix_bmap { 87294cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 87394cdb8bbSHariprasad Shenai unsigned int mapsize; 87494cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 87594cdb8bbSHariprasad Shenai }; 87694cdb8bbSHariprasad Shenai 87794cdb8bbSHariprasad Shenai struct uld_msix_info { 87894cdb8bbSHariprasad Shenai unsigned short vec; 87994cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 8800fbc81b3SHariprasad Shenai unsigned int idx; 88194cdb8bbSHariprasad Shenai }; 88294cdb8bbSHariprasad Shenai 883661dbeb9SHariprasad Shenai struct vf_info { 884661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 8858ea4fae9SGanesh Goudar unsigned int tx_rate; 886661dbeb9SHariprasad Shenai bool pf_set_mac; 8879d5fd927SGanesh Goudar u16 vlan; 888661dbeb9SHariprasad Shenai }; 889661dbeb9SHariprasad Shenai 8908b4e6b3cSArjun Vynipadath enum { 8918b4e6b3cSArjun Vynipadath HMA_DMA_MAPPED_FLAG = 1 8928b4e6b3cSArjun Vynipadath }; 8938b4e6b3cSArjun Vynipadath 8948b4e6b3cSArjun Vynipadath struct hma_data { 8958b4e6b3cSArjun Vynipadath unsigned char flags; 8968b4e6b3cSArjun Vynipadath struct sg_table *sgt; 8978b4e6b3cSArjun Vynipadath dma_addr_t *phy_addr; /* physical address of the page */ 8988b4e6b3cSArjun Vynipadath }; 8998b4e6b3cSArjun Vynipadath 9004055ae5eSHariprasad Shenai struct mbox_list { 9014055ae5eSHariprasad Shenai struct list_head list; 9024055ae5eSHariprasad Shenai }; 9034055ae5eSHariprasad Shenai 904846eac3fSGanesh Goudar struct mps_encap_entry { 905846eac3fSGanesh Goudar atomic_t refcnt; 906846eac3fSGanesh Goudar }; 907846eac3fSGanesh Goudar 908e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 909b1871915SGanesh Goudar struct ch_thermal { 910b1871915SGanesh Goudar struct thermal_zone_device *tzdev; 911b1871915SGanesh Goudar int trip_temp; 912b1871915SGanesh Goudar int trip_type; 913b1871915SGanesh Goudar }; 914b1871915SGanesh Goudar #endif 915b1871915SGanesh Goudar 916f7917c00SJeff Kirsher struct adapter { 917f7917c00SJeff Kirsher void __iomem *regs; 91822adfe0aSSantosh Rastapur void __iomem *bar2; 9190abfd152SHariprasad Shenai u32 t4_bar0; 920f7917c00SJeff Kirsher struct pci_dev *pdev; 921f7917c00SJeff Kirsher struct device *pdev_dev; 9220de72738SHariprasad Shenai const char *name; 9233069ee9bSVipul Pandya unsigned int mbox; 924b2612722SHariprasad Shenai unsigned int pf; 925f7917c00SJeff Kirsher unsigned int flags; 926e7b48a32SHariprasad Shenai unsigned int adap_idx; 9272422d9a3SSantosh Rastapur enum chip_type chip; 928d5fbda61SArjun Vynipadath u32 eth_flags; 929f7917c00SJeff Kirsher 930f7917c00SJeff Kirsher int msg_enable; 931846eac3fSGanesh Goudar __be16 vxlan_port; 932846eac3fSGanesh Goudar u8 vxlan_port_cnt; 933c746fc0eSGanesh Goudar __be16 geneve_port; 934c746fc0eSGanesh Goudar u8 geneve_port_cnt; 935f7917c00SJeff Kirsher 936f7917c00SJeff Kirsher struct adapter_params params; 937f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 938f7917c00SJeff Kirsher unsigned int swintr; 939f7917c00SJeff Kirsher 940f7917c00SJeff Kirsher struct { 941f7917c00SJeff Kirsher unsigned short vec; 942f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 943f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 94494cdb8bbSHariprasad Shenai struct uld_msix_info *msix_info_ulds; /* msix info for uld's */ 94594cdb8bbSHariprasad Shenai struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */ 9460fbc81b3SHariprasad Shenai int msi_idx; 947f7917c00SJeff Kirsher 948a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 949f7917c00SJeff Kirsher struct sge sge; 950f7917c00SJeff Kirsher 951f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 952f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 953f7917c00SJeff Kirsher 954661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 955661dbeb9SHariprasad Shenai u8 num_vfs; 956661dbeb9SHariprasad Shenai 957793dad94SVipul Pandya u32 filter_mode; 958636f9d37SVipul Pandya unsigned int l2t_start; 959636f9d37SVipul Pandya unsigned int l2t_end; 960f7917c00SJeff Kirsher struct l2t_data *l2t; 961b5a02f50SAnish Bhatt unsigned int clipt_start; 962b5a02f50SAnish Bhatt unsigned int clipt_end; 963b5a02f50SAnish Bhatt struct clip_tbl *clipt; 964846eac3fSGanesh Goudar unsigned int rawf_start; 965846eac3fSGanesh Goudar unsigned int rawf_cnt; 9663bdb376eSKumar Sanghvi struct smt_data *smt; 967846eac3fSGanesh Goudar struct mps_encap_entry *mps_encap; 9680fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 969f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 97094cdb8bbSHariprasad Shenai unsigned int num_uld; 9710fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 972f7917c00SJeff Kirsher struct list_head list_node; 97301bcca68SVipul Pandya struct list_head rcu_node; 974fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 975f7917c00SJeff Kirsher 9767714cb9eSVarun Prakash void *iscsi_ppm; 9777714cb9eSVarun Prakash 978f7917c00SJeff Kirsher struct tid_info tids; 979f7917c00SJeff Kirsher void **tid_release_head; 980f7917c00SJeff Kirsher spinlock_t tid_release_lock; 98129aaee65SAnish Bhatt struct workqueue_struct *workq; 982f7917c00SJeff Kirsher struct work_struct tid_release_task; 983881806bcSVipul Pandya struct work_struct db_full_task; 984881806bcSVipul Pandya struct work_struct db_drop_task; 9858b7372c1SGanesh Goudar struct work_struct fatal_err_notify_task; 986f7917c00SJeff Kirsher bool tid_release_task_busy; 987f7917c00SJeff Kirsher 9884055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 9894055ae5eSHariprasad Shenai spinlock_t mbox_lock; 9904055ae5eSHariprasad Shenai struct mbox_list mlist; 9914055ae5eSHariprasad Shenai 9927f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 9937f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 9947f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 9957f080c3fSHariprasad Shenai 9960fbc81b3SHariprasad Shenai struct mutex uld_mutex; 9970fbc81b3SHariprasad Shenai 998f7917c00SJeff Kirsher struct dentry *debugfs_root; 999621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1000621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 10018e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 10028e3d04fdSHariprasad Shenai * used for all 4 filters. 10038e3d04fdSHariprasad Shenai */ 1004f7917c00SJeff Kirsher 1005a4569504SAtul Gupta struct ptp_clock *ptp_clock; 1006a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 1007a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 1008a4569504SAtul Gupta /* ptp lock */ 1009a4569504SAtul Gupta spinlock_t ptp_lock; 1010f7917c00SJeff Kirsher spinlock_t stats_lock; 1011fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 1012d8931847SRahul Lakkireddy 1013d8931847SRahul Lakkireddy /* TC u32 offload */ 1014d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 1015ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 101662488e4bSKumar Sanghvi 101762488e4bSKumar Sanghvi /* TC flower offload */ 1018a081e115SCasey Leedom bool tc_flower_initialized; 101979e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 102079e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 1021e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 102279e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 1023ad75b7d3SRahul Lakkireddy 1024ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 1025ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 10268b4e6b3cSArjun Vynipadath 10278b4e6b3cSArjun Vynipadath /* HMA */ 10288b4e6b3cSArjun Vynipadath struct hma_data hma; 1029e4709475SRaju Rangoju 1030e4709475SRaju Rangoju struct srq_data *srq; 10311dde532dSRahul Lakkireddy 10321dde532dSRahul Lakkireddy /* Dump buffer for collecting logs in kdump kernel */ 10331dde532dSRahul Lakkireddy struct vmcoredd_data vmcoredd; 1034e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 1035b1871915SGanesh Goudar struct ch_thermal ch_thermal; 1036b1871915SGanesh Goudar #endif 1037f7917c00SJeff Kirsher }; 1038f7917c00SJeff Kirsher 1039b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 1040b72a32daSRahul Lakkireddy * programmed with various parameters. 1041b72a32daSRahul Lakkireddy */ 1042b72a32daSRahul Lakkireddy struct ch_sched_params { 1043b72a32daSRahul Lakkireddy s8 type; /* packet or flow */ 1044b72a32daSRahul Lakkireddy union { 1045b72a32daSRahul Lakkireddy struct { 1046b72a32daSRahul Lakkireddy s8 level; /* scheduler hierarchy level */ 1047b72a32daSRahul Lakkireddy s8 mode; /* per-class or per-flow */ 1048b72a32daSRahul Lakkireddy s8 rateunit; /* bit or packet rate */ 1049b72a32daSRahul Lakkireddy s8 ratemode; /* %port relative or kbps absolute */ 1050b72a32daSRahul Lakkireddy s8 channel; /* scheduler channel [0..N] */ 1051b72a32daSRahul Lakkireddy s8 class; /* scheduler class [0..N] */ 1052b72a32daSRahul Lakkireddy s32 minrate; /* minimum rate */ 1053b72a32daSRahul Lakkireddy s32 maxrate; /* maximum rate */ 1054b72a32daSRahul Lakkireddy s16 weight; /* percent weight */ 1055b72a32daSRahul Lakkireddy s16 pktsize; /* average packet size */ 1056b72a32daSRahul Lakkireddy } params; 1057b72a32daSRahul Lakkireddy } u; 1058b72a32daSRahul Lakkireddy }; 1059b72a32daSRahul Lakkireddy 106010a2604eSRahul Lakkireddy enum { 106110a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 106210a2604eSRahul Lakkireddy }; 106310a2604eSRahul Lakkireddy 106410a2604eSRahul Lakkireddy enum { 106510a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 106610a2604eSRahul Lakkireddy }; 106710a2604eSRahul Lakkireddy 106810a2604eSRahul Lakkireddy enum { 106910a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 107010a2604eSRahul Lakkireddy }; 107110a2604eSRahul Lakkireddy 107210a2604eSRahul Lakkireddy enum { 107310a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 107410a2604eSRahul Lakkireddy }; 107510a2604eSRahul Lakkireddy 107610a2604eSRahul Lakkireddy enum { 107710a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 107810a2604eSRahul Lakkireddy }; 107910a2604eSRahul Lakkireddy 1080a6ec572bSAtul Gupta struct tx_sw_desc { /* SW state per Tx descriptor */ 1081a6ec572bSAtul Gupta struct sk_buff *skb; 1082a6ec572bSAtul Gupta struct ulptx_sgl *sgl; 1083a6ec572bSAtul Gupta }; 1084a6ec572bSAtul Gupta 10856cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 10866cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 10876cede1f1SRahul Lakkireddy */ 10886cede1f1SRahul Lakkireddy struct ch_sched_queue { 10896cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 10906cede1f1SRahul Lakkireddy s8 class; /* class index */ 10916cede1f1SRahul Lakkireddy }; 10926cede1f1SRahul Lakkireddy 1093f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 1094f2b7e78dSVipul Pandya */ 1095f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 1096f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 1097f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 1098f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 1099f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 1100f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1101f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1102f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1103f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1104f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1105f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1106f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 110798f3697fSKumar Sanghvi #define ENCAP_VNI_BITWIDTH 24 1108f2b7e78dSVipul Pandya 1109f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1110f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1111f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1112f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1113f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1114f2b7e78dSVipul Pandya * matching rules are true. 1115f2b7e78dSVipul Pandya * 1116f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1117f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1118f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1119f2b7e78dSVipul Pandya * MPS match type) ... 1120f2b7e78dSVipul Pandya * 1121f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1122f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1123f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1124f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1125f2b7e78dSVipul Pandya */ 1126f2b7e78dSVipul Pandya struct ch_filter_tuple { 1127f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1128f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1129f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1130f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1131f2b7e78dSVipul Pandya * set of fields. 1132f2b7e78dSVipul Pandya */ 1133f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1134f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1135f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1136f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1137f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 113898f3697fSKumar Sanghvi uint32_t encap_vld:1; /* Encapsulation valid */ 1139f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1140f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1141f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1142f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1143f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1144f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1145f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1146f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1147f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1148f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 114998f3697fSKumar Sanghvi uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1150f2b7e78dSVipul Pandya 1151f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1152f2b7e78dSVipul Pandya * available for field rules. 1153f2b7e78dSVipul Pandya */ 1154f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1155f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1156f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1157f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1158f2b7e78dSVipul Pandya }; 1159f2b7e78dSVipul Pandya 1160f2b7e78dSVipul Pandya /* A filter ioctl command. 1161f2b7e78dSVipul Pandya */ 1162f2b7e78dSVipul Pandya struct ch_filter_specification { 1163f2b7e78dSVipul Pandya /* Administrative fields for filter. 1164f2b7e78dSVipul Pandya */ 1165f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1166f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1167f2b7e78dSVipul Pandya 1168f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1169f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1170f2b7e78dSVipul Pandya */ 1171f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 117212b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1173f2b7e78dSVipul Pandya 1174f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1175f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1176f2b7e78dSVipul Pandya * out as egress packets. 1177f2b7e78dSVipul Pandya */ 1178f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1179f2b7e78dSVipul Pandya 1180f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1181f2b7e78dSVipul Pandya 1182f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1183f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1184f2b7e78dSVipul Pandya 1185f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1186f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1187f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1188f2b7e78dSVipul Pandya 1189f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1190f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1191f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1192f2b7e78dSVipul Pandya */ 1193f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1194f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1195f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1196f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 11970ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1198f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1199f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1200f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1201f2b7e78dSVipul Pandya 12020ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 12030ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 12040ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 12050ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 12060ff90994SKumar Sanghvi 12070ff90994SKumar Sanghvi /* reservation for future additions */ 12080ff90994SKumar Sanghvi u8 rsvd[24]; 12090ff90994SKumar Sanghvi 1210f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1211f2b7e78dSVipul Pandya */ 1212f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1213f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1214f2b7e78dSVipul Pandya }; 1215f2b7e78dSVipul Pandya 1216f2b7e78dSVipul Pandya enum { 1217f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1218f2b7e78dSVipul Pandya FILTER_DROP, 1219f2b7e78dSVipul Pandya FILTER_SWITCH 1220f2b7e78dSVipul Pandya }; 1221f2b7e78dSVipul Pandya 1222f2b7e78dSVipul Pandya enum { 1223f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1224f2b7e78dSVipul Pandya VLAN_REMOVE, 1225f2b7e78dSVipul Pandya VLAN_INSERT, 1226f2b7e78dSVipul Pandya VLAN_REWRITE 1227f2b7e78dSVipul Pandya }; 1228f2b7e78dSVipul Pandya 1229557ccbf9SKumar Sanghvi enum { 123012b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 123112b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 123212b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 123312b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 123412b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 123512b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 123612b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 123712b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1238557ccbf9SKumar Sanghvi }; 1239557ccbf9SKumar Sanghvi 1240d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1241d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1242d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1243d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1244d57fd6caSRahul Lakkireddy * where the filter table is large. 1245d57fd6caSRahul Lakkireddy */ 1246d57fd6caSRahul Lakkireddy struct filter_entry { 1247d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1248d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1249d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1250d57fd6caSRahul Lakkireddy 1251d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1252578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1253d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 12543bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1255578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1256578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1257d57fd6caSRahul Lakkireddy 1258d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1259d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1260d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1261d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1262d57fd6caSRahul Lakkireddy */ 1263d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1264d57fd6caSRahul Lakkireddy }; 1265d57fd6caSRahul Lakkireddy 1266a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1267a4cfd929SHariprasad Shenai { 1268a4cfd929SHariprasad Shenai return adap->params.offload; 1269a4cfd929SHariprasad Shenai } 1270a4cfd929SHariprasad Shenai 12715c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 12725c31254eSKumar Sanghvi { 12735c31254eSKumar Sanghvi return adap->params.hash_filter; 12745c31254eSKumar Sanghvi } 12755c31254eSKumar Sanghvi 127694cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 127794cdb8bbSHariprasad Shenai { 127894cdb8bbSHariprasad Shenai return adap->params.crypto; 127994cdb8bbSHariprasad Shenai } 128094cdb8bbSHariprasad Shenai 12810fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 12820fbc81b3SHariprasad Shenai { 12830fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 12840fbc81b3SHariprasad Shenai } 12850fbc81b3SHariprasad Shenai 1286f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1287f7917c00SJeff Kirsher { 1288f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1289f7917c00SJeff Kirsher } 1290f7917c00SJeff Kirsher 1291f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1292f7917c00SJeff Kirsher { 1293f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1294f7917c00SJeff Kirsher } 1295f7917c00SJeff Kirsher 1296f7917c00SJeff Kirsher #ifndef readq 1297f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1298f7917c00SJeff Kirsher { 1299f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1300f7917c00SJeff Kirsher } 1301f7917c00SJeff Kirsher 1302f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1303f7917c00SJeff Kirsher { 1304f7917c00SJeff Kirsher writel(val, addr); 1305f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1306f7917c00SJeff Kirsher } 1307f7917c00SJeff Kirsher #endif 1308f7917c00SJeff Kirsher 1309f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1310f7917c00SJeff Kirsher { 1311f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1312f7917c00SJeff Kirsher } 1313f7917c00SJeff Kirsher 1314f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1315f7917c00SJeff Kirsher { 1316f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1317f7917c00SJeff Kirsher } 1318f7917c00SJeff Kirsher 1319f7917c00SJeff Kirsher /** 1320098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1321098ef6c2SHariprasad Shenai * @adapter: the adapter 1322098ef6c2SHariprasad Shenai * @port_idx: the port index 1323098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1324098ef6c2SHariprasad Shenai * 1325098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1326098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1327098ef6c2SHariprasad Shenai */ 1328098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1329098ef6c2SHariprasad Shenai u8 hw_addr[]) 1330098ef6c2SHariprasad Shenai { 1331098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1332098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1333098ef6c2SHariprasad Shenai } 1334098ef6c2SHariprasad Shenai 1335098ef6c2SHariprasad Shenai /** 1336f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1337f7917c00SJeff Kirsher * @dev: the netdev 1338f7917c00SJeff Kirsher * 1339f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1340f7917c00SJeff Kirsher */ 1341f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1342f7917c00SJeff Kirsher { 1343f7917c00SJeff Kirsher return netdev_priv(dev); 1344f7917c00SJeff Kirsher } 1345f7917c00SJeff Kirsher 1346f7917c00SJeff Kirsher /** 1347f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1348f7917c00SJeff Kirsher * @adap: the adapter 1349f7917c00SJeff Kirsher * @idx: the port index 1350f7917c00SJeff Kirsher * 1351f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1352f7917c00SJeff Kirsher */ 1353f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1354f7917c00SJeff Kirsher { 1355f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1356f7917c00SJeff Kirsher } 1357f7917c00SJeff Kirsher 1358f7917c00SJeff Kirsher /** 1359f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1360f7917c00SJeff Kirsher * @dev: the netdev 1361f7917c00SJeff Kirsher * 1362f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1363f7917c00SJeff Kirsher */ 1364f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1365f7917c00SJeff Kirsher { 1366f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1367f7917c00SJeff Kirsher } 1368f7917c00SJeff Kirsher 1369812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1370812034f1SHariprasad Shenai * - bits 0..9: chip version 1371812034f1SHariprasad Shenai * - bits 10..15: chip revision 1372812034f1SHariprasad Shenai * - bits 16..23: register dump version 1373812034f1SHariprasad Shenai */ 1374812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1375812034f1SHariprasad Shenai { 1376812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1377812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1378812034f1SHariprasad Shenai } 1379812034f1SHariprasad Shenai 1380812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1381812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1382812034f1SHariprasad Shenai const struct sge_rspq *q) 1383812034f1SHariprasad Shenai { 1384812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1385812034f1SHariprasad Shenai 1386812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1387812034f1SHariprasad Shenai } 1388812034f1SHariprasad Shenai 1389812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1390812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1391812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1392812034f1SHariprasad Shenai 13938156b0baSGanesh Goudar void t4_os_portmod_changed(struct adapter *adap, int port_id); 1394f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1395f7917c00SJeff Kirsher 1396f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 13975fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1398f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1399d5fbda61SArjun Vynipadath netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1400f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1401f7917c00SJeff Kirsher const struct pkt_gl *gl); 1402f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1403f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1404f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1405f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 14062337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 14072337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1408f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1409f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1410d429005fSVishal Kulkarni unsigned int iqid, u8 dbqt); 1411f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1412f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1413f7917c00SJeff Kirsher unsigned int cmplqid); 14140fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 14150fbc81b3SHariprasad Shenai unsigned int cmplqid); 1416ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1417ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1418ab677ff4SHariprasad Shenai unsigned int uld_type); 1419f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 142052367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1421f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1422f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1423d429005fSVishal Kulkarni int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1424d429005fSVishal Kulkarni int maxreclaim); 1425812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1426812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1427d0a1299cSGanesh Goudar enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 14283069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1429f7917c00SJeff Kirsher 1430f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1431f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1432f7917c00SJeff Kirsher 14339a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 14349a4da2cdSVipul Pandya { 14359a4da2cdSVipul Pandya return adap->params.bypass; 14369a4da2cdSVipul Pandya } 14379a4da2cdSVipul Pandya 14389a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 14399a4da2cdSVipul Pandya { 14409a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 14419a4da2cdSVipul Pandya switch (device) { 14429a4da2cdSVipul Pandya case 0x440b: 14439a4da2cdSVipul Pandya case 0x440c: 14449a4da2cdSVipul Pandya return 1; 14459a4da2cdSVipul Pandya default: 14469a4da2cdSVipul Pandya return 0; 14479a4da2cdSVipul Pandya } 14489a4da2cdSVipul Pandya } 14499a4da2cdSVipul Pandya 145001b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 145101b69614SHariprasad Shenai { 145201b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 145301b69614SHariprasad Shenai switch (device) { 145401b69614SHariprasad Shenai case 0x4409: 145501b69614SHariprasad Shenai case 0x4486: 145601b69614SHariprasad Shenai return 1; 145701b69614SHariprasad Shenai 145801b69614SHariprasad Shenai default: 145901b69614SHariprasad Shenai return 0; 146001b69614SHariprasad Shenai } 146101b69614SHariprasad Shenai } 146201b69614SHariprasad Shenai 1463f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1464f7917c00SJeff Kirsher { 1465f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1466f7917c00SJeff Kirsher } 1467f7917c00SJeff Kirsher 1468f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1469f7917c00SJeff Kirsher unsigned int us) 1470f7917c00SJeff Kirsher { 1471f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1472f7917c00SJeff Kirsher } 1473f7917c00SJeff Kirsher 147452367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 147552367a76SVipul Pandya unsigned int ticks) 147652367a76SVipul Pandya { 147752367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 147852367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 147952367a76SVipul Pandya adapter->params.vpd.cclk); 148052367a76SVipul Pandya } 148152367a76SVipul Pandya 148208c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 148308c4901bSRahul Lakkireddy unsigned int ticks) 148408c4901bSRahul Lakkireddy { 148508c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 148608c4901bSRahul Lakkireddy } 148708c4901bSRahul Lakkireddy 1488f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1489f7917c00SJeff Kirsher u32 val); 1490f7917c00SJeff Kirsher 149101b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 149201b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1493f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1494f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1495f7917c00SJeff Kirsher 149601b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 149701b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 149801b69614SHariprasad Shenai int timeout) 149901b69614SHariprasad Shenai { 150001b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 150101b69614SHariprasad Shenai timeout); 150201b69614SHariprasad Shenai } 150301b69614SHariprasad Shenai 1504f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1505f7917c00SJeff Kirsher int size, void *rpl) 1506f7917c00SJeff Kirsher { 1507f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1508f7917c00SJeff Kirsher } 1509f7917c00SJeff Kirsher 1510f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1511f7917c00SJeff Kirsher int size, void *rpl) 1512f7917c00SJeff Kirsher { 1513f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1514f7917c00SJeff Kirsher } 1515f7917c00SJeff Kirsher 1516fc08a01aSHariprasad Shenai /** 1517fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1518fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1519fc08a01aSHariprasad Shenai * 1520fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1521fc08a01aSHariprasad Shenai * (hash) address matching. 1522fc08a01aSHariprasad Shenai */ 1523fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1524fc08a01aSHariprasad Shenai { 1525fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1526fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1527fc08a01aSHariprasad Shenai 1528fc08a01aSHariprasad Shenai a ^= b; 1529fc08a01aSHariprasad Shenai a ^= (a >> 12); 1530fc08a01aSHariprasad Shenai a ^= (a >> 6); 1531fc08a01aSHariprasad Shenai return a & 0x3f; 1532fc08a01aSHariprasad Shenai } 1533fc08a01aSHariprasad Shenai 153494cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 153594cdb8bbSHariprasad Shenai unsigned int cnt); 153694cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 153794cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 153894cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 153994cdb8bbSHariprasad Shenai { 154094cdb8bbSHariprasad Shenai q->adap = adap; 154194cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 154294cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 154394cdb8bbSHariprasad Shenai q->size = size; 154494cdb8bbSHariprasad Shenai } 154594cdb8bbSHariprasad Shenai 1546f56ec676SArjun Vynipadath /** 1547f56ec676SArjun Vynipadath * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1548f56ec676SArjun Vynipadath * @fw_mod_type: the Firmware Mofule Type 1549f56ec676SArjun Vynipadath * 1550f56ec676SArjun Vynipadath * Return whether the Firmware Module Type represents a real Transceiver 1551f56ec676SArjun Vynipadath * Module/Cable Module Type which has been inserted. 1552f56ec676SArjun Vynipadath */ 1553f56ec676SArjun Vynipadath static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1554f56ec676SArjun Vynipadath { 1555f56ec676SArjun Vynipadath return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1556f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1557f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1558f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1559f56ec676SArjun Vynipadath } 1560f56ec676SArjun Vynipadath 156113ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 156213ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 156313ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1564f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1565f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1566f2b7e78dSVipul Pandya unsigned int start_idx); 15670abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1568f2b7e78dSVipul Pandya 1569f2b7e78dSVipul Pandya struct fw_filter_wr; 1570f2b7e78dSVipul Pandya 1571f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1572f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1573f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1574f7917c00SJeff Kirsher 15758203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 15768156b0baSGanesh Goudar 15778156b0baSGanesh Goudar int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 15788156b0baSGanesh Goudar unsigned int port, struct link_config *lc, 15798156b0baSGanesh Goudar bool sleep_ok, int timeout); 15808156b0baSGanesh Goudar 15818156b0baSGanesh Goudar static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 15828156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 15838156b0baSGanesh Goudar { 15848156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 15858156b0baSGanesh Goudar true, FW_CMD_MAX_TIMEOUT); 15868156b0baSGanesh Goudar } 15878156b0baSGanesh Goudar 15888156b0baSGanesh Goudar static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 15898156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 15908156b0baSGanesh Goudar { 15918156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 15928156b0baSGanesh Goudar false, FW_CMD_MAX_TIMEOUT); 15938156b0baSGanesh Goudar } 15948156b0baSGanesh Goudar 1595f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1596fc5ab020SHariprasad Shenai 1597b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1598b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1599b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1600b562fc37SHariprasad Shenai 16011a4330cdSRahul Lakkireddy int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 16021a4330cdSRahul Lakkireddy u32 *mem_base, u32 *mem_aperture); 16031a4330cdSRahul Lakkireddy void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 16041a4330cdSRahul Lakkireddy void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 16051a4330cdSRahul Lakkireddy int dir); 1606fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1607fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1608fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1609f01aa633SHariprasad Shenai void *buf, int dir); 1610fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1611fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1612fc5ab020SHariprasad Shenai { 1613fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1614fc5ab020SHariprasad Shenai } 1615fc5ab020SHariprasad Shenai 1616812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1617812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1618812034f1SHariprasad Shenai 1619940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1620f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1621098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1622098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 16230eaec62aSCasey Leedom int t4_get_pfres(struct adapter *adapter); 162449216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 162549216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1626f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 162701b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 162801b69614SHariprasad Shenai int win, spinlock_t *lock, 162901b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 163001b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 163101b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 163249216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 163322c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 163422c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1635acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1636636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1637a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 16384da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 163916e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 16400de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 164116e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1642ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1643760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1644760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1645760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1646760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 164716e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 164816e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 164916e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1650f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 16513be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1652e85c9a7aSHariprasad Shenai 1653e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1654b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1655e85c9a7aSHariprasad Shenai unsigned int qid, 1656e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 165766cf188eSHariprasad S int user, 1658e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1659e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1660e85c9a7aSHariprasad Shenai 1661dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1662dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1663ae469b68SHariprasad Shenai 1664ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1665e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 16665ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1667dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1668c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1669c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1670c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1671f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1672f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1673f988008aSGanesh Goudar unsigned int t4_chip_rss_size(struct adapter *adapter); 1674f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1675f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1676f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1677f7917c00SJeff Kirsher unsigned int flags); 1678c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1679c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1680688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 16815ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 16825ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 16835ccf9d04SRahul Lakkireddy bool sleep_ok); 1684688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 16855ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1686688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 16875ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 16885ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 16895ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1690688ea5feSHariprasad Shenai 1691193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1692193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1693b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1694b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1695e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1696e5f0e43bSHariprasad Shenai size_t n); 1697c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1698c778af7dSHariprasad Shenai size_t n); 1699f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1700f1ff24aaSHariprasad Shenai unsigned int *valp); 1701f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1702f1ff24aaSHariprasad Shenai const unsigned int *valp); 1703f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 170419689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 170519689609SHariprasad Shenai unsigned int *pif_req_wrptr, 170619689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 170726fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 170874b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 170972aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1710f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1711a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1712a4cfd929SHariprasad Shenai struct port_stats *stats, 1713a4cfd929SHariprasad Shenai struct port_stats *offset); 171465046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1715f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1716bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1717636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1718636f9d37SVipul Pandya unsigned int mask, unsigned int val); 17192d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 17205ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 17215ccf9d04SRahul Lakkireddy bool sleep_ok); 17225ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 17235ccf9d04SRahul Lakkireddy bool sleep_ok); 17245ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 17255ccf9d04SRahul Lakkireddy bool sleep_ok); 17265ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 17275ccf9d04SRahul Lakkireddy bool sleep_ok); 1728f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 17295ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1730a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 17315ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1732f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1733f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1734f7917c00SJeff Kirsher 1735797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1736797ff0f5SHariprasad Shenai 17377864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1738f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1739f2b7e78dSVipul Pandya 1740f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1741f7917c00SJeff Kirsher const u8 *addr); 1742f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1743f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1744f7917c00SJeff Kirsher 1745f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1746f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1747f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1748f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1749f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1750636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1751636f9d37SVipul Pandya unsigned int cache_line_size); 1752636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1753f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1754f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1755f7917c00SJeff Kirsher u32 *val); 17568f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 17578f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 17588f46d467SArjun Vynipadath u32 *val); 175901b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1760f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 17618f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 176201b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1763688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1764688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 176501b69614SHariprasad Shenai const u32 *val, int timeout); 176601b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 176701b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1768688848b1SAnish Bhatt const u32 *val); 1769f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1770f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1771f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1772f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1773f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1774f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1775f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 177602d805dcSSantosh Rastapur unsigned int *rss_size, u8 *vivld, u8 *vin); 17774f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 17784f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 17794f3a0fcfSHariprasad Shenai unsigned int viid); 1780f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1781f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1782f7917c00SJeff Kirsher bool sleep_ok); 1783846eac3fSGanesh Goudar int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1784846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1785846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 178698f3697fSKumar Sanghvi int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 178798f3697fSKumar Sanghvi bool sleep_ok); 178898f3697fSKumar Sanghvi int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 178998f3697fSKumar Sanghvi const u8 *addr, const u8 *mask, unsigned int vni, 179098f3697fSKumar Sanghvi unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 179198f3697fSKumar Sanghvi bool sleep_ok); 1792846eac3fSGanesh Goudar int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1793846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1794846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 1795f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1796f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1797f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1798fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1799fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1800fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1801f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 180202d805dcSSantosh Rastapur int idx, const u8 *addr, bool persist, u8 *smt_idx); 1803f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1804f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1805688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1806688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1807e2f4f4e9SArjun Vynipadath int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1808e2f4f4e9SArjun Vynipadath struct port_info *pi, 1809e2f4f4e9SArjun Vynipadath bool rx_en, bool tx_en, bool dcb_en); 1810f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1811f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1812f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1813f7917c00SJeff Kirsher unsigned int nblinks); 1814f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1815f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1816f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1817f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1818ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1819ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1820ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1821f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1822f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1823f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1824f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1825f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1826f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1827f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1828f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1829f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1830736c3b94SRahul Lakkireddy int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1831d429005fSVishal Kulkarni int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 1832d429005fSVishal Kulkarni u16 *dbqtimers); 183323853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 18342061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1835c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1836c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1837f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1838881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1839881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 18408e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 18418e3d04fdSHariprasad Shenai int filter_index, int enable); 18428e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 18438e3d04fdSHariprasad Shenai int filter_index, int *enabled); 18448caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 18458caa1e84SVipul Pandya u32 addr, u32 val); 184608c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 184708c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 184808c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 18499e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 18509e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 18519e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 18529e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 1853b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 1854b72a32daSRahul Lakkireddy int rateunit, int ratemode, int channel, int class, 1855b72a32daSRahul Lakkireddy int minrate, int maxrate, int weight, int pktsize); 185668bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1857a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1858a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1859a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1860a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1861a3bfb617SHariprasad Shenai int hz, int ticks); 1862858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1863858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 18645ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 18655ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 18664359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 18674359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 18685ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 18695ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 18705ccf9d04SRahul Lakkireddy 18710fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 18720fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 18730fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 18740fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 1875f56ec676SArjun Vynipadath int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1876f56ec676SArjun Vynipadath unsigned int devid, unsigned int offset, 1877f56ec676SArjun Vynipadath unsigned int len, u8 *buf); 187894cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 1879ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 1880ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 1881ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 1882a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 1883a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 1884a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 1885a6ec572bSAtul Gupta dma_addr_t *addr); 1886a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 1887a6ec572bSAtul Gupta void *pos); 1888a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 1889a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 1890a6ec572bSAtul Gupta const dma_addr_t *addr); 1891a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 18929d5fd927SGanesh Goudar int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 18939d5fd927SGanesh Goudar u16 vlan); 1894ebddd97aSGanesh Goudar int cxgb4_dcb_enabled(const struct net_device *dev); 1895b1871915SGanesh Goudar 1896b1871915SGanesh Goudar int cxgb4_thermal_init(struct adapter *adap); 1897b1871915SGanesh Goudar int cxgb4_thermal_remove(struct adapter *adap); 1898b1871915SGanesh Goudar 1899f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1900