1f7917c00SJeff Kirsher /*
2f7917c00SJeff Kirsher  * This file is part of the Chelsio T4 Ethernet driver for Linux.
3f7917c00SJeff Kirsher  *
4b72a32daSRahul Lakkireddy  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5f7917c00SJeff Kirsher  *
6f7917c00SJeff Kirsher  * This software is available to you under a choice of one of two
7f7917c00SJeff Kirsher  * licenses.  You may choose to be licensed under the terms of the GNU
8f7917c00SJeff Kirsher  * General Public License (GPL) Version 2, available from the file
9f7917c00SJeff Kirsher  * COPYING in the main directory of this source tree, or the
10f7917c00SJeff Kirsher  * OpenIB.org BSD license below:
11f7917c00SJeff Kirsher  *
12f7917c00SJeff Kirsher  *     Redistribution and use in source and binary forms, with or
13f7917c00SJeff Kirsher  *     without modification, are permitted provided that the following
14f7917c00SJeff Kirsher  *     conditions are met:
15f7917c00SJeff Kirsher  *
16f7917c00SJeff Kirsher  *      - Redistributions of source code must retain the above
17f7917c00SJeff Kirsher  *        copyright notice, this list of conditions and the following
18f7917c00SJeff Kirsher  *        disclaimer.
19f7917c00SJeff Kirsher  *
20f7917c00SJeff Kirsher  *      - Redistributions in binary form must reproduce the above
21f7917c00SJeff Kirsher  *        copyright notice, this list of conditions and the following
22f7917c00SJeff Kirsher  *        disclaimer in the documentation and/or other materials
23f7917c00SJeff Kirsher  *        provided with the distribution.
24f7917c00SJeff Kirsher  *
25f7917c00SJeff Kirsher  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26f7917c00SJeff Kirsher  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27f7917c00SJeff Kirsher  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28f7917c00SJeff Kirsher  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29f7917c00SJeff Kirsher  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30f7917c00SJeff Kirsher  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31f7917c00SJeff Kirsher  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32f7917c00SJeff Kirsher  * SOFTWARE.
33f7917c00SJeff Kirsher  */
34f7917c00SJeff Kirsher 
35f7917c00SJeff Kirsher #ifndef __CXGB4_H__
36f7917c00SJeff Kirsher #define __CXGB4_H__
37f7917c00SJeff Kirsher 
38dca4faebSVipul Pandya #include "t4_hw.h"
39dca4faebSVipul Pandya 
40f7917c00SJeff Kirsher #include <linux/bitops.h>
41f7917c00SJeff Kirsher #include <linux/cache.h>
42f7917c00SJeff Kirsher #include <linux/interrupt.h>
43f7917c00SJeff Kirsher #include <linux/list.h>
44f7917c00SJeff Kirsher #include <linux/netdevice.h>
45f7917c00SJeff Kirsher #include <linux/pci.h>
46f7917c00SJeff Kirsher #include <linux/spinlock.h>
47f7917c00SJeff Kirsher #include <linux/timer.h>
48c0b8b992SDavid S. Miller #include <linux/vmalloc.h>
49098ef6c2SHariprasad Shenai #include <linux/etherdevice.h>
505e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h>
51a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h>
52a4569504SAtul Gupta #include <linux/ptp_classify.h>
53f7917c00SJeff Kirsher #include <asm/io.h>
5427999805SHariprasad S #include "t4_chip_type.h"
55f7917c00SJeff Kirsher #include "cxgb4_uld.h"
56f7917c00SJeff Kirsher 
573069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
5894cdb8bbSHariprasad Shenai extern struct list_head adapter_list;
5994cdb8bbSHariprasad Shenai extern struct mutex uld_mutex;
603069ee9bSVipul Pandya 
61f7917c00SJeff Kirsher enum {
62f7917c00SJeff Kirsher 	MAX_NPORTS	= 4,     /* max # of ports */
63f7917c00SJeff Kirsher 	SERNUM_LEN	= 24,    /* Serial # length */
64f7917c00SJeff Kirsher 	EC_LEN		= 16,    /* E/C length */
65f7917c00SJeff Kirsher 	ID_LEN		= 16,    /* ID length */
66a94cd705SKumar Sanghvi 	PN_LEN		= 16,    /* Part Number length */
67098ef6c2SHariprasad Shenai 	MACADDR_LEN	= 12,    /* MAC Address length */
68f7917c00SJeff Kirsher };
69f7917c00SJeff Kirsher 
70f7917c00SJeff Kirsher enum {
71812034f1SHariprasad Shenai 	T4_REGMAP_SIZE = (160 * 1024),
72812034f1SHariprasad Shenai 	T5_REGMAP_SIZE = (332 * 1024),
73812034f1SHariprasad Shenai };
74812034f1SHariprasad Shenai 
75812034f1SHariprasad Shenai enum {
76f7917c00SJeff Kirsher 	MEM_EDC0,
77f7917c00SJeff Kirsher 	MEM_EDC1,
782422d9a3SSantosh Rastapur 	MEM_MC,
792422d9a3SSantosh Rastapur 	MEM_MC0 = MEM_MC,
804db0401fSRahul Lakkireddy 	MEM_MC1,
814db0401fSRahul Lakkireddy 	MEM_HMA,
82f7917c00SJeff Kirsher };
83f7917c00SJeff Kirsher 
843069ee9bSVipul Pandya enum {
853eb4afbfSVipul Pandya 	MEMWIN0_APERTURE = 2048,
863eb4afbfSVipul Pandya 	MEMWIN0_BASE     = 0x1b800,
873069ee9bSVipul Pandya 	MEMWIN1_APERTURE = 32768,
883069ee9bSVipul Pandya 	MEMWIN1_BASE     = 0x28000,
892422d9a3SSantosh Rastapur 	MEMWIN1_BASE_T5  = 0x52000,
903eb4afbfSVipul Pandya 	MEMWIN2_APERTURE = 65536,
913eb4afbfSVipul Pandya 	MEMWIN2_BASE     = 0x30000,
920abfd152SHariprasad Shenai 	MEMWIN2_APERTURE_T5 = 131072,
930abfd152SHariprasad Shenai 	MEMWIN2_BASE_T5  = 0x60000,
943069ee9bSVipul Pandya };
953069ee9bSVipul Pandya 
96f7917c00SJeff Kirsher enum dev_master {
97f7917c00SJeff Kirsher 	MASTER_CANT,
98f7917c00SJeff Kirsher 	MASTER_MAY,
99f7917c00SJeff Kirsher 	MASTER_MUST
100f7917c00SJeff Kirsher };
101f7917c00SJeff Kirsher 
102f7917c00SJeff Kirsher enum dev_state {
103f7917c00SJeff Kirsher 	DEV_STATE_UNINIT,
104f7917c00SJeff Kirsher 	DEV_STATE_INIT,
105f7917c00SJeff Kirsher 	DEV_STATE_ERR
106f7917c00SJeff Kirsher };
107f7917c00SJeff Kirsher 
108c3168cabSGanesh Goudar enum cc_pause {
109f7917c00SJeff Kirsher 	PAUSE_RX      = 1 << 0,
110f7917c00SJeff Kirsher 	PAUSE_TX      = 1 << 1,
111f7917c00SJeff Kirsher 	PAUSE_AUTONEG = 1 << 2
112f7917c00SJeff Kirsher };
113f7917c00SJeff Kirsher 
114c3168cabSGanesh Goudar enum cc_fec {
1153bb4858fSGanesh Goudar 	FEC_AUTO      = 1 << 0,	 /* IEEE 802.3 "automatic" */
1163bb4858fSGanesh Goudar 	FEC_RS        = 1 << 1,  /* Reed-Solomon */
1173bb4858fSGanesh Goudar 	FEC_BASER_RS  = 1 << 2   /* BaseR/Reed-Solomon */
1183bb4858fSGanesh Goudar };
1193bb4858fSGanesh Goudar 
120f7917c00SJeff Kirsher struct port_stats {
121f7917c00SJeff Kirsher 	u64 tx_octets;            /* total # of octets in good frames */
122f7917c00SJeff Kirsher 	u64 tx_frames;            /* all good frames */
123f7917c00SJeff Kirsher 	u64 tx_bcast_frames;      /* all broadcast frames */
124f7917c00SJeff Kirsher 	u64 tx_mcast_frames;      /* all multicast frames */
125f7917c00SJeff Kirsher 	u64 tx_ucast_frames;      /* all unicast frames */
126f7917c00SJeff Kirsher 	u64 tx_error_frames;      /* all error frames */
127f7917c00SJeff Kirsher 
128f7917c00SJeff Kirsher 	u64 tx_frames_64;         /* # of Tx frames in a particular range */
129f7917c00SJeff Kirsher 	u64 tx_frames_65_127;
130f7917c00SJeff Kirsher 	u64 tx_frames_128_255;
131f7917c00SJeff Kirsher 	u64 tx_frames_256_511;
132f7917c00SJeff Kirsher 	u64 tx_frames_512_1023;
133f7917c00SJeff Kirsher 	u64 tx_frames_1024_1518;
134f7917c00SJeff Kirsher 	u64 tx_frames_1519_max;
135f7917c00SJeff Kirsher 
136f7917c00SJeff Kirsher 	u64 tx_drop;              /* # of dropped Tx frames */
137f7917c00SJeff Kirsher 	u64 tx_pause;             /* # of transmitted pause frames */
138f7917c00SJeff Kirsher 	u64 tx_ppp0;              /* # of transmitted PPP prio 0 frames */
139f7917c00SJeff Kirsher 	u64 tx_ppp1;              /* # of transmitted PPP prio 1 frames */
140f7917c00SJeff Kirsher 	u64 tx_ppp2;              /* # of transmitted PPP prio 2 frames */
141f7917c00SJeff Kirsher 	u64 tx_ppp3;              /* # of transmitted PPP prio 3 frames */
142f7917c00SJeff Kirsher 	u64 tx_ppp4;              /* # of transmitted PPP prio 4 frames */
143f7917c00SJeff Kirsher 	u64 tx_ppp5;              /* # of transmitted PPP prio 5 frames */
144f7917c00SJeff Kirsher 	u64 tx_ppp6;              /* # of transmitted PPP prio 6 frames */
145f7917c00SJeff Kirsher 	u64 tx_ppp7;              /* # of transmitted PPP prio 7 frames */
146f7917c00SJeff Kirsher 
147f7917c00SJeff Kirsher 	u64 rx_octets;            /* total # of octets in good frames */
148f7917c00SJeff Kirsher 	u64 rx_frames;            /* all good frames */
149f7917c00SJeff Kirsher 	u64 rx_bcast_frames;      /* all broadcast frames */
150f7917c00SJeff Kirsher 	u64 rx_mcast_frames;      /* all multicast frames */
151f7917c00SJeff Kirsher 	u64 rx_ucast_frames;      /* all unicast frames */
152f7917c00SJeff Kirsher 	u64 rx_too_long;          /* # of frames exceeding MTU */
153f7917c00SJeff Kirsher 	u64 rx_jabber;            /* # of jabber frames */
154f7917c00SJeff Kirsher 	u64 rx_fcs_err;           /* # of received frames with bad FCS */
155f7917c00SJeff Kirsher 	u64 rx_len_err;           /* # of received frames with length error */
156f7917c00SJeff Kirsher 	u64 rx_symbol_err;        /* symbol errors */
157f7917c00SJeff Kirsher 	u64 rx_runt;              /* # of short frames */
158f7917c00SJeff Kirsher 
159f7917c00SJeff Kirsher 	u64 rx_frames_64;         /* # of Rx frames in a particular range */
160f7917c00SJeff Kirsher 	u64 rx_frames_65_127;
161f7917c00SJeff Kirsher 	u64 rx_frames_128_255;
162f7917c00SJeff Kirsher 	u64 rx_frames_256_511;
163f7917c00SJeff Kirsher 	u64 rx_frames_512_1023;
164f7917c00SJeff Kirsher 	u64 rx_frames_1024_1518;
165f7917c00SJeff Kirsher 	u64 rx_frames_1519_max;
166f7917c00SJeff Kirsher 
167f7917c00SJeff Kirsher 	u64 rx_pause;             /* # of received pause frames */
168f7917c00SJeff Kirsher 	u64 rx_ppp0;              /* # of received PPP prio 0 frames */
169f7917c00SJeff Kirsher 	u64 rx_ppp1;              /* # of received PPP prio 1 frames */
170f7917c00SJeff Kirsher 	u64 rx_ppp2;              /* # of received PPP prio 2 frames */
171f7917c00SJeff Kirsher 	u64 rx_ppp3;              /* # of received PPP prio 3 frames */
172f7917c00SJeff Kirsher 	u64 rx_ppp4;              /* # of received PPP prio 4 frames */
173f7917c00SJeff Kirsher 	u64 rx_ppp5;              /* # of received PPP prio 5 frames */
174f7917c00SJeff Kirsher 	u64 rx_ppp6;              /* # of received PPP prio 6 frames */
175f7917c00SJeff Kirsher 	u64 rx_ppp7;              /* # of received PPP prio 7 frames */
176f7917c00SJeff Kirsher 
177f7917c00SJeff Kirsher 	u64 rx_ovflow0;           /* drops due to buffer-group 0 overflows */
178f7917c00SJeff Kirsher 	u64 rx_ovflow1;           /* drops due to buffer-group 1 overflows */
179f7917c00SJeff Kirsher 	u64 rx_ovflow2;           /* drops due to buffer-group 2 overflows */
180f7917c00SJeff Kirsher 	u64 rx_ovflow3;           /* drops due to buffer-group 3 overflows */
181f7917c00SJeff Kirsher 	u64 rx_trunc0;            /* buffer-group 0 truncated packets */
182f7917c00SJeff Kirsher 	u64 rx_trunc1;            /* buffer-group 1 truncated packets */
183f7917c00SJeff Kirsher 	u64 rx_trunc2;            /* buffer-group 2 truncated packets */
184f7917c00SJeff Kirsher 	u64 rx_trunc3;            /* buffer-group 3 truncated packets */
185f7917c00SJeff Kirsher };
186f7917c00SJeff Kirsher 
187f7917c00SJeff Kirsher struct lb_port_stats {
188f7917c00SJeff Kirsher 	u64 octets;
189f7917c00SJeff Kirsher 	u64 frames;
190f7917c00SJeff Kirsher 	u64 bcast_frames;
191f7917c00SJeff Kirsher 	u64 mcast_frames;
192f7917c00SJeff Kirsher 	u64 ucast_frames;
193f7917c00SJeff Kirsher 	u64 error_frames;
194f7917c00SJeff Kirsher 
195f7917c00SJeff Kirsher 	u64 frames_64;
196f7917c00SJeff Kirsher 	u64 frames_65_127;
197f7917c00SJeff Kirsher 	u64 frames_128_255;
198f7917c00SJeff Kirsher 	u64 frames_256_511;
199f7917c00SJeff Kirsher 	u64 frames_512_1023;
200f7917c00SJeff Kirsher 	u64 frames_1024_1518;
201f7917c00SJeff Kirsher 	u64 frames_1519_max;
202f7917c00SJeff Kirsher 
203f7917c00SJeff Kirsher 	u64 drop;
204f7917c00SJeff Kirsher 
205f7917c00SJeff Kirsher 	u64 ovflow0;
206f7917c00SJeff Kirsher 	u64 ovflow1;
207f7917c00SJeff Kirsher 	u64 ovflow2;
208f7917c00SJeff Kirsher 	u64 ovflow3;
209f7917c00SJeff Kirsher 	u64 trunc0;
210f7917c00SJeff Kirsher 	u64 trunc1;
211f7917c00SJeff Kirsher 	u64 trunc2;
212f7917c00SJeff Kirsher 	u64 trunc3;
213f7917c00SJeff Kirsher };
214f7917c00SJeff Kirsher 
215f7917c00SJeff Kirsher struct tp_tcp_stats {
216a4cfd929SHariprasad Shenai 	u32 tcp_out_rsts;
217a4cfd929SHariprasad Shenai 	u64 tcp_in_segs;
218a4cfd929SHariprasad Shenai 	u64 tcp_out_segs;
219a4cfd929SHariprasad Shenai 	u64 tcp_retrans_segs;
220a4cfd929SHariprasad Shenai };
221a4cfd929SHariprasad Shenai 
222a4cfd929SHariprasad Shenai struct tp_usm_stats {
223a4cfd929SHariprasad Shenai 	u32 frames;
224a4cfd929SHariprasad Shenai 	u32 drops;
225a4cfd929SHariprasad Shenai 	u64 octets;
226f7917c00SJeff Kirsher };
227f7917c00SJeff Kirsher 
228a6222975SHariprasad Shenai struct tp_fcoe_stats {
229a6222975SHariprasad Shenai 	u32 frames_ddp;
230a6222975SHariprasad Shenai 	u32 frames_drop;
231a6222975SHariprasad Shenai 	u64 octets_ddp;
232f7917c00SJeff Kirsher };
233f7917c00SJeff Kirsher 
234f7917c00SJeff Kirsher struct tp_err_stats {
235a4cfd929SHariprasad Shenai 	u32 mac_in_errs[4];
236a4cfd929SHariprasad Shenai 	u32 hdr_in_errs[4];
237a4cfd929SHariprasad Shenai 	u32 tcp_in_errs[4];
238a4cfd929SHariprasad Shenai 	u32 tnl_cong_drops[4];
239a4cfd929SHariprasad Shenai 	u32 ofld_chan_drops[4];
240a4cfd929SHariprasad Shenai 	u32 tnl_tx_drops[4];
241a4cfd929SHariprasad Shenai 	u32 ofld_vlan_drops[4];
242a4cfd929SHariprasad Shenai 	u32 tcp6_in_errs[4];
243a4cfd929SHariprasad Shenai 	u32 ofld_no_neigh;
244a4cfd929SHariprasad Shenai 	u32 ofld_cong_defer;
245a4cfd929SHariprasad Shenai };
246a4cfd929SHariprasad Shenai 
247a6222975SHariprasad Shenai struct tp_cpl_stats {
248a6222975SHariprasad Shenai 	u32 req[4];
249a6222975SHariprasad Shenai 	u32 rsp[4];
250a6222975SHariprasad Shenai };
251a6222975SHariprasad Shenai 
252a4cfd929SHariprasad Shenai struct tp_rdma_stats {
253a4cfd929SHariprasad Shenai 	u32 rqe_dfr_pkt;
254a4cfd929SHariprasad Shenai 	u32 rqe_dfr_mod;
255f7917c00SJeff Kirsher };
256f7917c00SJeff Kirsher 
257e85c9a7aSHariprasad Shenai struct sge_params {
258e85c9a7aSHariprasad Shenai 	u32 hps;			/* host page size for our PF/VF */
259e85c9a7aSHariprasad Shenai 	u32 eq_qpp;			/* egress queues/page for our PF/VF */
260e85c9a7aSHariprasad Shenai 	u32 iq_qpp;			/* egress queues/page for our PF/VF */
261e85c9a7aSHariprasad Shenai };
262e85c9a7aSHariprasad Shenai 
263f7917c00SJeff Kirsher struct tp_params {
264f7917c00SJeff Kirsher 	unsigned int tre;            /* log2 of core clocks per TP tick */
2652d277b3bSHariprasad Shenai 	unsigned int la_mask;        /* what events are recorded by TP LA */
266dca4faebSVipul Pandya 	unsigned short tx_modq_map;  /* TX modulation scheduler queue to */
267dca4faebSVipul Pandya 				     /* channel map */
268636f9d37SVipul Pandya 
269636f9d37SVipul Pandya 	uint32_t dack_re;            /* DACK timer resolution */
270636f9d37SVipul Pandya 	unsigned short tx_modq[NCHAN];	/* channel to modulation queue map */
271dcf7b6f5SKumar Sanghvi 
272dcf7b6f5SKumar Sanghvi 	u32 vlan_pri_map;               /* cached TP_VLAN_PRI_MAP */
273dcf7b6f5SKumar Sanghvi 	u32 ingress_config;             /* cached TP_INGRESS_CONFIG */
274dcf7b6f5SKumar Sanghvi 
2758eb9f2f9SArjun V 	/* cached TP_OUT_CONFIG compressed error vector
2768eb9f2f9SArjun V 	 * and passing outer header info for encapsulated packets.
2778eb9f2f9SArjun V 	 */
2788eb9f2f9SArjun V 	int rx_pkt_encap;
2798eb9f2f9SArjun V 
280dcf7b6f5SKumar Sanghvi 	/* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets.  This is a
281dcf7b6f5SKumar Sanghvi 	 * subset of the set of fields which may be present in the Compressed
282dcf7b6f5SKumar Sanghvi 	 * Filter Tuple portion of filters and TCP TCB connections.  The
283dcf7b6f5SKumar Sanghvi 	 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
284dcf7b6f5SKumar Sanghvi 	 * Since a variable number of fields may or may not be present, their
285dcf7b6f5SKumar Sanghvi 	 * shifted field positions within the Compressed Filter Tuple may
286dcf7b6f5SKumar Sanghvi 	 * vary, or not even be present if the field isn't selected in
287dcf7b6f5SKumar Sanghvi 	 * TP_VLAN_PRI_MAP.  Since some of these fields are needed in various
288dcf7b6f5SKumar Sanghvi 	 * places we store their offsets here, or a -1 if the field isn't
289dcf7b6f5SKumar Sanghvi 	 * present.
290dcf7b6f5SKumar Sanghvi 	 */
2910ba9a3b6SKumar Sanghvi 	int fcoe_shift;
292dcf7b6f5SKumar Sanghvi 	int port_shift;
2930ba9a3b6SKumar Sanghvi 	int vnic_shift;
2940ba9a3b6SKumar Sanghvi 	int vlan_shift;
2950ba9a3b6SKumar Sanghvi 	int tos_shift;
296dcf7b6f5SKumar Sanghvi 	int protocol_shift;
2970ba9a3b6SKumar Sanghvi 	int ethertype_shift;
2980ba9a3b6SKumar Sanghvi 	int macmatch_shift;
2990ba9a3b6SKumar Sanghvi 	int matchtype_shift;
3000ba9a3b6SKumar Sanghvi 	int frag_shift;
3010ba9a3b6SKumar Sanghvi 
3020ba9a3b6SKumar Sanghvi 	u64 hash_filter_mask;
303f7917c00SJeff Kirsher };
304f7917c00SJeff Kirsher 
305f7917c00SJeff Kirsher struct vpd_params {
306f7917c00SJeff Kirsher 	unsigned int cclk;
307f7917c00SJeff Kirsher 	u8 ec[EC_LEN + 1];
308f7917c00SJeff Kirsher 	u8 sn[SERNUM_LEN + 1];
309f7917c00SJeff Kirsher 	u8 id[ID_LEN + 1];
310a94cd705SKumar Sanghvi 	u8 pn[PN_LEN + 1];
311098ef6c2SHariprasad Shenai 	u8 na[MACADDR_LEN + 1];
312f7917c00SJeff Kirsher };
313f7917c00SJeff Kirsher 
314f7917c00SJeff Kirsher struct pci_params {
315f7917c00SJeff Kirsher 	unsigned char speed;
316f7917c00SJeff Kirsher 	unsigned char width;
317f7917c00SJeff Kirsher };
318f7917c00SJeff Kirsher 
31949aa284fSHariprasad Shenai struct devlog_params {
32049aa284fSHariprasad Shenai 	u32 memtype;                    /* which memory (EDC0, EDC1, MC) */
32149aa284fSHariprasad Shenai 	u32 start;                      /* start of log in firmware memory */
32249aa284fSHariprasad Shenai 	u32 size;                       /* size of log */
32349aa284fSHariprasad Shenai };
32449aa284fSHariprasad Shenai 
3253ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */
3263ccc6cf7SHariprasad Shenai struct arch_specific_params {
3273ccc6cf7SHariprasad Shenai 	u8 nchan;
32844588560SHariprasad Shenai 	u8 pm_stats_cnt;
3292216d014SHariprasad Shenai 	u8 cng_ch_bits_log;		/* congestion channel map bits width */
3303ccc6cf7SHariprasad Shenai 	u16 mps_rplc_size;
3313ccc6cf7SHariprasad Shenai 	u16 vfcount;
3323ccc6cf7SHariprasad Shenai 	u32 sge_fl_db;
3333ccc6cf7SHariprasad Shenai 	u16 mps_tcam_size;
3343ccc6cf7SHariprasad Shenai };
3353ccc6cf7SHariprasad Shenai 
336f7917c00SJeff Kirsher struct adapter_params {
337e85c9a7aSHariprasad Shenai 	struct sge_params sge;
338f7917c00SJeff Kirsher 	struct tp_params  tp;
339f7917c00SJeff Kirsher 	struct vpd_params vpd;
340f7917c00SJeff Kirsher 	struct pci_params pci;
34149aa284fSHariprasad Shenai 	struct devlog_params devlog;
34249aa284fSHariprasad Shenai 	enum pcie_memwin drv_memwin;
343f7917c00SJeff Kirsher 
344f1ff24aaSHariprasad Shenai 	unsigned int cim_la_size;
345f1ff24aaSHariprasad Shenai 
346f7917c00SJeff Kirsher 	unsigned int sf_size;             /* serial flash size in bytes */
347f7917c00SJeff Kirsher 	unsigned int sf_nsec;             /* # of flash sectors */
348f7917c00SJeff Kirsher 	unsigned int sf_fw_start;         /* start of FW image in flash */
349f7917c00SJeff Kirsher 
350760446f9SGanesh Goudar 	unsigned int fw_vers;		  /* firmware version */
3510de72738SHariprasad Shenai 	unsigned int bs_vers;		  /* bootstrap version */
352760446f9SGanesh Goudar 	unsigned int tp_vers;		  /* TP microcode version */
3530de72738SHariprasad Shenai 	unsigned int er_vers;		  /* expansion ROM version */
354760446f9SGanesh Goudar 	unsigned int scfg_vers;		  /* Serial Configuration version */
355760446f9SGanesh Goudar 	unsigned int vpd_vers;		  /* VPD Version */
356f7917c00SJeff Kirsher 	u8 api_vers[7];
357f7917c00SJeff Kirsher 
358f7917c00SJeff Kirsher 	unsigned short mtus[NMTUS];
359f7917c00SJeff Kirsher 	unsigned short a_wnd[NCCTRL_WIN];
360f7917c00SJeff Kirsher 	unsigned short b_wnd[NCCTRL_WIN];
361f7917c00SJeff Kirsher 
362f7917c00SJeff Kirsher 	unsigned char nports;             /* # of ethernet ports */
363f7917c00SJeff Kirsher 	unsigned char portvec;
364d14807ddSHariprasad Shenai 	enum chip_type chip;               /* chip code */
3653ccc6cf7SHariprasad Shenai 	struct arch_specific_params arch;  /* chip specific params */
366f7917c00SJeff Kirsher 	unsigned char offload;
36794cdb8bbSHariprasad Shenai 	unsigned char crypto;		/* HW capability for crypto */
368f7917c00SJeff Kirsher 
3699a4da2cdSVipul Pandya 	unsigned char bypass;
3705c31254eSKumar Sanghvi 	unsigned char hash_filter;
3719a4da2cdSVipul Pandya 
372f7917c00SJeff Kirsher 	unsigned int ofldq_wr_cred;
3731ac0f095SKumar Sanghvi 	bool ulptx_memwrite_dsgl;          /* use of T5 DSGL allowed */
3744c2c5763SHariprasad Shenai 
375b72a32daSRahul Lakkireddy 	unsigned int nsched_cls;          /* number of traffic classes */
3764c2c5763SHariprasad Shenai 	unsigned int max_ordird_qp;       /* Max read depth per RDMA QP */
3774c2c5763SHariprasad Shenai 	unsigned int max_ird_adapter;     /* Max read depth per adapter */
378086de575SSteve Wise 	bool fr_nsmr_tpte_wr_support;	  /* FW support for FR_NSMR_TPTE_WR */
379c3168cabSGanesh Goudar 	u8 fw_caps_support;		/* 32-bit Port Capabilities */
3800ff90994SKumar Sanghvi 	bool filter2_wr_support;	/* FW support for FILTER2_WR */
3818f46d467SArjun Vynipadath 
3828f46d467SArjun Vynipadath 	/* MPS Buffer Group Map[per Port].  Bit i is set if buffer group i is
3838f46d467SArjun Vynipadath 	 * used by the Port
3848f46d467SArjun Vynipadath 	 */
3858f46d467SArjun Vynipadath 	u8 mps_bg_map[MAX_NPORTS];	/* MPS Buffer Group Map */
386f7917c00SJeff Kirsher };
387f7917c00SJeff Kirsher 
388a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities
389a3bfb617SHariprasad Shenai  * and possible hangs.
390a3bfb617SHariprasad Shenai  */
391a3bfb617SHariprasad Shenai struct sge_idma_monitor_state {
392a3bfb617SHariprasad Shenai 	unsigned int idma_1s_thresh;	/* 1s threshold in Core Clock ticks */
393a3bfb617SHariprasad Shenai 	unsigned int idma_stalled[2];	/* synthesized stalled timers in HZ */
394a3bfb617SHariprasad Shenai 	unsigned int idma_state[2];	/* IDMA Hang detect state */
395a3bfb617SHariprasad Shenai 	unsigned int idma_qid[2];	/* IDMA Hung Ingress Queue ID */
396a3bfb617SHariprasad Shenai 	unsigned int idma_warn[2];	/* time to warning in HZ */
397a3bfb617SHariprasad Shenai };
398a3bfb617SHariprasad Shenai 
3997f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log.  All values are in Host-Endian format.
4007f080c3fSHariprasad Shenai  * The access and execute times are signed in order to accommodate negative
4017f080c3fSHariprasad Shenai  * error returns.
4027f080c3fSHariprasad Shenai  */
4037f080c3fSHariprasad Shenai struct mbox_cmd {
4047f080c3fSHariprasad Shenai 	u64 cmd[MBOX_LEN / 8];		/* a Firmware Mailbox Command/Reply */
4057f080c3fSHariprasad Shenai 	u64 timestamp;			/* OS-dependent timestamp */
4067f080c3fSHariprasad Shenai 	u32 seqno;			/* sequence number */
4077f080c3fSHariprasad Shenai 	s16 access;			/* time (ms) to access mailbox */
4087f080c3fSHariprasad Shenai 	s16 execute;			/* time (ms) to execute */
4097f080c3fSHariprasad Shenai };
4107f080c3fSHariprasad Shenai 
4117f080c3fSHariprasad Shenai struct mbox_cmd_log {
4127f080c3fSHariprasad Shenai 	unsigned int size;		/* number of entries in the log */
4137f080c3fSHariprasad Shenai 	unsigned int cursor;		/* next position in the log to write */
4147f080c3fSHariprasad Shenai 	u32 seqno;			/* next sequence number */
4157f080c3fSHariprasad Shenai 	/* variable length mailbox command log starts here */
4167f080c3fSHariprasad Shenai };
4177f080c3fSHariprasad Shenai 
4187f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
4197f080c3fSHariprasad Shenai  * return a pointer to the specified entry.
4207f080c3fSHariprasad Shenai  */
4217f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
4227f080c3fSHariprasad Shenai 						  unsigned int entry_idx)
4237f080c3fSHariprasad Shenai {
4247f080c3fSHariprasad Shenai 	return &((struct mbox_cmd *)&(log)[1])[entry_idx];
4257f080c3fSHariprasad Shenai }
4267f080c3fSHariprasad Shenai 
42716e47624SHariprasad Shenai #include "t4fw_api.h"
42816e47624SHariprasad Shenai 
42916e47624SHariprasad Shenai #define FW_VERSION(chip) ( \
430b2e1a3f0SHariprasad Shenai 		FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
431b2e1a3f0SHariprasad Shenai 		FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
432b2e1a3f0SHariprasad Shenai 		FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
433b2e1a3f0SHariprasad Shenai 		FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
43416e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
43516e47624SHariprasad Shenai 
43616e47624SHariprasad Shenai struct fw_info {
43716e47624SHariprasad Shenai 	u8 chip;
43816e47624SHariprasad Shenai 	char *fs_name;
43916e47624SHariprasad Shenai 	char *fw_mod_name;
44016e47624SHariprasad Shenai 	struct fw_hdr fw_hdr;
44116e47624SHariprasad Shenai };
44216e47624SHariprasad Shenai 
443f7917c00SJeff Kirsher struct trace_params {
444f7917c00SJeff Kirsher 	u32 data[TRACE_LEN / 4];
445f7917c00SJeff Kirsher 	u32 mask[TRACE_LEN / 4];
446f7917c00SJeff Kirsher 	unsigned short snap_len;
447f7917c00SJeff Kirsher 	unsigned short min_len;
448f7917c00SJeff Kirsher 	unsigned char skip_ofst;
449f7917c00SJeff Kirsher 	unsigned char skip_len;
450f7917c00SJeff Kirsher 	unsigned char invert;
451f7917c00SJeff Kirsher 	unsigned char port;
452f7917c00SJeff Kirsher };
453f7917c00SJeff Kirsher 
454c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */
455c3168cabSGanesh Goudar 
456c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t;	/* 16-bit Port Capabilities integral value */
457c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t;	/* 32-bit Port Capabilities integral value */
458c3168cabSGanesh Goudar 
459c3168cabSGanesh Goudar enum fw_caps {
460c3168cabSGanesh Goudar 	FW_CAPS_UNKNOWN	= 0,	/* 0'ed out initial state */
461c3168cabSGanesh Goudar 	FW_CAPS16	= 1,	/* old Firmware: 16-bit Port Capabilities */
462c3168cabSGanesh Goudar 	FW_CAPS32	= 2,	/* new Firmware: 32-bit Port Capabilities */
463c3168cabSGanesh Goudar };
464c3168cabSGanesh Goudar 
465f7917c00SJeff Kirsher struct link_config {
466c3168cabSGanesh Goudar 	fw_port_cap32_t pcaps;           /* link capabilities */
467c3168cabSGanesh Goudar 	fw_port_cap32_t def_acaps;       /* default advertised capabilities */
468c3168cabSGanesh Goudar 	fw_port_cap32_t acaps;           /* advertised capabilities */
469c3168cabSGanesh Goudar 	fw_port_cap32_t lpacaps;         /* peer advertised capabilities */
470c3168cabSGanesh Goudar 
471c3168cabSGanesh Goudar 	fw_port_cap32_t speed_caps;      /* speed(s) user has requested */
472c3168cabSGanesh Goudar 	unsigned int   speed;            /* actual link speed (Mb/s) */
473c3168cabSGanesh Goudar 
474c3168cabSGanesh Goudar 	enum cc_pause  requested_fc;     /* flow control user has requested */
475c3168cabSGanesh Goudar 	enum cc_pause  fc;               /* actual link flow control */
476c3168cabSGanesh Goudar 
477c3168cabSGanesh Goudar 	enum cc_fec    requested_fec;	 /* Forward Error Correction: */
478c3168cabSGanesh Goudar 	enum cc_fec    fec;		 /* requested and actual in use */
479c3168cabSGanesh Goudar 
480f7917c00SJeff Kirsher 	unsigned char  autoneg;          /* autonegotiating? */
481c3168cabSGanesh Goudar 
482f7917c00SJeff Kirsher 	unsigned char  link_ok;          /* link up? */
483ddc7740dSHariprasad Shenai 	unsigned char  link_down_rc;     /* link down reason */
484f7917c00SJeff Kirsher };
485f7917c00SJeff Kirsher 
486e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
487f7917c00SJeff Kirsher 
488f7917c00SJeff Kirsher enum {
489f7917c00SJeff Kirsher 	MAX_ETH_QSETS = 32,           /* # of Ethernet Tx/Rx queue sets */
490f90ce561SHariprasad Shenai 	MAX_OFLD_QSETS = 16,          /* # of offload Tx, iscsi Rx queue sets */
491f7917c00SJeff Kirsher 	MAX_CTRL_QUEUES = NCHAN,      /* # of control Tx queues */
492f7917c00SJeff Kirsher };
493f7917c00SJeff Kirsher 
494f7917c00SJeff Kirsher enum {
495812034f1SHariprasad Shenai 	MAX_TXQ_ENTRIES      = 16384,
496812034f1SHariprasad Shenai 	MAX_CTRL_TXQ_ENTRIES = 1024,
497812034f1SHariprasad Shenai 	MAX_RSPQ_ENTRIES     = 16384,
498812034f1SHariprasad Shenai 	MAX_RX_BUFFERS       = 16384,
499812034f1SHariprasad Shenai 	MIN_TXQ_ENTRIES      = 32,
500812034f1SHariprasad Shenai 	MIN_CTRL_TXQ_ENTRIES = 32,
501812034f1SHariprasad Shenai 	MIN_RSPQ_ENTRIES     = 128,
502812034f1SHariprasad Shenai 	MIN_FL_ENTRIES       = 16
503812034f1SHariprasad Shenai };
504812034f1SHariprasad Shenai 
505812034f1SHariprasad Shenai enum {
506cf38be6dSHariprasad Shenai 	INGQ_EXTRAS = 2,        /* firmware event queue and */
507cf38be6dSHariprasad Shenai 				/*   forwarded interrupts */
5080fbc81b3SHariprasad Shenai 	MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
509f7917c00SJeff Kirsher };
510f7917c00SJeff Kirsher 
511f7917c00SJeff Kirsher struct adapter;
512f7917c00SJeff Kirsher struct sge_rspq;
513f7917c00SJeff Kirsher 
514688848b1SAnish Bhatt #include "cxgb4_dcb.h"
515688848b1SAnish Bhatt 
51676fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE
51776fed8a9SVarun Prakash #include "cxgb4_fcoe.h"
51876fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */
51976fed8a9SVarun Prakash 
520f7917c00SJeff Kirsher struct port_info {
521f7917c00SJeff Kirsher 	struct adapter *adapter;
522f7917c00SJeff Kirsher 	u16    viid;
523f7917c00SJeff Kirsher 	s16    xact_addr_filt;        /* index of exact MAC address filter */
524f7917c00SJeff Kirsher 	u16    rss_size;              /* size of VI's RSS table slice */
525f7917c00SJeff Kirsher 	s8     mdio_addr;
52640e9de4bSHariprasad Shenai 	enum fw_port_type port_type;
527f7917c00SJeff Kirsher 	u8     mod_type;
528f7917c00SJeff Kirsher 	u8     port_id;
529f7917c00SJeff Kirsher 	u8     tx_chan;
530f7917c00SJeff Kirsher 	u8     lport;                 /* associated offload logical port */
531f7917c00SJeff Kirsher 	u8     nqsets;                /* # of qsets */
532f7917c00SJeff Kirsher 	u8     first_qset;            /* index of first qset */
533f7917c00SJeff Kirsher 	u8     rss_mode;
534f7917c00SJeff Kirsher 	struct link_config link_cfg;
535f7917c00SJeff Kirsher 	u16   *rss;
536a4cfd929SHariprasad Shenai 	struct port_stats stats_base;
537688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB
538688848b1SAnish Bhatt 	struct port_dcb_info dcb;     /* Data Center Bridging support */
539688848b1SAnish Bhatt #endif
54076fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE
54176fed8a9SVarun Prakash 	struct cxgb_fcoe fcoe;
54276fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */
5435e2a5ebcSHariprasad Shenai 	bool rxtstamp;  /* Enable TS */
5445e2a5ebcSHariprasad Shenai 	struct hwtstamp_config tstamp_config;
545a4569504SAtul Gupta 	bool ptp_enable;
546b72a32daSRahul Lakkireddy 	struct sched_table *sched_tbl;
547f7917c00SJeff Kirsher };
548f7917c00SJeff Kirsher 
549f7917c00SJeff Kirsher struct dentry;
550f7917c00SJeff Kirsher struct work_struct;
551f7917c00SJeff Kirsher 
552f7917c00SJeff Kirsher enum {                                 /* adapter flags */
553f7917c00SJeff Kirsher 	FULL_INIT_DONE     = (1 << 0),
554144be3d9SGavin Shan 	DEV_ENABLED        = (1 << 1),
555144be3d9SGavin Shan 	USING_MSI          = (1 << 2),
556144be3d9SGavin Shan 	USING_MSIX         = (1 << 3),
557f7917c00SJeff Kirsher 	FW_OK              = (1 << 4),
55813ee15d3SVipul Pandya 	RSS_TNLALLLOOKUP   = (1 << 5),
55952367a76SVipul Pandya 	USING_SOFT_PARAMS  = (1 << 6),
56052367a76SVipul Pandya 	MASTER_PF          = (1 << 7),
56152367a76SVipul Pandya 	FW_OFLD_CONN       = (1 << 9),
562b0ba9d5fSCasey Leedom 	ROOT_NO_RELAXED_ORDERING = (1 << 10),
563e1f6198eSGanesh Goudar 	SHUTTING_DOWN	   = (1 << 11),
564f7917c00SJeff Kirsher };
565f7917c00SJeff Kirsher 
56694cdb8bbSHariprasad Shenai enum {
56794cdb8bbSHariprasad Shenai 	ULP_CRYPTO_LOOKASIDE = 1 << 0,
56894cdb8bbSHariprasad Shenai };
56994cdb8bbSHariprasad Shenai 
570f7917c00SJeff Kirsher struct rx_sw_desc;
571f7917c00SJeff Kirsher 
572f7917c00SJeff Kirsher struct sge_fl {                     /* SGE free-buffer queue state */
573f7917c00SJeff Kirsher 	unsigned int avail;         /* # of available Rx buffers */
574f7917c00SJeff Kirsher 	unsigned int pend_cred;     /* new buffers since last FL DB ring */
575f7917c00SJeff Kirsher 	unsigned int cidx;          /* consumer index */
576f7917c00SJeff Kirsher 	unsigned int pidx;          /* producer index */
577f7917c00SJeff Kirsher 	unsigned long alloc_failed; /* # of times buffer allocation failed */
578f7917c00SJeff Kirsher 	unsigned long large_alloc_failed;
57970055dd0SHariprasad Shenai 	unsigned long mapping_err;  /* # of RX Buffer DMA Mapping failures */
58070055dd0SHariprasad Shenai 	unsigned long low;          /* # of times momentarily starving */
581f7917c00SJeff Kirsher 	unsigned long starving;
582f7917c00SJeff Kirsher 	/* RO fields */
583f7917c00SJeff Kirsher 	unsigned int cntxt_id;      /* SGE context id for the free list */
584f7917c00SJeff Kirsher 	unsigned int size;          /* capacity of free list */
585f7917c00SJeff Kirsher 	struct rx_sw_desc *sdesc;   /* address of SW Rx descriptor ring */
586f7917c00SJeff Kirsher 	__be64 *desc;               /* address of HW Rx descriptor ring */
587f7917c00SJeff Kirsher 	dma_addr_t addr;            /* bus address of HW ring start */
588df64e4d3SHariprasad Shenai 	void __iomem *bar2_addr;    /* address of BAR2 Queue registers */
589df64e4d3SHariprasad Shenai 	unsigned int bar2_qid;      /* Queue ID for BAR2 Queue registers */
590f7917c00SJeff Kirsher };
591f7917c00SJeff Kirsher 
592f7917c00SJeff Kirsher /* A packet gather list */
593f7917c00SJeff Kirsher struct pkt_gl {
5945e2a5ebcSHariprasad Shenai 	u64 sgetstamp;		    /* SGE Time Stamp for Ingress Packet */
595e91b0f24SIan Campbell 	struct page_frag frags[MAX_SKB_FRAGS];
596f7917c00SJeff Kirsher 	void *va;                         /* virtual address of first byte */
597f7917c00SJeff Kirsher 	unsigned int nfrags;              /* # of fragments */
598f7917c00SJeff Kirsher 	unsigned int tot_len;             /* total length of fragments */
599f7917c00SJeff Kirsher };
600f7917c00SJeff Kirsher 
601f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
602f7917c00SJeff Kirsher 			      const struct pkt_gl *gl);
6032337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
6042337ba42SVarun Prakash /* LRO related declarations for ULD */
6052337ba42SVarun Prakash struct t4_lro_mgr {
6062337ba42SVarun Prakash #define MAX_LRO_SESSIONS		64
6072337ba42SVarun Prakash 	u8 lro_session_cnt;         /* # of sessions to aggregate */
6082337ba42SVarun Prakash 	unsigned long lro_pkts;     /* # of LRO super packets */
6092337ba42SVarun Prakash 	unsigned long lro_merged;   /* # of wire packets merged by LRO */
6102337ba42SVarun Prakash 	struct sk_buff_head lroq;   /* list of aggregated sessions */
6112337ba42SVarun Prakash };
612f7917c00SJeff Kirsher 
613f7917c00SJeff Kirsher struct sge_rspq {                   /* state for an SGE response queue */
614f7917c00SJeff Kirsher 	struct napi_struct napi;
615f7917c00SJeff Kirsher 	const __be64 *cur_desc;     /* current descriptor in queue */
616f7917c00SJeff Kirsher 	unsigned int cidx;          /* consumer index */
617f7917c00SJeff Kirsher 	u8 gen;                     /* current generation bit */
618f7917c00SJeff Kirsher 	u8 intr_params;             /* interrupt holdoff parameters */
619f7917c00SJeff Kirsher 	u8 next_intr_params;        /* holdoff params for next interrupt */
620e553ec3fSHariprasad Shenai 	u8 adaptive_rx;
621f7917c00SJeff Kirsher 	u8 pktcnt_idx;              /* interrupt packet threshold */
622f7917c00SJeff Kirsher 	u8 uld;                     /* ULD handling this queue */
623f7917c00SJeff Kirsher 	u8 idx;                     /* queue index within its group */
624f7917c00SJeff Kirsher 	int offset;                 /* offset into current Rx buffer */
625f7917c00SJeff Kirsher 	u16 cntxt_id;               /* SGE context id for the response q */
626f7917c00SJeff Kirsher 	u16 abs_id;                 /* absolute SGE id for the response q */
627f7917c00SJeff Kirsher 	__be64 *desc;               /* address of HW response ring */
628f7917c00SJeff Kirsher 	dma_addr_t phys_addr;       /* physical address of the ring */
629df64e4d3SHariprasad Shenai 	void __iomem *bar2_addr;    /* address of BAR2 Queue registers */
630df64e4d3SHariprasad Shenai 	unsigned int bar2_qid;      /* Queue ID for BAR2 Queue registers */
631f7917c00SJeff Kirsher 	unsigned int iqe_len;       /* entry size */
632f7917c00SJeff Kirsher 	unsigned int size;          /* capacity of response queue */
633f7917c00SJeff Kirsher 	struct adapter *adap;
634f7917c00SJeff Kirsher 	struct net_device *netdev;  /* associated net device */
635f7917c00SJeff Kirsher 	rspq_handler_t handler;
6362337ba42SVarun Prakash 	rspq_flush_handler_t flush_handler;
6372337ba42SVarun Prakash 	struct t4_lro_mgr lro_mgr;
638f7917c00SJeff Kirsher };
639f7917c00SJeff Kirsher 
640f7917c00SJeff Kirsher struct sge_eth_stats {              /* Ethernet queue statistics */
641f7917c00SJeff Kirsher 	unsigned long pkts;         /* # of ethernet packets */
642f7917c00SJeff Kirsher 	unsigned long lro_pkts;     /* # of LRO super packets */
643f7917c00SJeff Kirsher 	unsigned long lro_merged;   /* # of wire packets merged by LRO */
644f7917c00SJeff Kirsher 	unsigned long rx_cso;       /* # of Rx checksum offloads */
645f7917c00SJeff Kirsher 	unsigned long vlan_ex;      /* # of Rx VLAN extractions */
646f7917c00SJeff Kirsher 	unsigned long rx_drops;     /* # of packets dropped due to no mem */
647f7917c00SJeff Kirsher };
648f7917c00SJeff Kirsher 
649f7917c00SJeff Kirsher struct sge_eth_rxq {                /* SW Ethernet Rx queue */
650f7917c00SJeff Kirsher 	struct sge_rspq rspq;
651f7917c00SJeff Kirsher 	struct sge_fl fl;
652f7917c00SJeff Kirsher 	struct sge_eth_stats stats;
653f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp;
654f7917c00SJeff Kirsher 
655f7917c00SJeff Kirsher struct sge_ofld_stats {             /* offload queue statistics */
656f7917c00SJeff Kirsher 	unsigned long pkts;         /* # of packets */
657f7917c00SJeff Kirsher 	unsigned long imm;          /* # of immediate-data packets */
658f7917c00SJeff Kirsher 	unsigned long an;           /* # of asynchronous notifications */
659f7917c00SJeff Kirsher 	unsigned long nomem;        /* # of responses deferred due to no mem */
660f7917c00SJeff Kirsher };
661f7917c00SJeff Kirsher 
662f7917c00SJeff Kirsher struct sge_ofld_rxq {               /* SW offload Rx queue */
663f7917c00SJeff Kirsher 	struct sge_rspq rspq;
664f7917c00SJeff Kirsher 	struct sge_fl fl;
665f7917c00SJeff Kirsher 	struct sge_ofld_stats stats;
666f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp;
667f7917c00SJeff Kirsher 
668f7917c00SJeff Kirsher struct tx_desc {
669f7917c00SJeff Kirsher 	__be64 flit[8];
670f7917c00SJeff Kirsher };
671f7917c00SJeff Kirsher 
672f7917c00SJeff Kirsher struct tx_sw_desc;
673f7917c00SJeff Kirsher 
674f7917c00SJeff Kirsher struct sge_txq {
675f7917c00SJeff Kirsher 	unsigned int  in_use;       /* # of in-use Tx descriptors */
676ab677ff4SHariprasad Shenai 	unsigned int  q_type;	    /* Q type Eth/Ctrl/Ofld */
677f7917c00SJeff Kirsher 	unsigned int  size;         /* # of descriptors */
678f7917c00SJeff Kirsher 	unsigned int  cidx;         /* SW consumer index */
679f7917c00SJeff Kirsher 	unsigned int  pidx;         /* producer index */
680f7917c00SJeff Kirsher 	unsigned long stops;        /* # of times q has been stopped */
681f7917c00SJeff Kirsher 	unsigned long restarts;     /* # of queue restarts */
682f7917c00SJeff Kirsher 	unsigned int  cntxt_id;     /* SGE context id for the Tx q */
683f7917c00SJeff Kirsher 	struct tx_desc *desc;       /* address of HW Tx descriptor ring */
684f7917c00SJeff Kirsher 	struct tx_sw_desc *sdesc;   /* address of SW Tx descriptor ring */
685f7917c00SJeff Kirsher 	struct sge_qstat *stat;     /* queue status entry */
686f7917c00SJeff Kirsher 	dma_addr_t    phys_addr;    /* physical address of the ring */
6873069ee9bSVipul Pandya 	spinlock_t db_lock;
6883069ee9bSVipul Pandya 	int db_disabled;
6893069ee9bSVipul Pandya 	unsigned short db_pidx;
69005eb2389SSteve Wise 	unsigned short db_pidx_inc;
691df64e4d3SHariprasad Shenai 	void __iomem *bar2_addr;    /* address of BAR2 Queue registers */
692df64e4d3SHariprasad Shenai 	unsigned int bar2_qid;      /* Queue ID for BAR2 Queue registers */
693f7917c00SJeff Kirsher };
694f7917c00SJeff Kirsher 
695f7917c00SJeff Kirsher struct sge_eth_txq {                /* state for an SGE Ethernet Tx queue */
696f7917c00SJeff Kirsher 	struct sge_txq q;
697f7917c00SJeff Kirsher 	struct netdev_queue *txq;   /* associated netdev TX queue */
69810b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB
69910b00466SAnish Bhatt 	u8 dcb_prio;		    /* DCB Priority bound to queue */
70010b00466SAnish Bhatt #endif
701f7917c00SJeff Kirsher 	unsigned long tso;          /* # of TSO requests */
702f7917c00SJeff Kirsher 	unsigned long tx_cso;       /* # of Tx checksum offloads */
703f7917c00SJeff Kirsher 	unsigned long vlan_ins;     /* # of Tx VLAN insertions */
704f7917c00SJeff Kirsher 	unsigned long mapping_err;  /* # of I/O MMU packet mapping errors */
705f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp;
706f7917c00SJeff Kirsher 
707ab677ff4SHariprasad Shenai struct sge_uld_txq {               /* state for an SGE offload Tx queue */
708f7917c00SJeff Kirsher 	struct sge_txq q;
709f7917c00SJeff Kirsher 	struct adapter *adap;
710f7917c00SJeff Kirsher 	struct sk_buff_head sendq;  /* list of backpressured packets */
711f7917c00SJeff Kirsher 	struct tasklet_struct qresume_tsk; /* restarts the queue */
712126fca64SHariprasad Shenai 	bool service_ofldq_running; /* service_ofldq() is processing sendq */
713f7917c00SJeff Kirsher 	u8 full;                    /* the Tx ring is full */
714f7917c00SJeff Kirsher 	unsigned long mapping_err;  /* # of I/O MMU packet mapping errors */
715f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp;
716f7917c00SJeff Kirsher 
717f7917c00SJeff Kirsher struct sge_ctrl_txq {               /* state for an SGE control Tx queue */
718f7917c00SJeff Kirsher 	struct sge_txq q;
719f7917c00SJeff Kirsher 	struct adapter *adap;
720f7917c00SJeff Kirsher 	struct sk_buff_head sendq;  /* list of backpressured packets */
721f7917c00SJeff Kirsher 	struct tasklet_struct qresume_tsk; /* restarts the queue */
722f7917c00SJeff Kirsher 	u8 full;                    /* the Tx ring is full */
723f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp;
724f7917c00SJeff Kirsher 
72594cdb8bbSHariprasad Shenai struct sge_uld_rxq_info {
72694cdb8bbSHariprasad Shenai 	char name[IFNAMSIZ];	/* name of ULD driver */
72794cdb8bbSHariprasad Shenai 	struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
72894cdb8bbSHariprasad Shenai 	u16 *msix_tbl;		/* msix_tbl for uld */
72994cdb8bbSHariprasad Shenai 	u16 *rspq_id;		/* response queue id's of rxq */
73094cdb8bbSHariprasad Shenai 	u16 nrxq;		/* # of ingress uld queues */
73194cdb8bbSHariprasad Shenai 	u16 nciq;		/* # of completion queues */
73294cdb8bbSHariprasad Shenai 	u8 uld;			/* uld type */
73394cdb8bbSHariprasad Shenai };
73494cdb8bbSHariprasad Shenai 
735ab677ff4SHariprasad Shenai struct sge_uld_txq_info {
736ab677ff4SHariprasad Shenai 	struct sge_uld_txq *uldtxq; /* Txq's for ULD */
737ab677ff4SHariprasad Shenai 	atomic_t users;		/* num users */
738ab677ff4SHariprasad Shenai 	u16 ntxq;		/* # of egress uld queues */
739ab677ff4SHariprasad Shenai };
740ab677ff4SHariprasad Shenai 
741f7917c00SJeff Kirsher struct sge {
742f7917c00SJeff Kirsher 	struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
743a4569504SAtul Gupta 	struct sge_eth_txq ptptxq;
744f7917c00SJeff Kirsher 	struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
745f7917c00SJeff Kirsher 
746f7917c00SJeff Kirsher 	struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
747f7917c00SJeff Kirsher 	struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
74894cdb8bbSHariprasad Shenai 	struct sge_uld_rxq_info **uld_rxq_info;
749ab677ff4SHariprasad Shenai 	struct sge_uld_txq_info **uld_txq_info;
750f7917c00SJeff Kirsher 
751f7917c00SJeff Kirsher 	struct sge_rspq intrq ____cacheline_aligned_in_smp;
752f7917c00SJeff Kirsher 	spinlock_t intrq_lock;
753f7917c00SJeff Kirsher 
754f7917c00SJeff Kirsher 	u16 max_ethqsets;           /* # of available Ethernet queue sets */
755f7917c00SJeff Kirsher 	u16 ethqsets;               /* # of active Ethernet queue sets */
756f7917c00SJeff Kirsher 	u16 ethtxq_rover;           /* Tx queue to clean up next */
7570fbc81b3SHariprasad Shenai 	u16 ofldqsets;              /* # of active ofld queue sets */
75894cdb8bbSHariprasad Shenai 	u16 nqs_per_uld;	    /* # of Rx queues per ULD */
759f7917c00SJeff Kirsher 	u16 timer_val[SGE_NTIMERS];
760f7917c00SJeff Kirsher 	u8 counter_val[SGE_NCOUNTERS];
76152367a76SVipul Pandya 	u32 fl_pg_order;            /* large page allocation size */
76252367a76SVipul Pandya 	u32 stat_len;               /* length of status page at ring end */
76352367a76SVipul Pandya 	u32 pktshift;               /* padding between CPL & packet data */
76452367a76SVipul Pandya 	u32 fl_align;               /* response queue message alignment */
76552367a76SVipul Pandya 	u32 fl_starve_thres;        /* Free List starvation threshold */
7660f4d201fSKumar Sanghvi 
767a3bfb617SHariprasad Shenai 	struct sge_idma_monitor_state idma_monitor;
768f7917c00SJeff Kirsher 	unsigned int egr_start;
7694b8e27a8SHariprasad Shenai 	unsigned int egr_sz;
770f7917c00SJeff Kirsher 	unsigned int ingr_start;
7714b8e27a8SHariprasad Shenai 	unsigned int ingr_sz;
7724b8e27a8SHariprasad Shenai 	void **egr_map;    /* qid->queue egress queue map */
7734b8e27a8SHariprasad Shenai 	struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
7744b8e27a8SHariprasad Shenai 	unsigned long *starving_fl;
7754b8e27a8SHariprasad Shenai 	unsigned long *txq_maperr;
7765b377d11SHariprasad Shenai 	unsigned long *blocked_fl;
777f7917c00SJeff Kirsher 	struct timer_list rx_timer; /* refills starving FLs */
778f7917c00SJeff Kirsher 	struct timer_list tx_timer; /* checks Tx queues */
779f7917c00SJeff Kirsher };
780f7917c00SJeff Kirsher 
781f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
7820fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
783f7917c00SJeff Kirsher 
784f7917c00SJeff Kirsher struct l2t_data;
785f7917c00SJeff Kirsher 
7862422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV
7872422d9a3SSantosh Rastapur 
7887d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7.  However, the Serial
7897d6727cfSSantosh Rastapur  * Configuration initialization for T5 only has SR-IOV functionality enabled
7907d6727cfSSantosh Rastapur  * on PF0-3 in order to simplify everything.
7912422d9a3SSantosh Rastapur  */
7927d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4
7932422d9a3SSantosh Rastapur 
7942422d9a3SSantosh Rastapur #endif
7952422d9a3SSantosh Rastapur 
796a4cfd929SHariprasad Shenai struct doorbell_stats {
797a4cfd929SHariprasad Shenai 	u32 db_drop;
798a4cfd929SHariprasad Shenai 	u32 db_empty;
799a4cfd929SHariprasad Shenai 	u32 db_full;
800a4cfd929SHariprasad Shenai };
801a4cfd929SHariprasad Shenai 
802fc08a01aSHariprasad Shenai struct hash_mac_addr {
803fc08a01aSHariprasad Shenai 	struct list_head list;
804fc08a01aSHariprasad Shenai 	u8 addr[ETH_ALEN];
805fc08a01aSHariprasad Shenai };
806fc08a01aSHariprasad Shenai 
80794cdb8bbSHariprasad Shenai struct uld_msix_bmap {
80894cdb8bbSHariprasad Shenai 	unsigned long *msix_bmap;
80994cdb8bbSHariprasad Shenai 	unsigned int mapsize;
81094cdb8bbSHariprasad Shenai 	spinlock_t lock; /* lock for acquiring bitmap */
81194cdb8bbSHariprasad Shenai };
81294cdb8bbSHariprasad Shenai 
81394cdb8bbSHariprasad Shenai struct uld_msix_info {
81494cdb8bbSHariprasad Shenai 	unsigned short vec;
81594cdb8bbSHariprasad Shenai 	char desc[IFNAMSIZ + 10];
8160fbc81b3SHariprasad Shenai 	unsigned int idx;
81794cdb8bbSHariprasad Shenai };
81894cdb8bbSHariprasad Shenai 
819661dbeb9SHariprasad Shenai struct vf_info {
820661dbeb9SHariprasad Shenai 	unsigned char vf_mac_addr[ETH_ALEN];
8218ea4fae9SGanesh Goudar 	unsigned int tx_rate;
822661dbeb9SHariprasad Shenai 	bool pf_set_mac;
823661dbeb9SHariprasad Shenai };
824661dbeb9SHariprasad Shenai 
8254055ae5eSHariprasad Shenai struct mbox_list {
8264055ae5eSHariprasad Shenai 	struct list_head list;
8274055ae5eSHariprasad Shenai };
8284055ae5eSHariprasad Shenai 
829f7917c00SJeff Kirsher struct adapter {
830f7917c00SJeff Kirsher 	void __iomem *regs;
83122adfe0aSSantosh Rastapur 	void __iomem *bar2;
8320abfd152SHariprasad Shenai 	u32 t4_bar0;
833f7917c00SJeff Kirsher 	struct pci_dev *pdev;
834f7917c00SJeff Kirsher 	struct device *pdev_dev;
8350de72738SHariprasad Shenai 	const char *name;
8363069ee9bSVipul Pandya 	unsigned int mbox;
837b2612722SHariprasad Shenai 	unsigned int pf;
838f7917c00SJeff Kirsher 	unsigned int flags;
839e7b48a32SHariprasad Shenai 	unsigned int adap_idx;
8402422d9a3SSantosh Rastapur 	enum chip_type chip;
841f7917c00SJeff Kirsher 
842f7917c00SJeff Kirsher 	int msg_enable;
843f7917c00SJeff Kirsher 
844f7917c00SJeff Kirsher 	struct adapter_params params;
845f7917c00SJeff Kirsher 	struct cxgb4_virt_res vres;
846f7917c00SJeff Kirsher 	unsigned int swintr;
847f7917c00SJeff Kirsher 
848f7917c00SJeff Kirsher 	struct {
849f7917c00SJeff Kirsher 		unsigned short vec;
850f7917c00SJeff Kirsher 		char desc[IFNAMSIZ + 10];
851f7917c00SJeff Kirsher 	} msix_info[MAX_INGQ + 1];
85294cdb8bbSHariprasad Shenai 	struct uld_msix_info *msix_info_ulds; /* msix info for uld's */
85394cdb8bbSHariprasad Shenai 	struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */
8540fbc81b3SHariprasad Shenai 	int msi_idx;
855f7917c00SJeff Kirsher 
856a4cfd929SHariprasad Shenai 	struct doorbell_stats db_stats;
857f7917c00SJeff Kirsher 	struct sge sge;
858f7917c00SJeff Kirsher 
859f7917c00SJeff Kirsher 	struct net_device *port[MAX_NPORTS];
860f7917c00SJeff Kirsher 	u8 chan_map[NCHAN];                   /* channel -> port map */
861f7917c00SJeff Kirsher 
862661dbeb9SHariprasad Shenai 	struct vf_info *vfinfo;
863661dbeb9SHariprasad Shenai 	u8 num_vfs;
864661dbeb9SHariprasad Shenai 
865793dad94SVipul Pandya 	u32 filter_mode;
866636f9d37SVipul Pandya 	unsigned int l2t_start;
867636f9d37SVipul Pandya 	unsigned int l2t_end;
868f7917c00SJeff Kirsher 	struct l2t_data *l2t;
869b5a02f50SAnish Bhatt 	unsigned int clipt_start;
870b5a02f50SAnish Bhatt 	unsigned int clipt_end;
871b5a02f50SAnish Bhatt 	struct clip_tbl *clipt;
8723bdb376eSKumar Sanghvi 	struct smt_data *smt;
8730fbc81b3SHariprasad Shenai 	struct cxgb4_uld_info *uld;
874f7917c00SJeff Kirsher 	void *uld_handle[CXGB4_ULD_MAX];
87594cdb8bbSHariprasad Shenai 	unsigned int num_uld;
8760fbc81b3SHariprasad Shenai 	unsigned int num_ofld_uld;
877f7917c00SJeff Kirsher 	struct list_head list_node;
87801bcca68SVipul Pandya 	struct list_head rcu_node;
879fc08a01aSHariprasad Shenai 	struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
880f7917c00SJeff Kirsher 
8817714cb9eSVarun Prakash 	void *iscsi_ppm;
8827714cb9eSVarun Prakash 
883f7917c00SJeff Kirsher 	struct tid_info tids;
884f7917c00SJeff Kirsher 	void **tid_release_head;
885f7917c00SJeff Kirsher 	spinlock_t tid_release_lock;
88629aaee65SAnish Bhatt 	struct workqueue_struct *workq;
887f7917c00SJeff Kirsher 	struct work_struct tid_release_task;
888881806bcSVipul Pandya 	struct work_struct db_full_task;
889881806bcSVipul Pandya 	struct work_struct db_drop_task;
890f7917c00SJeff Kirsher 	bool tid_release_task_busy;
891f7917c00SJeff Kirsher 
8924055ae5eSHariprasad Shenai 	/* lock for mailbox cmd list */
8934055ae5eSHariprasad Shenai 	spinlock_t mbox_lock;
8944055ae5eSHariprasad Shenai 	struct mbox_list mlist;
8954055ae5eSHariprasad Shenai 
8967f080c3fSHariprasad Shenai 	/* support for mailbox command/reply logging */
8977f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256
8987f080c3fSHariprasad Shenai 	struct mbox_cmd_log *mbox_log;
8997f080c3fSHariprasad Shenai 
9000fbc81b3SHariprasad Shenai 	struct mutex uld_mutex;
9010fbc81b3SHariprasad Shenai 
902f7917c00SJeff Kirsher 	struct dentry *debugfs_root;
903621a5f7aSViresh Kumar 	bool use_bd;     /* Use SGE Back Door intfc for reading SGE Contexts */
904621a5f7aSViresh Kumar 	bool trace_rss;	/* 1 implies that different RSS flit per filter is
9058e3d04fdSHariprasad Shenai 			 * used per filter else if 0 default RSS flit is
9068e3d04fdSHariprasad Shenai 			 * used for all 4 filters.
9078e3d04fdSHariprasad Shenai 			 */
908f7917c00SJeff Kirsher 
909a4569504SAtul Gupta 	struct ptp_clock *ptp_clock;
910a4569504SAtul Gupta 	struct ptp_clock_info ptp_clock_info;
911a4569504SAtul Gupta 	struct sk_buff *ptp_tx_skb;
912a4569504SAtul Gupta 	/* ptp lock */
913a4569504SAtul Gupta 	spinlock_t ptp_lock;
914f7917c00SJeff Kirsher 	spinlock_t stats_lock;
915fc5ab020SHariprasad Shenai 	spinlock_t win0_lock ____cacheline_aligned_in_smp;
916d8931847SRahul Lakkireddy 
917d8931847SRahul Lakkireddy 	/* TC u32 offload */
918d8931847SRahul Lakkireddy 	struct cxgb4_tc_u32_table *tc_u32;
919ee0863baSHarsh Jain 	struct chcr_stats_debug chcr_stats;
92062488e4bSKumar Sanghvi 
92162488e4bSKumar Sanghvi 	/* TC flower offload */
92279e6d46aSKumar Sanghvi 	struct rhashtable flower_tbl;
92379e6d46aSKumar Sanghvi 	struct rhashtable_params flower_ht_params;
924e0f911c8SKumar Sanghvi 	struct timer_list flower_stats_timer;
92579e6d46aSKumar Sanghvi 	struct work_struct flower_stats_work;
926ad75b7d3SRahul Lakkireddy 
927ad75b7d3SRahul Lakkireddy 	/* Ethtool Dump */
928ad75b7d3SRahul Lakkireddy 	struct ethtool_dump eth_dump;
929f7917c00SJeff Kirsher };
930f7917c00SJeff Kirsher 
931b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be
932b72a32daSRahul Lakkireddy  * programmed with various parameters.
933b72a32daSRahul Lakkireddy  */
934b72a32daSRahul Lakkireddy struct ch_sched_params {
935b72a32daSRahul Lakkireddy 	s8   type;                     /* packet or flow */
936b72a32daSRahul Lakkireddy 	union {
937b72a32daSRahul Lakkireddy 		struct {
938b72a32daSRahul Lakkireddy 			s8   level;    /* scheduler hierarchy level */
939b72a32daSRahul Lakkireddy 			s8   mode;     /* per-class or per-flow */
940b72a32daSRahul Lakkireddy 			s8   rateunit; /* bit or packet rate */
941b72a32daSRahul Lakkireddy 			s8   ratemode; /* %port relative or kbps absolute */
942b72a32daSRahul Lakkireddy 			s8   channel;  /* scheduler channel [0..N] */
943b72a32daSRahul Lakkireddy 			s8   class;    /* scheduler class [0..N] */
944b72a32daSRahul Lakkireddy 			s32  minrate;  /* minimum rate */
945b72a32daSRahul Lakkireddy 			s32  maxrate;  /* maximum rate */
946b72a32daSRahul Lakkireddy 			s16  weight;   /* percent weight */
947b72a32daSRahul Lakkireddy 			s16  pktsize;  /* average packet size */
948b72a32daSRahul Lakkireddy 		} params;
949b72a32daSRahul Lakkireddy 	} u;
950b72a32daSRahul Lakkireddy };
951b72a32daSRahul Lakkireddy 
95210a2604eSRahul Lakkireddy enum {
95310a2604eSRahul Lakkireddy 	SCHED_CLASS_TYPE_PACKET = 0,    /* class type */
95410a2604eSRahul Lakkireddy };
95510a2604eSRahul Lakkireddy 
95610a2604eSRahul Lakkireddy enum {
95710a2604eSRahul Lakkireddy 	SCHED_CLASS_LEVEL_CL_RL = 0,    /* class rate limiter */
95810a2604eSRahul Lakkireddy };
95910a2604eSRahul Lakkireddy 
96010a2604eSRahul Lakkireddy enum {
96110a2604eSRahul Lakkireddy 	SCHED_CLASS_MODE_CLASS = 0,     /* per-class scheduling */
96210a2604eSRahul Lakkireddy };
96310a2604eSRahul Lakkireddy 
96410a2604eSRahul Lakkireddy enum {
96510a2604eSRahul Lakkireddy 	SCHED_CLASS_RATEUNIT_BITS = 0,  /* bit rate scheduling */
96610a2604eSRahul Lakkireddy };
96710a2604eSRahul Lakkireddy 
96810a2604eSRahul Lakkireddy enum {
96910a2604eSRahul Lakkireddy 	SCHED_CLASS_RATEMODE_ABS = 1,   /* Kb/s */
97010a2604eSRahul Lakkireddy };
97110a2604eSRahul Lakkireddy 
9726cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues
9736cede1f1SRahul Lakkireddy  * to be bound to a TX Scheduling Class.
9746cede1f1SRahul Lakkireddy  */
9756cede1f1SRahul Lakkireddy struct ch_sched_queue {
9766cede1f1SRahul Lakkireddy 	s8   queue;    /* queue index */
9776cede1f1SRahul Lakkireddy 	s8   class;    /* class index */
9786cede1f1SRahul Lakkireddy };
9796cede1f1SRahul Lakkireddy 
980f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples
981f2b7e78dSVipul Pandya  */
982f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16
983f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1
984f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9
985f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1
986f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3
987f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3
988f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8
989f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8
990f2b7e78dSVipul Pandya #define PF_BITWIDTH 8
991f2b7e78dSVipul Pandya #define VF_BITWIDTH 8
992f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16
993f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16
994f2b7e78dSVipul Pandya 
995f2b7e78dSVipul Pandya /* Filter matching rules.  These consist of a set of ingress packet field
996f2b7e78dSVipul Pandya  * (value, mask) tuples.  The associated ingress packet field matches the
997f2b7e78dSVipul Pandya  * tuple when ((field & mask) == value).  (Thus a wildcard "don't care" field
998f2b7e78dSVipul Pandya  * rule can be constructed by specifying a tuple of (0, 0).)  A filter rule
999f2b7e78dSVipul Pandya  * matches an ingress packet when all of the individual individual field
1000f2b7e78dSVipul Pandya  * matching rules are true.
1001f2b7e78dSVipul Pandya  *
1002f2b7e78dSVipul Pandya  * Partial field masks are always valid, however, while it may be easy to
1003f2b7e78dSVipul Pandya  * understand their meanings for some fields (e.g. IP address to match a
1004f2b7e78dSVipul Pandya  * subnet), for others making sensible partial masks is less intuitive (e.g.
1005f2b7e78dSVipul Pandya  * MPS match type) ...
1006f2b7e78dSVipul Pandya  *
1007f2b7e78dSVipul Pandya  * Most of the following data structures are modeled on T4 capabilities.
1008f2b7e78dSVipul Pandya  * Drivers for earlier chips use the subsets which make sense for those chips.
1009f2b7e78dSVipul Pandya  * We really need to come up with a hardware-independent mechanism to
1010f2b7e78dSVipul Pandya  * represent hardware filter capabilities ...
1011f2b7e78dSVipul Pandya  */
1012f2b7e78dSVipul Pandya struct ch_filter_tuple {
1013f2b7e78dSVipul Pandya 	/* Compressed header matching field rules.  The TP_VLAN_PRI_MAP
1014f2b7e78dSVipul Pandya 	 * register selects which of these fields will participate in the
1015f2b7e78dSVipul Pandya 	 * filter match rules -- up to a maximum of 36 bits.  Because
1016f2b7e78dSVipul Pandya 	 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
1017f2b7e78dSVipul Pandya 	 * set of fields.
1018f2b7e78dSVipul Pandya 	 */
1019f2b7e78dSVipul Pandya 	uint32_t ethtype:ETHTYPE_BITWIDTH;      /* Ethernet type */
1020f2b7e78dSVipul Pandya 	uint32_t frag:FRAG_BITWIDTH;            /* IP fragmentation header */
1021f2b7e78dSVipul Pandya 	uint32_t ivlan_vld:1;                   /* inner VLAN valid */
1022f2b7e78dSVipul Pandya 	uint32_t ovlan_vld:1;                   /* outer VLAN valid */
1023f2b7e78dSVipul Pandya 	uint32_t pfvf_vld:1;                    /* PF/VF valid */
1024f2b7e78dSVipul Pandya 	uint32_t macidx:MACIDX_BITWIDTH;        /* exact match MAC index */
1025f2b7e78dSVipul Pandya 	uint32_t fcoe:FCOE_BITWIDTH;            /* FCoE packet */
1026f2b7e78dSVipul Pandya 	uint32_t iport:IPORT_BITWIDTH;          /* ingress port */
1027f2b7e78dSVipul Pandya 	uint32_t matchtype:MATCHTYPE_BITWIDTH;  /* MPS match type */
1028f2b7e78dSVipul Pandya 	uint32_t proto:PROTO_BITWIDTH;          /* protocol type */
1029f2b7e78dSVipul Pandya 	uint32_t tos:TOS_BITWIDTH;              /* TOS/Traffic Type */
1030f2b7e78dSVipul Pandya 	uint32_t pf:PF_BITWIDTH;                /* PCI-E PF ID */
1031f2b7e78dSVipul Pandya 	uint32_t vf:VF_BITWIDTH;                /* PCI-E VF ID */
1032f2b7e78dSVipul Pandya 	uint32_t ivlan:IVLAN_BITWIDTH;          /* inner VLAN */
1033f2b7e78dSVipul Pandya 	uint32_t ovlan:OVLAN_BITWIDTH;          /* outer VLAN */
1034f2b7e78dSVipul Pandya 
1035f2b7e78dSVipul Pandya 	/* Uncompressed header matching field rules.  These are always
1036f2b7e78dSVipul Pandya 	 * available for field rules.
1037f2b7e78dSVipul Pandya 	 */
1038f2b7e78dSVipul Pandya 	uint8_t lip[16];        /* local IP address (IPv4 in [3:0]) */
1039f2b7e78dSVipul Pandya 	uint8_t fip[16];        /* foreign IP address (IPv4 in [3:0]) */
1040f2b7e78dSVipul Pandya 	uint16_t lport;         /* local port */
1041f2b7e78dSVipul Pandya 	uint16_t fport;         /* foreign port */
1042f2b7e78dSVipul Pandya };
1043f2b7e78dSVipul Pandya 
1044f2b7e78dSVipul Pandya /* A filter ioctl command.
1045f2b7e78dSVipul Pandya  */
1046f2b7e78dSVipul Pandya struct ch_filter_specification {
1047f2b7e78dSVipul Pandya 	/* Administrative fields for filter.
1048f2b7e78dSVipul Pandya 	 */
1049f2b7e78dSVipul Pandya 	uint32_t hitcnts:1;     /* count filter hits in TCB */
1050f2b7e78dSVipul Pandya 	uint32_t prio:1;        /* filter has priority over active/server */
1051f2b7e78dSVipul Pandya 
1052f2b7e78dSVipul Pandya 	/* Fundamental filter typing.  This is the one element of filter
1053f2b7e78dSVipul Pandya 	 * matching that doesn't exist as a (value, mask) tuple.
1054f2b7e78dSVipul Pandya 	 */
1055f2b7e78dSVipul Pandya 	uint32_t type:1;        /* 0 => IPv4, 1 => IPv6 */
105612b276fbSKumar Sanghvi 	u32 hash:1;		/* 0 => wild-card, 1 => exact-match */
1057f2b7e78dSVipul Pandya 
1058f2b7e78dSVipul Pandya 	/* Packet dispatch information.  Ingress packets which match the
1059f2b7e78dSVipul Pandya 	 * filter rules will be dropped, passed to the host or switched back
1060f2b7e78dSVipul Pandya 	 * out as egress packets.
1061f2b7e78dSVipul Pandya 	 */
1062f2b7e78dSVipul Pandya 	uint32_t action:2;      /* drop, pass, switch */
1063f2b7e78dSVipul Pandya 
1064f2b7e78dSVipul Pandya 	uint32_t rpttid:1;      /* report TID in RSS hash field */
1065f2b7e78dSVipul Pandya 
1066f2b7e78dSVipul Pandya 	uint32_t dirsteer:1;    /* 0 => RSS, 1 => steer to iq */
1067f2b7e78dSVipul Pandya 	uint32_t iq:10;         /* ingress queue */
1068f2b7e78dSVipul Pandya 
1069f2b7e78dSVipul Pandya 	uint32_t maskhash:1;    /* dirsteer=0: store RSS hash in TCB */
1070f2b7e78dSVipul Pandya 	uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1071f2b7e78dSVipul Pandya 				/*             1 => TCB contains IQ ID */
1072f2b7e78dSVipul Pandya 
1073f2b7e78dSVipul Pandya 	/* Switch proxy/rewrite fields.  An ingress packet which matches a
1074f2b7e78dSVipul Pandya 	 * filter with "switch" set will be looped back out as an egress
1075f2b7e78dSVipul Pandya 	 * packet -- potentially with some Ethernet header rewriting.
1076f2b7e78dSVipul Pandya 	 */
1077f2b7e78dSVipul Pandya 	uint32_t eport:2;       /* egress port to switch packet out */
1078f2b7e78dSVipul Pandya 	uint32_t newdmac:1;     /* rewrite destination MAC address */
1079f2b7e78dSVipul Pandya 	uint32_t newsmac:1;     /* rewrite source MAC address */
1080f2b7e78dSVipul Pandya 	uint32_t newvlan:2;     /* rewrite VLAN Tag */
10810ff90994SKumar Sanghvi 	uint32_t nat_mode:3;    /* specify NAT operation mode */
1082f2b7e78dSVipul Pandya 	uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1083f2b7e78dSVipul Pandya 	uint8_t smac[ETH_ALEN]; /* new source MAC address */
1084f2b7e78dSVipul Pandya 	uint16_t vlan;          /* VLAN Tag to insert */
1085f2b7e78dSVipul Pandya 
10860ff90994SKumar Sanghvi 	u8 nat_lip[16];		/* local IP to use after NAT'ing */
10870ff90994SKumar Sanghvi 	u8 nat_fip[16];		/* foreign IP to use after NAT'ing */
10880ff90994SKumar Sanghvi 	u16 nat_lport;		/* local port to use after NAT'ing */
10890ff90994SKumar Sanghvi 	u16 nat_fport;		/* foreign port to use after NAT'ing */
10900ff90994SKumar Sanghvi 
10910ff90994SKumar Sanghvi 	/* reservation for future additions */
10920ff90994SKumar Sanghvi 	u8 rsvd[24];
10930ff90994SKumar Sanghvi 
1094f2b7e78dSVipul Pandya 	/* Filter rule value/mask pairs.
1095f2b7e78dSVipul Pandya 	 */
1096f2b7e78dSVipul Pandya 	struct ch_filter_tuple val;
1097f2b7e78dSVipul Pandya 	struct ch_filter_tuple mask;
1098f2b7e78dSVipul Pandya };
1099f2b7e78dSVipul Pandya 
1100f2b7e78dSVipul Pandya enum {
1101f2b7e78dSVipul Pandya 	FILTER_PASS = 0,        /* default */
1102f2b7e78dSVipul Pandya 	FILTER_DROP,
1103f2b7e78dSVipul Pandya 	FILTER_SWITCH
1104f2b7e78dSVipul Pandya };
1105f2b7e78dSVipul Pandya 
1106f2b7e78dSVipul Pandya enum {
1107f2b7e78dSVipul Pandya 	VLAN_NOCHANGE = 0,      /* default */
1108f2b7e78dSVipul Pandya 	VLAN_REMOVE,
1109f2b7e78dSVipul Pandya 	VLAN_INSERT,
1110f2b7e78dSVipul Pandya 	VLAN_REWRITE
1111f2b7e78dSVipul Pandya };
1112f2b7e78dSVipul Pandya 
1113557ccbf9SKumar Sanghvi enum {
111412b276fbSKumar Sanghvi 	NAT_MODE_NONE = 0,	/* No NAT performed */
111512b276fbSKumar Sanghvi 	NAT_MODE_DIP,		/* NAT on Dst IP */
111612b276fbSKumar Sanghvi 	NAT_MODE_DIP_DP,	/* NAT on Dst IP, Dst Port */
111712b276fbSKumar Sanghvi 	NAT_MODE_DIP_DP_SIP,	/* NAT on Dst IP, Dst Port and Src IP */
111812b276fbSKumar Sanghvi 	NAT_MODE_DIP_DP_SP,	/* NAT on Dst IP, Dst Port and Src Port */
111912b276fbSKumar Sanghvi 	NAT_MODE_SIP_SP,	/* NAT on Src IP and Src Port */
112012b276fbSKumar Sanghvi 	NAT_MODE_DIP_SIP_SP,	/* NAT on Dst IP, Src IP and Src Port */
112112b276fbSKumar Sanghvi 	NAT_MODE_ALL		/* NAT on entire 4-tuple */
1122557ccbf9SKumar Sanghvi };
1123557ccbf9SKumar Sanghvi 
1124d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry.  This is in host native format
1125d57fd6caSRahul Lakkireddy  * and doesn't match the ordering or bit order, etc. of the hardware of the
1126d57fd6caSRahul Lakkireddy  * firmware command.  The use of bit-field structure elements is purely to
1127d57fd6caSRahul Lakkireddy  * remind ourselves of the field size limitations and save memory in the case
1128d57fd6caSRahul Lakkireddy  * where the filter table is large.
1129d57fd6caSRahul Lakkireddy  */
1130d57fd6caSRahul Lakkireddy struct filter_entry {
1131d57fd6caSRahul Lakkireddy 	/* Administrative fields for filter. */
1132d57fd6caSRahul Lakkireddy 	u32 valid:1;            /* filter allocated and valid */
1133d57fd6caSRahul Lakkireddy 	u32 locked:1;           /* filter is administratively locked */
1134d57fd6caSRahul Lakkireddy 
1135d57fd6caSRahul Lakkireddy 	u32 pending:1;          /* filter action is pending firmware reply */
1136578b46b9SRahul Lakkireddy 	struct filter_ctx *ctx; /* Caller's completion hook */
1137d57fd6caSRahul Lakkireddy 	struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
11383bdb376eSKumar Sanghvi 	struct smt_entry *smt;  /* Source Mac Table entry for smac */
1139578b46b9SRahul Lakkireddy 	struct net_device *dev; /* Associated net device */
1140578b46b9SRahul Lakkireddy 	u32 tid;                /* This will store the actual tid */
1141d57fd6caSRahul Lakkireddy 
1142d57fd6caSRahul Lakkireddy 	/* The filter itself.  Most of this is a straight copy of information
1143d57fd6caSRahul Lakkireddy 	 * provided by the extended ioctl().  Some fields are translated to
1144d57fd6caSRahul Lakkireddy 	 * internal forms -- for instance the Ingress Queue ID passed in from
1145d57fd6caSRahul Lakkireddy 	 * the ioctl() is translated into the Absolute Ingress Queue ID.
1146d57fd6caSRahul Lakkireddy 	 */
1147d57fd6caSRahul Lakkireddy 	struct ch_filter_specification fs;
1148d57fd6caSRahul Lakkireddy };
1149d57fd6caSRahul Lakkireddy 
1150a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap)
1151a4cfd929SHariprasad Shenai {
1152a4cfd929SHariprasad Shenai 	return adap->params.offload;
1153a4cfd929SHariprasad Shenai }
1154a4cfd929SHariprasad Shenai 
11555c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap)
11565c31254eSKumar Sanghvi {
11575c31254eSKumar Sanghvi 	return adap->params.hash_filter;
11585c31254eSKumar Sanghvi }
11595c31254eSKumar Sanghvi 
116094cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap)
116194cdb8bbSHariprasad Shenai {
116294cdb8bbSHariprasad Shenai 	return adap->params.crypto;
116394cdb8bbSHariprasad Shenai }
116494cdb8bbSHariprasad Shenai 
11650fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap)
11660fbc81b3SHariprasad Shenai {
11670fbc81b3SHariprasad Shenai 	return (adap->params.offload || adap->params.crypto);
11680fbc81b3SHariprasad Shenai }
11690fbc81b3SHariprasad Shenai 
1170f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1171f7917c00SJeff Kirsher {
1172f7917c00SJeff Kirsher 	return readl(adap->regs + reg_addr);
1173f7917c00SJeff Kirsher }
1174f7917c00SJeff Kirsher 
1175f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1176f7917c00SJeff Kirsher {
1177f7917c00SJeff Kirsher 	writel(val, adap->regs + reg_addr);
1178f7917c00SJeff Kirsher }
1179f7917c00SJeff Kirsher 
1180f7917c00SJeff Kirsher #ifndef readq
1181f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr)
1182f7917c00SJeff Kirsher {
1183f7917c00SJeff Kirsher 	return readl(addr) + ((u64)readl(addr + 4) << 32);
1184f7917c00SJeff Kirsher }
1185f7917c00SJeff Kirsher 
1186f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr)
1187f7917c00SJeff Kirsher {
1188f7917c00SJeff Kirsher 	writel(val, addr);
1189f7917c00SJeff Kirsher 	writel(val >> 32, addr + 4);
1190f7917c00SJeff Kirsher }
1191f7917c00SJeff Kirsher #endif
1192f7917c00SJeff Kirsher 
1193f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1194f7917c00SJeff Kirsher {
1195f7917c00SJeff Kirsher 	return readq(adap->regs + reg_addr);
1196f7917c00SJeff Kirsher }
1197f7917c00SJeff Kirsher 
1198f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1199f7917c00SJeff Kirsher {
1200f7917c00SJeff Kirsher 	writeq(val, adap->regs + reg_addr);
1201f7917c00SJeff Kirsher }
1202f7917c00SJeff Kirsher 
1203f7917c00SJeff Kirsher /**
1204098ef6c2SHariprasad Shenai  * t4_set_hw_addr - store a port's MAC address in SW
1205098ef6c2SHariprasad Shenai  * @adapter: the adapter
1206098ef6c2SHariprasad Shenai  * @port_idx: the port index
1207098ef6c2SHariprasad Shenai  * @hw_addr: the Ethernet address
1208098ef6c2SHariprasad Shenai  *
1209098ef6c2SHariprasad Shenai  * Store the Ethernet address of the given port in SW.  Called by the common
1210098ef6c2SHariprasad Shenai  * code when it retrieves a port's Ethernet address from EEPROM.
1211098ef6c2SHariprasad Shenai  */
1212098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1213098ef6c2SHariprasad Shenai 				  u8 hw_addr[])
1214098ef6c2SHariprasad Shenai {
1215098ef6c2SHariprasad Shenai 	ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1216098ef6c2SHariprasad Shenai 	ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1217098ef6c2SHariprasad Shenai }
1218098ef6c2SHariprasad Shenai 
1219098ef6c2SHariprasad Shenai /**
1220f7917c00SJeff Kirsher  * netdev2pinfo - return the port_info structure associated with a net_device
1221f7917c00SJeff Kirsher  * @dev: the netdev
1222f7917c00SJeff Kirsher  *
1223f7917c00SJeff Kirsher  * Return the struct port_info associated with a net_device
1224f7917c00SJeff Kirsher  */
1225f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1226f7917c00SJeff Kirsher {
1227f7917c00SJeff Kirsher 	return netdev_priv(dev);
1228f7917c00SJeff Kirsher }
1229f7917c00SJeff Kirsher 
1230f7917c00SJeff Kirsher /**
1231f7917c00SJeff Kirsher  * adap2pinfo - return the port_info of a port
1232f7917c00SJeff Kirsher  * @adap: the adapter
1233f7917c00SJeff Kirsher  * @idx: the port index
1234f7917c00SJeff Kirsher  *
1235f7917c00SJeff Kirsher  * Return the port_info structure for the port of the given index.
1236f7917c00SJeff Kirsher  */
1237f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1238f7917c00SJeff Kirsher {
1239f7917c00SJeff Kirsher 	return netdev_priv(adap->port[idx]);
1240f7917c00SJeff Kirsher }
1241f7917c00SJeff Kirsher 
1242f7917c00SJeff Kirsher /**
1243f7917c00SJeff Kirsher  * netdev2adap - return the adapter structure associated with a net_device
1244f7917c00SJeff Kirsher  * @dev: the netdev
1245f7917c00SJeff Kirsher  *
1246f7917c00SJeff Kirsher  * Return the struct adapter associated with a net_device
1247f7917c00SJeff Kirsher  */
1248f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev)
1249f7917c00SJeff Kirsher {
1250f7917c00SJeff Kirsher 	return netdev2pinfo(dev)->adapter;
1251f7917c00SJeff Kirsher }
1252f7917c00SJeff Kirsher 
1253812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter.  The scheme is:
1254812034f1SHariprasad Shenai  * - bits 0..9: chip version
1255812034f1SHariprasad Shenai  * - bits 10..15: chip revision
1256812034f1SHariprasad Shenai  * - bits 16..23: register dump version
1257812034f1SHariprasad Shenai  */
1258812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap)
1259812034f1SHariprasad Shenai {
1260812034f1SHariprasad Shenai 	return CHELSIO_CHIP_VERSION(ap->params.chip) |
1261812034f1SHariprasad Shenai 		(CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1262812034f1SHariprasad Shenai }
1263812034f1SHariprasad Shenai 
1264812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us.  0 means no timer. */
1265812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap,
1266812034f1SHariprasad Shenai 				      const struct sge_rspq *q)
1267812034f1SHariprasad Shenai {
1268812034f1SHariprasad Shenai 	unsigned int idx = q->intr_params >> 1;
1269812034f1SHariprasad Shenai 
1270812034f1SHariprasad Shenai 	return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1271812034f1SHariprasad Shenai }
1272812034f1SHariprasad Shenai 
1273812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */
1274812034f1SHariprasad Shenai extern char cxgb4_driver_name[];
1275812034f1SHariprasad Shenai extern const char cxgb4_driver_version[];
1276812034f1SHariprasad Shenai 
1277f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1278f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1279f7917c00SJeff Kirsher 
1280f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap);
12815fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1282f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap);
1283f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1284f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1285f7917c00SJeff Kirsher 		     const struct pkt_gl *gl);
1286f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1287f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1288f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1289f7917c00SJeff Kirsher 		     struct net_device *dev, int intr_idx,
12902337ba42SVarun Prakash 		     struct sge_fl *fl, rspq_handler_t hnd,
12912337ba42SVarun Prakash 		     rspq_flush_handler_t flush_handler, int cong);
1292f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1293f7917c00SJeff Kirsher 			 struct net_device *dev, struct netdev_queue *netdevq,
1294f7917c00SJeff Kirsher 			 unsigned int iqid);
1295f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1296f7917c00SJeff Kirsher 			  struct net_device *dev, unsigned int iqid,
1297f7917c00SJeff Kirsher 			  unsigned int cmplqid);
12980fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
12990fbc81b3SHariprasad Shenai 			unsigned int cmplqid);
1300ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1301ab677ff4SHariprasad Shenai 			 struct net_device *dev, unsigned int iqid,
1302ab677ff4SHariprasad Shenai 			 unsigned int uld_type);
1303f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
130452367a76SVipul Pandya int t4_sge_init(struct adapter *adap);
1305f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap);
1306f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap);
1307812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev);
1308812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
13093069ee9bSVipul Pandya extern int dbfifo_int_thresh;
1310f7917c00SJeff Kirsher 
1311f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \
1312f7917c00SJeff Kirsher 	for (iter = 0; iter < (adapter)->params.nports; ++iter)
1313f7917c00SJeff Kirsher 
13149a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap)
13159a4da2cdSVipul Pandya {
13169a4da2cdSVipul Pandya 	return adap->params.bypass;
13179a4da2cdSVipul Pandya }
13189a4da2cdSVipul Pandya 
13199a4da2cdSVipul Pandya static inline int is_bypass_device(int device)
13209a4da2cdSVipul Pandya {
13219a4da2cdSVipul Pandya 	/* this should be set based upon device capabilities */
13229a4da2cdSVipul Pandya 	switch (device) {
13239a4da2cdSVipul Pandya 	case 0x440b:
13249a4da2cdSVipul Pandya 	case 0x440c:
13259a4da2cdSVipul Pandya 		return 1;
13269a4da2cdSVipul Pandya 	default:
13279a4da2cdSVipul Pandya 		return 0;
13289a4da2cdSVipul Pandya 	}
13299a4da2cdSVipul Pandya }
13309a4da2cdSVipul Pandya 
133101b69614SHariprasad Shenai static inline int is_10gbt_device(int device)
133201b69614SHariprasad Shenai {
133301b69614SHariprasad Shenai 	/* this should be set based upon device capabilities */
133401b69614SHariprasad Shenai 	switch (device) {
133501b69614SHariprasad Shenai 	case 0x4409:
133601b69614SHariprasad Shenai 	case 0x4486:
133701b69614SHariprasad Shenai 		return 1;
133801b69614SHariprasad Shenai 
133901b69614SHariprasad Shenai 	default:
134001b69614SHariprasad Shenai 		return 0;
134101b69614SHariprasad Shenai 	}
134201b69614SHariprasad Shenai }
134301b69614SHariprasad Shenai 
1344f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1345f7917c00SJeff Kirsher {
1346f7917c00SJeff Kirsher 	return adap->params.vpd.cclk / 1000;
1347f7917c00SJeff Kirsher }
1348f7917c00SJeff Kirsher 
1349f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1350f7917c00SJeff Kirsher 					    unsigned int us)
1351f7917c00SJeff Kirsher {
1352f7917c00SJeff Kirsher 	return (us * adap->params.vpd.cclk) / 1000;
1353f7917c00SJeff Kirsher }
1354f7917c00SJeff Kirsher 
135552367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
135652367a76SVipul Pandya 					    unsigned int ticks)
135752367a76SVipul Pandya {
135852367a76SVipul Pandya 	/* add Core Clock / 2 to round ticks to nearest uS */
135952367a76SVipul Pandya 	return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
136052367a76SVipul Pandya 		adapter->params.vpd.cclk);
136152367a76SVipul Pandya }
136252367a76SVipul Pandya 
136308c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
136408c4901bSRahul Lakkireddy 					      unsigned int ticks)
136508c4901bSRahul Lakkireddy {
136608c4901bSRahul Lakkireddy 	return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
136708c4901bSRahul Lakkireddy }
136808c4901bSRahul Lakkireddy 
1369f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1370f7917c00SJeff Kirsher 		      u32 val);
1371f7917c00SJeff Kirsher 
137201b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
137301b69614SHariprasad Shenai 			    int size, void *rpl, bool sleep_ok, int timeout);
1374f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1375f7917c00SJeff Kirsher 		    void *rpl, bool sleep_ok);
1376f7917c00SJeff Kirsher 
137701b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
137801b69614SHariprasad Shenai 				     const void *cmd, int size, void *rpl,
137901b69614SHariprasad Shenai 				     int timeout)
138001b69614SHariprasad Shenai {
138101b69614SHariprasad Shenai 	return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
138201b69614SHariprasad Shenai 				       timeout);
138301b69614SHariprasad Shenai }
138401b69614SHariprasad Shenai 
1385f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1386f7917c00SJeff Kirsher 			     int size, void *rpl)
1387f7917c00SJeff Kirsher {
1388f7917c00SJeff Kirsher 	return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1389f7917c00SJeff Kirsher }
1390f7917c00SJeff Kirsher 
1391f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1392f7917c00SJeff Kirsher 				int size, void *rpl)
1393f7917c00SJeff Kirsher {
1394f7917c00SJeff Kirsher 	return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1395f7917c00SJeff Kirsher }
1396f7917c00SJeff Kirsher 
1397fc08a01aSHariprasad Shenai /**
1398fc08a01aSHariprasad Shenai  *	hash_mac_addr - return the hash value of a MAC address
1399fc08a01aSHariprasad Shenai  *	@addr: the 48-bit Ethernet MAC address
1400fc08a01aSHariprasad Shenai  *
1401fc08a01aSHariprasad Shenai  *	Hashes a MAC address according to the hash function used by HW inexact
1402fc08a01aSHariprasad Shenai  *	(hash) address matching.
1403fc08a01aSHariprasad Shenai  */
1404fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr)
1405fc08a01aSHariprasad Shenai {
1406fc08a01aSHariprasad Shenai 	u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1407fc08a01aSHariprasad Shenai 	u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1408fc08a01aSHariprasad Shenai 
1409fc08a01aSHariprasad Shenai 	a ^= b;
1410fc08a01aSHariprasad Shenai 	a ^= (a >> 12);
1411fc08a01aSHariprasad Shenai 	a ^= (a >> 6);
1412fc08a01aSHariprasad Shenai 	return a & 0x3f;
1413fc08a01aSHariprasad Shenai }
1414fc08a01aSHariprasad Shenai 
141594cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
141694cdb8bbSHariprasad Shenai 			       unsigned int cnt);
141794cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
141894cdb8bbSHariprasad Shenai 			     unsigned int us, unsigned int cnt,
141994cdb8bbSHariprasad Shenai 			     unsigned int size, unsigned int iqe_size)
142094cdb8bbSHariprasad Shenai {
142194cdb8bbSHariprasad Shenai 	q->adap = adap;
142294cdb8bbSHariprasad Shenai 	cxgb4_set_rspq_intr_params(q, us, cnt);
142394cdb8bbSHariprasad Shenai 	q->iqe_len = iqe_size;
142494cdb8bbSHariprasad Shenai 	q->size = size;
142594cdb8bbSHariprasad Shenai }
142694cdb8bbSHariprasad Shenai 
142713ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
142813ee15d3SVipul Pandya 		       unsigned int data_reg, const u32 *vals,
142913ee15d3SVipul Pandya 		       unsigned int nregs, unsigned int start_idx);
1430f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1431f2b7e78dSVipul Pandya 		      unsigned int data_reg, u32 *vals, unsigned int nregs,
1432f2b7e78dSVipul Pandya 		      unsigned int start_idx);
14330abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1434f2b7e78dSVipul Pandya 
1435f2b7e78dSVipul Pandya struct fw_filter_wr;
1436f2b7e78dSVipul Pandya 
1437f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter);
1438f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter);
1439f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter);
1440f7917c00SJeff Kirsher 
14418203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs);
14424036da90SHariprasad Shenai int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1443f7917c00SJeff Kirsher 		  struct link_config *lc);
1444f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1445fc5ab020SHariprasad Shenai 
1446b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1447b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap);
1448b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1449b562fc37SHariprasad Shenai 
1450fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE	0
1451fc5ab020SHariprasad Shenai #define T4_MEMORY_READ	1
1452fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1453f01aa633SHariprasad Shenai 		 void *buf, int dir);
1454fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1455fc5ab020SHariprasad Shenai 				  u32 len, __be32 *buf)
1456fc5ab020SHariprasad Shenai {
1457fc5ab020SHariprasad Shenai 	return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1458fc5ab020SHariprasad Shenai }
1459fc5ab020SHariprasad Shenai 
1460812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter);
1461812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1462812034f1SHariprasad Shenai 
1463940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1464f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable);
1465098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1466098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
146749216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr,
146849216c1cSHariprasad Shenai 		  unsigned int nwords, u32 *data, int byte_oriented);
1469f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
147001b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap,
147101b69614SHariprasad Shenai 		   int win, spinlock_t *lock,
147201b69614SHariprasad Shenai 		   int (*phy_fw_version)(const u8 *, size_t),
147301b69614SHariprasad Shenai 		   const u8 *phy_fw_data, size_t phy_fw_size);
147401b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
147549216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
147622c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
147722c0b963SHariprasad Shenai 		  const u8 *fw_data, unsigned int size, int force);
1478acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap);
1479636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1480a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap);
14814da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
148216e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers);
14830de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers);
148416e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1485ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1486760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1487760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1488760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter);
1489760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter);
149016e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
149116e47624SHariprasad Shenai 	       const u8 *fw_data, unsigned int fw_size,
149216e47624SHariprasad Shenai 	       struct fw_hdr *card_fw, enum dev_state state, int *reset);
1493f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter);
14943be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter);
1495e85c9a7aSHariprasad Shenai 
1496e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1497b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter,
1498e85c9a7aSHariprasad Shenai 		      unsigned int qid,
1499e85c9a7aSHariprasad Shenai 		      enum t4_bar2_qtype qtype,
150066cf188eSHariprasad S 		      int user,
1501e85c9a7aSHariprasad Shenai 		      u64 *pbar2_qoffset,
1502e85c9a7aSHariprasad Shenai 		      unsigned int *pbar2_qid);
1503e85c9a7aSHariprasad Shenai 
1504dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap,
1505dc9daab2SHariprasad Shenai 			const struct sge_rspq *q);
1506ae469b68SHariprasad Shenai 
1507ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter);
1508e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter);
15095ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1510dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1511c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox);
1512c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox,
1513c3e324e3SHariprasad Shenai 		     int port, int pf, int vf, u8 mac[]);
1514f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1515f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter);
1516f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1517f7917c00SJeff Kirsher 			int start, int n, const u16 *rspq, unsigned int nrspq);
1518f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1519f7917c00SJeff Kirsher 		       unsigned int flags);
1520c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1521c035e183SHariprasad Shenai 		     unsigned int flags, unsigned int defq);
1522688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries);
15235ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
15245ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
15255ccf9d04SRahul Lakkireddy 		      bool sleep_ok);
1526688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
15275ccf9d04SRahul Lakkireddy 			   u32 *valp, bool sleep_ok);
1528688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
15295ccf9d04SRahul Lakkireddy 			   u32 *vfl, u32 *vfh, bool sleep_ok);
15305ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
15315ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1532688ea5feSHariprasad Shenai 
1533193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1534193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1535b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1536b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1537e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1538e5f0e43bSHariprasad Shenai 		    size_t n);
1539c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1540c778af7dSHariprasad Shenai 		    size_t n);
1541f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1542f1ff24aaSHariprasad Shenai 		unsigned int *valp);
1543f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1544f1ff24aaSHariprasad Shenai 		 const unsigned int *valp);
1545f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
154619689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
154719689609SHariprasad Shenai 			unsigned int *pif_req_wrptr,
154819689609SHariprasad Shenai 			unsigned int *pif_rsp_wrptr);
154926fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
155074b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
155172aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type);
1552f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1553a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx,
1554a4cfd929SHariprasad Shenai 			      struct port_stats *stats,
1555a4cfd929SHariprasad Shenai 			      struct port_stats *offset);
155665046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1557f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1558bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1559636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1560636f9d37SVipul Pandya 			    unsigned int mask, unsigned int val);
15612d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
15625ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
15635ccf9d04SRahul Lakkireddy 			 bool sleep_ok);
15645ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
15655ccf9d04SRahul Lakkireddy 			 bool sleep_ok);
15665ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
15675ccf9d04SRahul Lakkireddy 			  bool sleep_ok);
15685ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
15695ccf9d04SRahul Lakkireddy 		      bool sleep_ok);
1570f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
15715ccf9d04SRahul Lakkireddy 			 struct tp_tcp_stats *v6, bool sleep_ok);
1572a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
15735ccf9d04SRahul Lakkireddy 		       struct tp_fcoe_stats *st, bool sleep_ok);
1574f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1575f7917c00SJeff Kirsher 		  const unsigned short *alpha, const unsigned short *beta);
1576f7917c00SJeff Kirsher 
1577797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1578797ff0f5SHariprasad Shenai 
15797864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1580f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1581f2b7e78dSVipul Pandya 
1582f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1583f7917c00SJeff Kirsher 			 const u8 *addr);
1584f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1585f7917c00SJeff Kirsher 		      u64 mask0, u64 mask1, unsigned int crc, bool enable);
1586f7917c00SJeff Kirsher 
1587f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1588f7917c00SJeff Kirsher 		enum dev_master master, enum dev_state *state);
1589f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1590f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox);
1591f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1592636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1593636f9d37SVipul Pandya 			  unsigned int cache_line_size);
1594636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1595f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1596f7917c00SJeff Kirsher 		    unsigned int vf, unsigned int nparams, const u32 *params,
1597f7917c00SJeff Kirsher 		    u32 *val);
15988f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
15998f46d467SArjun Vynipadath 		       unsigned int vf, unsigned int nparams, const u32 *params,
16008f46d467SArjun Vynipadath 		       u32 *val);
160101b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1602f7917c00SJeff Kirsher 		       unsigned int vf, unsigned int nparams, const u32 *params,
16038f46d467SArjun Vynipadath 		       u32 *val, int rw, bool sleep_ok);
160401b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1605688848b1SAnish Bhatt 			  unsigned int pf, unsigned int vf,
1606688848b1SAnish Bhatt 			  unsigned int nparams, const u32 *params,
160701b69614SHariprasad Shenai 			  const u32 *val, int timeout);
160801b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
160901b69614SHariprasad Shenai 		  unsigned int vf, unsigned int nparams, const u32 *params,
1610688848b1SAnish Bhatt 		  const u32 *val);
1611f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1612f7917c00SJeff Kirsher 		unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1613f7917c00SJeff Kirsher 		unsigned int rxqi, unsigned int rxq, unsigned int tc,
1614f7917c00SJeff Kirsher 		unsigned int vi, unsigned int cmask, unsigned int pmask,
1615f7917c00SJeff Kirsher 		unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1616f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1617f7917c00SJeff Kirsher 		unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1618f7917c00SJeff Kirsher 		unsigned int *rss_size);
16194f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox,
16204f3a0fcfSHariprasad Shenai 	       unsigned int pf, unsigned int vf,
16214f3a0fcfSHariprasad Shenai 	       unsigned int viid);
1622f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1623f7917c00SJeff Kirsher 		int mtu, int promisc, int all_multi, int bcast, int vlanex,
1624f7917c00SJeff Kirsher 		bool sleep_ok);
1625f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1626f7917c00SJeff Kirsher 		      unsigned int viid, bool free, unsigned int naddr,
1627f7917c00SJeff Kirsher 		      const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1628fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1629fc08a01aSHariprasad Shenai 		     unsigned int viid, unsigned int naddr,
1630fc08a01aSHariprasad Shenai 		     const u8 **addr, bool sleep_ok);
1631f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1632f7917c00SJeff Kirsher 		  int idx, const u8 *addr, bool persist, bool add_smt);
1633f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1634f7917c00SJeff Kirsher 		     bool ucast, u64 vec, bool sleep_ok);
1635688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1636688848b1SAnish Bhatt 			unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1637f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1638f7917c00SJeff Kirsher 		 bool rx_en, bool tx_en);
1639f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1640f7917c00SJeff Kirsher 		     unsigned int nblinks);
1641f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1642f7917c00SJeff Kirsher 	       unsigned int mmd, unsigned int reg, u16 *valp);
1643f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1644f7917c00SJeff Kirsher 	       unsigned int mmd, unsigned int reg, u16 val);
1645ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1646ebf4dc2bSHariprasad Shenai 	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
1647ebf4dc2bSHariprasad Shenai 	       unsigned int fl0id, unsigned int fl1id);
1648f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1649f7917c00SJeff Kirsher 	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
1650f7917c00SJeff Kirsher 	       unsigned int fl0id, unsigned int fl1id);
1651f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1652f7917c00SJeff Kirsher 		   unsigned int vf, unsigned int eqid);
1653f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1654f7917c00SJeff Kirsher 		    unsigned int vf, unsigned int eqid);
1655f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1656f7917c00SJeff Kirsher 		    unsigned int vf, unsigned int eqid);
16575d700ecbSHariprasad Shenai int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
165823853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
16592061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi);
1660c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1661c3168cabSGanesh Goudar 		       unsigned int *speedp, unsigned int *mtup);
1662f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1663881806bcSVipul Pandya void t4_db_full(struct adapter *adapter);
1664881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter);
16658e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
16668e3d04fdSHariprasad Shenai 			int filter_index, int enable);
16678e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
16688e3d04fdSHariprasad Shenai 			 int filter_index, int *enabled);
16698caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
16708caa1e84SVipul Pandya 			 u32 addr, u32 val);
167108c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
167208c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
167308c4901bSRahul Lakkireddy 		     unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
16749e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
16759e5c598cSRahul Lakkireddy 		   enum ctxt_type ctype, u32 *data);
16769e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
16779e5c598cSRahul Lakkireddy 		      enum ctxt_type ctype, u32 *data);
1678b72a32daSRahul Lakkireddy int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1679b72a32daSRahul Lakkireddy 		    int rateunit, int ratemode, int channel, int class,
1680b72a32daSRahul Lakkireddy 		    int minrate, int maxrate, int weight, int pktsize);
168168bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1682a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter,
1683a3bfb617SHariprasad Shenai 			  struct sge_idma_monitor_state *idma);
1684a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter,
1685a3bfb617SHariprasad Shenai 		     struct sge_idma_monitor_state *idma,
1686a3bfb617SHariprasad Shenai 		     int hz, int ticks);
1687858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1688858aa65cSHariprasad Shenai 		      unsigned int naddr, u8 *addr);
16895ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
16905ccf9d04SRahul Lakkireddy 		    u32 start_index, bool sleep_ok);
16914359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
16924359cf33SRahul Lakkireddy 		       u32 start_index, bool sleep_ok);
16935ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
16945ccf9d04SRahul Lakkireddy 		    u32 start_index, bool sleep_ok);
16955ccf9d04SRahul Lakkireddy 
16960fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap);
16970fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap);
16980fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap);
16990fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void);
170094cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1701ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1702ab677ff4SHariprasad Shenai 		  unsigned int n, bool unmap);
1703ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q);
1704f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */
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