1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 490eb71a9dSNeilBrown #include <linux/rhashtable.h> 50098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 515e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 52a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 53a4569504SAtul Gupta #include <linux/ptp_classify.h> 541dde532dSRahul Lakkireddy #include <linux/crash_dump.h> 55b1871915SGanesh Goudar #include <linux/thermal.h> 56f7917c00SJeff Kirsher #include <asm/io.h> 5727999805SHariprasad S #include "t4_chip_type.h" 58f7917c00SJeff Kirsher #include "cxgb4_uld.h" 59c2193999SShahjada Abul Husain #include "t4fw_api.h" 60f7917c00SJeff Kirsher 613069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 6294cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 6393a09e74SPotnuri Bharat Teja extern struct list_head uld_list; 6494cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 653069ee9bSVipul Pandya 66a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 67a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 68a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 69a6ec572bSAtul Gupta */ 70a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 71a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 72a6ec572bSAtul Gupta 73c2193999SShahjada Abul Husain #define FW_PARAM_DEV(param) \ 74c2193999SShahjada Abul Husain (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 75c2193999SShahjada Abul Husain FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 76c2193999SShahjada Abul Husain 77c2193999SShahjada Abul Husain #define FW_PARAM_PFVF(param) \ 78c2193999SShahjada Abul Husain (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 79c2193999SShahjada Abul Husain FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 80c2193999SShahjada Abul Husain FW_PARAMS_PARAM_Y_V(0) | \ 81c2193999SShahjada Abul Husain FW_PARAMS_PARAM_Z_V(0)) 82c2193999SShahjada Abul Husain 83f7917c00SJeff Kirsher enum { 84f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 85f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 86f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 87f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 88a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 89098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 90f7917c00SJeff Kirsher }; 91f7917c00SJeff Kirsher 92f7917c00SJeff Kirsher enum { 93812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 94812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 95812034f1SHariprasad Shenai }; 96812034f1SHariprasad Shenai 97812034f1SHariprasad Shenai enum { 98f7917c00SJeff Kirsher MEM_EDC0, 99f7917c00SJeff Kirsher MEM_EDC1, 1002422d9a3SSantosh Rastapur MEM_MC, 1012422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 1024db0401fSRahul Lakkireddy MEM_MC1, 1034db0401fSRahul Lakkireddy MEM_HMA, 104f7917c00SJeff Kirsher }; 105f7917c00SJeff Kirsher 1063069ee9bSVipul Pandya enum { 1073eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 1083eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 1093069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 1103069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 1112422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 1123eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 1133eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 1140abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 1150abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1163069ee9bSVipul Pandya }; 1173069ee9bSVipul Pandya 118f7917c00SJeff Kirsher enum dev_master { 119f7917c00SJeff Kirsher MASTER_CANT, 120f7917c00SJeff Kirsher MASTER_MAY, 121f7917c00SJeff Kirsher MASTER_MUST 122f7917c00SJeff Kirsher }; 123f7917c00SJeff Kirsher 124f7917c00SJeff Kirsher enum dev_state { 125f7917c00SJeff Kirsher DEV_STATE_UNINIT, 126f7917c00SJeff Kirsher DEV_STATE_INIT, 127f7917c00SJeff Kirsher DEV_STATE_ERR 128f7917c00SJeff Kirsher }; 129f7917c00SJeff Kirsher 130c3168cabSGanesh Goudar enum cc_pause { 131f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 132f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 133f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 134f7917c00SJeff Kirsher }; 135f7917c00SJeff Kirsher 136c3168cabSGanesh Goudar enum cc_fec { 1373bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1383bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1393bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1403bb4858fSGanesh Goudar }; 1413bb4858fSGanesh Goudar 1423893c905SVishal Kulkarni enum { 1433893c905SVishal Kulkarni CXGB4_ETHTOOL_FLASH_FW = 1, 1443893c905SVishal Kulkarni }; 1453893c905SVishal Kulkarni 146f7917c00SJeff Kirsher struct port_stats { 147f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 148f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 149f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 150f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 151f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 152f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 153f7917c00SJeff Kirsher 154f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 155f7917c00SJeff Kirsher u64 tx_frames_65_127; 156f7917c00SJeff Kirsher u64 tx_frames_128_255; 157f7917c00SJeff Kirsher u64 tx_frames_256_511; 158f7917c00SJeff Kirsher u64 tx_frames_512_1023; 159f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 160f7917c00SJeff Kirsher u64 tx_frames_1519_max; 161f7917c00SJeff Kirsher 162f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 163f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 164f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 165f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 166f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 167f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 168f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 169f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 170f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 171f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 172f7917c00SJeff Kirsher 173f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 174f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 175f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 176f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 177f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 178f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 179f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 180f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 181f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 182f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 183f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 184f7917c00SJeff Kirsher 185f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 186f7917c00SJeff Kirsher u64 rx_frames_65_127; 187f7917c00SJeff Kirsher u64 rx_frames_128_255; 188f7917c00SJeff Kirsher u64 rx_frames_256_511; 189f7917c00SJeff Kirsher u64 rx_frames_512_1023; 190f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 191f7917c00SJeff Kirsher u64 rx_frames_1519_max; 192f7917c00SJeff Kirsher 193f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 194f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 195f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 196f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 197f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 198f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 199f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 200f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 201f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 202f7917c00SJeff Kirsher 203f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 204f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 205f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 206f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 207f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 208f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 209f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 210f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 211f7917c00SJeff Kirsher }; 212f7917c00SJeff Kirsher 213f7917c00SJeff Kirsher struct lb_port_stats { 214f7917c00SJeff Kirsher u64 octets; 215f7917c00SJeff Kirsher u64 frames; 216f7917c00SJeff Kirsher u64 bcast_frames; 217f7917c00SJeff Kirsher u64 mcast_frames; 218f7917c00SJeff Kirsher u64 ucast_frames; 219f7917c00SJeff Kirsher u64 error_frames; 220f7917c00SJeff Kirsher 221f7917c00SJeff Kirsher u64 frames_64; 222f7917c00SJeff Kirsher u64 frames_65_127; 223f7917c00SJeff Kirsher u64 frames_128_255; 224f7917c00SJeff Kirsher u64 frames_256_511; 225f7917c00SJeff Kirsher u64 frames_512_1023; 226f7917c00SJeff Kirsher u64 frames_1024_1518; 227f7917c00SJeff Kirsher u64 frames_1519_max; 228f7917c00SJeff Kirsher 229f7917c00SJeff Kirsher u64 drop; 230f7917c00SJeff Kirsher 231f7917c00SJeff Kirsher u64 ovflow0; 232f7917c00SJeff Kirsher u64 ovflow1; 233f7917c00SJeff Kirsher u64 ovflow2; 234f7917c00SJeff Kirsher u64 ovflow3; 235f7917c00SJeff Kirsher u64 trunc0; 236f7917c00SJeff Kirsher u64 trunc1; 237f7917c00SJeff Kirsher u64 trunc2; 238f7917c00SJeff Kirsher u64 trunc3; 239f7917c00SJeff Kirsher }; 240f7917c00SJeff Kirsher 241f7917c00SJeff Kirsher struct tp_tcp_stats { 242a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 243a4cfd929SHariprasad Shenai u64 tcp_in_segs; 244a4cfd929SHariprasad Shenai u64 tcp_out_segs; 245a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 246a4cfd929SHariprasad Shenai }; 247a4cfd929SHariprasad Shenai 248a4cfd929SHariprasad Shenai struct tp_usm_stats { 249a4cfd929SHariprasad Shenai u32 frames; 250a4cfd929SHariprasad Shenai u32 drops; 251a4cfd929SHariprasad Shenai u64 octets; 252f7917c00SJeff Kirsher }; 253f7917c00SJeff Kirsher 254a6222975SHariprasad Shenai struct tp_fcoe_stats { 255a6222975SHariprasad Shenai u32 frames_ddp; 256a6222975SHariprasad Shenai u32 frames_drop; 257a6222975SHariprasad Shenai u64 octets_ddp; 258f7917c00SJeff Kirsher }; 259f7917c00SJeff Kirsher 260f7917c00SJeff Kirsher struct tp_err_stats { 261a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 262a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 263a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 264a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 265a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 266a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 267a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 268a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 269a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 270a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 271a4cfd929SHariprasad Shenai }; 272a4cfd929SHariprasad Shenai 273a6222975SHariprasad Shenai struct tp_cpl_stats { 274a6222975SHariprasad Shenai u32 req[4]; 275a6222975SHariprasad Shenai u32 rsp[4]; 276a6222975SHariprasad Shenai }; 277a6222975SHariprasad Shenai 278a4cfd929SHariprasad Shenai struct tp_rdma_stats { 279a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 280a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 281f7917c00SJeff Kirsher }; 282f7917c00SJeff Kirsher 283e85c9a7aSHariprasad Shenai struct sge_params { 284e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 285e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 286e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 287e85c9a7aSHariprasad Shenai }; 288e85c9a7aSHariprasad Shenai 289f7917c00SJeff Kirsher struct tp_params { 290f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2912d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 292dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 293dca4faebSVipul Pandya /* channel map */ 294636f9d37SVipul Pandya 295636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 296636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 297dcf7b6f5SKumar Sanghvi 298dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 299dcf10ec7SRaju Rangoju u32 filter_mask; 300dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 301dcf7b6f5SKumar Sanghvi 3028eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 3038eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 3048eb9f2f9SArjun V */ 3058eb9f2f9SArjun V int rx_pkt_encap; 3068eb9f2f9SArjun V 307dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 308dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 309dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 310dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 311dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 312dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 313dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 314dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 315dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 316dcf7b6f5SKumar Sanghvi * present. 317dcf7b6f5SKumar Sanghvi */ 3180ba9a3b6SKumar Sanghvi int fcoe_shift; 319dcf7b6f5SKumar Sanghvi int port_shift; 3200ba9a3b6SKumar Sanghvi int vnic_shift; 3210ba9a3b6SKumar Sanghvi int vlan_shift; 3220ba9a3b6SKumar Sanghvi int tos_shift; 323dcf7b6f5SKumar Sanghvi int protocol_shift; 3240ba9a3b6SKumar Sanghvi int ethertype_shift; 3250ba9a3b6SKumar Sanghvi int macmatch_shift; 3260ba9a3b6SKumar Sanghvi int matchtype_shift; 3270ba9a3b6SKumar Sanghvi int frag_shift; 3280ba9a3b6SKumar Sanghvi 3290ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 330f7917c00SJeff Kirsher }; 331f7917c00SJeff Kirsher 332f7917c00SJeff Kirsher struct vpd_params { 333f7917c00SJeff Kirsher unsigned int cclk; 334f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 335f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 336f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 337a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 338098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 339f7917c00SJeff Kirsher }; 340f7917c00SJeff Kirsher 3410eaec62aSCasey Leedom /* Maximum resources provisioned for a PCI PF. 3420eaec62aSCasey Leedom */ 3430eaec62aSCasey Leedom struct pf_resources { 3440eaec62aSCasey Leedom unsigned int nvi; /* N virtual interfaces */ 3450eaec62aSCasey Leedom unsigned int neq; /* N egress Qs */ 3460eaec62aSCasey Leedom unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 3470eaec62aSCasey Leedom unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 3480eaec62aSCasey Leedom unsigned int niq; /* N ingress Qs */ 3490eaec62aSCasey Leedom unsigned int tc; /* PCI-E traffic class */ 3500eaec62aSCasey Leedom unsigned int pmask; /* port access rights mask */ 3510eaec62aSCasey Leedom unsigned int nexactf; /* N exact MPS filters */ 3520eaec62aSCasey Leedom unsigned int r_caps; /* read capabilities */ 3530eaec62aSCasey Leedom unsigned int wx_caps; /* write/execute capabilities */ 3540eaec62aSCasey Leedom }; 3550eaec62aSCasey Leedom 356f7917c00SJeff Kirsher struct pci_params { 357baf50868SGanesh Goudar unsigned int vpd_cap_addr; 358f7917c00SJeff Kirsher unsigned char speed; 359f7917c00SJeff Kirsher unsigned char width; 360f7917c00SJeff Kirsher }; 361f7917c00SJeff Kirsher 36249aa284fSHariprasad Shenai struct devlog_params { 36349aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 36449aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 36549aa284fSHariprasad Shenai u32 size; /* size of log */ 36649aa284fSHariprasad Shenai }; 36749aa284fSHariprasad Shenai 3683ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 3693ccc6cf7SHariprasad Shenai struct arch_specific_params { 3703ccc6cf7SHariprasad Shenai u8 nchan; 37144588560SHariprasad Shenai u8 pm_stats_cnt; 3722216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 3733ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 3743ccc6cf7SHariprasad Shenai u16 vfcount; 3753ccc6cf7SHariprasad Shenai u32 sge_fl_db; 3763ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 3773ccc6cf7SHariprasad Shenai }; 3783ccc6cf7SHariprasad Shenai 379f7917c00SJeff Kirsher struct adapter_params { 380e85c9a7aSHariprasad Shenai struct sge_params sge; 381f7917c00SJeff Kirsher struct tp_params tp; 382f7917c00SJeff Kirsher struct vpd_params vpd; 3830eaec62aSCasey Leedom struct pf_resources pfres; 384f7917c00SJeff Kirsher struct pci_params pci; 38549aa284fSHariprasad Shenai struct devlog_params devlog; 38649aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 387f7917c00SJeff Kirsher 388f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 389f1ff24aaSHariprasad Shenai 390f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 391f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 392f7917c00SJeff Kirsher 393760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 3940de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 395760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 3960de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 397760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 398760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 399f7917c00SJeff Kirsher u8 api_vers[7]; 400f7917c00SJeff Kirsher 401f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 402f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 403f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 404f7917c00SJeff Kirsher 405f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 406f7917c00SJeff Kirsher unsigned char portvec; 407d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 4083ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 409f7917c00SJeff Kirsher unsigned char offload; 41094cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 411ab0367eaSRahul Lakkireddy unsigned char ethofld; /* QoS support */ 412f7917c00SJeff Kirsher 4139a4da2cdSVipul Pandya unsigned char bypass; 4145c31254eSKumar Sanghvi unsigned char hash_filter; 4159a4da2cdSVipul Pandya 416f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 4171ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 4184c2c5763SHariprasad Shenai 419b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 4204c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 4214c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 422086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 423c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 4240ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 42502d805dcSSantosh Rastapur unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 4268f46d467SArjun Vynipadath 4278f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 4288f46d467SArjun Vynipadath * used by the Port 4298f46d467SArjun Vynipadath */ 4308f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 43143db9296SRaju Rangoju bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 432f3910c62SRaju Rangoju bool write_cmpl_support; /* FW supports WRITE_CMPL */ 433f7917c00SJeff Kirsher }; 434f7917c00SJeff Kirsher 435a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 436a3bfb617SHariprasad Shenai * and possible hangs. 437a3bfb617SHariprasad Shenai */ 438a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 439a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 440a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 441a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 442a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 443a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 444a3bfb617SHariprasad Shenai }; 445a3bfb617SHariprasad Shenai 4467f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 4477f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 4487f080c3fSHariprasad Shenai * error returns. 4497f080c3fSHariprasad Shenai */ 4507f080c3fSHariprasad Shenai struct mbox_cmd { 4517f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 4527f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 4537f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 4547f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 4557f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 4567f080c3fSHariprasad Shenai }; 4577f080c3fSHariprasad Shenai 4587f080c3fSHariprasad Shenai struct mbox_cmd_log { 4597f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 4607f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 4617f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 4627f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 4637f080c3fSHariprasad Shenai }; 4647f080c3fSHariprasad Shenai 4657f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 4667f080c3fSHariprasad Shenai * return a pointer to the specified entry. 4677f080c3fSHariprasad Shenai */ 4687f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 4697f080c3fSHariprasad Shenai unsigned int entry_idx) 4707f080c3fSHariprasad Shenai { 4717f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 4727f080c3fSHariprasad Shenai } 4737f080c3fSHariprasad Shenai 47416e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 475b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 476b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 477b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 478b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 47916e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 48016e47624SHariprasad Shenai 48116e47624SHariprasad Shenai struct fw_info { 48216e47624SHariprasad Shenai u8 chip; 48316e47624SHariprasad Shenai char *fs_name; 48416e47624SHariprasad Shenai char *fw_mod_name; 48516e47624SHariprasad Shenai struct fw_hdr fw_hdr; 48616e47624SHariprasad Shenai }; 48716e47624SHariprasad Shenai 488f7917c00SJeff Kirsher struct trace_params { 489f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 490f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 491f7917c00SJeff Kirsher unsigned short snap_len; 492f7917c00SJeff Kirsher unsigned short min_len; 493f7917c00SJeff Kirsher unsigned char skip_ofst; 494f7917c00SJeff Kirsher unsigned char skip_len; 495f7917c00SJeff Kirsher unsigned char invert; 496f7917c00SJeff Kirsher unsigned char port; 497f7917c00SJeff Kirsher }; 498f7917c00SJeff Kirsher 4993893c905SVishal Kulkarni struct cxgb4_fw_data { 5003893c905SVishal Kulkarni __be32 signature; 5013893c905SVishal Kulkarni __u8 reserved[4]; 5023893c905SVishal Kulkarni }; 5033893c905SVishal Kulkarni 504c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 505c3168cabSGanesh Goudar 506c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 507c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 508c3168cabSGanesh Goudar 509c3168cabSGanesh Goudar enum fw_caps { 510c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 511c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 512c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 513c3168cabSGanesh Goudar }; 514c3168cabSGanesh Goudar 515f7917c00SJeff Kirsher struct link_config { 516c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 517c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 518c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 519c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 520c3168cabSGanesh Goudar 521c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 522c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 523c3168cabSGanesh Goudar 524c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 525c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 5260caeaf6aSRahul Lakkireddy enum cc_pause advertised_fc; /* actual advertised flow control */ 527c3168cabSGanesh Goudar 528c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 529c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 530c3168cabSGanesh Goudar 531f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 532c3168cabSGanesh Goudar 533f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 534ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 5358156b0baSGanesh Goudar 5368156b0baSGanesh Goudar bool new_module; /* ->OS Transceiver Module inserted */ 5378156b0baSGanesh Goudar bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 538f7917c00SJeff Kirsher }; 539f7917c00SJeff Kirsher 540e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 541f7917c00SJeff Kirsher 542f7917c00SJeff Kirsher enum { 543f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 544f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 545f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 546f7917c00SJeff Kirsher }; 547f7917c00SJeff Kirsher 548f7917c00SJeff Kirsher enum { 549812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 550812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 551812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 552812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 553812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 554812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 555812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 556812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 557812034f1SHariprasad Shenai }; 558812034f1SHariprasad Shenai 559812034f1SHariprasad Shenai enum { 56068ddc82aSRahul Lakkireddy MAX_TXQ_DESC_SIZE = 64, 56168ddc82aSRahul Lakkireddy MAX_RXQ_DESC_SIZE = 128, 56268ddc82aSRahul Lakkireddy MAX_FL_DESC_SIZE = 8, 56368ddc82aSRahul Lakkireddy MAX_CTRL_TXQ_DESC_SIZE = 64, 56468ddc82aSRahul Lakkireddy }; 56568ddc82aSRahul Lakkireddy 56668ddc82aSRahul Lakkireddy enum { 567cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 568cf38be6dSHariprasad Shenai /* forwarded interrupts */ 5690fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 570f7917c00SJeff Kirsher }; 571f7917c00SJeff Kirsher 572d5fbda61SArjun Vynipadath enum { 573d5fbda61SArjun Vynipadath PRIV_FLAG_PORT_TX_VM_BIT, 574d5fbda61SArjun Vynipadath }; 575d5fbda61SArjun Vynipadath 576d5fbda61SArjun Vynipadath #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 577d5fbda61SArjun Vynipadath 578d5fbda61SArjun Vynipadath #define PRIV_FLAGS_ADAP 0 579d5fbda61SArjun Vynipadath #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 580d5fbda61SArjun Vynipadath 581f7917c00SJeff Kirsher struct adapter; 582f7917c00SJeff Kirsher struct sge_rspq; 583f7917c00SJeff Kirsher 584688848b1SAnish Bhatt #include "cxgb4_dcb.h" 585688848b1SAnish Bhatt 58676fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 58776fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 58876fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 58976fed8a9SVarun Prakash 590f7917c00SJeff Kirsher struct port_info { 591f7917c00SJeff Kirsher struct adapter *adapter; 592f7917c00SJeff Kirsher u16 viid; 5933f8cfd0dSArjun Vynipadath int xact_addr_filt; /* index of exact MAC address filter */ 594f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 595f7917c00SJeff Kirsher s8 mdio_addr; 59640e9de4bSHariprasad Shenai enum fw_port_type port_type; 597f7917c00SJeff Kirsher u8 mod_type; 598f7917c00SJeff Kirsher u8 port_id; 599f7917c00SJeff Kirsher u8 tx_chan; 600f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 601f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 602f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 603f7917c00SJeff Kirsher u8 rss_mode; 604f7917c00SJeff Kirsher struct link_config link_cfg; 605f7917c00SJeff Kirsher u16 *rss; 606a4cfd929SHariprasad Shenai struct port_stats stats_base; 607688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 608688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 609688848b1SAnish Bhatt #endif 61076fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 61176fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 61276fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 6135e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 6145e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 615a4569504SAtul Gupta bool ptp_enable; 616b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 617d5fbda61SArjun Vynipadath u32 eth_flags; 61802d805dcSSantosh Rastapur 61902d805dcSSantosh Rastapur /* viid and smt fields either returned by fw 62002d805dcSSantosh Rastapur * or decoded by parsing viid by driver. 62102d805dcSSantosh Rastapur */ 62202d805dcSSantosh Rastapur u8 vin; 62302d805dcSSantosh Rastapur u8 vivld; 62402d805dcSSantosh Rastapur u8 smt_idx; 62574dd5aa1SVishal Kulkarni u8 rx_cchan; 6264ec4762dSRahul Lakkireddy 6274ec4762dSRahul Lakkireddy bool tc_block_shared; 628f7917c00SJeff Kirsher }; 629f7917c00SJeff Kirsher 630f7917c00SJeff Kirsher struct dentry; 631f7917c00SJeff Kirsher struct work_struct; 632f7917c00SJeff Kirsher 633f7917c00SJeff Kirsher enum { /* adapter flags */ 63480f61f19SArjun Vynipadath CXGB4_FULL_INIT_DONE = (1 << 0), 63580f61f19SArjun Vynipadath CXGB4_DEV_ENABLED = (1 << 1), 63680f61f19SArjun Vynipadath CXGB4_USING_MSI = (1 << 2), 63780f61f19SArjun Vynipadath CXGB4_USING_MSIX = (1 << 3), 63880f61f19SArjun Vynipadath CXGB4_FW_OK = (1 << 4), 63980f61f19SArjun Vynipadath CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 64080f61f19SArjun Vynipadath CXGB4_USING_SOFT_PARAMS = (1 << 6), 64180f61f19SArjun Vynipadath CXGB4_MASTER_PF = (1 << 7), 64280f61f19SArjun Vynipadath CXGB4_FW_OFLD_CONN = (1 << 9), 64380f61f19SArjun Vynipadath CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 64480f61f19SArjun Vynipadath CXGB4_SHUTTING_DOWN = (1 << 11), 64580f61f19SArjun Vynipadath CXGB4_SGE_DBQ_TIMER = (1 << 12), 646f7917c00SJeff Kirsher }; 647f7917c00SJeff Kirsher 64894cdb8bbSHariprasad Shenai enum { 64994cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 650a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 65134aba2c4SRohit Maheshwari ULP_CRYPTO_KTLS_INLINE = 1 << 3, 65294cdb8bbSHariprasad Shenai }; 65394cdb8bbSHariprasad Shenai 654f7917c00SJeff Kirsher struct rx_sw_desc; 655f7917c00SJeff Kirsher 656f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 657f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 658f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 659f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 660f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 661f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 662f7917c00SJeff Kirsher unsigned long large_alloc_failed; 66370055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 66470055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 665f7917c00SJeff Kirsher unsigned long starving; 666f7917c00SJeff Kirsher /* RO fields */ 667f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 668f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 669f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 670f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 671f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 672df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 673df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 674f7917c00SJeff Kirsher }; 675f7917c00SJeff Kirsher 676f7917c00SJeff Kirsher /* A packet gather list */ 677f7917c00SJeff Kirsher struct pkt_gl { 6785e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 679e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 680f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 681f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 682f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 683f7917c00SJeff Kirsher }; 684f7917c00SJeff Kirsher 685f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 686f7917c00SJeff Kirsher const struct pkt_gl *gl); 6872337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 6882337ba42SVarun Prakash /* LRO related declarations for ULD */ 6892337ba42SVarun Prakash struct t4_lro_mgr { 6902337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 6912337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 6922337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 6932337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 6942337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 6952337ba42SVarun Prakash }; 696f7917c00SJeff Kirsher 697f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 698f7917c00SJeff Kirsher struct napi_struct napi; 699f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 700f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 701f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 702f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 703f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 704e553ec3fSHariprasad Shenai u8 adaptive_rx; 705f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 706f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 707f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 708f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 709f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 710f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 711f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 712f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 713df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 714df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 715f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 716f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 717f7917c00SJeff Kirsher struct adapter *adap; 718f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 719f7917c00SJeff Kirsher rspq_handler_t handler; 7202337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 7212337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 722f7917c00SJeff Kirsher }; 723f7917c00SJeff Kirsher 724f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 725f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 726f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 727f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 728f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 729f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 730f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 731992bea8eSGanesh Goudar unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 732f7917c00SJeff Kirsher }; 733f7917c00SJeff Kirsher 734f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 735f7917c00SJeff Kirsher struct sge_rspq rspq; 736f7917c00SJeff Kirsher struct sge_fl fl; 737f7917c00SJeff Kirsher struct sge_eth_stats stats; 73876c3a552SRahul Lakkireddy struct msix_info *msix; 739f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 740f7917c00SJeff Kirsher 741f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 742f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 743f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 744f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 745f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 746f7917c00SJeff Kirsher }; 747f7917c00SJeff Kirsher 748f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 749f7917c00SJeff Kirsher struct sge_rspq rspq; 750f7917c00SJeff Kirsher struct sge_fl fl; 751f7917c00SJeff Kirsher struct sge_ofld_stats stats; 75276c3a552SRahul Lakkireddy struct msix_info *msix; 753f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 754f7917c00SJeff Kirsher 755f7917c00SJeff Kirsher struct tx_desc { 756f7917c00SJeff Kirsher __be64 flit[8]; 757f7917c00SJeff Kirsher }; 758f7917c00SJeff Kirsher 7590ed96b46SRahul Lakkireddy struct ulptx_sgl; 7600ed96b46SRahul Lakkireddy 7610ed96b46SRahul Lakkireddy struct tx_sw_desc { 7620ed96b46SRahul Lakkireddy struct sk_buff *skb; /* SKB to free after getting completion */ 7630ed96b46SRahul Lakkireddy dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 7640ed96b46SRahul Lakkireddy }; 765f7917c00SJeff Kirsher 766f7917c00SJeff Kirsher struct sge_txq { 767f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 768ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 769f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 770f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 771f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 772f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 773f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 774f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 775f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 776f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 777f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 778f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 7793069ee9bSVipul Pandya spinlock_t db_lock; 7803069ee9bSVipul Pandya int db_disabled; 7813069ee9bSVipul Pandya unsigned short db_pidx; 78205eb2389SSteve Wise unsigned short db_pidx_inc; 783df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 784df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 785f7917c00SJeff Kirsher }; 786f7917c00SJeff Kirsher 787f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 788f7917c00SJeff Kirsher struct sge_txq q; 789f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 79010b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 79110b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 79210b00466SAnish Bhatt #endif 793d429005fSVishal Kulkarni u8 dbqt; /* SGE Doorbell Queue Timer in use */ 794d429005fSVishal Kulkarni unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 795f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 7961a2a14fbSRahul Lakkireddy unsigned long uso; /* # of USO requests */ 797f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 798f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 799f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 800f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 801f7917c00SJeff Kirsher 802ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 803f7917c00SJeff Kirsher struct sge_txq q; 804f7917c00SJeff Kirsher struct adapter *adap; 805f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 806f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 807126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 808f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 809f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 810f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 811f7917c00SJeff Kirsher 812f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 813f7917c00SJeff Kirsher struct sge_txq q; 814f7917c00SJeff Kirsher struct adapter *adap; 815f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 816f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 817f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 818f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 819f7917c00SJeff Kirsher 82094cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 82194cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 82294cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 82394cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 82494cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 82594cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 82694cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 82794cdb8bbSHariprasad Shenai }; 82894cdb8bbSHariprasad Shenai 829ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 830ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 831ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 832ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 833ab677ff4SHariprasad Shenai }; 834ab677ff4SHariprasad Shenai 83593a09e74SPotnuri Bharat Teja /* struct to maintain ULD list to reallocate ULD resources on hotplug */ 83693a09e74SPotnuri Bharat Teja struct cxgb4_uld_list { 83793a09e74SPotnuri Bharat Teja struct cxgb4_uld_info uld_info; 83893a09e74SPotnuri Bharat Teja struct list_head list_node; 83993a09e74SPotnuri Bharat Teja enum cxgb4_uld uld_type; 84093a09e74SPotnuri Bharat Teja }; 84193a09e74SPotnuri Bharat Teja 842b1396c2bSRahul Lakkireddy enum sge_eosw_state { 843b1396c2bSRahul Lakkireddy CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 8440e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 8450e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 8464846d533SRahul Lakkireddy CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 8470e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 8480e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 849b1396c2bSRahul Lakkireddy }; 850b1396c2bSRahul Lakkireddy 851b1396c2bSRahul Lakkireddy struct sge_eosw_txq { 852b1396c2bSRahul Lakkireddy spinlock_t lock; /* Per queue lock to synchronize completions */ 853b1396c2bSRahul Lakkireddy enum sge_eosw_state state; /* Current ETHOFLD State */ 8540ed96b46SRahul Lakkireddy struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ 855b1396c2bSRahul Lakkireddy u32 ndesc; /* Number of descriptors */ 856b1396c2bSRahul Lakkireddy u32 pidx; /* Current Producer Index */ 857b1396c2bSRahul Lakkireddy u32 last_pidx; /* Last successfully transmitted Producer Index */ 858b1396c2bSRahul Lakkireddy u32 cidx; /* Current Consumer Index */ 859b1396c2bSRahul Lakkireddy u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 8600e395b3cSRahul Lakkireddy u32 flowc_idx; /* Descriptor containing a FLOWC request */ 861b1396c2bSRahul Lakkireddy u32 inuse; /* Number of packets held in ring */ 862b1396c2bSRahul Lakkireddy 863b1396c2bSRahul Lakkireddy u32 cred; /* Current available credits */ 864b1396c2bSRahul Lakkireddy u32 ncompl; /* # of completions posted */ 865b1396c2bSRahul Lakkireddy u32 last_compl; /* # of credits consumed since last completion req */ 866b1396c2bSRahul Lakkireddy 867b1396c2bSRahul Lakkireddy u32 eotid; /* Index into EOTID table in software */ 868b1396c2bSRahul Lakkireddy u32 hwtid; /* Hardware EOTID index */ 869b1396c2bSRahul Lakkireddy 870b1396c2bSRahul Lakkireddy u32 hwqid; /* Underlying hardware queue index */ 871b1396c2bSRahul Lakkireddy struct net_device *netdev; /* Pointer to netdevice */ 872b1396c2bSRahul Lakkireddy struct tasklet_struct qresume_tsk; /* Restarts the queue */ 8730e395b3cSRahul Lakkireddy struct completion completion; /* completion for FLOWC rendezvous */ 874b1396c2bSRahul Lakkireddy }; 875b1396c2bSRahul Lakkireddy 8762d0cb84dSRahul Lakkireddy struct sge_eohw_txq { 8772d0cb84dSRahul Lakkireddy spinlock_t lock; /* Per queue lock */ 8782d0cb84dSRahul Lakkireddy struct sge_txq q; /* HW Txq */ 8792d0cb84dSRahul Lakkireddy struct adapter *adap; /* Backpointer to adapter */ 8802d0cb84dSRahul Lakkireddy unsigned long tso; /* # of TSO requests */ 8818311f0beSRahul Lakkireddy unsigned long uso; /* # of USO requests */ 8822d0cb84dSRahul Lakkireddy unsigned long tx_cso; /* # of Tx checksum offloads */ 8832d0cb84dSRahul Lakkireddy unsigned long vlan_ins; /* # of Tx VLAN insertions */ 8842d0cb84dSRahul Lakkireddy unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 8852d0cb84dSRahul Lakkireddy }; 8862d0cb84dSRahul Lakkireddy 887f7917c00SJeff Kirsher struct sge { 888f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 889a4569504SAtul Gupta struct sge_eth_txq ptptxq; 890f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 891f7917c00SJeff Kirsher 892f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 893f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 89494cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 895ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 896f7917c00SJeff Kirsher 897f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 898f7917c00SJeff Kirsher spinlock_t intrq_lock; 899f7917c00SJeff Kirsher 9002d0cb84dSRahul Lakkireddy struct sge_eohw_txq *eohw_txq; 9012d0cb84dSRahul Lakkireddy struct sge_ofld_rxq *eohw_rxq; 9022d0cb84dSRahul Lakkireddy 903f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 904f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 905f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 9060fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 90794cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 9082d0cb84dSRahul Lakkireddy u16 eoqsets; /* # of ETHOFLD queues */ 9092d0cb84dSRahul Lakkireddy 910f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 911f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 912543a1b85SVishal Kulkarni u16 dbqtimer_tick; 913d429005fSVishal Kulkarni u16 dbqtimer_val[SGE_NDBQTIMERS]; 91452367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 91552367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 91652367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 91752367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 91852367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 9190f4d201fSKumar Sanghvi 920a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 921f7917c00SJeff Kirsher unsigned int egr_start; 9224b8e27a8SHariprasad Shenai unsigned int egr_sz; 923f7917c00SJeff Kirsher unsigned int ingr_start; 9244b8e27a8SHariprasad Shenai unsigned int ingr_sz; 9254b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 9264b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 9274b8e27a8SHariprasad Shenai unsigned long *starving_fl; 9284b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 9295b377d11SHariprasad Shenai unsigned long *blocked_fl; 930f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 931f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 93276c3a552SRahul Lakkireddy 93376c3a552SRahul Lakkireddy int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 93476c3a552SRahul Lakkireddy int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 935f7917c00SJeff Kirsher }; 936f7917c00SJeff Kirsher 937f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 9380fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 939f7917c00SJeff Kirsher 940f7917c00SJeff Kirsher struct l2t_data; 941f7917c00SJeff Kirsher 9422422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 9432422d9a3SSantosh Rastapur 9447d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 9457d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 9467d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 9472422d9a3SSantosh Rastapur */ 9487d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 9492422d9a3SSantosh Rastapur 9502422d9a3SSantosh Rastapur #endif 9512422d9a3SSantosh Rastapur 952a4cfd929SHariprasad Shenai struct doorbell_stats { 953a4cfd929SHariprasad Shenai u32 db_drop; 954a4cfd929SHariprasad Shenai u32 db_empty; 955a4cfd929SHariprasad Shenai u32 db_full; 956a4cfd929SHariprasad Shenai }; 957a4cfd929SHariprasad Shenai 958fc08a01aSHariprasad Shenai struct hash_mac_addr { 959fc08a01aSHariprasad Shenai struct list_head list; 960fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 9613f8cfd0dSArjun Vynipadath unsigned int iface_mac; 962fc08a01aSHariprasad Shenai }; 963fc08a01aSHariprasad Shenai 96476c3a552SRahul Lakkireddy struct msix_bmap { 96594cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 96694cdb8bbSHariprasad Shenai unsigned int mapsize; 96794cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 96894cdb8bbSHariprasad Shenai }; 96994cdb8bbSHariprasad Shenai 97076c3a552SRahul Lakkireddy struct msix_info { 97194cdb8bbSHariprasad Shenai unsigned short vec; 97294cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 9730fbc81b3SHariprasad Shenai unsigned int idx; 974c9765074SNirranjan Kirubaharan cpumask_var_t aff_mask; 97594cdb8bbSHariprasad Shenai }; 97694cdb8bbSHariprasad Shenai 977661dbeb9SHariprasad Shenai struct vf_info { 978661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 9798ea4fae9SGanesh Goudar unsigned int tx_rate; 980661dbeb9SHariprasad Shenai bool pf_set_mac; 9819d5fd927SGanesh Goudar u16 vlan; 9828b965f3fSArjun Vynipadath int link_state; 983661dbeb9SHariprasad Shenai }; 984661dbeb9SHariprasad Shenai 9858b4e6b3cSArjun Vynipadath enum { 9868b4e6b3cSArjun Vynipadath HMA_DMA_MAPPED_FLAG = 1 9878b4e6b3cSArjun Vynipadath }; 9888b4e6b3cSArjun Vynipadath 9898b4e6b3cSArjun Vynipadath struct hma_data { 9908b4e6b3cSArjun Vynipadath unsigned char flags; 9918b4e6b3cSArjun Vynipadath struct sg_table *sgt; 9928b4e6b3cSArjun Vynipadath dma_addr_t *phy_addr; /* physical address of the page */ 9938b4e6b3cSArjun Vynipadath }; 9948b4e6b3cSArjun Vynipadath 9954055ae5eSHariprasad Shenai struct mbox_list { 9964055ae5eSHariprasad Shenai struct list_head list; 9974055ae5eSHariprasad Shenai }; 9984055ae5eSHariprasad Shenai 999e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 1000b1871915SGanesh Goudar struct ch_thermal { 1001b1871915SGanesh Goudar struct thermal_zone_device *tzdev; 1002b1871915SGanesh Goudar int trip_temp; 1003b1871915SGanesh Goudar int trip_type; 1004b1871915SGanesh Goudar }; 1005b1871915SGanesh Goudar #endif 1006b1871915SGanesh Goudar 100728b38705SRaju Rangoju struct mps_entries_ref { 100828b38705SRaju Rangoju struct list_head list; 100928b38705SRaju Rangoju u8 addr[ETH_ALEN]; 101028b38705SRaju Rangoju u8 mask[ETH_ALEN]; 101128b38705SRaju Rangoju u16 idx; 101228b38705SRaju Rangoju refcount_t refcnt; 101328b38705SRaju Rangoju }; 101428b38705SRaju Rangoju 1015f7917c00SJeff Kirsher struct adapter { 1016f7917c00SJeff Kirsher void __iomem *regs; 101722adfe0aSSantosh Rastapur void __iomem *bar2; 10180abfd152SHariprasad Shenai u32 t4_bar0; 1019f7917c00SJeff Kirsher struct pci_dev *pdev; 1020f7917c00SJeff Kirsher struct device *pdev_dev; 10210de72738SHariprasad Shenai const char *name; 10223069ee9bSVipul Pandya unsigned int mbox; 1023b2612722SHariprasad Shenai unsigned int pf; 1024f7917c00SJeff Kirsher unsigned int flags; 1025e7b48a32SHariprasad Shenai unsigned int adap_idx; 10262422d9a3SSantosh Rastapur enum chip_type chip; 1027d5fbda61SArjun Vynipadath u32 eth_flags; 1028f7917c00SJeff Kirsher 1029f7917c00SJeff Kirsher int msg_enable; 1030846eac3fSGanesh Goudar __be16 vxlan_port; 1031846eac3fSGanesh Goudar u8 vxlan_port_cnt; 1032c746fc0eSGanesh Goudar __be16 geneve_port; 1033c746fc0eSGanesh Goudar u8 geneve_port_cnt; 1034f7917c00SJeff Kirsher 1035f7917c00SJeff Kirsher struct adapter_params params; 1036f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 1037f7917c00SJeff Kirsher unsigned int swintr; 1038f7917c00SJeff Kirsher 103976c3a552SRahul Lakkireddy /* MSI-X Info for NIC and OFLD queues */ 104076c3a552SRahul Lakkireddy struct msix_info *msix_info; 104176c3a552SRahul Lakkireddy struct msix_bmap msix_bmap; 1042f7917c00SJeff Kirsher 1043a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 1044f7917c00SJeff Kirsher struct sge sge; 1045f7917c00SJeff Kirsher 1046f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 1047f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 1048f7917c00SJeff Kirsher 1049661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 1050661dbeb9SHariprasad Shenai u8 num_vfs; 1051661dbeb9SHariprasad Shenai 1052793dad94SVipul Pandya u32 filter_mode; 1053636f9d37SVipul Pandya unsigned int l2t_start; 1054636f9d37SVipul Pandya unsigned int l2t_end; 1055f7917c00SJeff Kirsher struct l2t_data *l2t; 1056b5a02f50SAnish Bhatt unsigned int clipt_start; 1057b5a02f50SAnish Bhatt unsigned int clipt_end; 1058b5a02f50SAnish Bhatt struct clip_tbl *clipt; 1059846eac3fSGanesh Goudar unsigned int rawf_start; 1060846eac3fSGanesh Goudar unsigned int rawf_cnt; 10613bdb376eSKumar Sanghvi struct smt_data *smt; 10620fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 1063f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 106494cdb8bbSHariprasad Shenai unsigned int num_uld; 10650fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 1066f7917c00SJeff Kirsher struct list_head list_node; 106701bcca68SVipul Pandya struct list_head rcu_node; 1068fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 106928b38705SRaju Rangoju struct list_head mps_ref; 107028b38705SRaju Rangoju spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1071f7917c00SJeff Kirsher 10727714cb9eSVarun Prakash void *iscsi_ppm; 10737714cb9eSVarun Prakash 1074f7917c00SJeff Kirsher struct tid_info tids; 1075f7917c00SJeff Kirsher void **tid_release_head; 1076f7917c00SJeff Kirsher spinlock_t tid_release_lock; 107729aaee65SAnish Bhatt struct workqueue_struct *workq; 1078f7917c00SJeff Kirsher struct work_struct tid_release_task; 1079881806bcSVipul Pandya struct work_struct db_full_task; 1080881806bcSVipul Pandya struct work_struct db_drop_task; 10818b7372c1SGanesh Goudar struct work_struct fatal_err_notify_task; 1082f7917c00SJeff Kirsher bool tid_release_task_busy; 1083f7917c00SJeff Kirsher 10844055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 10854055ae5eSHariprasad Shenai spinlock_t mbox_lock; 10864055ae5eSHariprasad Shenai struct mbox_list mlist; 10874055ae5eSHariprasad Shenai 10887f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 10897f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 10907f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 10917f080c3fSHariprasad Shenai 10920fbc81b3SHariprasad Shenai struct mutex uld_mutex; 10930fbc81b3SHariprasad Shenai 1094f7917c00SJeff Kirsher struct dentry *debugfs_root; 1095621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1096621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 10978e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 10988e3d04fdSHariprasad Shenai * used for all 4 filters. 10998e3d04fdSHariprasad Shenai */ 1100f7917c00SJeff Kirsher 1101a4569504SAtul Gupta struct ptp_clock *ptp_clock; 1102a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 1103a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 1104a4569504SAtul Gupta /* ptp lock */ 1105a4569504SAtul Gupta spinlock_t ptp_lock; 1106f7917c00SJeff Kirsher spinlock_t stats_lock; 1107fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 1108d8931847SRahul Lakkireddy 1109d8931847SRahul Lakkireddy /* TC u32 offload */ 1110d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 1111a3ac249aSRohit Maheshwari struct chcr_ktls chcr_ktls; 1112ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 111362488e4bSKumar Sanghvi 111462488e4bSKumar Sanghvi /* TC flower offload */ 1115a081e115SCasey Leedom bool tc_flower_initialized; 111679e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 111779e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 1118e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 111979e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 1120ad75b7d3SRahul Lakkireddy 1121ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 1122ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 11238b4e6b3cSArjun Vynipadath 11248b4e6b3cSArjun Vynipadath /* HMA */ 11258b4e6b3cSArjun Vynipadath struct hma_data hma; 1126e4709475SRaju Rangoju 1127e4709475SRaju Rangoju struct srq_data *srq; 11281dde532dSRahul Lakkireddy 11291dde532dSRahul Lakkireddy /* Dump buffer for collecting logs in kdump kernel */ 11301dde532dSRahul Lakkireddy struct vmcoredd_data vmcoredd; 1131e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 1132b1871915SGanesh Goudar struct ch_thermal ch_thermal; 1133b1871915SGanesh Goudar #endif 1134b1396c2bSRahul Lakkireddy 1135b1396c2bSRahul Lakkireddy /* TC MQPRIO offload */ 1136b1396c2bSRahul Lakkireddy struct cxgb4_tc_mqprio *tc_mqprio; 11374ec4762dSRahul Lakkireddy 11384ec4762dSRahul Lakkireddy /* TC MATCHALL classifier offload */ 11394ec4762dSRahul Lakkireddy struct cxgb4_tc_matchall *tc_matchall; 1140f7917c00SJeff Kirsher }; 1141f7917c00SJeff Kirsher 1142b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 1143b72a32daSRahul Lakkireddy * programmed with various parameters. 1144b72a32daSRahul Lakkireddy */ 1145b72a32daSRahul Lakkireddy struct ch_sched_params { 11464bccfc03SRahul Lakkireddy u8 type; /* packet or flow */ 1147b72a32daSRahul Lakkireddy union { 1148b72a32daSRahul Lakkireddy struct { 11494bccfc03SRahul Lakkireddy u8 level; /* scheduler hierarchy level */ 11504bccfc03SRahul Lakkireddy u8 mode; /* per-class or per-flow */ 11514bccfc03SRahul Lakkireddy u8 rateunit; /* bit or packet rate */ 11524bccfc03SRahul Lakkireddy u8 ratemode; /* %port relative or kbps absolute */ 11534bccfc03SRahul Lakkireddy u8 channel; /* scheduler channel [0..N] */ 11544bccfc03SRahul Lakkireddy u8 class; /* scheduler class [0..N] */ 11554bccfc03SRahul Lakkireddy u32 minrate; /* minimum rate */ 11564bccfc03SRahul Lakkireddy u32 maxrate; /* maximum rate */ 11574bccfc03SRahul Lakkireddy u16 weight; /* percent weight */ 11584bccfc03SRahul Lakkireddy u16 pktsize; /* average packet size */ 11594bccfc03SRahul Lakkireddy u16 burstsize; /* burst buffer size */ 1160b72a32daSRahul Lakkireddy } params; 1161b72a32daSRahul Lakkireddy } u; 1162b72a32daSRahul Lakkireddy }; 1163b72a32daSRahul Lakkireddy 116410a2604eSRahul Lakkireddy enum { 116510a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 116610a2604eSRahul Lakkireddy }; 116710a2604eSRahul Lakkireddy 116810a2604eSRahul Lakkireddy enum { 116910a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 11704ec4762dSRahul Lakkireddy SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ 117110a2604eSRahul Lakkireddy }; 117210a2604eSRahul Lakkireddy 117310a2604eSRahul Lakkireddy enum { 117410a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 11750e395b3cSRahul Lakkireddy SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 117610a2604eSRahul Lakkireddy }; 117710a2604eSRahul Lakkireddy 117810a2604eSRahul Lakkireddy enum { 117910a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 118010a2604eSRahul Lakkireddy }; 118110a2604eSRahul Lakkireddy 118210a2604eSRahul Lakkireddy enum { 118310a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 118410a2604eSRahul Lakkireddy }; 118510a2604eSRahul Lakkireddy 11866cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 11876cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 11886cede1f1SRahul Lakkireddy */ 11896cede1f1SRahul Lakkireddy struct ch_sched_queue { 11906cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 11916cede1f1SRahul Lakkireddy s8 class; /* class index */ 11926cede1f1SRahul Lakkireddy }; 11936cede1f1SRahul Lakkireddy 11940e395b3cSRahul Lakkireddy /* Support for "sched_flowc" command to allow one or more FLOWC 11950e395b3cSRahul Lakkireddy * to be bound to a TX Scheduling Class. 11960e395b3cSRahul Lakkireddy */ 11970e395b3cSRahul Lakkireddy struct ch_sched_flowc { 11980e395b3cSRahul Lakkireddy s32 tid; /* TID to bind */ 11990e395b3cSRahul Lakkireddy s8 class; /* class index */ 12000e395b3cSRahul Lakkireddy }; 12010e395b3cSRahul Lakkireddy 1202f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 1203f2b7e78dSVipul Pandya */ 1204f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 1205f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 1206f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 1207f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 1208f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 1209f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1210f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1211f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1212f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1213f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1214f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1215f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 121698f3697fSKumar Sanghvi #define ENCAP_VNI_BITWIDTH 24 1217f2b7e78dSVipul Pandya 1218f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1219f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1220f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1221f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1222f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1223f2b7e78dSVipul Pandya * matching rules are true. 1224f2b7e78dSVipul Pandya * 1225f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1226f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1227f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1228f2b7e78dSVipul Pandya * MPS match type) ... 1229f2b7e78dSVipul Pandya * 1230f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1231f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1232f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1233f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1234f2b7e78dSVipul Pandya */ 1235f2b7e78dSVipul Pandya struct ch_filter_tuple { 1236f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1237f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1238f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1239f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1240f2b7e78dSVipul Pandya * set of fields. 1241f2b7e78dSVipul Pandya */ 1242f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1243f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1244f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1245f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1246f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 124798f3697fSKumar Sanghvi uint32_t encap_vld:1; /* Encapsulation valid */ 1248f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1249f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1250f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1251f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1252f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1253f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1254f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1255f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1256f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1257f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 125898f3697fSKumar Sanghvi uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1259f2b7e78dSVipul Pandya 1260f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1261f2b7e78dSVipul Pandya * available for field rules. 1262f2b7e78dSVipul Pandya */ 1263f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1264f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1265f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1266f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1267f2b7e78dSVipul Pandya }; 1268f2b7e78dSVipul Pandya 1269f2b7e78dSVipul Pandya /* A filter ioctl command. 1270f2b7e78dSVipul Pandya */ 1271f2b7e78dSVipul Pandya struct ch_filter_specification { 1272f2b7e78dSVipul Pandya /* Administrative fields for filter. 1273f2b7e78dSVipul Pandya */ 1274f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1275f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1276f2b7e78dSVipul Pandya 1277f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1278f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1279f2b7e78dSVipul Pandya */ 1280f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 128112b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1282f2b7e78dSVipul Pandya 1283f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1284f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1285f2b7e78dSVipul Pandya * out as egress packets. 1286f2b7e78dSVipul Pandya */ 1287f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1288f2b7e78dSVipul Pandya 1289f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1290f2b7e78dSVipul Pandya 1291f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1292f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1293f2b7e78dSVipul Pandya 1294f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1295f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1296f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1297f2b7e78dSVipul Pandya 1298f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1299f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1300f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1301f2b7e78dSVipul Pandya */ 1302f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1303f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1304f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1305f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 13060ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1307f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1308f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1309f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1310f2b7e78dSVipul Pandya 13110ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 13120ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 13130ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 13140ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 13150ff90994SKumar Sanghvi 131641ec03e5SRahul Lakkireddy u32 tc_prio; /* TC's filter priority index */ 131741ec03e5SRahul Lakkireddy u64 tc_cookie; /* Unique cookie identifying TC rules */ 131841ec03e5SRahul Lakkireddy 13190ff90994SKumar Sanghvi /* reservation for future additions */ 132041ec03e5SRahul Lakkireddy u8 rsvd[12]; 13210ff90994SKumar Sanghvi 1322f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1323f2b7e78dSVipul Pandya */ 1324f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1325f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1326f2b7e78dSVipul Pandya }; 1327f2b7e78dSVipul Pandya 1328f2b7e78dSVipul Pandya enum { 1329f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1330f2b7e78dSVipul Pandya FILTER_DROP, 1331f2b7e78dSVipul Pandya FILTER_SWITCH 1332f2b7e78dSVipul Pandya }; 1333f2b7e78dSVipul Pandya 1334f2b7e78dSVipul Pandya enum { 1335f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1336f2b7e78dSVipul Pandya VLAN_REMOVE, 1337f2b7e78dSVipul Pandya VLAN_INSERT, 1338f2b7e78dSVipul Pandya VLAN_REWRITE 1339f2b7e78dSVipul Pandya }; 1340f2b7e78dSVipul Pandya 1341557ccbf9SKumar Sanghvi enum { 134212b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 134312b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 134412b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 134512b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 134612b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 134712b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 134812b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 134912b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1350557ccbf9SKumar Sanghvi }; 1351557ccbf9SKumar Sanghvi 1352d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1353d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1354d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1355d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1356d57fd6caSRahul Lakkireddy * where the filter table is large. 1357d57fd6caSRahul Lakkireddy */ 1358d57fd6caSRahul Lakkireddy struct filter_entry { 1359d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1360d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1361d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1362d57fd6caSRahul Lakkireddy 1363d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1364578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1365d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 13663bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1367578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1368578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1369d57fd6caSRahul Lakkireddy 1370d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1371d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1372d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1373d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1374d57fd6caSRahul Lakkireddy */ 1375d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1376d57fd6caSRahul Lakkireddy }; 1377d57fd6caSRahul Lakkireddy 1378a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1379a4cfd929SHariprasad Shenai { 1380a4cfd929SHariprasad Shenai return adap->params.offload; 1381a4cfd929SHariprasad Shenai } 1382a4cfd929SHariprasad Shenai 13835c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 13845c31254eSKumar Sanghvi { 13855c31254eSKumar Sanghvi return adap->params.hash_filter; 13865c31254eSKumar Sanghvi } 13875c31254eSKumar Sanghvi 138894cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 138994cdb8bbSHariprasad Shenai { 139094cdb8bbSHariprasad Shenai return adap->params.crypto; 139194cdb8bbSHariprasad Shenai } 139294cdb8bbSHariprasad Shenai 13930fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 13940fbc81b3SHariprasad Shenai { 13950fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 13960fbc81b3SHariprasad Shenai } 13970fbc81b3SHariprasad Shenai 1398ab0367eaSRahul Lakkireddy static inline int is_ethofld(const struct adapter *adap) 1399ab0367eaSRahul Lakkireddy { 1400ab0367eaSRahul Lakkireddy return adap->params.ethofld; 1401ab0367eaSRahul Lakkireddy } 1402ab0367eaSRahul Lakkireddy 1403f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1404f7917c00SJeff Kirsher { 1405f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1406f7917c00SJeff Kirsher } 1407f7917c00SJeff Kirsher 1408f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1409f7917c00SJeff Kirsher { 1410f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1411f7917c00SJeff Kirsher } 1412f7917c00SJeff Kirsher 1413f7917c00SJeff Kirsher #ifndef readq 1414f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1415f7917c00SJeff Kirsher { 1416f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1417f7917c00SJeff Kirsher } 1418f7917c00SJeff Kirsher 1419f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1420f7917c00SJeff Kirsher { 1421f7917c00SJeff Kirsher writel(val, addr); 1422f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1423f7917c00SJeff Kirsher } 1424f7917c00SJeff Kirsher #endif 1425f7917c00SJeff Kirsher 1426f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1427f7917c00SJeff Kirsher { 1428f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1429f7917c00SJeff Kirsher } 1430f7917c00SJeff Kirsher 1431f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1432f7917c00SJeff Kirsher { 1433f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1434f7917c00SJeff Kirsher } 1435f7917c00SJeff Kirsher 1436f7917c00SJeff Kirsher /** 1437098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1438098ef6c2SHariprasad Shenai * @adapter: the adapter 1439098ef6c2SHariprasad Shenai * @port_idx: the port index 1440098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1441098ef6c2SHariprasad Shenai * 1442098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1443098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1444098ef6c2SHariprasad Shenai */ 1445098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1446098ef6c2SHariprasad Shenai u8 hw_addr[]) 1447098ef6c2SHariprasad Shenai { 1448098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1449098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1450098ef6c2SHariprasad Shenai } 1451098ef6c2SHariprasad Shenai 1452098ef6c2SHariprasad Shenai /** 1453f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1454f7917c00SJeff Kirsher * @dev: the netdev 1455f7917c00SJeff Kirsher * 1456f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1457f7917c00SJeff Kirsher */ 1458f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1459f7917c00SJeff Kirsher { 1460f7917c00SJeff Kirsher return netdev_priv(dev); 1461f7917c00SJeff Kirsher } 1462f7917c00SJeff Kirsher 1463f7917c00SJeff Kirsher /** 1464f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1465f7917c00SJeff Kirsher * @adap: the adapter 1466f7917c00SJeff Kirsher * @idx: the port index 1467f7917c00SJeff Kirsher * 1468f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1469f7917c00SJeff Kirsher */ 1470f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1471f7917c00SJeff Kirsher { 1472f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1473f7917c00SJeff Kirsher } 1474f7917c00SJeff Kirsher 1475f7917c00SJeff Kirsher /** 1476f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1477f7917c00SJeff Kirsher * @dev: the netdev 1478f7917c00SJeff Kirsher * 1479f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1480f7917c00SJeff Kirsher */ 1481f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1482f7917c00SJeff Kirsher { 1483f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1484f7917c00SJeff Kirsher } 1485f7917c00SJeff Kirsher 1486812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1487812034f1SHariprasad Shenai * - bits 0..9: chip version 1488812034f1SHariprasad Shenai * - bits 10..15: chip revision 1489812034f1SHariprasad Shenai * - bits 16..23: register dump version 1490812034f1SHariprasad Shenai */ 1491812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1492812034f1SHariprasad Shenai { 1493812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1494812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1495812034f1SHariprasad Shenai } 1496812034f1SHariprasad Shenai 1497812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1498812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1499812034f1SHariprasad Shenai const struct sge_rspq *q) 1500812034f1SHariprasad Shenai { 1501812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1502812034f1SHariprasad Shenai 1503812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1504812034f1SHariprasad Shenai } 1505812034f1SHariprasad Shenai 150601e392aaSLeon Romanovsky /* driver name used for ethtool_drvinfo */ 1507812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1508812034f1SHariprasad Shenai 15098156b0baSGanesh Goudar void t4_os_portmod_changed(struct adapter *adap, int port_id); 1510f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1511f7917c00SJeff Kirsher 1512f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 15135fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1514f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1515d5fbda61SArjun Vynipadath netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 1516f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1517f7917c00SJeff Kirsher const struct pkt_gl *gl); 1518f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1519f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1520f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1521f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 15222337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 15232337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1524f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1525f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1526d429005fSVishal Kulkarni unsigned int iqid, u8 dbqt); 1527f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1528f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1529f7917c00SJeff Kirsher unsigned int cmplqid); 15300fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 15310fbc81b3SHariprasad Shenai unsigned int cmplqid); 1532ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1533ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1534ab677ff4SHariprasad Shenai unsigned int uld_type); 15352d0cb84dSRahul Lakkireddy int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 15362d0cb84dSRahul Lakkireddy struct net_device *dev, u32 iqid); 15372d0cb84dSRahul Lakkireddy void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1538f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 153952367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1540f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1541f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1542d429005fSVishal Kulkarni int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1543d429005fSVishal Kulkarni int maxreclaim); 1544812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1545812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1546d0a1299cSGanesh Goudar enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 15473069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1548f7917c00SJeff Kirsher 1549f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1550f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1551f7917c00SJeff Kirsher 15529a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 15539a4da2cdSVipul Pandya { 15549a4da2cdSVipul Pandya return adap->params.bypass; 15559a4da2cdSVipul Pandya } 15569a4da2cdSVipul Pandya 15579a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 15589a4da2cdSVipul Pandya { 15599a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 15609a4da2cdSVipul Pandya switch (device) { 15619a4da2cdSVipul Pandya case 0x440b: 15629a4da2cdSVipul Pandya case 0x440c: 15639a4da2cdSVipul Pandya return 1; 15649a4da2cdSVipul Pandya default: 15659a4da2cdSVipul Pandya return 0; 15669a4da2cdSVipul Pandya } 15679a4da2cdSVipul Pandya } 15689a4da2cdSVipul Pandya 156901b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 157001b69614SHariprasad Shenai { 157101b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 157201b69614SHariprasad Shenai switch (device) { 157301b69614SHariprasad Shenai case 0x4409: 157401b69614SHariprasad Shenai case 0x4486: 157501b69614SHariprasad Shenai return 1; 157601b69614SHariprasad Shenai 157701b69614SHariprasad Shenai default: 157801b69614SHariprasad Shenai return 0; 157901b69614SHariprasad Shenai } 158001b69614SHariprasad Shenai } 158101b69614SHariprasad Shenai 1582f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1583f7917c00SJeff Kirsher { 1584f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1585f7917c00SJeff Kirsher } 1586f7917c00SJeff Kirsher 1587f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1588f7917c00SJeff Kirsher unsigned int us) 1589f7917c00SJeff Kirsher { 1590f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1591f7917c00SJeff Kirsher } 1592f7917c00SJeff Kirsher 159352367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 159452367a76SVipul Pandya unsigned int ticks) 159552367a76SVipul Pandya { 159652367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 159752367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 159852367a76SVipul Pandya adapter->params.vpd.cclk); 159952367a76SVipul Pandya } 160052367a76SVipul Pandya 160108c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 160208c4901bSRahul Lakkireddy unsigned int ticks) 160308c4901bSRahul Lakkireddy { 160408c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 160508c4901bSRahul Lakkireddy } 160608c4901bSRahul Lakkireddy 1607f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1608f7917c00SJeff Kirsher u32 val); 1609f7917c00SJeff Kirsher 161001b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 161101b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1612f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1613f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1614f7917c00SJeff Kirsher 161501b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 161601b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 161701b69614SHariprasad Shenai int timeout) 161801b69614SHariprasad Shenai { 161901b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 162001b69614SHariprasad Shenai timeout); 162101b69614SHariprasad Shenai } 162201b69614SHariprasad Shenai 1623f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1624f7917c00SJeff Kirsher int size, void *rpl) 1625f7917c00SJeff Kirsher { 1626f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1627f7917c00SJeff Kirsher } 1628f7917c00SJeff Kirsher 1629f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1630f7917c00SJeff Kirsher int size, void *rpl) 1631f7917c00SJeff Kirsher { 1632f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1633f7917c00SJeff Kirsher } 1634f7917c00SJeff Kirsher 1635fc08a01aSHariprasad Shenai /** 1636fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1637fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1638fc08a01aSHariprasad Shenai * 1639fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1640fc08a01aSHariprasad Shenai * (hash) address matching. 1641fc08a01aSHariprasad Shenai */ 1642fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1643fc08a01aSHariprasad Shenai { 1644fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1645fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1646fc08a01aSHariprasad Shenai 1647fc08a01aSHariprasad Shenai a ^= b; 1648fc08a01aSHariprasad Shenai a ^= (a >> 12); 1649fc08a01aSHariprasad Shenai a ^= (a >> 6); 1650fc08a01aSHariprasad Shenai return a & 0x3f; 1651fc08a01aSHariprasad Shenai } 1652fc08a01aSHariprasad Shenai 165394cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 165494cdb8bbSHariprasad Shenai unsigned int cnt); 165594cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 165694cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 165794cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 165894cdb8bbSHariprasad Shenai { 165994cdb8bbSHariprasad Shenai q->adap = adap; 166094cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 166194cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 166294cdb8bbSHariprasad Shenai q->size = size; 166394cdb8bbSHariprasad Shenai } 166494cdb8bbSHariprasad Shenai 1665f56ec676SArjun Vynipadath /** 1666f56ec676SArjun Vynipadath * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1667f56ec676SArjun Vynipadath * @fw_mod_type: the Firmware Mofule Type 1668f56ec676SArjun Vynipadath * 1669f56ec676SArjun Vynipadath * Return whether the Firmware Module Type represents a real Transceiver 1670f56ec676SArjun Vynipadath * Module/Cable Module Type which has been inserted. 1671f56ec676SArjun Vynipadath */ 1672f56ec676SArjun Vynipadath static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1673f56ec676SArjun Vynipadath { 1674f56ec676SArjun Vynipadath return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1675f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1676f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1677f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1678f56ec676SArjun Vynipadath } 1679f56ec676SArjun Vynipadath 168013ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 168113ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 168213ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1683f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1684f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1685f2b7e78dSVipul Pandya unsigned int start_idx); 16860abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1687f2b7e78dSVipul Pandya 1688f2b7e78dSVipul Pandya struct fw_filter_wr; 1689f2b7e78dSVipul Pandya 1690f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1691f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1692f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1693f7917c00SJeff Kirsher 16948203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 16958156b0baSGanesh Goudar 16969f764898SVishal Kulkarni fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 16979f764898SVishal Kulkarni struct link_config *lc); 16988156b0baSGanesh Goudar int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 16998156b0baSGanesh Goudar unsigned int port, struct link_config *lc, 17009f764898SVishal Kulkarni u8 sleep_ok, int timeout); 17018156b0baSGanesh Goudar 17028156b0baSGanesh Goudar static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 17038156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 17048156b0baSGanesh Goudar { 17058156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 17068156b0baSGanesh Goudar true, FW_CMD_MAX_TIMEOUT); 17078156b0baSGanesh Goudar } 17088156b0baSGanesh Goudar 17098156b0baSGanesh Goudar static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 17108156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 17118156b0baSGanesh Goudar { 17128156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 17138156b0baSGanesh Goudar false, FW_CMD_MAX_TIMEOUT); 17148156b0baSGanesh Goudar } 17158156b0baSGanesh Goudar 1716f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1717fc5ab020SHariprasad Shenai 1718b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1719b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1720b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1721b562fc37SHariprasad Shenai 17221a4330cdSRahul Lakkireddy int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 17231a4330cdSRahul Lakkireddy u32 *mem_base, u32 *mem_aperture); 17241a4330cdSRahul Lakkireddy void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 17251a4330cdSRahul Lakkireddy void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 17261a4330cdSRahul Lakkireddy int dir); 1727fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1728fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1729fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1730f01aa633SHariprasad Shenai void *buf, int dir); 1731fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1732fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1733fc5ab020SHariprasad Shenai { 1734fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1735fc5ab020SHariprasad Shenai } 1736fc5ab020SHariprasad Shenai 1737812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1738812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1739812034f1SHariprasad Shenai 1740940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1741f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1742098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1743098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 17440eaec62aSCasey Leedom int t4_get_pfres(struct adapter *adapter); 174549216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 174649216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1747f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 174801b69614SHariprasad Shenai int t4_load_phy_fw(struct adapter *adap, 174901b69614SHariprasad Shenai int win, spinlock_t *lock, 175001b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 175101b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 175201b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 175349216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 175422c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 175522c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1756acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1757636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1758a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 17594da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 176016e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 17610de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 176216e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1763ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1764760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1765760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1766760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1767760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 176816e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 176916e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 177016e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1771f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 17723be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1773e85c9a7aSHariprasad Shenai 1774e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1775b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1776e85c9a7aSHariprasad Shenai unsigned int qid, 1777e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 177866cf188eSHariprasad S int user, 1779e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1780e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1781e85c9a7aSHariprasad Shenai 1782dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1783dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1784ae469b68SHariprasad Shenai 1785ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1786e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 17875ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1788dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1789c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1790c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1791c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1792f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1793f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1794f988008aSGanesh Goudar unsigned int t4_chip_rss_size(struct adapter *adapter); 1795f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1796f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1797f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1798f7917c00SJeff Kirsher unsigned int flags); 1799c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1800c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1801688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 18025ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 18035ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 18045ccf9d04SRahul Lakkireddy bool sleep_ok); 1805688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 18065ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1807688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 18085ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 18095ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 18105ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1811688ea5feSHariprasad Shenai 1812193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1813193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1814b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1815b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1816e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1817e5f0e43bSHariprasad Shenai size_t n); 1818c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1819c778af7dSHariprasad Shenai size_t n); 1820f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1821f1ff24aaSHariprasad Shenai unsigned int *valp); 1822f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1823f1ff24aaSHariprasad Shenai const unsigned int *valp); 1824f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 182519689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 182619689609SHariprasad Shenai unsigned int *pif_req_wrptr, 182719689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 182826fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 182974b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 183072aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1831f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1832a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1833a4cfd929SHariprasad Shenai struct port_stats *stats, 1834a4cfd929SHariprasad Shenai struct port_stats *offset); 183565046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1836f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1837bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1838636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1839636f9d37SVipul Pandya unsigned int mask, unsigned int val); 18402d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 18415ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 18425ccf9d04SRahul Lakkireddy bool sleep_ok); 18435ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 18445ccf9d04SRahul Lakkireddy bool sleep_ok); 18455ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 18465ccf9d04SRahul Lakkireddy bool sleep_ok); 18475ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 18485ccf9d04SRahul Lakkireddy bool sleep_ok); 1849f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 18505ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1851a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 18525ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1853f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1854f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1855f7917c00SJeff Kirsher 1856797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1857797ff0f5SHariprasad Shenai 18587864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1859f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1860f2b7e78dSVipul Pandya 1861f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1862f7917c00SJeff Kirsher const u8 *addr); 1863f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1864f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1865f7917c00SJeff Kirsher 1866f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1867f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1868f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1869f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1870f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1871636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1872636f9d37SVipul Pandya unsigned int cache_line_size); 1873636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1874f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1875f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1876f7917c00SJeff Kirsher u32 *val); 18778f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 18788f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 18798f46d467SArjun Vynipadath u32 *val); 188001b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1881f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 18828f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 188301b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1884688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1885688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 188601b69614SHariprasad Shenai const u32 *val, int timeout); 188701b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 188801b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1889688848b1SAnish Bhatt const u32 *val); 1890f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1891f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1892f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1893f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1894f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1895f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1896f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 189702d805dcSSantosh Rastapur unsigned int *rss_size, u8 *vivld, u8 *vin); 18984f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 18994f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 19004f3a0fcfSHariprasad Shenai unsigned int viid); 1901f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1902f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1903f7917c00SJeff Kirsher bool sleep_ok); 1904846eac3fSGanesh Goudar int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 1905846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1906846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 190798f3697fSKumar Sanghvi int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 190898f3697fSKumar Sanghvi bool sleep_ok); 190998f3697fSKumar Sanghvi int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 191098f3697fSKumar Sanghvi const u8 *addr, const u8 *mask, unsigned int vni, 191198f3697fSKumar Sanghvi unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 191298f3697fSKumar Sanghvi bool sleep_ok); 1913846eac3fSGanesh Goudar int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 1914846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 1915846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 1916f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1917f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1918f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1919fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 1920fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 1921fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 1922f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 192302d805dcSSantosh Rastapur int idx, const u8 *addr, bool persist, u8 *smt_idx); 1924f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1925f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1926688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1927688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1928e2f4f4e9SArjun Vynipadath int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 1929e2f4f4e9SArjun Vynipadath struct port_info *pi, 1930e2f4f4e9SArjun Vynipadath bool rx_en, bool tx_en, bool dcb_en); 1931f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1932f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1933f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1934f7917c00SJeff Kirsher unsigned int nblinks); 1935f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1936f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1937f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1938f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1939ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 1940ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 1941ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 1942f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1943f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1944f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1945f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1946f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1947f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1948f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1949f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1950f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1951736c3b94SRahul Lakkireddy int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 1952d429005fSVishal Kulkarni int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 1953d429005fSVishal Kulkarni u16 *dbqtimers); 195423853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 19552061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 1956c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 1957c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 1958f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1959881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1960881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 19618e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 19628e3d04fdSHariprasad Shenai int filter_index, int enable); 19638e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 19648e3d04fdSHariprasad Shenai int filter_index, int *enabled); 19658caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 19668caa1e84SVipul Pandya u32 addr, u32 val); 196708c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 196808c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 196908c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 19709e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 19719e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 19729e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 19739e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 19744bccfc03SRahul Lakkireddy int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode, 19754bccfc03SRahul Lakkireddy u8 rateunit, u8 ratemode, u8 channel, u8 class, 19764bccfc03SRahul Lakkireddy u32 minrate, u32 maxrate, u16 weight, u16 pktsize, 19774bccfc03SRahul Lakkireddy u16 burstsize); 197868bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1979a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 1980a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 1981a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 1982a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 1983a3bfb617SHariprasad Shenai int hz, int ticks); 1984858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 1985858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 19865ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 19875ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 19884359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 19894359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 19905ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 19915ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 19925ccf9d04SRahul Lakkireddy 19930fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 19940fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 19950fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 19960fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 1997f56ec676SArjun Vynipadath int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 1998f56ec676SArjun Vynipadath unsigned int devid, unsigned int offset, 1999f56ec676SArjun Vynipadath unsigned int len, u8 *buf); 200094cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 2001ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 2002ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 2003b1396c2bSRahul Lakkireddy void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 2004b1396c2bSRahul Lakkireddy u32 ndesc); 20050e395b3cSRahul Lakkireddy int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 2006b1396c2bSRahul Lakkireddy void cxgb4_ethofld_restart(unsigned long data); 20074846d533SRahul Lakkireddy int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 20084846d533SRahul Lakkireddy const struct pkt_gl *si); 2009ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 2010a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 2011a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 2012a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 2013a6ec572bSAtul Gupta dma_addr_t *addr); 2014a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 2015a6ec572bSAtul Gupta void *pos); 2016a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 2017a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 2018a6ec572bSAtul Gupta const dma_addr_t *addr); 2019a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 20209d5fd927SGanesh Goudar int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 20219d5fd927SGanesh Goudar u16 vlan); 2022ebddd97aSGanesh Goudar int cxgb4_dcb_enabled(const struct net_device *dev); 2023b1871915SGanesh Goudar 2024b1871915SGanesh Goudar int cxgb4_thermal_init(struct adapter *adap); 2025b1871915SGanesh Goudar int cxgb4_thermal_remove(struct adapter *adap); 2026c9765074SNirranjan Kirubaharan int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 2027c9765074SNirranjan Kirubaharan cpumask_var_t *aff_mask, int idx); 2028c9765074SNirranjan Kirubaharan void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 2029b1871915SGanesh Goudar 20302f0b9406SRaju Rangoju int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 20312f0b9406SRaju Rangoju int *tcam_idx, const u8 *addr, 20322f0b9406SRaju Rangoju bool persistent, u8 *smt_idx); 20332f0b9406SRaju Rangoju 2034f9f329adSRaju Rangoju int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 2035f9f329adSRaju Rangoju bool free, unsigned int naddr, 2036f9f329adSRaju Rangoju const u8 **addr, u16 *idx, 2037f9f329adSRaju Rangoju u64 *hash, bool sleep_ok); 2038f9f329adSRaju Rangoju int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2039f9f329adSRaju Rangoju unsigned int naddr, const u8 **addr, bool sleep_ok); 204028b38705SRaju Rangoju int cxgb4_init_mps_ref_entries(struct adapter *adap); 204128b38705SRaju Rangoju void cxgb4_free_mps_ref_entries(struct adapter *adap); 204228b38705SRaju Rangoju int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 204328b38705SRaju Rangoju const u8 *addr, const u8 *mask, 204428b38705SRaju Rangoju unsigned int vni, unsigned int vni_mask, 204528b38705SRaju Rangoju u8 dip_hit, u8 lookup_type, bool sleep_ok); 204628b38705SRaju Rangoju int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 204728b38705SRaju Rangoju int idx, bool sleep_ok); 20485fab5158SRaju Rangoju int cxgb4_free_raw_mac_filt(struct adapter *adap, 20495fab5158SRaju Rangoju unsigned int viid, 20505fab5158SRaju Rangoju const u8 *addr, 20515fab5158SRaju Rangoju const u8 *mask, 20525fab5158SRaju Rangoju unsigned int idx, 20535fab5158SRaju Rangoju u8 lookup_type, 20545fab5158SRaju Rangoju u8 port_id, 20555fab5158SRaju Rangoju bool sleep_ok); 20565fab5158SRaju Rangoju int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 20575fab5158SRaju Rangoju unsigned int viid, 20585fab5158SRaju Rangoju const u8 *addr, 20595fab5158SRaju Rangoju const u8 *mask, 20605fab5158SRaju Rangoju unsigned int idx, 20615fab5158SRaju Rangoju u8 lookup_type, 20625fab5158SRaju Rangoju u8 port_id, 20635fab5158SRaju Rangoju bool sleep_ok); 20642f0b9406SRaju Rangoju int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 20652f0b9406SRaju Rangoju int *tcam_idx, const u8 *addr, 20662f0b9406SRaju Rangoju bool persistent, u8 *smt_idx); 206776c3a552SRahul Lakkireddy int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 206876c3a552SRahul Lakkireddy void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2069b1396c2bSRahul Lakkireddy int cxgb_open(struct net_device *dev); 2070b1396c2bSRahul Lakkireddy int cxgb_close(struct net_device *dev); 20712d0cb84dSRahul Lakkireddy void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 20722d0cb84dSRahul Lakkireddy void cxgb4_quiesce_rx(struct sge_rspq *q); 2073a3ac249aSRohit Maheshwari #ifdef CONFIG_CHELSIO_TLS_DEVICE 2074a3ac249aSRohit Maheshwari int cxgb4_set_ktls_feature(struct adapter *adap, bool enable); 2075a3ac249aSRohit Maheshwari #endif 2076f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 2077