1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4ce100b8bSAnish Bhatt * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49f7917c00SJeff Kirsher #include <asm/io.h> 50f7917c00SJeff Kirsher #include "cxgb4_uld.h" 51f7917c00SJeff Kirsher 5216e47624SHariprasad Shenai #define T4FW_VERSION_MAJOR 0x01 536c5caae0SHariprasad Shenai #define T4FW_VERSION_MINOR 0x0B 546c5caae0SHariprasad Shenai #define T4FW_VERSION_MICRO 0x1B 5516e47624SHariprasad Shenai #define T4FW_VERSION_BUILD 0x00 56f7917c00SJeff Kirsher 5716e47624SHariprasad Shenai #define T5FW_VERSION_MAJOR 0x01 586c5caae0SHariprasad Shenai #define T5FW_VERSION_MINOR 0x0B 596c5caae0SHariprasad Shenai #define T5FW_VERSION_MICRO 0x1B 6016e47624SHariprasad Shenai #define T5FW_VERSION_BUILD 0x00 612422d9a3SSantosh Rastapur 623069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 633069ee9bSVipul Pandya 64f7917c00SJeff Kirsher enum { 65f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 66f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 67f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 68f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 69a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 70f7917c00SJeff Kirsher }; 71f7917c00SJeff Kirsher 72f7917c00SJeff Kirsher enum { 73f7917c00SJeff Kirsher MEM_EDC0, 74f7917c00SJeff Kirsher MEM_EDC1, 752422d9a3SSantosh Rastapur MEM_MC, 762422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 772422d9a3SSantosh Rastapur MEM_MC1 78f7917c00SJeff Kirsher }; 79f7917c00SJeff Kirsher 803069ee9bSVipul Pandya enum { 813eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 823eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 833069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 843069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 852422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 863eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 873eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 880abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 890abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 903069ee9bSVipul Pandya }; 913069ee9bSVipul Pandya 92f7917c00SJeff Kirsher enum dev_master { 93f7917c00SJeff Kirsher MASTER_CANT, 94f7917c00SJeff Kirsher MASTER_MAY, 95f7917c00SJeff Kirsher MASTER_MUST 96f7917c00SJeff Kirsher }; 97f7917c00SJeff Kirsher 98f7917c00SJeff Kirsher enum dev_state { 99f7917c00SJeff Kirsher DEV_STATE_UNINIT, 100f7917c00SJeff Kirsher DEV_STATE_INIT, 101f7917c00SJeff Kirsher DEV_STATE_ERR 102f7917c00SJeff Kirsher }; 103f7917c00SJeff Kirsher 104f7917c00SJeff Kirsher enum { 105f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 106f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 107f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 108f7917c00SJeff Kirsher }; 109f7917c00SJeff Kirsher 110f7917c00SJeff Kirsher struct port_stats { 111f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 112f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 113f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 114f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 115f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 116f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 117f7917c00SJeff Kirsher 118f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 119f7917c00SJeff Kirsher u64 tx_frames_65_127; 120f7917c00SJeff Kirsher u64 tx_frames_128_255; 121f7917c00SJeff Kirsher u64 tx_frames_256_511; 122f7917c00SJeff Kirsher u64 tx_frames_512_1023; 123f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 124f7917c00SJeff Kirsher u64 tx_frames_1519_max; 125f7917c00SJeff Kirsher 126f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 127f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 128f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 129f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 130f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 131f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 132f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 133f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 134f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 135f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 136f7917c00SJeff Kirsher 137f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 138f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 139f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 140f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 141f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 142f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 143f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 144f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 145f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 146f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 147f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 148f7917c00SJeff Kirsher 149f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 150f7917c00SJeff Kirsher u64 rx_frames_65_127; 151f7917c00SJeff Kirsher u64 rx_frames_128_255; 152f7917c00SJeff Kirsher u64 rx_frames_256_511; 153f7917c00SJeff Kirsher u64 rx_frames_512_1023; 154f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 155f7917c00SJeff Kirsher u64 rx_frames_1519_max; 156f7917c00SJeff Kirsher 157f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 158f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 159f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 160f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 161f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 162f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 163f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 164f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 165f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 166f7917c00SJeff Kirsher 167f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 168f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 169f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 170f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 171f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 172f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 173f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 174f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 175f7917c00SJeff Kirsher }; 176f7917c00SJeff Kirsher 177f7917c00SJeff Kirsher struct lb_port_stats { 178f7917c00SJeff Kirsher u64 octets; 179f7917c00SJeff Kirsher u64 frames; 180f7917c00SJeff Kirsher u64 bcast_frames; 181f7917c00SJeff Kirsher u64 mcast_frames; 182f7917c00SJeff Kirsher u64 ucast_frames; 183f7917c00SJeff Kirsher u64 error_frames; 184f7917c00SJeff Kirsher 185f7917c00SJeff Kirsher u64 frames_64; 186f7917c00SJeff Kirsher u64 frames_65_127; 187f7917c00SJeff Kirsher u64 frames_128_255; 188f7917c00SJeff Kirsher u64 frames_256_511; 189f7917c00SJeff Kirsher u64 frames_512_1023; 190f7917c00SJeff Kirsher u64 frames_1024_1518; 191f7917c00SJeff Kirsher u64 frames_1519_max; 192f7917c00SJeff Kirsher 193f7917c00SJeff Kirsher u64 drop; 194f7917c00SJeff Kirsher 195f7917c00SJeff Kirsher u64 ovflow0; 196f7917c00SJeff Kirsher u64 ovflow1; 197f7917c00SJeff Kirsher u64 ovflow2; 198f7917c00SJeff Kirsher u64 ovflow3; 199f7917c00SJeff Kirsher u64 trunc0; 200f7917c00SJeff Kirsher u64 trunc1; 201f7917c00SJeff Kirsher u64 trunc2; 202f7917c00SJeff Kirsher u64 trunc3; 203f7917c00SJeff Kirsher }; 204f7917c00SJeff Kirsher 205f7917c00SJeff Kirsher struct tp_tcp_stats { 206f7917c00SJeff Kirsher u32 tcpOutRsts; 207f7917c00SJeff Kirsher u64 tcpInSegs; 208f7917c00SJeff Kirsher u64 tcpOutSegs; 209f7917c00SJeff Kirsher u64 tcpRetransSegs; 210f7917c00SJeff Kirsher }; 211f7917c00SJeff Kirsher 212f7917c00SJeff Kirsher struct tp_err_stats { 213f7917c00SJeff Kirsher u32 macInErrs[4]; 214f7917c00SJeff Kirsher u32 hdrInErrs[4]; 215f7917c00SJeff Kirsher u32 tcpInErrs[4]; 216f7917c00SJeff Kirsher u32 tnlCongDrops[4]; 217f7917c00SJeff Kirsher u32 ofldChanDrops[4]; 218f7917c00SJeff Kirsher u32 tnlTxDrops[4]; 219f7917c00SJeff Kirsher u32 ofldVlanDrops[4]; 220f7917c00SJeff Kirsher u32 tcp6InErrs[4]; 221f7917c00SJeff Kirsher u32 ofldNoNeigh; 222f7917c00SJeff Kirsher u32 ofldCongDefer; 223f7917c00SJeff Kirsher }; 224f7917c00SJeff Kirsher 225f7917c00SJeff Kirsher struct tp_params { 226f7917c00SJeff Kirsher unsigned int ntxchan; /* # of Tx channels */ 227f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 228dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 229dca4faebSVipul Pandya /* channel map */ 230636f9d37SVipul Pandya 231636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 232636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 233dcf7b6f5SKumar Sanghvi 234dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 235dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 236dcf7b6f5SKumar Sanghvi 237dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 238dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 239dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 240dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 241dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 242dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 243dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 244dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 245dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 246dcf7b6f5SKumar Sanghvi * present. 247dcf7b6f5SKumar Sanghvi */ 248dcf7b6f5SKumar Sanghvi int vlan_shift; 249dcf7b6f5SKumar Sanghvi int vnic_shift; 250dcf7b6f5SKumar Sanghvi int port_shift; 251dcf7b6f5SKumar Sanghvi int protocol_shift; 252f7917c00SJeff Kirsher }; 253f7917c00SJeff Kirsher 254f7917c00SJeff Kirsher struct vpd_params { 255f7917c00SJeff Kirsher unsigned int cclk; 256f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 257f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 258f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 259a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 260f7917c00SJeff Kirsher }; 261f7917c00SJeff Kirsher 262f7917c00SJeff Kirsher struct pci_params { 263f7917c00SJeff Kirsher unsigned char speed; 264f7917c00SJeff Kirsher unsigned char width; 265f7917c00SJeff Kirsher }; 266f7917c00SJeff Kirsher 267d14807ddSHariprasad Shenai #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) 268d14807ddSHariprasad Shenai #define CHELSIO_CHIP_FPGA 0x100 269d14807ddSHariprasad Shenai #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) 270d14807ddSHariprasad Shenai #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) 271d14807ddSHariprasad Shenai 272d14807ddSHariprasad Shenai #define CHELSIO_T4 0x4 273d14807ddSHariprasad Shenai #define CHELSIO_T5 0x5 274d14807ddSHariprasad Shenai 275d14807ddSHariprasad Shenai enum chip_type { 276d14807ddSHariprasad Shenai T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 277d14807ddSHariprasad Shenai T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), 278d14807ddSHariprasad Shenai T4_FIRST_REV = T4_A1, 279d14807ddSHariprasad Shenai T4_LAST_REV = T4_A2, 280d14807ddSHariprasad Shenai 281d14807ddSHariprasad Shenai T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 282d14807ddSHariprasad Shenai T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), 283d14807ddSHariprasad Shenai T5_FIRST_REV = T5_A0, 284d14807ddSHariprasad Shenai T5_LAST_REV = T5_A1, 285d14807ddSHariprasad Shenai }; 286d14807ddSHariprasad Shenai 287f7917c00SJeff Kirsher struct adapter_params { 288f7917c00SJeff Kirsher struct tp_params tp; 289f7917c00SJeff Kirsher struct vpd_params vpd; 290f7917c00SJeff Kirsher struct pci_params pci; 291f7917c00SJeff Kirsher 292f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 293f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 294f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 295f7917c00SJeff Kirsher 296f7917c00SJeff Kirsher unsigned int fw_vers; 297f7917c00SJeff Kirsher unsigned int tp_vers; 298f7917c00SJeff Kirsher u8 api_vers[7]; 299f7917c00SJeff Kirsher 300f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 301f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 302f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 303f7917c00SJeff Kirsher 304f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 305f7917c00SJeff Kirsher unsigned char portvec; 306d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 307f7917c00SJeff Kirsher unsigned char offload; 308f7917c00SJeff Kirsher 3099a4da2cdSVipul Pandya unsigned char bypass; 3109a4da2cdSVipul Pandya 311f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3121ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3134c2c5763SHariprasad Shenai 3144c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3154c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 316f7917c00SJeff Kirsher }; 317f7917c00SJeff Kirsher 31816e47624SHariprasad Shenai #include "t4fw_api.h" 31916e47624SHariprasad Shenai 32016e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 32116e47624SHariprasad Shenai FW_HDR_FW_VER_MAJOR_GET(chip##FW_VERSION_MAJOR) | \ 32216e47624SHariprasad Shenai FW_HDR_FW_VER_MINOR_GET(chip##FW_VERSION_MINOR) | \ 32316e47624SHariprasad Shenai FW_HDR_FW_VER_MICRO_GET(chip##FW_VERSION_MICRO) | \ 32416e47624SHariprasad Shenai FW_HDR_FW_VER_BUILD_GET(chip##FW_VERSION_BUILD)) 32516e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 32616e47624SHariprasad Shenai 32716e47624SHariprasad Shenai struct fw_info { 32816e47624SHariprasad Shenai u8 chip; 32916e47624SHariprasad Shenai char *fs_name; 33016e47624SHariprasad Shenai char *fw_mod_name; 33116e47624SHariprasad Shenai struct fw_hdr fw_hdr; 33216e47624SHariprasad Shenai }; 33316e47624SHariprasad Shenai 33416e47624SHariprasad Shenai 335f7917c00SJeff Kirsher struct trace_params { 336f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 337f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 338f7917c00SJeff Kirsher unsigned short snap_len; 339f7917c00SJeff Kirsher unsigned short min_len; 340f7917c00SJeff Kirsher unsigned char skip_ofst; 341f7917c00SJeff Kirsher unsigned char skip_len; 342f7917c00SJeff Kirsher unsigned char invert; 343f7917c00SJeff Kirsher unsigned char port; 344f7917c00SJeff Kirsher }; 345f7917c00SJeff Kirsher 346f7917c00SJeff Kirsher struct link_config { 347f7917c00SJeff Kirsher unsigned short supported; /* link capabilities */ 348f7917c00SJeff Kirsher unsigned short advertising; /* advertised capabilities */ 349f7917c00SJeff Kirsher unsigned short requested_speed; /* speed user has requested */ 350f7917c00SJeff Kirsher unsigned short speed; /* actual link speed */ 351f7917c00SJeff Kirsher unsigned char requested_fc; /* flow control user has requested */ 352f7917c00SJeff Kirsher unsigned char fc; /* actual link flow control */ 353f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 354f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 355f7917c00SJeff Kirsher }; 356f7917c00SJeff Kirsher 357f7917c00SJeff Kirsher #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16) 358f7917c00SJeff Kirsher 359f7917c00SJeff Kirsher enum { 360f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 361f7917c00SJeff Kirsher MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 362f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 363f7917c00SJeff Kirsher MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 364cf38be6dSHariprasad Shenai MAX_RDMA_CIQS = NCHAN, /* # of RDMA concentrator IQs */ 365cf38be6dSHariprasad Shenai MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */ 366f7917c00SJeff Kirsher }; 367f7917c00SJeff Kirsher 368f7917c00SJeff Kirsher enum { 369cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 370cf38be6dSHariprasad Shenai /* forwarded interrupts */ 371cf38be6dSHariprasad Shenai MAX_EGRQ = MAX_ETH_QSETS*2 + MAX_OFLD_QSETS*2 372cf38be6dSHariprasad Shenai + MAX_CTRL_QUEUES + MAX_RDMA_QUEUES + MAX_ISCSI_QUEUES, 373cf38be6dSHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES 374cf38be6dSHariprasad Shenai + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS, 375f7917c00SJeff Kirsher }; 376f7917c00SJeff Kirsher 377f7917c00SJeff Kirsher struct adapter; 378f7917c00SJeff Kirsher struct sge_rspq; 379f7917c00SJeff Kirsher 380688848b1SAnish Bhatt #include "cxgb4_dcb.h" 381688848b1SAnish Bhatt 382f7917c00SJeff Kirsher struct port_info { 383f7917c00SJeff Kirsher struct adapter *adapter; 384f7917c00SJeff Kirsher u16 viid; 385f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 386f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 387f7917c00SJeff Kirsher s8 mdio_addr; 388f7917c00SJeff Kirsher u8 port_type; 389f7917c00SJeff Kirsher u8 mod_type; 390f7917c00SJeff Kirsher u8 port_id; 391f7917c00SJeff Kirsher u8 tx_chan; 392f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 393f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 394f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 395f7917c00SJeff Kirsher u8 rss_mode; 396f7917c00SJeff Kirsher struct link_config link_cfg; 397f7917c00SJeff Kirsher u16 *rss; 398688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 399688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 400688848b1SAnish Bhatt #endif 401f7917c00SJeff Kirsher }; 402f7917c00SJeff Kirsher 403f7917c00SJeff Kirsher struct dentry; 404f7917c00SJeff Kirsher struct work_struct; 405f7917c00SJeff Kirsher 406f7917c00SJeff Kirsher enum { /* adapter flags */ 407f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 408144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 409144be3d9SGavin Shan USING_MSI = (1 << 2), 410144be3d9SGavin Shan USING_MSIX = (1 << 3), 411f7917c00SJeff Kirsher FW_OK = (1 << 4), 41213ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 41352367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 41452367a76SVipul Pandya MASTER_PF = (1 << 7), 41552367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 416f7917c00SJeff Kirsher }; 417f7917c00SJeff Kirsher 418f7917c00SJeff Kirsher struct rx_sw_desc; 419f7917c00SJeff Kirsher 420f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 421f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 422f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 423f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 424f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 425f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 426f7917c00SJeff Kirsher unsigned long large_alloc_failed; 427f7917c00SJeff Kirsher unsigned long starving; 428f7917c00SJeff Kirsher /* RO fields */ 429f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 430f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 431f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 432f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 433f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 434d63a6dcfSHariprasad Shenai u64 udb; /* BAR2 offset of User Doorbell area */ 435f7917c00SJeff Kirsher }; 436f7917c00SJeff Kirsher 437f7917c00SJeff Kirsher /* A packet gather list */ 438f7917c00SJeff Kirsher struct pkt_gl { 439e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 440f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 441f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 442f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 443f7917c00SJeff Kirsher }; 444f7917c00SJeff Kirsher 445f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 446f7917c00SJeff Kirsher const struct pkt_gl *gl); 447f7917c00SJeff Kirsher 448f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 449f7917c00SJeff Kirsher struct napi_struct napi; 450f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 451f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 452f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 453f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 454f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 455e553ec3fSHariprasad Shenai u8 adaptive_rx; 456f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 457f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 458f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 459f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 460f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 461f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 462f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 463f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 464d63a6dcfSHariprasad Shenai u64 udb; /* BAR2 offset of User Doorbell area */ 465f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 466f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 467f7917c00SJeff Kirsher struct adapter *adap; 468f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 469f7917c00SJeff Kirsher rspq_handler_t handler; 470f7917c00SJeff Kirsher }; 471f7917c00SJeff Kirsher 472f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 473f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 474f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 475f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 476f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 477f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 478f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 479f7917c00SJeff Kirsher }; 480f7917c00SJeff Kirsher 481f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 482f7917c00SJeff Kirsher struct sge_rspq rspq; 483f7917c00SJeff Kirsher struct sge_fl fl; 484f7917c00SJeff Kirsher struct sge_eth_stats stats; 485f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 486f7917c00SJeff Kirsher 487f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 488f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 489f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 490f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 491f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 492f7917c00SJeff Kirsher }; 493f7917c00SJeff Kirsher 494f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 495f7917c00SJeff Kirsher struct sge_rspq rspq; 496f7917c00SJeff Kirsher struct sge_fl fl; 497f7917c00SJeff Kirsher struct sge_ofld_stats stats; 498f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 499f7917c00SJeff Kirsher 500f7917c00SJeff Kirsher struct tx_desc { 501f7917c00SJeff Kirsher __be64 flit[8]; 502f7917c00SJeff Kirsher }; 503f7917c00SJeff Kirsher 504f7917c00SJeff Kirsher struct tx_sw_desc; 505f7917c00SJeff Kirsher 506f7917c00SJeff Kirsher struct sge_txq { 507f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 508f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 509f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 510f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 511f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 512f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 513f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 514f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 515f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 516f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 517f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 5183069ee9bSVipul Pandya spinlock_t db_lock; 5193069ee9bSVipul Pandya int db_disabled; 5203069ee9bSVipul Pandya unsigned short db_pidx; 52105eb2389SSteve Wise unsigned short db_pidx_inc; 522d63a6dcfSHariprasad Shenai u64 udb; /* BAR2 offset of User Doorbell area */ 523f7917c00SJeff Kirsher }; 524f7917c00SJeff Kirsher 525f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 526f7917c00SJeff Kirsher struct sge_txq q; 527f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 52810b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 52910b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 53010b00466SAnish Bhatt #endif 531f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 532f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 533f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 534f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 535f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 536f7917c00SJeff Kirsher 537f7917c00SJeff Kirsher struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 538f7917c00SJeff Kirsher struct sge_txq q; 539f7917c00SJeff Kirsher struct adapter *adap; 540f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 541f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 542f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 543f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 544f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 545f7917c00SJeff Kirsher 546f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 547f7917c00SJeff Kirsher struct sge_txq q; 548f7917c00SJeff Kirsher struct adapter *adap; 549f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 550f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 551f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 552f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 553f7917c00SJeff Kirsher 554f7917c00SJeff Kirsher struct sge { 555f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 556f7917c00SJeff Kirsher struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 557f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 558f7917c00SJeff Kirsher 559f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 560f7917c00SJeff Kirsher struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 561f7917c00SJeff Kirsher struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 562cf38be6dSHariprasad Shenai struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 563f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 564f7917c00SJeff Kirsher 565f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 566f7917c00SJeff Kirsher spinlock_t intrq_lock; 567f7917c00SJeff Kirsher 568f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 569f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 570f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 571f7917c00SJeff Kirsher u16 ofldqsets; /* # of active offload queue sets */ 572f7917c00SJeff Kirsher u16 rdmaqs; /* # of available RDMA Rx queues */ 573cf38be6dSHariprasad Shenai u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 574f7917c00SJeff Kirsher u16 ofld_rxq[MAX_OFLD_QSETS]; 575f7917c00SJeff Kirsher u16 rdma_rxq[NCHAN]; 576cf38be6dSHariprasad Shenai u16 rdma_ciq[NCHAN]; 577f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 578f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 57952367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 58052367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 58152367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 58252367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 58352367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 5840f4d201fSKumar Sanghvi 5850f4d201fSKumar Sanghvi /* State variables for detecting an SGE Ingress DMA hang */ 5860f4d201fSKumar Sanghvi unsigned int idma_1s_thresh;/* SGE same State Counter 1s threshold */ 5870f4d201fSKumar Sanghvi unsigned int idma_stalled[2];/* SGE synthesized stalled timers in HZ */ 5880f4d201fSKumar Sanghvi unsigned int idma_state[2]; /* SGE IDMA Hang detect state */ 5890f4d201fSKumar Sanghvi unsigned int idma_qid[2]; /* SGE IDMA Hung Ingress Queue ID */ 5900f4d201fSKumar Sanghvi 591f7917c00SJeff Kirsher unsigned int egr_start; 592f7917c00SJeff Kirsher unsigned int ingr_start; 593f7917c00SJeff Kirsher void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */ 594f7917c00SJeff Kirsher struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */ 595f7917c00SJeff Kirsher DECLARE_BITMAP(starving_fl, MAX_EGRQ); 596f7917c00SJeff Kirsher DECLARE_BITMAP(txq_maperr, MAX_EGRQ); 597f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 598f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 599f7917c00SJeff Kirsher }; 600f7917c00SJeff Kirsher 601f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 602f7917c00SJeff Kirsher #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 603f7917c00SJeff Kirsher #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 604cf38be6dSHariprasad Shenai #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 605f7917c00SJeff Kirsher 606f7917c00SJeff Kirsher struct l2t_data; 607f7917c00SJeff Kirsher 6082422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 6092422d9a3SSantosh Rastapur 6107d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 6117d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 6127d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 6132422d9a3SSantosh Rastapur */ 6147d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 6152422d9a3SSantosh Rastapur 6162422d9a3SSantosh Rastapur #endif 6172422d9a3SSantosh Rastapur 618f7917c00SJeff Kirsher struct adapter { 619f7917c00SJeff Kirsher void __iomem *regs; 62022adfe0aSSantosh Rastapur void __iomem *bar2; 6210abfd152SHariprasad Shenai u32 t4_bar0; 622f7917c00SJeff Kirsher struct pci_dev *pdev; 623f7917c00SJeff Kirsher struct device *pdev_dev; 6243069ee9bSVipul Pandya unsigned int mbox; 625f7917c00SJeff Kirsher unsigned int fn; 626f7917c00SJeff Kirsher unsigned int flags; 6272422d9a3SSantosh Rastapur enum chip_type chip; 628f7917c00SJeff Kirsher 629f7917c00SJeff Kirsher int msg_enable; 630f7917c00SJeff Kirsher 631f7917c00SJeff Kirsher struct adapter_params params; 632f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 633f7917c00SJeff Kirsher unsigned int swintr; 634f7917c00SJeff Kirsher 635f7917c00SJeff Kirsher unsigned int wol; 636f7917c00SJeff Kirsher 637f7917c00SJeff Kirsher struct { 638f7917c00SJeff Kirsher unsigned short vec; 639f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 640f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 641f7917c00SJeff Kirsher 642f7917c00SJeff Kirsher struct sge sge; 643f7917c00SJeff Kirsher 644f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 645f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 646f7917c00SJeff Kirsher 647793dad94SVipul Pandya u32 filter_mode; 648636f9d37SVipul Pandya unsigned int l2t_start; 649636f9d37SVipul Pandya unsigned int l2t_end; 650f7917c00SJeff Kirsher struct l2t_data *l2t; 651f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 652f7917c00SJeff Kirsher struct list_head list_node; 65301bcca68SVipul Pandya struct list_head rcu_node; 654f7917c00SJeff Kirsher 655f7917c00SJeff Kirsher struct tid_info tids; 656f7917c00SJeff Kirsher void **tid_release_head; 657f7917c00SJeff Kirsher spinlock_t tid_release_lock; 65829aaee65SAnish Bhatt struct workqueue_struct *workq; 659f7917c00SJeff Kirsher struct work_struct tid_release_task; 660881806bcSVipul Pandya struct work_struct db_full_task; 661881806bcSVipul Pandya struct work_struct db_drop_task; 662f7917c00SJeff Kirsher bool tid_release_task_busy; 663f7917c00SJeff Kirsher 664f7917c00SJeff Kirsher struct dentry *debugfs_root; 665f7917c00SJeff Kirsher 666f7917c00SJeff Kirsher spinlock_t stats_lock; 667fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 668f7917c00SJeff Kirsher }; 669f7917c00SJeff Kirsher 670f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 671f2b7e78dSVipul Pandya */ 672f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 673f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 674f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 675f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 676f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 677f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 678f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 679f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 680f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 681f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 682f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 683f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 684f2b7e78dSVipul Pandya 685f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 686f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 687f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 688f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 689f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 690f2b7e78dSVipul Pandya * matching rules are true. 691f2b7e78dSVipul Pandya * 692f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 693f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 694f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 695f2b7e78dSVipul Pandya * MPS match type) ... 696f2b7e78dSVipul Pandya * 697f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 698f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 699f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 700f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 701f2b7e78dSVipul Pandya */ 702f2b7e78dSVipul Pandya struct ch_filter_tuple { 703f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 704f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 705f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 706f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 707f2b7e78dSVipul Pandya * set of fields. 708f2b7e78dSVipul Pandya */ 709f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 710f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 711f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 712f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 713f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 714f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 715f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 716f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 717f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 718f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 719f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 720f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 721f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 722f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 723f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 724f2b7e78dSVipul Pandya 725f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 726f2b7e78dSVipul Pandya * available for field rules. 727f2b7e78dSVipul Pandya */ 728f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 729f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 730f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 731f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 732f2b7e78dSVipul Pandya }; 733f2b7e78dSVipul Pandya 734f2b7e78dSVipul Pandya /* A filter ioctl command. 735f2b7e78dSVipul Pandya */ 736f2b7e78dSVipul Pandya struct ch_filter_specification { 737f2b7e78dSVipul Pandya /* Administrative fields for filter. 738f2b7e78dSVipul Pandya */ 739f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 740f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 741f2b7e78dSVipul Pandya 742f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 743f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 744f2b7e78dSVipul Pandya */ 745f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 746f2b7e78dSVipul Pandya 747f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 748f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 749f2b7e78dSVipul Pandya * out as egress packets. 750f2b7e78dSVipul Pandya */ 751f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 752f2b7e78dSVipul Pandya 753f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 754f2b7e78dSVipul Pandya 755f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 756f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 757f2b7e78dSVipul Pandya 758f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 759f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 760f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 761f2b7e78dSVipul Pandya 762f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 763f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 764f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 765f2b7e78dSVipul Pandya */ 766f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 767f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 768f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 769f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 770f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 771f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 772f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 773f2b7e78dSVipul Pandya 774f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 775f2b7e78dSVipul Pandya */ 776f2b7e78dSVipul Pandya struct ch_filter_tuple val; 777f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 778f2b7e78dSVipul Pandya }; 779f2b7e78dSVipul Pandya 780f2b7e78dSVipul Pandya enum { 781f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 782f2b7e78dSVipul Pandya FILTER_DROP, 783f2b7e78dSVipul Pandya FILTER_SWITCH 784f2b7e78dSVipul Pandya }; 785f2b7e78dSVipul Pandya 786f2b7e78dSVipul Pandya enum { 787f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 788f2b7e78dSVipul Pandya VLAN_REMOVE, 789f2b7e78dSVipul Pandya VLAN_INSERT, 790f2b7e78dSVipul Pandya VLAN_REWRITE 791f2b7e78dSVipul Pandya }; 792f2b7e78dSVipul Pandya 7932422d9a3SSantosh Rastapur static inline int is_t5(enum chip_type chip) 7942422d9a3SSantosh Rastapur { 795d14807ddSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5; 7962422d9a3SSantosh Rastapur } 7972422d9a3SSantosh Rastapur 7982422d9a3SSantosh Rastapur static inline int is_t4(enum chip_type chip) 7992422d9a3SSantosh Rastapur { 800d14807ddSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; 8012422d9a3SSantosh Rastapur } 8022422d9a3SSantosh Rastapur 803f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 804f7917c00SJeff Kirsher { 805f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 806f7917c00SJeff Kirsher } 807f7917c00SJeff Kirsher 808f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 809f7917c00SJeff Kirsher { 810f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 811f7917c00SJeff Kirsher } 812f7917c00SJeff Kirsher 813f7917c00SJeff Kirsher #ifndef readq 814f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 815f7917c00SJeff Kirsher { 816f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 817f7917c00SJeff Kirsher } 818f7917c00SJeff Kirsher 819f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 820f7917c00SJeff Kirsher { 821f7917c00SJeff Kirsher writel(val, addr); 822f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 823f7917c00SJeff Kirsher } 824f7917c00SJeff Kirsher #endif 825f7917c00SJeff Kirsher 826f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 827f7917c00SJeff Kirsher { 828f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 829f7917c00SJeff Kirsher } 830f7917c00SJeff Kirsher 831f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 832f7917c00SJeff Kirsher { 833f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 834f7917c00SJeff Kirsher } 835f7917c00SJeff Kirsher 836f7917c00SJeff Kirsher /** 837f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 838f7917c00SJeff Kirsher * @dev: the netdev 839f7917c00SJeff Kirsher * 840f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 841f7917c00SJeff Kirsher */ 842f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 843f7917c00SJeff Kirsher { 844f7917c00SJeff Kirsher return netdev_priv(dev); 845f7917c00SJeff Kirsher } 846f7917c00SJeff Kirsher 847f7917c00SJeff Kirsher /** 848f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 849f7917c00SJeff Kirsher * @adap: the adapter 850f7917c00SJeff Kirsher * @idx: the port index 851f7917c00SJeff Kirsher * 852f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 853f7917c00SJeff Kirsher */ 854f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 855f7917c00SJeff Kirsher { 856f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 857f7917c00SJeff Kirsher } 858f7917c00SJeff Kirsher 859f7917c00SJeff Kirsher /** 860f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 861f7917c00SJeff Kirsher * @dev: the netdev 862f7917c00SJeff Kirsher * 863f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 864f7917c00SJeff Kirsher */ 865f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 866f7917c00SJeff Kirsher { 867f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 868f7917c00SJeff Kirsher } 869f7917c00SJeff Kirsher 870f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 871f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 872f7917c00SJeff Kirsher 873f7917c00SJeff Kirsher void *t4_alloc_mem(size_t size); 874f7917c00SJeff Kirsher 875f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 8765fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 877f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 878f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 879f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 880f7917c00SJeff Kirsher const struct pkt_gl *gl); 881f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 882f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 883f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 884f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 885f7917c00SJeff Kirsher struct sge_fl *fl, rspq_handler_t hnd); 886f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 887f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 888f7917c00SJeff Kirsher unsigned int iqid); 889f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 890f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 891f7917c00SJeff Kirsher unsigned int cmplqid); 892f7917c00SJeff Kirsher int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 893f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid); 894f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 89552367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 896f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 897f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 8983069ee9bSVipul Pandya extern int dbfifo_int_thresh; 899f7917c00SJeff Kirsher 900f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 901f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 902f7917c00SJeff Kirsher 9039a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 9049a4da2cdSVipul Pandya { 9059a4da2cdSVipul Pandya return adap->params.bypass; 9069a4da2cdSVipul Pandya } 9079a4da2cdSVipul Pandya 9089a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 9099a4da2cdSVipul Pandya { 9109a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 9119a4da2cdSVipul Pandya switch (device) { 9129a4da2cdSVipul Pandya case 0x440b: 9139a4da2cdSVipul Pandya case 0x440c: 9149a4da2cdSVipul Pandya return 1; 9159a4da2cdSVipul Pandya default: 9169a4da2cdSVipul Pandya return 0; 9179a4da2cdSVipul Pandya } 9189a4da2cdSVipul Pandya } 9199a4da2cdSVipul Pandya 920f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 921f7917c00SJeff Kirsher { 922f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 923f7917c00SJeff Kirsher } 924f7917c00SJeff Kirsher 925f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 926f7917c00SJeff Kirsher unsigned int us) 927f7917c00SJeff Kirsher { 928f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 929f7917c00SJeff Kirsher } 930f7917c00SJeff Kirsher 93152367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 93252367a76SVipul Pandya unsigned int ticks) 93352367a76SVipul Pandya { 93452367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 93552367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 93652367a76SVipul Pandya adapter->params.vpd.cclk); 93752367a76SVipul Pandya } 93852367a76SVipul Pandya 939f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 940f7917c00SJeff Kirsher u32 val); 941f7917c00SJeff Kirsher 942f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 943f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 944f7917c00SJeff Kirsher 945f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 946f7917c00SJeff Kirsher int size, void *rpl) 947f7917c00SJeff Kirsher { 948f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 949f7917c00SJeff Kirsher } 950f7917c00SJeff Kirsher 951f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 952f7917c00SJeff Kirsher int size, void *rpl) 953f7917c00SJeff Kirsher { 954f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 955f7917c00SJeff Kirsher } 956f7917c00SJeff Kirsher 95713ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 95813ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 95913ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 960f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 961f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 962f2b7e78dSVipul Pandya unsigned int start_idx); 9630abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 964f2b7e78dSVipul Pandya 965f2b7e78dSVipul Pandya struct fw_filter_wr; 966f2b7e78dSVipul Pandya 967f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 968f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 969f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 970f7917c00SJeff Kirsher 9718203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 972f7917c00SJeff Kirsher int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 973f7917c00SJeff Kirsher struct link_config *lc); 974f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 975fc5ab020SHariprasad Shenai 976fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 977fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 978fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 979fc5ab020SHariprasad Shenai __be32 *buf, int dir); 980fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 981fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 982fc5ab020SHariprasad Shenai { 983fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 984fc5ab020SHariprasad Shenai } 985fc5ab020SHariprasad Shenai 986f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 987636f9d37SVipul Pandya int get_vpd_params(struct adapter *adapter, struct vpd_params *p); 988f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 98922c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 99022c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 991636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 99216e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 99316e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 99416e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 99516e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 99616e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 997f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 998dcf7b6f5SKumar Sanghvi int t4_init_tp_params(struct adapter *adap); 999dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1000f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1001f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1002f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1003f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1004f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1005f7917c00SJeff Kirsher unsigned int flags); 100619dd37baSSantosh Rastapur int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 100719dd37baSSantosh Rastapur u64 *parity); 1008f7917c00SJeff Kirsher int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 1009f7917c00SJeff Kirsher u64 *parity); 101072aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1011f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1012f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1013636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1014636f9d37SVipul Pandya unsigned int mask, unsigned int val); 1015f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1016f7917c00SJeff Kirsher struct tp_tcp_stats *v6); 1017f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1018f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1019f7917c00SJeff Kirsher 1020f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1021f2b7e78dSVipul Pandya 1022f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1023f7917c00SJeff Kirsher const u8 *addr); 1024f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1025f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1026f7917c00SJeff Kirsher 1027f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1028f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1029f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1030f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1031f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1032636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1033636f9d37SVipul Pandya unsigned int cache_line_size); 1034636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1035f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1036f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1037f7917c00SJeff Kirsher u32 *val); 1038f7917c00SJeff Kirsher int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1039f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1040f7917c00SJeff Kirsher const u32 *val); 1041688848b1SAnish Bhatt int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox, 1042688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1043688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 1044688848b1SAnish Bhatt const u32 *val); 1045f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1046f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1047f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1048f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1049f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1050f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1051f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1052f7917c00SJeff Kirsher unsigned int *rss_size); 1053f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1054f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1055f7917c00SJeff Kirsher bool sleep_ok); 1056f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1057f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1058f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1059f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1060f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1061f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1062f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1063688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1064688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1065f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1066f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1067f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1068f7917c00SJeff Kirsher unsigned int nblinks); 1069f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1070f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1071f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1072f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1073f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1074f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1075f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1076f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1077f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1078f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1079f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1080f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1081f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1082f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1083881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1084881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 10858caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 10868caa1e84SVipul Pandya u32 addr, u32 val); 108768bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1088f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1089