1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4ce100b8bSAnish Bhatt * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 49f7917c00SJeff Kirsher #include <asm/io.h> 50f7917c00SJeff Kirsher #include "cxgb4_uld.h" 51f7917c00SJeff Kirsher 523069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 533069ee9bSVipul Pandya 54f7917c00SJeff Kirsher enum { 55f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 56f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 57f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 58f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 59a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 60f7917c00SJeff Kirsher }; 61f7917c00SJeff Kirsher 62f7917c00SJeff Kirsher enum { 63812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 64812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 65812034f1SHariprasad Shenai }; 66812034f1SHariprasad Shenai 67812034f1SHariprasad Shenai enum { 68f7917c00SJeff Kirsher MEM_EDC0, 69f7917c00SJeff Kirsher MEM_EDC1, 702422d9a3SSantosh Rastapur MEM_MC, 712422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 722422d9a3SSantosh Rastapur MEM_MC1 73f7917c00SJeff Kirsher }; 74f7917c00SJeff Kirsher 753069ee9bSVipul Pandya enum { 763eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 773eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 783069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 793069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 802422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 813eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 823eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 830abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 840abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 853069ee9bSVipul Pandya }; 863069ee9bSVipul Pandya 87f7917c00SJeff Kirsher enum dev_master { 88f7917c00SJeff Kirsher MASTER_CANT, 89f7917c00SJeff Kirsher MASTER_MAY, 90f7917c00SJeff Kirsher MASTER_MUST 91f7917c00SJeff Kirsher }; 92f7917c00SJeff Kirsher 93f7917c00SJeff Kirsher enum dev_state { 94f7917c00SJeff Kirsher DEV_STATE_UNINIT, 95f7917c00SJeff Kirsher DEV_STATE_INIT, 96f7917c00SJeff Kirsher DEV_STATE_ERR 97f7917c00SJeff Kirsher }; 98f7917c00SJeff Kirsher 99f7917c00SJeff Kirsher enum { 100f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 101f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 102f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 103f7917c00SJeff Kirsher }; 104f7917c00SJeff Kirsher 105f7917c00SJeff Kirsher struct port_stats { 106f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 107f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 108f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 109f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 110f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 111f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 112f7917c00SJeff Kirsher 113f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 114f7917c00SJeff Kirsher u64 tx_frames_65_127; 115f7917c00SJeff Kirsher u64 tx_frames_128_255; 116f7917c00SJeff Kirsher u64 tx_frames_256_511; 117f7917c00SJeff Kirsher u64 tx_frames_512_1023; 118f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 119f7917c00SJeff Kirsher u64 tx_frames_1519_max; 120f7917c00SJeff Kirsher 121f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 122f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 123f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 124f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 125f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 126f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 127f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 128f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 129f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 130f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 131f7917c00SJeff Kirsher 132f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 133f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 134f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 135f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 136f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 137f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 138f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 139f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 140f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 141f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 142f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 143f7917c00SJeff Kirsher 144f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 145f7917c00SJeff Kirsher u64 rx_frames_65_127; 146f7917c00SJeff Kirsher u64 rx_frames_128_255; 147f7917c00SJeff Kirsher u64 rx_frames_256_511; 148f7917c00SJeff Kirsher u64 rx_frames_512_1023; 149f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 150f7917c00SJeff Kirsher u64 rx_frames_1519_max; 151f7917c00SJeff Kirsher 152f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 153f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 154f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 155f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 156f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 157f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 158f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 159f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 160f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 161f7917c00SJeff Kirsher 162f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 163f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 164f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 165f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 166f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 167f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 168f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 169f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 170f7917c00SJeff Kirsher }; 171f7917c00SJeff Kirsher 172f7917c00SJeff Kirsher struct lb_port_stats { 173f7917c00SJeff Kirsher u64 octets; 174f7917c00SJeff Kirsher u64 frames; 175f7917c00SJeff Kirsher u64 bcast_frames; 176f7917c00SJeff Kirsher u64 mcast_frames; 177f7917c00SJeff Kirsher u64 ucast_frames; 178f7917c00SJeff Kirsher u64 error_frames; 179f7917c00SJeff Kirsher 180f7917c00SJeff Kirsher u64 frames_64; 181f7917c00SJeff Kirsher u64 frames_65_127; 182f7917c00SJeff Kirsher u64 frames_128_255; 183f7917c00SJeff Kirsher u64 frames_256_511; 184f7917c00SJeff Kirsher u64 frames_512_1023; 185f7917c00SJeff Kirsher u64 frames_1024_1518; 186f7917c00SJeff Kirsher u64 frames_1519_max; 187f7917c00SJeff Kirsher 188f7917c00SJeff Kirsher u64 drop; 189f7917c00SJeff Kirsher 190f7917c00SJeff Kirsher u64 ovflow0; 191f7917c00SJeff Kirsher u64 ovflow1; 192f7917c00SJeff Kirsher u64 ovflow2; 193f7917c00SJeff Kirsher u64 ovflow3; 194f7917c00SJeff Kirsher u64 trunc0; 195f7917c00SJeff Kirsher u64 trunc1; 196f7917c00SJeff Kirsher u64 trunc2; 197f7917c00SJeff Kirsher u64 trunc3; 198f7917c00SJeff Kirsher }; 199f7917c00SJeff Kirsher 200f7917c00SJeff Kirsher struct tp_tcp_stats { 201f7917c00SJeff Kirsher u32 tcpOutRsts; 202f7917c00SJeff Kirsher u64 tcpInSegs; 203f7917c00SJeff Kirsher u64 tcpOutSegs; 204f7917c00SJeff Kirsher u64 tcpRetransSegs; 205f7917c00SJeff Kirsher }; 206f7917c00SJeff Kirsher 207f7917c00SJeff Kirsher struct tp_err_stats { 208f7917c00SJeff Kirsher u32 macInErrs[4]; 209f7917c00SJeff Kirsher u32 hdrInErrs[4]; 210f7917c00SJeff Kirsher u32 tcpInErrs[4]; 211f7917c00SJeff Kirsher u32 tnlCongDrops[4]; 212f7917c00SJeff Kirsher u32 ofldChanDrops[4]; 213f7917c00SJeff Kirsher u32 tnlTxDrops[4]; 214f7917c00SJeff Kirsher u32 ofldVlanDrops[4]; 215f7917c00SJeff Kirsher u32 tcp6InErrs[4]; 216f7917c00SJeff Kirsher u32 ofldNoNeigh; 217f7917c00SJeff Kirsher u32 ofldCongDefer; 218f7917c00SJeff Kirsher }; 219f7917c00SJeff Kirsher 220e85c9a7aSHariprasad Shenai struct sge_params { 221e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 222e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 223e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 224e85c9a7aSHariprasad Shenai }; 225e85c9a7aSHariprasad Shenai 226f7917c00SJeff Kirsher struct tp_params { 227f7917c00SJeff Kirsher unsigned int ntxchan; /* # of Tx channels */ 228f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 2292d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 230dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 231dca4faebSVipul Pandya /* channel map */ 232636f9d37SVipul Pandya 233636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 234636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 235dcf7b6f5SKumar Sanghvi 236dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 237dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 238dcf7b6f5SKumar Sanghvi 239dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 240dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 241dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 242dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 243dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 244dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 245dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 246dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 247dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 248dcf7b6f5SKumar Sanghvi * present. 249dcf7b6f5SKumar Sanghvi */ 250dcf7b6f5SKumar Sanghvi int vlan_shift; 251dcf7b6f5SKumar Sanghvi int vnic_shift; 252dcf7b6f5SKumar Sanghvi int port_shift; 253dcf7b6f5SKumar Sanghvi int protocol_shift; 254f7917c00SJeff Kirsher }; 255f7917c00SJeff Kirsher 256f7917c00SJeff Kirsher struct vpd_params { 257f7917c00SJeff Kirsher unsigned int cclk; 258f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 259f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 260f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 261a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 262f7917c00SJeff Kirsher }; 263f7917c00SJeff Kirsher 264f7917c00SJeff Kirsher struct pci_params { 265f7917c00SJeff Kirsher unsigned char speed; 266f7917c00SJeff Kirsher unsigned char width; 267f7917c00SJeff Kirsher }; 268f7917c00SJeff Kirsher 269d14807ddSHariprasad Shenai #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) 270d14807ddSHariprasad Shenai #define CHELSIO_CHIP_FPGA 0x100 271d14807ddSHariprasad Shenai #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) 272d14807ddSHariprasad Shenai #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) 273d14807ddSHariprasad Shenai 274d14807ddSHariprasad Shenai #define CHELSIO_T4 0x4 275d14807ddSHariprasad Shenai #define CHELSIO_T5 0x5 276d14807ddSHariprasad Shenai 277d14807ddSHariprasad Shenai enum chip_type { 278d14807ddSHariprasad Shenai T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 279d14807ddSHariprasad Shenai T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), 280d14807ddSHariprasad Shenai T4_FIRST_REV = T4_A1, 281d14807ddSHariprasad Shenai T4_LAST_REV = T4_A2, 282d14807ddSHariprasad Shenai 283d14807ddSHariprasad Shenai T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 284d14807ddSHariprasad Shenai T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), 285d14807ddSHariprasad Shenai T5_FIRST_REV = T5_A0, 286d14807ddSHariprasad Shenai T5_LAST_REV = T5_A1, 287d14807ddSHariprasad Shenai }; 288d14807ddSHariprasad Shenai 28949aa284fSHariprasad Shenai struct devlog_params { 29049aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 29149aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 29249aa284fSHariprasad Shenai u32 size; /* size of log */ 29349aa284fSHariprasad Shenai }; 29449aa284fSHariprasad Shenai 295f7917c00SJeff Kirsher struct adapter_params { 296e85c9a7aSHariprasad Shenai struct sge_params sge; 297f7917c00SJeff Kirsher struct tp_params tp; 298f7917c00SJeff Kirsher struct vpd_params vpd; 299f7917c00SJeff Kirsher struct pci_params pci; 30049aa284fSHariprasad Shenai struct devlog_params devlog; 30149aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 302f7917c00SJeff Kirsher 303f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 304f1ff24aaSHariprasad Shenai 305f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 306f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 307f7917c00SJeff Kirsher unsigned int sf_fw_start; /* start of FW image in flash */ 308f7917c00SJeff Kirsher 309f7917c00SJeff Kirsher unsigned int fw_vers; 310f7917c00SJeff Kirsher unsigned int tp_vers; 311f7917c00SJeff Kirsher u8 api_vers[7]; 312f7917c00SJeff Kirsher 313f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 314f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 315f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 316f7917c00SJeff Kirsher 317f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 318f7917c00SJeff Kirsher unsigned char portvec; 319d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 320f7917c00SJeff Kirsher unsigned char offload; 321f7917c00SJeff Kirsher 3229a4da2cdSVipul Pandya unsigned char bypass; 3239a4da2cdSVipul Pandya 324f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 3251ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 3264c2c5763SHariprasad Shenai 3274c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 3284c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 329f7917c00SJeff Kirsher }; 330f7917c00SJeff Kirsher 33116e47624SHariprasad Shenai #include "t4fw_api.h" 33216e47624SHariprasad Shenai 33316e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 334b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 335b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 336b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 337b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 33816e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 33916e47624SHariprasad Shenai 34016e47624SHariprasad Shenai struct fw_info { 34116e47624SHariprasad Shenai u8 chip; 34216e47624SHariprasad Shenai char *fs_name; 34316e47624SHariprasad Shenai char *fw_mod_name; 34416e47624SHariprasad Shenai struct fw_hdr fw_hdr; 34516e47624SHariprasad Shenai }; 34616e47624SHariprasad Shenai 34716e47624SHariprasad Shenai 348f7917c00SJeff Kirsher struct trace_params { 349f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 350f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 351f7917c00SJeff Kirsher unsigned short snap_len; 352f7917c00SJeff Kirsher unsigned short min_len; 353f7917c00SJeff Kirsher unsigned char skip_ofst; 354f7917c00SJeff Kirsher unsigned char skip_len; 355f7917c00SJeff Kirsher unsigned char invert; 356f7917c00SJeff Kirsher unsigned char port; 357f7917c00SJeff Kirsher }; 358f7917c00SJeff Kirsher 359f7917c00SJeff Kirsher struct link_config { 360f7917c00SJeff Kirsher unsigned short supported; /* link capabilities */ 361f7917c00SJeff Kirsher unsigned short advertising; /* advertised capabilities */ 362f7917c00SJeff Kirsher unsigned short requested_speed; /* speed user has requested */ 363f7917c00SJeff Kirsher unsigned short speed; /* actual link speed */ 364f7917c00SJeff Kirsher unsigned char requested_fc; /* flow control user has requested */ 365f7917c00SJeff Kirsher unsigned char fc; /* actual link flow control */ 366f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 367f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 368f7917c00SJeff Kirsher }; 369f7917c00SJeff Kirsher 370e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 371f7917c00SJeff Kirsher 372f7917c00SJeff Kirsher enum { 373f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 374f7917c00SJeff Kirsher MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */ 375f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 376f7917c00SJeff Kirsher MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */ 377f36e58e5SHariprasad Shenai MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */ 378cf38be6dSHariprasad Shenai MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */ 379f7917c00SJeff Kirsher }; 380f7917c00SJeff Kirsher 381f7917c00SJeff Kirsher enum { 382812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 383812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 384812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 385812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 386812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 387812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 388812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 389812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 390812034f1SHariprasad Shenai }; 391812034f1SHariprasad Shenai 392812034f1SHariprasad Shenai enum { 393cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 394cf38be6dSHariprasad Shenai /* forwarded interrupts */ 395cf38be6dSHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES 396cf38be6dSHariprasad Shenai + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS, 397f7917c00SJeff Kirsher }; 398f7917c00SJeff Kirsher 399f7917c00SJeff Kirsher struct adapter; 400f7917c00SJeff Kirsher struct sge_rspq; 401f7917c00SJeff Kirsher 402688848b1SAnish Bhatt #include "cxgb4_dcb.h" 403688848b1SAnish Bhatt 40476fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 40576fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 40676fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 40776fed8a9SVarun Prakash 408f7917c00SJeff Kirsher struct port_info { 409f7917c00SJeff Kirsher struct adapter *adapter; 410f7917c00SJeff Kirsher u16 viid; 411f7917c00SJeff Kirsher s16 xact_addr_filt; /* index of exact MAC address filter */ 412f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 413f7917c00SJeff Kirsher s8 mdio_addr; 41440e9de4bSHariprasad Shenai enum fw_port_type port_type; 415f7917c00SJeff Kirsher u8 mod_type; 416f7917c00SJeff Kirsher u8 port_id; 417f7917c00SJeff Kirsher u8 tx_chan; 418f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 419f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 420f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 421f7917c00SJeff Kirsher u8 rss_mode; 422f7917c00SJeff Kirsher struct link_config link_cfg; 423f7917c00SJeff Kirsher u16 *rss; 424688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 425688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 426688848b1SAnish Bhatt #endif 42776fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 42876fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 42976fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 430f7917c00SJeff Kirsher }; 431f7917c00SJeff Kirsher 432f7917c00SJeff Kirsher struct dentry; 433f7917c00SJeff Kirsher struct work_struct; 434f7917c00SJeff Kirsher 435f7917c00SJeff Kirsher enum { /* adapter flags */ 436f7917c00SJeff Kirsher FULL_INIT_DONE = (1 << 0), 437144be3d9SGavin Shan DEV_ENABLED = (1 << 1), 438144be3d9SGavin Shan USING_MSI = (1 << 2), 439144be3d9SGavin Shan USING_MSIX = (1 << 3), 440f7917c00SJeff Kirsher FW_OK = (1 << 4), 44113ee15d3SVipul Pandya RSS_TNLALLLOOKUP = (1 << 5), 44252367a76SVipul Pandya USING_SOFT_PARAMS = (1 << 6), 44352367a76SVipul Pandya MASTER_PF = (1 << 7), 44452367a76SVipul Pandya FW_OFLD_CONN = (1 << 9), 445f7917c00SJeff Kirsher }; 446f7917c00SJeff Kirsher 447f7917c00SJeff Kirsher struct rx_sw_desc; 448f7917c00SJeff Kirsher 449f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 450f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 451f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 452f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 453f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 454f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 455f7917c00SJeff Kirsher unsigned long large_alloc_failed; 456f7917c00SJeff Kirsher unsigned long starving; 457f7917c00SJeff Kirsher /* RO fields */ 458f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 459f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 460f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 461f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 462f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 463df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 464df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 465f7917c00SJeff Kirsher }; 466f7917c00SJeff Kirsher 467f7917c00SJeff Kirsher /* A packet gather list */ 468f7917c00SJeff Kirsher struct pkt_gl { 469e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 470f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 471f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 472f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 473f7917c00SJeff Kirsher }; 474f7917c00SJeff Kirsher 475f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 476f7917c00SJeff Kirsher const struct pkt_gl *gl); 477f7917c00SJeff Kirsher 478f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 479f7917c00SJeff Kirsher struct napi_struct napi; 480f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 481f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 482f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 483f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 484f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 485e553ec3fSHariprasad Shenai u8 adaptive_rx; 486f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 487f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 488f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 489f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 490f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 491f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 492f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 493f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 494df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 495df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 496f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 497f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 498f7917c00SJeff Kirsher struct adapter *adap; 499f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 500f7917c00SJeff Kirsher rspq_handler_t handler; 5013a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 5023a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_IDLE 0 5033a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */ 5043a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */ 5053a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */ 5063a336cb1SHariprasad Shenai #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */ 5073a336cb1SHariprasad Shenai #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \ 5083a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5093a336cb1SHariprasad Shenai #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \ 5103a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL) 5113a336cb1SHariprasad Shenai #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \ 5123a336cb1SHariprasad Shenai CXGB_POLL_STATE_POLL_YIELD) 5133a336cb1SHariprasad Shenai unsigned int bpoll_state; 5143a336cb1SHariprasad Shenai spinlock_t bpoll_lock; /* lock for busy poll */ 5153a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 5163a336cb1SHariprasad Shenai 517f7917c00SJeff Kirsher }; 518f7917c00SJeff Kirsher 519f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 520f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 521f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 522f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 523f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 524f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 525f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 526f7917c00SJeff Kirsher }; 527f7917c00SJeff Kirsher 528f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 529f7917c00SJeff Kirsher struct sge_rspq rspq; 530f7917c00SJeff Kirsher struct sge_fl fl; 531f7917c00SJeff Kirsher struct sge_eth_stats stats; 532f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 533f7917c00SJeff Kirsher 534f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 535f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 536f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 537f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 538f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 539f7917c00SJeff Kirsher }; 540f7917c00SJeff Kirsher 541f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 542f7917c00SJeff Kirsher struct sge_rspq rspq; 543f7917c00SJeff Kirsher struct sge_fl fl; 544f7917c00SJeff Kirsher struct sge_ofld_stats stats; 545f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 546f7917c00SJeff Kirsher 547f7917c00SJeff Kirsher struct tx_desc { 548f7917c00SJeff Kirsher __be64 flit[8]; 549f7917c00SJeff Kirsher }; 550f7917c00SJeff Kirsher 551f7917c00SJeff Kirsher struct tx_sw_desc; 552f7917c00SJeff Kirsher 553f7917c00SJeff Kirsher struct sge_txq { 554f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 555f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 556f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 557f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 558f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 559f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 560f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 561f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 562f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 563f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 564f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 5653069ee9bSVipul Pandya spinlock_t db_lock; 5663069ee9bSVipul Pandya int db_disabled; 5673069ee9bSVipul Pandya unsigned short db_pidx; 56805eb2389SSteve Wise unsigned short db_pidx_inc; 569df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 570df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 571f7917c00SJeff Kirsher }; 572f7917c00SJeff Kirsher 573f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 574f7917c00SJeff Kirsher struct sge_txq q; 575f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 57610b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 57710b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 57810b00466SAnish Bhatt #endif 579f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 580f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 581f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 582f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 583f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 584f7917c00SJeff Kirsher 585f7917c00SJeff Kirsher struct sge_ofld_txq { /* state for an SGE offload Tx queue */ 586f7917c00SJeff Kirsher struct sge_txq q; 587f7917c00SJeff Kirsher struct adapter *adap; 588f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 589f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 590f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 591f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 592f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 593f7917c00SJeff Kirsher 594f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 595f7917c00SJeff Kirsher struct sge_txq q; 596f7917c00SJeff Kirsher struct adapter *adap; 597f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 598f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 599f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 600f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 601f7917c00SJeff Kirsher 602f7917c00SJeff Kirsher struct sge { 603f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 604f7917c00SJeff Kirsher struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS]; 605f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 606f7917c00SJeff Kirsher 607f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 608f7917c00SJeff Kirsher struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS]; 609f7917c00SJeff Kirsher struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES]; 610cf38be6dSHariprasad Shenai struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS]; 611f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 612f7917c00SJeff Kirsher 613f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 614f7917c00SJeff Kirsher spinlock_t intrq_lock; 615f7917c00SJeff Kirsher 616f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 617f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 618f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 619f7917c00SJeff Kirsher u16 ofldqsets; /* # of active offload queue sets */ 620f7917c00SJeff Kirsher u16 rdmaqs; /* # of available RDMA Rx queues */ 621cf38be6dSHariprasad Shenai u16 rdmaciqs; /* # of available RDMA concentrator IQs */ 622f7917c00SJeff Kirsher u16 ofld_rxq[MAX_OFLD_QSETS]; 623f36e58e5SHariprasad Shenai u16 rdma_rxq[MAX_RDMA_QUEUES]; 624f36e58e5SHariprasad Shenai u16 rdma_ciq[MAX_RDMA_CIQS]; 625f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 626f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 62752367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 62852367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 62952367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 63052367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 63152367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 6320f4d201fSKumar Sanghvi 6330f4d201fSKumar Sanghvi /* State variables for detecting an SGE Ingress DMA hang */ 6340f4d201fSKumar Sanghvi unsigned int idma_1s_thresh;/* SGE same State Counter 1s threshold */ 6350f4d201fSKumar Sanghvi unsigned int idma_stalled[2];/* SGE synthesized stalled timers in HZ */ 6360f4d201fSKumar Sanghvi unsigned int idma_state[2]; /* SGE IDMA Hang detect state */ 6370f4d201fSKumar Sanghvi unsigned int idma_qid[2]; /* SGE IDMA Hung Ingress Queue ID */ 6380f4d201fSKumar Sanghvi 639f7917c00SJeff Kirsher unsigned int egr_start; 6404b8e27a8SHariprasad Shenai unsigned int egr_sz; 641f7917c00SJeff Kirsher unsigned int ingr_start; 6424b8e27a8SHariprasad Shenai unsigned int ingr_sz; 6434b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 6444b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 6454b8e27a8SHariprasad Shenai unsigned long *starving_fl; 6464b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 647f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 648f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 649f7917c00SJeff Kirsher }; 650f7917c00SJeff Kirsher 651f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 652f7917c00SJeff Kirsher #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 653f7917c00SJeff Kirsher #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++) 654cf38be6dSHariprasad Shenai #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++) 655f7917c00SJeff Kirsher 656f7917c00SJeff Kirsher struct l2t_data; 657f7917c00SJeff Kirsher 6582422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 6592422d9a3SSantosh Rastapur 6607d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 6617d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 6627d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 6632422d9a3SSantosh Rastapur */ 6647d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 6652422d9a3SSantosh Rastapur 6662422d9a3SSantosh Rastapur #endif 6672422d9a3SSantosh Rastapur 668f7917c00SJeff Kirsher struct adapter { 669f7917c00SJeff Kirsher void __iomem *regs; 67022adfe0aSSantosh Rastapur void __iomem *bar2; 6710abfd152SHariprasad Shenai u32 t4_bar0; 672f7917c00SJeff Kirsher struct pci_dev *pdev; 673f7917c00SJeff Kirsher struct device *pdev_dev; 6743069ee9bSVipul Pandya unsigned int mbox; 675f7917c00SJeff Kirsher unsigned int fn; 676f7917c00SJeff Kirsher unsigned int flags; 6772422d9a3SSantosh Rastapur enum chip_type chip; 678f7917c00SJeff Kirsher 679f7917c00SJeff Kirsher int msg_enable; 680f7917c00SJeff Kirsher 681f7917c00SJeff Kirsher struct adapter_params params; 682f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 683f7917c00SJeff Kirsher unsigned int swintr; 684f7917c00SJeff Kirsher 685f7917c00SJeff Kirsher unsigned int wol; 686f7917c00SJeff Kirsher 687f7917c00SJeff Kirsher struct { 688f7917c00SJeff Kirsher unsigned short vec; 689f7917c00SJeff Kirsher char desc[IFNAMSIZ + 10]; 690f7917c00SJeff Kirsher } msix_info[MAX_INGQ + 1]; 691f7917c00SJeff Kirsher 692f7917c00SJeff Kirsher struct sge sge; 693f7917c00SJeff Kirsher 694f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 695f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 696f7917c00SJeff Kirsher 697793dad94SVipul Pandya u32 filter_mode; 698636f9d37SVipul Pandya unsigned int l2t_start; 699636f9d37SVipul Pandya unsigned int l2t_end; 700f7917c00SJeff Kirsher struct l2t_data *l2t; 701b5a02f50SAnish Bhatt unsigned int clipt_start; 702b5a02f50SAnish Bhatt unsigned int clipt_end; 703b5a02f50SAnish Bhatt struct clip_tbl *clipt; 704f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 705f7917c00SJeff Kirsher struct list_head list_node; 70601bcca68SVipul Pandya struct list_head rcu_node; 707f7917c00SJeff Kirsher 708f7917c00SJeff Kirsher struct tid_info tids; 709f7917c00SJeff Kirsher void **tid_release_head; 710f7917c00SJeff Kirsher spinlock_t tid_release_lock; 71129aaee65SAnish Bhatt struct workqueue_struct *workq; 712f7917c00SJeff Kirsher struct work_struct tid_release_task; 713881806bcSVipul Pandya struct work_struct db_full_task; 714881806bcSVipul Pandya struct work_struct db_drop_task; 715f7917c00SJeff Kirsher bool tid_release_task_busy; 716f7917c00SJeff Kirsher 717f7917c00SJeff Kirsher struct dentry *debugfs_root; 718f7917c00SJeff Kirsher 719f7917c00SJeff Kirsher spinlock_t stats_lock; 720fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 721f7917c00SJeff Kirsher }; 722f7917c00SJeff Kirsher 723f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 724f2b7e78dSVipul Pandya */ 725f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 726f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 727f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 728f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 729f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 730f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 731f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 732f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 733f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 734f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 735f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 736f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 737f2b7e78dSVipul Pandya 738f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 739f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 740f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 741f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 742f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 743f2b7e78dSVipul Pandya * matching rules are true. 744f2b7e78dSVipul Pandya * 745f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 746f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 747f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 748f2b7e78dSVipul Pandya * MPS match type) ... 749f2b7e78dSVipul Pandya * 750f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 751f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 752f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 753f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 754f2b7e78dSVipul Pandya */ 755f2b7e78dSVipul Pandya struct ch_filter_tuple { 756f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 757f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 758f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 759f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 760f2b7e78dSVipul Pandya * set of fields. 761f2b7e78dSVipul Pandya */ 762f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 763f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 764f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 765f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 766f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 767f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 768f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 769f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 770f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 771f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 772f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 773f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 774f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 775f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 776f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 777f2b7e78dSVipul Pandya 778f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 779f2b7e78dSVipul Pandya * available for field rules. 780f2b7e78dSVipul Pandya */ 781f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 782f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 783f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 784f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 785f2b7e78dSVipul Pandya }; 786f2b7e78dSVipul Pandya 787f2b7e78dSVipul Pandya /* A filter ioctl command. 788f2b7e78dSVipul Pandya */ 789f2b7e78dSVipul Pandya struct ch_filter_specification { 790f2b7e78dSVipul Pandya /* Administrative fields for filter. 791f2b7e78dSVipul Pandya */ 792f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 793f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 794f2b7e78dSVipul Pandya 795f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 796f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 797f2b7e78dSVipul Pandya */ 798f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 799f2b7e78dSVipul Pandya 800f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 801f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 802f2b7e78dSVipul Pandya * out as egress packets. 803f2b7e78dSVipul Pandya */ 804f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 805f2b7e78dSVipul Pandya 806f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 807f2b7e78dSVipul Pandya 808f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 809f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 810f2b7e78dSVipul Pandya 811f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 812f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 813f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 814f2b7e78dSVipul Pandya 815f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 816f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 817f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 818f2b7e78dSVipul Pandya */ 819f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 820f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 821f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 822f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 823f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 824f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 825f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 826f2b7e78dSVipul Pandya 827f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 828f2b7e78dSVipul Pandya */ 829f2b7e78dSVipul Pandya struct ch_filter_tuple val; 830f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 831f2b7e78dSVipul Pandya }; 832f2b7e78dSVipul Pandya 833f2b7e78dSVipul Pandya enum { 834f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 835f2b7e78dSVipul Pandya FILTER_DROP, 836f2b7e78dSVipul Pandya FILTER_SWITCH 837f2b7e78dSVipul Pandya }; 838f2b7e78dSVipul Pandya 839f2b7e78dSVipul Pandya enum { 840f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 841f2b7e78dSVipul Pandya VLAN_REMOVE, 842f2b7e78dSVipul Pandya VLAN_INSERT, 843f2b7e78dSVipul Pandya VLAN_REWRITE 844f2b7e78dSVipul Pandya }; 845f2b7e78dSVipul Pandya 8462422d9a3SSantosh Rastapur static inline int is_t5(enum chip_type chip) 8472422d9a3SSantosh Rastapur { 848d14807ddSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5; 8492422d9a3SSantosh Rastapur } 8502422d9a3SSantosh Rastapur 8512422d9a3SSantosh Rastapur static inline int is_t4(enum chip_type chip) 8522422d9a3SSantosh Rastapur { 853d14807ddSHariprasad Shenai return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; 8542422d9a3SSantosh Rastapur } 8552422d9a3SSantosh Rastapur 856f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 857f7917c00SJeff Kirsher { 858f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 859f7917c00SJeff Kirsher } 860f7917c00SJeff Kirsher 861f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 862f7917c00SJeff Kirsher { 863f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 864f7917c00SJeff Kirsher } 865f7917c00SJeff Kirsher 866f7917c00SJeff Kirsher #ifndef readq 867f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 868f7917c00SJeff Kirsher { 869f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 870f7917c00SJeff Kirsher } 871f7917c00SJeff Kirsher 872f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 873f7917c00SJeff Kirsher { 874f7917c00SJeff Kirsher writel(val, addr); 875f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 876f7917c00SJeff Kirsher } 877f7917c00SJeff Kirsher #endif 878f7917c00SJeff Kirsher 879f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 880f7917c00SJeff Kirsher { 881f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 882f7917c00SJeff Kirsher } 883f7917c00SJeff Kirsher 884f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 885f7917c00SJeff Kirsher { 886f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 887f7917c00SJeff Kirsher } 888f7917c00SJeff Kirsher 889f7917c00SJeff Kirsher /** 890f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 891f7917c00SJeff Kirsher * @dev: the netdev 892f7917c00SJeff Kirsher * 893f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 894f7917c00SJeff Kirsher */ 895f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 896f7917c00SJeff Kirsher { 897f7917c00SJeff Kirsher return netdev_priv(dev); 898f7917c00SJeff Kirsher } 899f7917c00SJeff Kirsher 900f7917c00SJeff Kirsher /** 901f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 902f7917c00SJeff Kirsher * @adap: the adapter 903f7917c00SJeff Kirsher * @idx: the port index 904f7917c00SJeff Kirsher * 905f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 906f7917c00SJeff Kirsher */ 907f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 908f7917c00SJeff Kirsher { 909f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 910f7917c00SJeff Kirsher } 911f7917c00SJeff Kirsher 912f7917c00SJeff Kirsher /** 913f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 914f7917c00SJeff Kirsher * @dev: the netdev 915f7917c00SJeff Kirsher * 916f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 917f7917c00SJeff Kirsher */ 918f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 919f7917c00SJeff Kirsher { 920f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 921f7917c00SJeff Kirsher } 922f7917c00SJeff Kirsher 9233a336cb1SHariprasad Shenai #ifdef CONFIG_NET_RX_BUSY_POLL 9243a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 9253a336cb1SHariprasad Shenai { 9263a336cb1SHariprasad Shenai spin_lock_init(&q->bpoll_lock); 9273a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 9283a336cb1SHariprasad Shenai } 9293a336cb1SHariprasad Shenai 9303a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 9313a336cb1SHariprasad Shenai { 9323a336cb1SHariprasad Shenai bool rc = true; 9333a336cb1SHariprasad Shenai 9343a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 9353a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 9363a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD; 9373a336cb1SHariprasad Shenai rc = false; 9383a336cb1SHariprasad Shenai } else { 9393a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_NAPI; 9403a336cb1SHariprasad Shenai } 9413a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 9423a336cb1SHariprasad Shenai return rc; 9433a336cb1SHariprasad Shenai } 9443a336cb1SHariprasad Shenai 9453a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 9463a336cb1SHariprasad Shenai { 9473a336cb1SHariprasad Shenai bool rc = false; 9483a336cb1SHariprasad Shenai 9493a336cb1SHariprasad Shenai spin_lock(&q->bpoll_lock); 9503a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 9513a336cb1SHariprasad Shenai rc = true; 9523a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 9533a336cb1SHariprasad Shenai spin_unlock(&q->bpoll_lock); 9543a336cb1SHariprasad Shenai return rc; 9553a336cb1SHariprasad Shenai } 9563a336cb1SHariprasad Shenai 9573a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 9583a336cb1SHariprasad Shenai { 9593a336cb1SHariprasad Shenai bool rc = true; 9603a336cb1SHariprasad Shenai 9613a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 9623a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_LOCKED) { 9633a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD; 9643a336cb1SHariprasad Shenai rc = false; 9653a336cb1SHariprasad Shenai } else { 9663a336cb1SHariprasad Shenai q->bpoll_state |= CXGB_POLL_STATE_POLL; 9673a336cb1SHariprasad Shenai } 9683a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 9693a336cb1SHariprasad Shenai return rc; 9703a336cb1SHariprasad Shenai } 9713a336cb1SHariprasad Shenai 9723a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 9733a336cb1SHariprasad Shenai { 9743a336cb1SHariprasad Shenai bool rc = false; 9753a336cb1SHariprasad Shenai 9763a336cb1SHariprasad Shenai spin_lock_bh(&q->bpoll_lock); 9773a336cb1SHariprasad Shenai if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD) 9783a336cb1SHariprasad Shenai rc = true; 9793a336cb1SHariprasad Shenai q->bpoll_state = CXGB_POLL_STATE_IDLE; 9803a336cb1SHariprasad Shenai spin_unlock_bh(&q->bpoll_lock); 9813a336cb1SHariprasad Shenai return rc; 9823a336cb1SHariprasad Shenai } 9833a336cb1SHariprasad Shenai 9843a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 9853a336cb1SHariprasad Shenai { 9863a336cb1SHariprasad Shenai return q->bpoll_state & CXGB_POLL_USER_PEND; 9873a336cb1SHariprasad Shenai } 9883a336cb1SHariprasad Shenai #else 9893a336cb1SHariprasad Shenai static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q) 9903a336cb1SHariprasad Shenai { 9913a336cb1SHariprasad Shenai } 9923a336cb1SHariprasad Shenai 9933a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_napi(struct sge_rspq *q) 9943a336cb1SHariprasad Shenai { 9953a336cb1SHariprasad Shenai return true; 9963a336cb1SHariprasad Shenai } 9973a336cb1SHariprasad Shenai 9983a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q) 9993a336cb1SHariprasad Shenai { 10003a336cb1SHariprasad Shenai return false; 10013a336cb1SHariprasad Shenai } 10023a336cb1SHariprasad Shenai 10033a336cb1SHariprasad Shenai static inline bool cxgb_poll_lock_poll(struct sge_rspq *q) 10043a336cb1SHariprasad Shenai { 10053a336cb1SHariprasad Shenai return false; 10063a336cb1SHariprasad Shenai } 10073a336cb1SHariprasad Shenai 10083a336cb1SHariprasad Shenai static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q) 10093a336cb1SHariprasad Shenai { 10103a336cb1SHariprasad Shenai return false; 10113a336cb1SHariprasad Shenai } 10123a336cb1SHariprasad Shenai 10133a336cb1SHariprasad Shenai static inline bool cxgb_poll_busy_polling(struct sge_rspq *q) 10143a336cb1SHariprasad Shenai { 10153a336cb1SHariprasad Shenai return false; 10163a336cb1SHariprasad Shenai } 10173a336cb1SHariprasad Shenai #endif /* CONFIG_NET_RX_BUSY_POLL */ 10183a336cb1SHariprasad Shenai 1019812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1020812034f1SHariprasad Shenai * - bits 0..9: chip version 1021812034f1SHariprasad Shenai * - bits 10..15: chip revision 1022812034f1SHariprasad Shenai * - bits 16..23: register dump version 1023812034f1SHariprasad Shenai */ 1024812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1025812034f1SHariprasad Shenai { 1026812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1027812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1028812034f1SHariprasad Shenai } 1029812034f1SHariprasad Shenai 1030812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1031812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1032812034f1SHariprasad Shenai const struct sge_rspq *q) 1033812034f1SHariprasad Shenai { 1034812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1035812034f1SHariprasad Shenai 1036812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1037812034f1SHariprasad Shenai } 1038812034f1SHariprasad Shenai 1039812034f1SHariprasad Shenai /* driver version & name used for ethtool_drvinfo */ 1040812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1041812034f1SHariprasad Shenai extern const char cxgb4_driver_version[]; 1042812034f1SHariprasad Shenai 1043f7917c00SJeff Kirsher void t4_os_portmod_changed(const struct adapter *adap, int port_id); 1044f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1045f7917c00SJeff Kirsher 1046f7917c00SJeff Kirsher void *t4_alloc_mem(size_t size); 1047f7917c00SJeff Kirsher 1048f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 10495fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1050f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1051f7917c00SJeff Kirsher netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev); 1052f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1053f7917c00SJeff Kirsher const struct pkt_gl *gl); 1054f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1055f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1056f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1057f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 1058145ef8a5SHariprasad Shenai struct sge_fl *fl, rspq_handler_t hnd, int cong); 1059f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1060f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1061f7917c00SJeff Kirsher unsigned int iqid); 1062f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1063f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1064f7917c00SJeff Kirsher unsigned int cmplqid); 1065f7917c00SJeff Kirsher int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, 1066f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid); 1067f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 106852367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1069f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1070f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 10713a336cb1SHariprasad Shenai int cxgb_busy_poll(struct napi_struct *napi); 1072812034f1SHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 1073812034f1SHariprasad Shenai unsigned int cnt); 1074812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1075812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 10763069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1077f7917c00SJeff Kirsher 1078f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1079f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1080f7917c00SJeff Kirsher 10819a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 10829a4da2cdSVipul Pandya { 10839a4da2cdSVipul Pandya return adap->params.bypass; 10849a4da2cdSVipul Pandya } 10859a4da2cdSVipul Pandya 10869a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 10879a4da2cdSVipul Pandya { 10889a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 10899a4da2cdSVipul Pandya switch (device) { 10909a4da2cdSVipul Pandya case 0x440b: 10919a4da2cdSVipul Pandya case 0x440c: 10929a4da2cdSVipul Pandya return 1; 10939a4da2cdSVipul Pandya default: 10949a4da2cdSVipul Pandya return 0; 10959a4da2cdSVipul Pandya } 10969a4da2cdSVipul Pandya } 10979a4da2cdSVipul Pandya 1098f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1099f7917c00SJeff Kirsher { 1100f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1101f7917c00SJeff Kirsher } 1102f7917c00SJeff Kirsher 1103f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1104f7917c00SJeff Kirsher unsigned int us) 1105f7917c00SJeff Kirsher { 1106f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1107f7917c00SJeff Kirsher } 1108f7917c00SJeff Kirsher 110952367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 111052367a76SVipul Pandya unsigned int ticks) 111152367a76SVipul Pandya { 111252367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 111352367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 111452367a76SVipul Pandya adapter->params.vpd.cclk); 111552367a76SVipul Pandya } 111652367a76SVipul Pandya 1117f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1118f7917c00SJeff Kirsher u32 val); 1119f7917c00SJeff Kirsher 1120f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1121f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1122f7917c00SJeff Kirsher 1123f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1124f7917c00SJeff Kirsher int size, void *rpl) 1125f7917c00SJeff Kirsher { 1126f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1127f7917c00SJeff Kirsher } 1128f7917c00SJeff Kirsher 1129f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1130f7917c00SJeff Kirsher int size, void *rpl) 1131f7917c00SJeff Kirsher { 1132f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1133f7917c00SJeff Kirsher } 1134f7917c00SJeff Kirsher 113513ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 113613ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 113713ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1138f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1139f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1140f2b7e78dSVipul Pandya unsigned int start_idx); 11410abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1142f2b7e78dSVipul Pandya 1143f2b7e78dSVipul Pandya struct fw_filter_wr; 1144f2b7e78dSVipul Pandya 1145f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1146f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1147f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1148f7917c00SJeff Kirsher 11498203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 1150f7917c00SJeff Kirsher int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 1151f7917c00SJeff Kirsher struct link_config *lc); 1152f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1153fc5ab020SHariprasad Shenai 1154fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1155fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1156fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1157f01aa633SHariprasad Shenai void *buf, int dir); 1158fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1159fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1160fc5ab020SHariprasad Shenai { 1161fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1162fc5ab020SHariprasad Shenai } 1163fc5ab020SHariprasad Shenai 1164812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1165812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1166812034f1SHariprasad Shenai 1167f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1168636f9d37SVipul Pandya int get_vpd_params(struct adapter *adapter, struct vpd_params *p); 116949216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 117049216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1171f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 117249216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 117322c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 117422c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1175636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 117616e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 117716e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1178ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 117916e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 118016e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 118116e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1182f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 1183e85c9a7aSHariprasad Shenai 1184e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1185dd0bcc0bSStephen Rothwell int cxgb4_t4_bar2_sge_qregs(struct adapter *adapter, 1186e85c9a7aSHariprasad Shenai unsigned int qid, 1187e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 1188e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1189e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1190e85c9a7aSHariprasad Shenai 1191dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1192dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1193ae469b68SHariprasad Shenai 1194ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1195e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 1196dcf7b6f5SKumar Sanghvi int t4_init_tp_params(struct adapter *adap); 1197dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1198f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1199f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1200f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1201f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1202f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1203f7917c00SJeff Kirsher unsigned int flags); 1204688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 1205688ea5feSHariprasad Shenai void t4_read_rss_key(struct adapter *adapter, u32 *key); 1206688ea5feSHariprasad Shenai void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 1207688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 1208688ea5feSHariprasad Shenai u32 *valp); 1209688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 1210688ea5feSHariprasad Shenai u32 *vfl, u32 *vfh); 1211688ea5feSHariprasad Shenai u32 t4_read_rss_pf_map(struct adapter *adapter); 1212688ea5feSHariprasad Shenai u32 t4_read_rss_pf_mask(struct adapter *adapter); 1213688ea5feSHariprasad Shenai 121419dd37baSSantosh Rastapur int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 121519dd37baSSantosh Rastapur u64 *parity); 1216f7917c00SJeff Kirsher int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 1217f7917c00SJeff Kirsher u64 *parity); 1218145ef8a5SHariprasad Shenai unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx); 1219b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1220b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1221e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1222e5f0e43bSHariprasad Shenai size_t n); 1223c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1224c778af7dSHariprasad Shenai size_t n); 1225f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1226f1ff24aaSHariprasad Shenai unsigned int *valp); 1227f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1228f1ff24aaSHariprasad Shenai const unsigned int *valp); 1229f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 123074b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 123172aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1232f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1233f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1234bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1235636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1236636f9d37SVipul Pandya unsigned int mask, unsigned int val); 12372d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 1238f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 1239f7917c00SJeff Kirsher struct tp_tcp_stats *v6); 1240f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1241f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1242f7917c00SJeff Kirsher 1243797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1244797ff0f5SHariprasad Shenai 1245f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1246f2b7e78dSVipul Pandya 1247f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1248f7917c00SJeff Kirsher const u8 *addr); 1249f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1250f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1251f7917c00SJeff Kirsher 1252f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1253f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1254f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1255f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1256f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1257636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1258636f9d37SVipul Pandya unsigned int cache_line_size); 1259636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1260f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1261f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1262f7917c00SJeff Kirsher u32 *val); 1263f7917c00SJeff Kirsher int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1264f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1265f7917c00SJeff Kirsher const u32 *val); 1266688848b1SAnish Bhatt int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox, 1267688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1268688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 1269688848b1SAnish Bhatt const u32 *val); 1270f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1271f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1272f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1273f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1274f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1275f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 1276f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 1277f7917c00SJeff Kirsher unsigned int *rss_size); 1278f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 1279f7917c00SJeff Kirsher int mtu, int promisc, int all_multi, int bcast, int vlanex, 1280f7917c00SJeff Kirsher bool sleep_ok); 1281f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 1282f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 1283f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 1284f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 1285f7917c00SJeff Kirsher int idx, const u8 *addr, bool persist, bool add_smt); 1286f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 1287f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 1288688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 1289688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 1290f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 1291f7917c00SJeff Kirsher bool rx_en, bool tx_en); 1292f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 1293f7917c00SJeff Kirsher unsigned int nblinks); 1294f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1295f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 1296f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 1297f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 1298f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1299f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 1300f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 1301f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1302f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1303f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1304f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1305f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 1306f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 1307f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 1308881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 1309881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 13108caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 13118caa1e84SVipul Pandya u32 addr, u32 val); 131268bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 1313fd88b31aSHariprasad Shenai void t4_free_mem(void *addr); 1314f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 1315