1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __CXGB4_H__ 36f7917c00SJeff Kirsher #define __CXGB4_H__ 37f7917c00SJeff Kirsher 38dca4faebSVipul Pandya #include "t4_hw.h" 39dca4faebSVipul Pandya 40f7917c00SJeff Kirsher #include <linux/bitops.h> 41f7917c00SJeff Kirsher #include <linux/cache.h> 42f7917c00SJeff Kirsher #include <linux/interrupt.h> 43f7917c00SJeff Kirsher #include <linux/list.h> 44f7917c00SJeff Kirsher #include <linux/netdevice.h> 45f7917c00SJeff Kirsher #include <linux/pci.h> 46f7917c00SJeff Kirsher #include <linux/spinlock.h> 47f7917c00SJeff Kirsher #include <linux/timer.h> 48c0b8b992SDavid S. Miller #include <linux/vmalloc.h> 490eb71a9dSNeilBrown #include <linux/rhashtable.h> 50098ef6c2SHariprasad Shenai #include <linux/etherdevice.h> 515e2a5ebcSHariprasad Shenai #include <linux/net_tstamp.h> 52a4569504SAtul Gupta #include <linux/ptp_clock_kernel.h> 53a4569504SAtul Gupta #include <linux/ptp_classify.h> 541dde532dSRahul Lakkireddy #include <linux/crash_dump.h> 55b1871915SGanesh Goudar #include <linux/thermal.h> 56f7917c00SJeff Kirsher #include <asm/io.h> 5727999805SHariprasad S #include "t4_chip_type.h" 58f7917c00SJeff Kirsher #include "cxgb4_uld.h" 59c2193999SShahjada Abul Husain #include "t4fw_api.h" 60f7917c00SJeff Kirsher 613069ee9bSVipul Pandya #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) 6294cdb8bbSHariprasad Shenai extern struct list_head adapter_list; 6393a09e74SPotnuri Bharat Teja extern struct list_head uld_list; 6494cdb8bbSHariprasad Shenai extern struct mutex uld_mutex; 653069ee9bSVipul Pandya 66a6ec572bSAtul Gupta /* Suspend an Ethernet Tx queue with fewer available descriptors than this. 67a6ec572bSAtul Gupta * This is the same as calc_tx_descs() for a TSO packet with 68a6ec572bSAtul Gupta * nr_frags == MAX_SKB_FRAGS. 69a6ec572bSAtul Gupta */ 70a6ec572bSAtul Gupta #define ETHTXQ_STOP_THRES \ 71a6ec572bSAtul Gupta (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8)) 72a6ec572bSAtul Gupta 73c2193999SShahjada Abul Husain #define FW_PARAM_DEV(param) \ 74c2193999SShahjada Abul Husain (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 75c2193999SShahjada Abul Husain FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 76c2193999SShahjada Abul Husain 77c2193999SShahjada Abul Husain #define FW_PARAM_PFVF(param) \ 78c2193999SShahjada Abul Husain (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 79c2193999SShahjada Abul Husain FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \ 80c2193999SShahjada Abul Husain FW_PARAMS_PARAM_Y_V(0) | \ 81c2193999SShahjada Abul Husain FW_PARAMS_PARAM_Z_V(0)) 82c2193999SShahjada Abul Husain 83f7917c00SJeff Kirsher enum { 84f7917c00SJeff Kirsher MAX_NPORTS = 4, /* max # of ports */ 85f7917c00SJeff Kirsher SERNUM_LEN = 24, /* Serial # length */ 86f7917c00SJeff Kirsher EC_LEN = 16, /* E/C length */ 87f7917c00SJeff Kirsher ID_LEN = 16, /* ID length */ 88a94cd705SKumar Sanghvi PN_LEN = 16, /* Part Number length */ 89098ef6c2SHariprasad Shenai MACADDR_LEN = 12, /* MAC Address length */ 90f7917c00SJeff Kirsher }; 91f7917c00SJeff Kirsher 92f7917c00SJeff Kirsher enum { 93812034f1SHariprasad Shenai T4_REGMAP_SIZE = (160 * 1024), 94812034f1SHariprasad Shenai T5_REGMAP_SIZE = (332 * 1024), 95812034f1SHariprasad Shenai }; 96812034f1SHariprasad Shenai 97812034f1SHariprasad Shenai enum { 98f7917c00SJeff Kirsher MEM_EDC0, 99f7917c00SJeff Kirsher MEM_EDC1, 1002422d9a3SSantosh Rastapur MEM_MC, 1012422d9a3SSantosh Rastapur MEM_MC0 = MEM_MC, 1024db0401fSRahul Lakkireddy MEM_MC1, 1034db0401fSRahul Lakkireddy MEM_HMA, 104f7917c00SJeff Kirsher }; 105f7917c00SJeff Kirsher 1063069ee9bSVipul Pandya enum { 1073eb4afbfSVipul Pandya MEMWIN0_APERTURE = 2048, 1083eb4afbfSVipul Pandya MEMWIN0_BASE = 0x1b800, 1093069ee9bSVipul Pandya MEMWIN1_APERTURE = 32768, 1103069ee9bSVipul Pandya MEMWIN1_BASE = 0x28000, 1112422d9a3SSantosh Rastapur MEMWIN1_BASE_T5 = 0x52000, 1123eb4afbfSVipul Pandya MEMWIN2_APERTURE = 65536, 1133eb4afbfSVipul Pandya MEMWIN2_BASE = 0x30000, 1140abfd152SHariprasad Shenai MEMWIN2_APERTURE_T5 = 131072, 1150abfd152SHariprasad Shenai MEMWIN2_BASE_T5 = 0x60000, 1163069ee9bSVipul Pandya }; 1173069ee9bSVipul Pandya 118f7917c00SJeff Kirsher enum dev_master { 119f7917c00SJeff Kirsher MASTER_CANT, 120f7917c00SJeff Kirsher MASTER_MAY, 121f7917c00SJeff Kirsher MASTER_MUST 122f7917c00SJeff Kirsher }; 123f7917c00SJeff Kirsher 124f7917c00SJeff Kirsher enum dev_state { 125f7917c00SJeff Kirsher DEV_STATE_UNINIT, 126f7917c00SJeff Kirsher DEV_STATE_INIT, 127f7917c00SJeff Kirsher DEV_STATE_ERR 128f7917c00SJeff Kirsher }; 129f7917c00SJeff Kirsher 130c3168cabSGanesh Goudar enum cc_pause { 131f7917c00SJeff Kirsher PAUSE_RX = 1 << 0, 132f7917c00SJeff Kirsher PAUSE_TX = 1 << 1, 133f7917c00SJeff Kirsher PAUSE_AUTONEG = 1 << 2 134f7917c00SJeff Kirsher }; 135f7917c00SJeff Kirsher 136c3168cabSGanesh Goudar enum cc_fec { 1373bb4858fSGanesh Goudar FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 1383bb4858fSGanesh Goudar FEC_RS = 1 << 1, /* Reed-Solomon */ 1393bb4858fSGanesh Goudar FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */ 1403bb4858fSGanesh Goudar }; 1413bb4858fSGanesh Goudar 1423893c905SVishal Kulkarni enum { 1433893c905SVishal Kulkarni CXGB4_ETHTOOL_FLASH_FW = 1, 1444ee339e1SVishal Kulkarni CXGB4_ETHTOOL_FLASH_PHY = 2, 14555088355SVishal Kulkarni CXGB4_ETHTOOL_FLASH_BOOT = 3, 146d5002c9aSVishal Kulkarni CXGB4_ETHTOOL_FLASH_BOOTCFG = 4 147d5002c9aSVishal Kulkarni }; 148d5002c9aSVishal Kulkarni 14976f919ebSAyush Sawal enum cxgb4_netdev_tls_ops { 15076f919ebSAyush Sawal CXGB4_TLSDEV_OPS = 1, 15176f919ebSAyush Sawal CXGB4_XFRMDEV_OPS 15276f919ebSAyush Sawal }; 15376f919ebSAyush Sawal 154d5002c9aSVishal Kulkarni struct cxgb4_bootcfg_data { 155d5002c9aSVishal Kulkarni __le16 signature; 156d5002c9aSVishal Kulkarni __u8 reserved[2]; 15755088355SVishal Kulkarni }; 15855088355SVishal Kulkarni 15955088355SVishal Kulkarni struct cxgb4_pcir_data { 16055088355SVishal Kulkarni __le32 signature; /* Signature. The string "PCIR" */ 16155088355SVishal Kulkarni __le16 vendor_id; /* Vendor Identification */ 16255088355SVishal Kulkarni __le16 device_id; /* Device Identification */ 16355088355SVishal Kulkarni __u8 vital_product[2]; /* Pointer to Vital Product Data */ 16455088355SVishal Kulkarni __u8 length[2]; /* PCIR Data Structure Length */ 16555088355SVishal Kulkarni __u8 revision; /* PCIR Data Structure Revision */ 16655088355SVishal Kulkarni __u8 class_code[3]; /* Class Code */ 16755088355SVishal Kulkarni __u8 image_length[2]; /* Image Length. Multiple of 512B */ 16855088355SVishal Kulkarni __u8 code_revision[2]; /* Revision Level of Code/Data */ 16955088355SVishal Kulkarni __u8 code_type; 17055088355SVishal Kulkarni __u8 indicator; 17155088355SVishal Kulkarni __u8 reserved[2]; 17255088355SVishal Kulkarni }; 17355088355SVishal Kulkarni 17455088355SVishal Kulkarni /* BIOS boot headers */ 17555088355SVishal Kulkarni struct cxgb4_pci_exp_rom_header { 17655088355SVishal Kulkarni __le16 signature; /* ROM Signature. Should be 0xaa55 */ 17755088355SVishal Kulkarni __u8 reserved[22]; /* Reserved per processor Architecture data */ 17855088355SVishal Kulkarni __le16 pcir_offset; /* Offset to PCI Data Structure */ 17955088355SVishal Kulkarni }; 18055088355SVishal Kulkarni 18155088355SVishal Kulkarni /* Legacy PCI Expansion ROM Header */ 18255088355SVishal Kulkarni struct legacy_pci_rom_hdr { 18355088355SVishal Kulkarni __u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 18455088355SVishal Kulkarni __u8 size512; /* Current Image Size in units of 512 bytes */ 18555088355SVishal Kulkarni __u8 initentry_point[4]; 18655088355SVishal Kulkarni __u8 cksum; /* Checksum computed on the entire Image */ 18755088355SVishal Kulkarni __u8 reserved[16]; /* Reserved */ 18855088355SVishal Kulkarni __le16 pcir_offset; /* Offset to PCI Data Struture */ 18955088355SVishal Kulkarni }; 19055088355SVishal Kulkarni 19155088355SVishal Kulkarni #define CXGB4_HDR_CODE1 0x00 19255088355SVishal Kulkarni #define CXGB4_HDR_CODE2 0x03 19355088355SVishal Kulkarni #define CXGB4_HDR_INDI 0x80 19455088355SVishal Kulkarni 19555088355SVishal Kulkarni /* BOOT constants */ 19655088355SVishal Kulkarni enum { 197d5002c9aSVishal Kulkarni BOOT_CFG_SIG = 0x4243, 19855088355SVishal Kulkarni BOOT_SIZE_INC = 512, 19955088355SVishal Kulkarni BOOT_SIGNATURE = 0xaa55, 20055088355SVishal Kulkarni BOOT_MIN_SIZE = sizeof(struct cxgb4_pci_exp_rom_header), 20155088355SVishal Kulkarni BOOT_MAX_SIZE = 1024 * BOOT_SIZE_INC, 20255088355SVishal Kulkarni PCIR_SIGNATURE = 0x52494350 2033893c905SVishal Kulkarni }; 2043893c905SVishal Kulkarni 205f7917c00SJeff Kirsher struct port_stats { 206f7917c00SJeff Kirsher u64 tx_octets; /* total # of octets in good frames */ 207f7917c00SJeff Kirsher u64 tx_frames; /* all good frames */ 208f7917c00SJeff Kirsher u64 tx_bcast_frames; /* all broadcast frames */ 209f7917c00SJeff Kirsher u64 tx_mcast_frames; /* all multicast frames */ 210f7917c00SJeff Kirsher u64 tx_ucast_frames; /* all unicast frames */ 211f7917c00SJeff Kirsher u64 tx_error_frames; /* all error frames */ 212f7917c00SJeff Kirsher 213f7917c00SJeff Kirsher u64 tx_frames_64; /* # of Tx frames in a particular range */ 214f7917c00SJeff Kirsher u64 tx_frames_65_127; 215f7917c00SJeff Kirsher u64 tx_frames_128_255; 216f7917c00SJeff Kirsher u64 tx_frames_256_511; 217f7917c00SJeff Kirsher u64 tx_frames_512_1023; 218f7917c00SJeff Kirsher u64 tx_frames_1024_1518; 219f7917c00SJeff Kirsher u64 tx_frames_1519_max; 220f7917c00SJeff Kirsher 221f7917c00SJeff Kirsher u64 tx_drop; /* # of dropped Tx frames */ 222f7917c00SJeff Kirsher u64 tx_pause; /* # of transmitted pause frames */ 223f7917c00SJeff Kirsher u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 224f7917c00SJeff Kirsher u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 225f7917c00SJeff Kirsher u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 226f7917c00SJeff Kirsher u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 227f7917c00SJeff Kirsher u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 228f7917c00SJeff Kirsher u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 229f7917c00SJeff Kirsher u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 230f7917c00SJeff Kirsher u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 231f7917c00SJeff Kirsher 232f7917c00SJeff Kirsher u64 rx_octets; /* total # of octets in good frames */ 233f7917c00SJeff Kirsher u64 rx_frames; /* all good frames */ 234f7917c00SJeff Kirsher u64 rx_bcast_frames; /* all broadcast frames */ 235f7917c00SJeff Kirsher u64 rx_mcast_frames; /* all multicast frames */ 236f7917c00SJeff Kirsher u64 rx_ucast_frames; /* all unicast frames */ 237f7917c00SJeff Kirsher u64 rx_too_long; /* # of frames exceeding MTU */ 238f7917c00SJeff Kirsher u64 rx_jabber; /* # of jabber frames */ 239f7917c00SJeff Kirsher u64 rx_fcs_err; /* # of received frames with bad FCS */ 240f7917c00SJeff Kirsher u64 rx_len_err; /* # of received frames with length error */ 241f7917c00SJeff Kirsher u64 rx_symbol_err; /* symbol errors */ 242f7917c00SJeff Kirsher u64 rx_runt; /* # of short frames */ 243f7917c00SJeff Kirsher 244f7917c00SJeff Kirsher u64 rx_frames_64; /* # of Rx frames in a particular range */ 245f7917c00SJeff Kirsher u64 rx_frames_65_127; 246f7917c00SJeff Kirsher u64 rx_frames_128_255; 247f7917c00SJeff Kirsher u64 rx_frames_256_511; 248f7917c00SJeff Kirsher u64 rx_frames_512_1023; 249f7917c00SJeff Kirsher u64 rx_frames_1024_1518; 250f7917c00SJeff Kirsher u64 rx_frames_1519_max; 251f7917c00SJeff Kirsher 252f7917c00SJeff Kirsher u64 rx_pause; /* # of received pause frames */ 253f7917c00SJeff Kirsher u64 rx_ppp0; /* # of received PPP prio 0 frames */ 254f7917c00SJeff Kirsher u64 rx_ppp1; /* # of received PPP prio 1 frames */ 255f7917c00SJeff Kirsher u64 rx_ppp2; /* # of received PPP prio 2 frames */ 256f7917c00SJeff Kirsher u64 rx_ppp3; /* # of received PPP prio 3 frames */ 257f7917c00SJeff Kirsher u64 rx_ppp4; /* # of received PPP prio 4 frames */ 258f7917c00SJeff Kirsher u64 rx_ppp5; /* # of received PPP prio 5 frames */ 259f7917c00SJeff Kirsher u64 rx_ppp6; /* # of received PPP prio 6 frames */ 260f7917c00SJeff Kirsher u64 rx_ppp7; /* # of received PPP prio 7 frames */ 261f7917c00SJeff Kirsher 262f7917c00SJeff Kirsher u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 263f7917c00SJeff Kirsher u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 264f7917c00SJeff Kirsher u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 265f7917c00SJeff Kirsher u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 266f7917c00SJeff Kirsher u64 rx_trunc0; /* buffer-group 0 truncated packets */ 267f7917c00SJeff Kirsher u64 rx_trunc1; /* buffer-group 1 truncated packets */ 268f7917c00SJeff Kirsher u64 rx_trunc2; /* buffer-group 2 truncated packets */ 269f7917c00SJeff Kirsher u64 rx_trunc3; /* buffer-group 3 truncated packets */ 270f7917c00SJeff Kirsher }; 271f7917c00SJeff Kirsher 272f7917c00SJeff Kirsher struct lb_port_stats { 273f7917c00SJeff Kirsher u64 octets; 274f7917c00SJeff Kirsher u64 frames; 275f7917c00SJeff Kirsher u64 bcast_frames; 276f7917c00SJeff Kirsher u64 mcast_frames; 277f7917c00SJeff Kirsher u64 ucast_frames; 278f7917c00SJeff Kirsher u64 error_frames; 279f7917c00SJeff Kirsher 280f7917c00SJeff Kirsher u64 frames_64; 281f7917c00SJeff Kirsher u64 frames_65_127; 282f7917c00SJeff Kirsher u64 frames_128_255; 283f7917c00SJeff Kirsher u64 frames_256_511; 284f7917c00SJeff Kirsher u64 frames_512_1023; 285f7917c00SJeff Kirsher u64 frames_1024_1518; 286f7917c00SJeff Kirsher u64 frames_1519_max; 287f7917c00SJeff Kirsher 288f7917c00SJeff Kirsher u64 drop; 289f7917c00SJeff Kirsher 290f7917c00SJeff Kirsher u64 ovflow0; 291f7917c00SJeff Kirsher u64 ovflow1; 292f7917c00SJeff Kirsher u64 ovflow2; 293f7917c00SJeff Kirsher u64 ovflow3; 294f7917c00SJeff Kirsher u64 trunc0; 295f7917c00SJeff Kirsher u64 trunc1; 296f7917c00SJeff Kirsher u64 trunc2; 297f7917c00SJeff Kirsher u64 trunc3; 298f7917c00SJeff Kirsher }; 299f7917c00SJeff Kirsher 300f7917c00SJeff Kirsher struct tp_tcp_stats { 301a4cfd929SHariprasad Shenai u32 tcp_out_rsts; 302a4cfd929SHariprasad Shenai u64 tcp_in_segs; 303a4cfd929SHariprasad Shenai u64 tcp_out_segs; 304a4cfd929SHariprasad Shenai u64 tcp_retrans_segs; 305a4cfd929SHariprasad Shenai }; 306a4cfd929SHariprasad Shenai 307a4cfd929SHariprasad Shenai struct tp_usm_stats { 308a4cfd929SHariprasad Shenai u32 frames; 309a4cfd929SHariprasad Shenai u32 drops; 310a4cfd929SHariprasad Shenai u64 octets; 311f7917c00SJeff Kirsher }; 312f7917c00SJeff Kirsher 313a6222975SHariprasad Shenai struct tp_fcoe_stats { 314a6222975SHariprasad Shenai u32 frames_ddp; 315a6222975SHariprasad Shenai u32 frames_drop; 316a6222975SHariprasad Shenai u64 octets_ddp; 317f7917c00SJeff Kirsher }; 318f7917c00SJeff Kirsher 319f7917c00SJeff Kirsher struct tp_err_stats { 320a4cfd929SHariprasad Shenai u32 mac_in_errs[4]; 321a4cfd929SHariprasad Shenai u32 hdr_in_errs[4]; 322a4cfd929SHariprasad Shenai u32 tcp_in_errs[4]; 323a4cfd929SHariprasad Shenai u32 tnl_cong_drops[4]; 324a4cfd929SHariprasad Shenai u32 ofld_chan_drops[4]; 325a4cfd929SHariprasad Shenai u32 tnl_tx_drops[4]; 326a4cfd929SHariprasad Shenai u32 ofld_vlan_drops[4]; 327a4cfd929SHariprasad Shenai u32 tcp6_in_errs[4]; 328a4cfd929SHariprasad Shenai u32 ofld_no_neigh; 329a4cfd929SHariprasad Shenai u32 ofld_cong_defer; 330a4cfd929SHariprasad Shenai }; 331a4cfd929SHariprasad Shenai 332a6222975SHariprasad Shenai struct tp_cpl_stats { 333a6222975SHariprasad Shenai u32 req[4]; 334a6222975SHariprasad Shenai u32 rsp[4]; 335a6222975SHariprasad Shenai }; 336a6222975SHariprasad Shenai 337a4cfd929SHariprasad Shenai struct tp_rdma_stats { 338a4cfd929SHariprasad Shenai u32 rqe_dfr_pkt; 339a4cfd929SHariprasad Shenai u32 rqe_dfr_mod; 340f7917c00SJeff Kirsher }; 341f7917c00SJeff Kirsher 342e85c9a7aSHariprasad Shenai struct sge_params { 343e85c9a7aSHariprasad Shenai u32 hps; /* host page size for our PF/VF */ 344e85c9a7aSHariprasad Shenai u32 eq_qpp; /* egress queues/page for our PF/VF */ 345e85c9a7aSHariprasad Shenai u32 iq_qpp; /* egress queues/page for our PF/VF */ 346e85c9a7aSHariprasad Shenai }; 347e85c9a7aSHariprasad Shenai 348f7917c00SJeff Kirsher struct tp_params { 349f7917c00SJeff Kirsher unsigned int tre; /* log2 of core clocks per TP tick */ 3502d277b3bSHariprasad Shenai unsigned int la_mask; /* what events are recorded by TP LA */ 351dca4faebSVipul Pandya unsigned short tx_modq_map; /* TX modulation scheduler queue to */ 352dca4faebSVipul Pandya /* channel map */ 353636f9d37SVipul Pandya 354636f9d37SVipul Pandya uint32_t dack_re; /* DACK timer resolution */ 355636f9d37SVipul Pandya unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 356dcf7b6f5SKumar Sanghvi 357dcf7b6f5SKumar Sanghvi u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */ 358dcf10ec7SRaju Rangoju u32 filter_mask; 359dcf7b6f5SKumar Sanghvi u32 ingress_config; /* cached TP_INGRESS_CONFIG */ 360dcf7b6f5SKumar Sanghvi 3618eb9f2f9SArjun V /* cached TP_OUT_CONFIG compressed error vector 3628eb9f2f9SArjun V * and passing outer header info for encapsulated packets. 3638eb9f2f9SArjun V */ 3648eb9f2f9SArjun V int rx_pkt_encap; 3658eb9f2f9SArjun V 366dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a 367dcf7b6f5SKumar Sanghvi * subset of the set of fields which may be present in the Compressed 368dcf7b6f5SKumar Sanghvi * Filter Tuple portion of filters and TCP TCB connections. The 369dcf7b6f5SKumar Sanghvi * fields which are present are controlled by the TP_VLAN_PRI_MAP. 370dcf7b6f5SKumar Sanghvi * Since a variable number of fields may or may not be present, their 371dcf7b6f5SKumar Sanghvi * shifted field positions within the Compressed Filter Tuple may 372dcf7b6f5SKumar Sanghvi * vary, or not even be present if the field isn't selected in 373dcf7b6f5SKumar Sanghvi * TP_VLAN_PRI_MAP. Since some of these fields are needed in various 374dcf7b6f5SKumar Sanghvi * places we store their offsets here, or a -1 if the field isn't 375dcf7b6f5SKumar Sanghvi * present. 376dcf7b6f5SKumar Sanghvi */ 3770ba9a3b6SKumar Sanghvi int fcoe_shift; 378dcf7b6f5SKumar Sanghvi int port_shift; 3790ba9a3b6SKumar Sanghvi int vnic_shift; 3800ba9a3b6SKumar Sanghvi int vlan_shift; 3810ba9a3b6SKumar Sanghvi int tos_shift; 382dcf7b6f5SKumar Sanghvi int protocol_shift; 3830ba9a3b6SKumar Sanghvi int ethertype_shift; 3840ba9a3b6SKumar Sanghvi int macmatch_shift; 3850ba9a3b6SKumar Sanghvi int matchtype_shift; 3860ba9a3b6SKumar Sanghvi int frag_shift; 3870ba9a3b6SKumar Sanghvi 3880ba9a3b6SKumar Sanghvi u64 hash_filter_mask; 389f7917c00SJeff Kirsher }; 390f7917c00SJeff Kirsher 391f7917c00SJeff Kirsher struct vpd_params { 392f7917c00SJeff Kirsher unsigned int cclk; 393f7917c00SJeff Kirsher u8 ec[EC_LEN + 1]; 394f7917c00SJeff Kirsher u8 sn[SERNUM_LEN + 1]; 395f7917c00SJeff Kirsher u8 id[ID_LEN + 1]; 396a94cd705SKumar Sanghvi u8 pn[PN_LEN + 1]; 397098ef6c2SHariprasad Shenai u8 na[MACADDR_LEN + 1]; 398f7917c00SJeff Kirsher }; 399f7917c00SJeff Kirsher 4000eaec62aSCasey Leedom /* Maximum resources provisioned for a PCI PF. 4010eaec62aSCasey Leedom */ 4020eaec62aSCasey Leedom struct pf_resources { 4030eaec62aSCasey Leedom unsigned int nvi; /* N virtual interfaces */ 4040eaec62aSCasey Leedom unsigned int neq; /* N egress Qs */ 4050eaec62aSCasey Leedom unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 4060eaec62aSCasey Leedom unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 4070eaec62aSCasey Leedom unsigned int niq; /* N ingress Qs */ 4080eaec62aSCasey Leedom unsigned int tc; /* PCI-E traffic class */ 4090eaec62aSCasey Leedom unsigned int pmask; /* port access rights mask */ 4100eaec62aSCasey Leedom unsigned int nexactf; /* N exact MPS filters */ 4110eaec62aSCasey Leedom unsigned int r_caps; /* read capabilities */ 4120eaec62aSCasey Leedom unsigned int wx_caps; /* write/execute capabilities */ 4130eaec62aSCasey Leedom }; 4140eaec62aSCasey Leedom 415f7917c00SJeff Kirsher struct pci_params { 416baf50868SGanesh Goudar unsigned int vpd_cap_addr; 417f7917c00SJeff Kirsher unsigned char speed; 418f7917c00SJeff Kirsher unsigned char width; 419f7917c00SJeff Kirsher }; 420f7917c00SJeff Kirsher 42149aa284fSHariprasad Shenai struct devlog_params { 42249aa284fSHariprasad Shenai u32 memtype; /* which memory (EDC0, EDC1, MC) */ 42349aa284fSHariprasad Shenai u32 start; /* start of log in firmware memory */ 42449aa284fSHariprasad Shenai u32 size; /* size of log */ 42549aa284fSHariprasad Shenai }; 42649aa284fSHariprasad Shenai 4273ccc6cf7SHariprasad Shenai /* Stores chip specific parameters */ 4283ccc6cf7SHariprasad Shenai struct arch_specific_params { 4293ccc6cf7SHariprasad Shenai u8 nchan; 43044588560SHariprasad Shenai u8 pm_stats_cnt; 4312216d014SHariprasad Shenai u8 cng_ch_bits_log; /* congestion channel map bits width */ 4323ccc6cf7SHariprasad Shenai u16 mps_rplc_size; 4333ccc6cf7SHariprasad Shenai u16 vfcount; 4343ccc6cf7SHariprasad Shenai u32 sge_fl_db; 4353ccc6cf7SHariprasad Shenai u16 mps_tcam_size; 4363ccc6cf7SHariprasad Shenai }; 4373ccc6cf7SHariprasad Shenai 438f7917c00SJeff Kirsher struct adapter_params { 439e85c9a7aSHariprasad Shenai struct sge_params sge; 440f7917c00SJeff Kirsher struct tp_params tp; 441f7917c00SJeff Kirsher struct vpd_params vpd; 4420eaec62aSCasey Leedom struct pf_resources pfres; 443f7917c00SJeff Kirsher struct pci_params pci; 44449aa284fSHariprasad Shenai struct devlog_params devlog; 44549aa284fSHariprasad Shenai enum pcie_memwin drv_memwin; 446f7917c00SJeff Kirsher 447f1ff24aaSHariprasad Shenai unsigned int cim_la_size; 448f1ff24aaSHariprasad Shenai 449f7917c00SJeff Kirsher unsigned int sf_size; /* serial flash size in bytes */ 450f7917c00SJeff Kirsher unsigned int sf_nsec; /* # of flash sectors */ 451f7917c00SJeff Kirsher 452760446f9SGanesh Goudar unsigned int fw_vers; /* firmware version */ 4530de72738SHariprasad Shenai unsigned int bs_vers; /* bootstrap version */ 454760446f9SGanesh Goudar unsigned int tp_vers; /* TP microcode version */ 4550de72738SHariprasad Shenai unsigned int er_vers; /* expansion ROM version */ 456760446f9SGanesh Goudar unsigned int scfg_vers; /* Serial Configuration version */ 457760446f9SGanesh Goudar unsigned int vpd_vers; /* VPD Version */ 458f7917c00SJeff Kirsher u8 api_vers[7]; 459f7917c00SJeff Kirsher 460f7917c00SJeff Kirsher unsigned short mtus[NMTUS]; 461f7917c00SJeff Kirsher unsigned short a_wnd[NCCTRL_WIN]; 462f7917c00SJeff Kirsher unsigned short b_wnd[NCCTRL_WIN]; 463f7917c00SJeff Kirsher 464f7917c00SJeff Kirsher unsigned char nports; /* # of ethernet ports */ 465f7917c00SJeff Kirsher unsigned char portvec; 466d14807ddSHariprasad Shenai enum chip_type chip; /* chip code */ 4673ccc6cf7SHariprasad Shenai struct arch_specific_params arch; /* chip specific params */ 468f7917c00SJeff Kirsher unsigned char offload; 46994cdb8bbSHariprasad Shenai unsigned char crypto; /* HW capability for crypto */ 470ab0367eaSRahul Lakkireddy unsigned char ethofld; /* QoS support */ 471f7917c00SJeff Kirsher 4729a4da2cdSVipul Pandya unsigned char bypass; 4735c31254eSKumar Sanghvi unsigned char hash_filter; 4749a4da2cdSVipul Pandya 475f7917c00SJeff Kirsher unsigned int ofldq_wr_cred; 4761ac0f095SKumar Sanghvi bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 4774c2c5763SHariprasad Shenai 478b72a32daSRahul Lakkireddy unsigned int nsched_cls; /* number of traffic classes */ 4794c2c5763SHariprasad Shenai unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 4804c2c5763SHariprasad Shenai unsigned int max_ird_adapter; /* Max read depth per adapter */ 481086de575SSteve Wise bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 482c3168cabSGanesh Goudar u8 fw_caps_support; /* 32-bit Port Capabilities */ 4830ff90994SKumar Sanghvi bool filter2_wr_support; /* FW support for FILTER2_WR */ 48402d805dcSSantosh Rastapur unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */ 4858f46d467SArjun Vynipadath 4868f46d467SArjun Vynipadath /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is 4878f46d467SArjun Vynipadath * used by the Port 4888f46d467SArjun Vynipadath */ 4898f46d467SArjun Vynipadath u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */ 49043db9296SRaju Rangoju bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 491f3910c62SRaju Rangoju bool write_cmpl_support; /* FW supports WRITE_CMPL */ 492f7917c00SJeff Kirsher }; 493f7917c00SJeff Kirsher 494a3bfb617SHariprasad Shenai /* State needed to monitor the forward progress of SGE Ingress DMA activities 495a3bfb617SHariprasad Shenai * and possible hangs. 496a3bfb617SHariprasad Shenai */ 497a3bfb617SHariprasad Shenai struct sge_idma_monitor_state { 498a3bfb617SHariprasad Shenai unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 499a3bfb617SHariprasad Shenai unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 500a3bfb617SHariprasad Shenai unsigned int idma_state[2]; /* IDMA Hang detect state */ 501a3bfb617SHariprasad Shenai unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 502a3bfb617SHariprasad Shenai unsigned int idma_warn[2]; /* time to warning in HZ */ 503a3bfb617SHariprasad Shenai }; 504a3bfb617SHariprasad Shenai 5057f080c3fSHariprasad Shenai /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 5067f080c3fSHariprasad Shenai * The access and execute times are signed in order to accommodate negative 5077f080c3fSHariprasad Shenai * error returns. 5087f080c3fSHariprasad Shenai */ 5097f080c3fSHariprasad Shenai struct mbox_cmd { 5107f080c3fSHariprasad Shenai u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 5117f080c3fSHariprasad Shenai u64 timestamp; /* OS-dependent timestamp */ 5127f080c3fSHariprasad Shenai u32 seqno; /* sequence number */ 5137f080c3fSHariprasad Shenai s16 access; /* time (ms) to access mailbox */ 5147f080c3fSHariprasad Shenai s16 execute; /* time (ms) to execute */ 5157f080c3fSHariprasad Shenai }; 5167f080c3fSHariprasad Shenai 5177f080c3fSHariprasad Shenai struct mbox_cmd_log { 5187f080c3fSHariprasad Shenai unsigned int size; /* number of entries in the log */ 5197f080c3fSHariprasad Shenai unsigned int cursor; /* next position in the log to write */ 5207f080c3fSHariprasad Shenai u32 seqno; /* next sequence number */ 5217f080c3fSHariprasad Shenai /* variable length mailbox command log starts here */ 5227f080c3fSHariprasad Shenai }; 5237f080c3fSHariprasad Shenai 5247f080c3fSHariprasad Shenai /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 5257f080c3fSHariprasad Shenai * return a pointer to the specified entry. 5267f080c3fSHariprasad Shenai */ 5277f080c3fSHariprasad Shenai static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 5287f080c3fSHariprasad Shenai unsigned int entry_idx) 5297f080c3fSHariprasad Shenai { 5307f080c3fSHariprasad Shenai return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 5317f080c3fSHariprasad Shenai } 5327f080c3fSHariprasad Shenai 53316e47624SHariprasad Shenai #define FW_VERSION(chip) ( \ 534b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \ 535b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \ 536b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \ 537b2e1a3f0SHariprasad Shenai FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD)) 53816e47624SHariprasad Shenai #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf) 53916e47624SHariprasad Shenai 5407235ffaeSVishal Kulkarni struct cxgb4_ethtool_lb_test { 5417235ffaeSVishal Kulkarni struct completion completion; 5427235ffaeSVishal Kulkarni int result; 5437235ffaeSVishal Kulkarni int loopback; 5447235ffaeSVishal Kulkarni }; 5457235ffaeSVishal Kulkarni 54616e47624SHariprasad Shenai struct fw_info { 54716e47624SHariprasad Shenai u8 chip; 54816e47624SHariprasad Shenai char *fs_name; 54916e47624SHariprasad Shenai char *fw_mod_name; 55016e47624SHariprasad Shenai struct fw_hdr fw_hdr; 55116e47624SHariprasad Shenai }; 55216e47624SHariprasad Shenai 553f7917c00SJeff Kirsher struct trace_params { 554f7917c00SJeff Kirsher u32 data[TRACE_LEN / 4]; 555f7917c00SJeff Kirsher u32 mask[TRACE_LEN / 4]; 556f7917c00SJeff Kirsher unsigned short snap_len; 557f7917c00SJeff Kirsher unsigned short min_len; 558f7917c00SJeff Kirsher unsigned char skip_ofst; 559f7917c00SJeff Kirsher unsigned char skip_len; 560f7917c00SJeff Kirsher unsigned char invert; 561f7917c00SJeff Kirsher unsigned char port; 562f7917c00SJeff Kirsher }; 563f7917c00SJeff Kirsher 5643893c905SVishal Kulkarni struct cxgb4_fw_data { 5653893c905SVishal Kulkarni __be32 signature; 5663893c905SVishal Kulkarni __u8 reserved[4]; 5673893c905SVishal Kulkarni }; 5683893c905SVishal Kulkarni 569c3168cabSGanesh Goudar /* Firmware Port Capabilities types. */ 570c3168cabSGanesh Goudar 571c3168cabSGanesh Goudar typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 572c3168cabSGanesh Goudar typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 573c3168cabSGanesh Goudar 574c3168cabSGanesh Goudar enum fw_caps { 575c3168cabSGanesh Goudar FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 576c3168cabSGanesh Goudar FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 577c3168cabSGanesh Goudar FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 578c3168cabSGanesh Goudar }; 579c3168cabSGanesh Goudar 580f7917c00SJeff Kirsher struct link_config { 581c3168cabSGanesh Goudar fw_port_cap32_t pcaps; /* link capabilities */ 582c3168cabSGanesh Goudar fw_port_cap32_t def_acaps; /* default advertised capabilities */ 583c3168cabSGanesh Goudar fw_port_cap32_t acaps; /* advertised capabilities */ 584c3168cabSGanesh Goudar fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 585c3168cabSGanesh Goudar 586c3168cabSGanesh Goudar fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 587c3168cabSGanesh Goudar unsigned int speed; /* actual link speed (Mb/s) */ 588c3168cabSGanesh Goudar 589c3168cabSGanesh Goudar enum cc_pause requested_fc; /* flow control user has requested */ 590c3168cabSGanesh Goudar enum cc_pause fc; /* actual link flow control */ 5910caeaf6aSRahul Lakkireddy enum cc_pause advertised_fc; /* actual advertised flow control */ 592c3168cabSGanesh Goudar 593c3168cabSGanesh Goudar enum cc_fec requested_fec; /* Forward Error Correction: */ 594c3168cabSGanesh Goudar enum cc_fec fec; /* requested and actual in use */ 595c3168cabSGanesh Goudar 596f7917c00SJeff Kirsher unsigned char autoneg; /* autonegotiating? */ 597c3168cabSGanesh Goudar 598f7917c00SJeff Kirsher unsigned char link_ok; /* link up? */ 599ddc7740dSHariprasad Shenai unsigned char link_down_rc; /* link down reason */ 6008156b0baSGanesh Goudar 6018156b0baSGanesh Goudar bool new_module; /* ->OS Transceiver Module inserted */ 6028156b0baSGanesh Goudar bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */ 603f7917c00SJeff Kirsher }; 604f7917c00SJeff Kirsher 605e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 606f7917c00SJeff Kirsher 607f7917c00SJeff Kirsher enum { 608f7917c00SJeff Kirsher MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ 609f90ce561SHariprasad Shenai MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */ 610f7917c00SJeff Kirsher MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 611f7917c00SJeff Kirsher }; 612f7917c00SJeff Kirsher 613f7917c00SJeff Kirsher enum { 614812034f1SHariprasad Shenai MAX_TXQ_ENTRIES = 16384, 615812034f1SHariprasad Shenai MAX_CTRL_TXQ_ENTRIES = 1024, 616812034f1SHariprasad Shenai MAX_RSPQ_ENTRIES = 16384, 617812034f1SHariprasad Shenai MAX_RX_BUFFERS = 16384, 618812034f1SHariprasad Shenai MIN_TXQ_ENTRIES = 32, 619812034f1SHariprasad Shenai MIN_CTRL_TXQ_ENTRIES = 32, 620812034f1SHariprasad Shenai MIN_RSPQ_ENTRIES = 128, 621812034f1SHariprasad Shenai MIN_FL_ENTRIES = 16 622812034f1SHariprasad Shenai }; 623812034f1SHariprasad Shenai 624812034f1SHariprasad Shenai enum { 62568ddc82aSRahul Lakkireddy MAX_TXQ_DESC_SIZE = 64, 62668ddc82aSRahul Lakkireddy MAX_RXQ_DESC_SIZE = 128, 62768ddc82aSRahul Lakkireddy MAX_FL_DESC_SIZE = 8, 62868ddc82aSRahul Lakkireddy MAX_CTRL_TXQ_DESC_SIZE = 64, 62968ddc82aSRahul Lakkireddy }; 63068ddc82aSRahul Lakkireddy 63168ddc82aSRahul Lakkireddy enum { 632cf38be6dSHariprasad Shenai INGQ_EXTRAS = 2, /* firmware event queue and */ 633cf38be6dSHariprasad Shenai /* forwarded interrupts */ 6340fbc81b3SHariprasad Shenai MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS, 635f7917c00SJeff Kirsher }; 636f7917c00SJeff Kirsher 637d5fbda61SArjun Vynipadath enum { 638d5fbda61SArjun Vynipadath PRIV_FLAG_PORT_TX_VM_BIT, 639d5fbda61SArjun Vynipadath }; 640d5fbda61SArjun Vynipadath 641d5fbda61SArjun Vynipadath #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT) 642d5fbda61SArjun Vynipadath 643d5fbda61SArjun Vynipadath #define PRIV_FLAGS_ADAP 0 644d5fbda61SArjun Vynipadath #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM 645d5fbda61SArjun Vynipadath 646f7917c00SJeff Kirsher struct adapter; 647f7917c00SJeff Kirsher struct sge_rspq; 648f7917c00SJeff Kirsher 649688848b1SAnish Bhatt #include "cxgb4_dcb.h" 650688848b1SAnish Bhatt 65176fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 65276fed8a9SVarun Prakash #include "cxgb4_fcoe.h" 65376fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 65476fed8a9SVarun Prakash 655f7917c00SJeff Kirsher struct port_info { 656f7917c00SJeff Kirsher struct adapter *adapter; 657f7917c00SJeff Kirsher u16 viid; 6583f8cfd0dSArjun Vynipadath int xact_addr_filt; /* index of exact MAC address filter */ 659f7917c00SJeff Kirsher u16 rss_size; /* size of VI's RSS table slice */ 660f7917c00SJeff Kirsher s8 mdio_addr; 66140e9de4bSHariprasad Shenai enum fw_port_type port_type; 662f7917c00SJeff Kirsher u8 mod_type; 663f7917c00SJeff Kirsher u8 port_id; 664f7917c00SJeff Kirsher u8 tx_chan; 665f7917c00SJeff Kirsher u8 lport; /* associated offload logical port */ 666f7917c00SJeff Kirsher u8 nqsets; /* # of qsets */ 667f7917c00SJeff Kirsher u8 first_qset; /* index of first qset */ 668f7917c00SJeff Kirsher u8 rss_mode; 669f7917c00SJeff Kirsher struct link_config link_cfg; 670f7917c00SJeff Kirsher u16 *rss; 671a4cfd929SHariprasad Shenai struct port_stats stats_base; 672688848b1SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 673688848b1SAnish Bhatt struct port_dcb_info dcb; /* Data Center Bridging support */ 674688848b1SAnish Bhatt #endif 67576fed8a9SVarun Prakash #ifdef CONFIG_CHELSIO_T4_FCOE 67676fed8a9SVarun Prakash struct cxgb_fcoe fcoe; 67776fed8a9SVarun Prakash #endif /* CONFIG_CHELSIO_T4_FCOE */ 6785e2a5ebcSHariprasad Shenai bool rxtstamp; /* Enable TS */ 6795e2a5ebcSHariprasad Shenai struct hwtstamp_config tstamp_config; 680a4569504SAtul Gupta bool ptp_enable; 681b72a32daSRahul Lakkireddy struct sched_table *sched_tbl; 682d5fbda61SArjun Vynipadath u32 eth_flags; 68302d805dcSSantosh Rastapur 68402d805dcSSantosh Rastapur /* viid and smt fields either returned by fw 68502d805dcSSantosh Rastapur * or decoded by parsing viid by driver. 68602d805dcSSantosh Rastapur */ 68702d805dcSSantosh Rastapur u8 vin; 68802d805dcSSantosh Rastapur u8 vivld; 68902d805dcSSantosh Rastapur u8 smt_idx; 69074dd5aa1SVishal Kulkarni u8 rx_cchan; 6914ec4762dSRahul Lakkireddy 6924ec4762dSRahul Lakkireddy bool tc_block_shared; 693fd2261d8SRahul Lakkireddy 694fd2261d8SRahul Lakkireddy /* Mirror VI information */ 695fd2261d8SRahul Lakkireddy u16 viid_mirror; 696fd2261d8SRahul Lakkireddy u16 nmirrorqsets; 697fd2261d8SRahul Lakkireddy u32 vi_mirror_count; 698fd2261d8SRahul Lakkireddy struct mutex vi_mirror_mutex; /* Sync access to Mirror VI info */ 6997235ffaeSVishal Kulkarni struct cxgb4_ethtool_lb_test ethtool_lb; 700f7917c00SJeff Kirsher }; 701f7917c00SJeff Kirsher 702f7917c00SJeff Kirsher struct dentry; 703f7917c00SJeff Kirsher struct work_struct; 704f7917c00SJeff Kirsher 705f7917c00SJeff Kirsher enum { /* adapter flags */ 70680f61f19SArjun Vynipadath CXGB4_FULL_INIT_DONE = (1 << 0), 70780f61f19SArjun Vynipadath CXGB4_DEV_ENABLED = (1 << 1), 70880f61f19SArjun Vynipadath CXGB4_USING_MSI = (1 << 2), 70980f61f19SArjun Vynipadath CXGB4_USING_MSIX = (1 << 3), 71080f61f19SArjun Vynipadath CXGB4_FW_OK = (1 << 4), 71180f61f19SArjun Vynipadath CXGB4_RSS_TNLALLLOOKUP = (1 << 5), 71280f61f19SArjun Vynipadath CXGB4_USING_SOFT_PARAMS = (1 << 6), 71380f61f19SArjun Vynipadath CXGB4_MASTER_PF = (1 << 7), 71480f61f19SArjun Vynipadath CXGB4_FW_OFLD_CONN = (1 << 9), 71580f61f19SArjun Vynipadath CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10), 71680f61f19SArjun Vynipadath CXGB4_SHUTTING_DOWN = (1 << 11), 71780f61f19SArjun Vynipadath CXGB4_SGE_DBQ_TIMER = (1 << 12), 718f7917c00SJeff Kirsher }; 719f7917c00SJeff Kirsher 72094cdb8bbSHariprasad Shenai enum { 72194cdb8bbSHariprasad Shenai ULP_CRYPTO_LOOKASIDE = 1 << 0, 722a6ec572bSAtul Gupta ULP_CRYPTO_IPSEC_INLINE = 1 << 1, 72334aba2c4SRohit Maheshwari ULP_CRYPTO_KTLS_INLINE = 1 << 3, 72494cdb8bbSHariprasad Shenai }; 72594cdb8bbSHariprasad Shenai 7262b465ed0SRahul Lakkireddy #define CXGB4_MIRROR_RXQ_DEFAULT_DESC_NUM 1024 7272b465ed0SRahul Lakkireddy #define CXGB4_MIRROR_RXQ_DEFAULT_DESC_SIZE 64 7282b465ed0SRahul Lakkireddy #define CXGB4_MIRROR_RXQ_DEFAULT_INTR_USEC 5 7292b465ed0SRahul Lakkireddy #define CXGB4_MIRROR_RXQ_DEFAULT_PKT_CNT 8 7302b465ed0SRahul Lakkireddy 7312b465ed0SRahul Lakkireddy #define CXGB4_MIRROR_FLQ_DEFAULT_DESC_NUM 72 7322b465ed0SRahul Lakkireddy 733f7917c00SJeff Kirsher struct rx_sw_desc; 734f7917c00SJeff Kirsher 735f7917c00SJeff Kirsher struct sge_fl { /* SGE free-buffer queue state */ 736f7917c00SJeff Kirsher unsigned int avail; /* # of available Rx buffers */ 737f7917c00SJeff Kirsher unsigned int pend_cred; /* new buffers since last FL DB ring */ 738f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 739f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 740f7917c00SJeff Kirsher unsigned long alloc_failed; /* # of times buffer allocation failed */ 741f7917c00SJeff Kirsher unsigned long large_alloc_failed; 74270055dd0SHariprasad Shenai unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */ 74370055dd0SHariprasad Shenai unsigned long low; /* # of times momentarily starving */ 744f7917c00SJeff Kirsher unsigned long starving; 745f7917c00SJeff Kirsher /* RO fields */ 746f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the free list */ 747f7917c00SJeff Kirsher unsigned int size; /* capacity of free list */ 748f7917c00SJeff Kirsher struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 749f7917c00SJeff Kirsher __be64 *desc; /* address of HW Rx descriptor ring */ 750f7917c00SJeff Kirsher dma_addr_t addr; /* bus address of HW ring start */ 751df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 752df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 753f7917c00SJeff Kirsher }; 754f7917c00SJeff Kirsher 755f7917c00SJeff Kirsher /* A packet gather list */ 756f7917c00SJeff Kirsher struct pkt_gl { 7575e2a5ebcSHariprasad Shenai u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */ 758e91b0f24SIan Campbell struct page_frag frags[MAX_SKB_FRAGS]; 759f7917c00SJeff Kirsher void *va; /* virtual address of first byte */ 760f7917c00SJeff Kirsher unsigned int nfrags; /* # of fragments */ 761f7917c00SJeff Kirsher unsigned int tot_len; /* total length of fragments */ 762f7917c00SJeff Kirsher }; 763f7917c00SJeff Kirsher 764f7917c00SJeff Kirsher typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 765f7917c00SJeff Kirsher const struct pkt_gl *gl); 7662337ba42SVarun Prakash typedef void (*rspq_flush_handler_t)(struct sge_rspq *q); 7672337ba42SVarun Prakash /* LRO related declarations for ULD */ 7682337ba42SVarun Prakash struct t4_lro_mgr { 7692337ba42SVarun Prakash #define MAX_LRO_SESSIONS 64 7702337ba42SVarun Prakash u8 lro_session_cnt; /* # of sessions to aggregate */ 7712337ba42SVarun Prakash unsigned long lro_pkts; /* # of LRO super packets */ 7722337ba42SVarun Prakash unsigned long lro_merged; /* # of wire packets merged by LRO */ 7732337ba42SVarun Prakash struct sk_buff_head lroq; /* list of aggregated sessions */ 7742337ba42SVarun Prakash }; 775f7917c00SJeff Kirsher 776f7917c00SJeff Kirsher struct sge_rspq { /* state for an SGE response queue */ 777f7917c00SJeff Kirsher struct napi_struct napi; 778f7917c00SJeff Kirsher const __be64 *cur_desc; /* current descriptor in queue */ 779f7917c00SJeff Kirsher unsigned int cidx; /* consumer index */ 780f7917c00SJeff Kirsher u8 gen; /* current generation bit */ 781f7917c00SJeff Kirsher u8 intr_params; /* interrupt holdoff parameters */ 782f7917c00SJeff Kirsher u8 next_intr_params; /* holdoff params for next interrupt */ 783e553ec3fSHariprasad Shenai u8 adaptive_rx; 784f7917c00SJeff Kirsher u8 pktcnt_idx; /* interrupt packet threshold */ 785f7917c00SJeff Kirsher u8 uld; /* ULD handling this queue */ 786f7917c00SJeff Kirsher u8 idx; /* queue index within its group */ 787f7917c00SJeff Kirsher int offset; /* offset into current Rx buffer */ 788f7917c00SJeff Kirsher u16 cntxt_id; /* SGE context id for the response q */ 789f7917c00SJeff Kirsher u16 abs_id; /* absolute SGE id for the response q */ 790f7917c00SJeff Kirsher __be64 *desc; /* address of HW response ring */ 791f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 792df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 793df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 794f7917c00SJeff Kirsher unsigned int iqe_len; /* entry size */ 795f7917c00SJeff Kirsher unsigned int size; /* capacity of response queue */ 796f7917c00SJeff Kirsher struct adapter *adap; 797f7917c00SJeff Kirsher struct net_device *netdev; /* associated net device */ 798f7917c00SJeff Kirsher rspq_handler_t handler; 7992337ba42SVarun Prakash rspq_flush_handler_t flush_handler; 8002337ba42SVarun Prakash struct t4_lro_mgr lro_mgr; 801f7917c00SJeff Kirsher }; 802f7917c00SJeff Kirsher 803f7917c00SJeff Kirsher struct sge_eth_stats { /* Ethernet queue statistics */ 804f7917c00SJeff Kirsher unsigned long pkts; /* # of ethernet packets */ 805f7917c00SJeff Kirsher unsigned long lro_pkts; /* # of LRO super packets */ 806f7917c00SJeff Kirsher unsigned long lro_merged; /* # of wire packets merged by LRO */ 807f7917c00SJeff Kirsher unsigned long rx_cso; /* # of Rx checksum offloads */ 808f7917c00SJeff Kirsher unsigned long vlan_ex; /* # of Rx VLAN extractions */ 809f7917c00SJeff Kirsher unsigned long rx_drops; /* # of packets dropped due to no mem */ 810992bea8eSGanesh Goudar unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */ 811f7917c00SJeff Kirsher }; 812f7917c00SJeff Kirsher 813f7917c00SJeff Kirsher struct sge_eth_rxq { /* SW Ethernet Rx queue */ 814f7917c00SJeff Kirsher struct sge_rspq rspq; 815f7917c00SJeff Kirsher struct sge_fl fl; 816f7917c00SJeff Kirsher struct sge_eth_stats stats; 81776c3a552SRahul Lakkireddy struct msix_info *msix; 818f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 819f7917c00SJeff Kirsher 820f7917c00SJeff Kirsher struct sge_ofld_stats { /* offload queue statistics */ 821f7917c00SJeff Kirsher unsigned long pkts; /* # of packets */ 822f7917c00SJeff Kirsher unsigned long imm; /* # of immediate-data packets */ 823f7917c00SJeff Kirsher unsigned long an; /* # of asynchronous notifications */ 824f7917c00SJeff Kirsher unsigned long nomem; /* # of responses deferred due to no mem */ 825f7917c00SJeff Kirsher }; 826f7917c00SJeff Kirsher 827f7917c00SJeff Kirsher struct sge_ofld_rxq { /* SW offload Rx queue */ 828f7917c00SJeff Kirsher struct sge_rspq rspq; 829f7917c00SJeff Kirsher struct sge_fl fl; 830f7917c00SJeff Kirsher struct sge_ofld_stats stats; 83176c3a552SRahul Lakkireddy struct msix_info *msix; 832f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 833f7917c00SJeff Kirsher 834f7917c00SJeff Kirsher struct tx_desc { 835f7917c00SJeff Kirsher __be64 flit[8]; 836f7917c00SJeff Kirsher }; 837f7917c00SJeff Kirsher 8380ed96b46SRahul Lakkireddy struct ulptx_sgl; 8390ed96b46SRahul Lakkireddy 8400ed96b46SRahul Lakkireddy struct tx_sw_desc { 8410ed96b46SRahul Lakkireddy struct sk_buff *skb; /* SKB to free after getting completion */ 8420ed96b46SRahul Lakkireddy dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */ 8430ed96b46SRahul Lakkireddy }; 844f7917c00SJeff Kirsher 845f7917c00SJeff Kirsher struct sge_txq { 846f7917c00SJeff Kirsher unsigned int in_use; /* # of in-use Tx descriptors */ 847ab677ff4SHariprasad Shenai unsigned int q_type; /* Q type Eth/Ctrl/Ofld */ 848f7917c00SJeff Kirsher unsigned int size; /* # of descriptors */ 849f7917c00SJeff Kirsher unsigned int cidx; /* SW consumer index */ 850f7917c00SJeff Kirsher unsigned int pidx; /* producer index */ 851f7917c00SJeff Kirsher unsigned long stops; /* # of times q has been stopped */ 852f7917c00SJeff Kirsher unsigned long restarts; /* # of queue restarts */ 853f7917c00SJeff Kirsher unsigned int cntxt_id; /* SGE context id for the Tx q */ 854f7917c00SJeff Kirsher struct tx_desc *desc; /* address of HW Tx descriptor ring */ 855f7917c00SJeff Kirsher struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 856f7917c00SJeff Kirsher struct sge_qstat *stat; /* queue status entry */ 857f7917c00SJeff Kirsher dma_addr_t phys_addr; /* physical address of the ring */ 8583069ee9bSVipul Pandya spinlock_t db_lock; 8593069ee9bSVipul Pandya int db_disabled; 8603069ee9bSVipul Pandya unsigned short db_pidx; 86105eb2389SSteve Wise unsigned short db_pidx_inc; 862df64e4d3SHariprasad Shenai void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 863df64e4d3SHariprasad Shenai unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 864f7917c00SJeff Kirsher }; 865f7917c00SJeff Kirsher 866f7917c00SJeff Kirsher struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 867f7917c00SJeff Kirsher struct sge_txq q; 868f7917c00SJeff Kirsher struct netdev_queue *txq; /* associated netdev TX queue */ 86910b00466SAnish Bhatt #ifdef CONFIG_CHELSIO_T4_DCB 87010b00466SAnish Bhatt u8 dcb_prio; /* DCB Priority bound to queue */ 87110b00466SAnish Bhatt #endif 872d429005fSVishal Kulkarni u8 dbqt; /* SGE Doorbell Queue Timer in use */ 873d429005fSVishal Kulkarni unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */ 874f7917c00SJeff Kirsher unsigned long tso; /* # of TSO requests */ 8751a2a14fbSRahul Lakkireddy unsigned long uso; /* # of USO requests */ 876f7917c00SJeff Kirsher unsigned long tx_cso; /* # of Tx checksum offloads */ 877f7917c00SJeff Kirsher unsigned long vlan_ins; /* # of Tx VLAN insertions */ 878f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 879f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 880f7917c00SJeff Kirsher 881ab677ff4SHariprasad Shenai struct sge_uld_txq { /* state for an SGE offload Tx queue */ 882f7917c00SJeff Kirsher struct sge_txq q; 883f7917c00SJeff Kirsher struct adapter *adap; 884f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 885f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 886126fca64SHariprasad Shenai bool service_ofldq_running; /* service_ofldq() is processing sendq */ 887f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 888f7917c00SJeff Kirsher unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 889f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 890f7917c00SJeff Kirsher 891f7917c00SJeff Kirsher struct sge_ctrl_txq { /* state for an SGE control Tx queue */ 892f7917c00SJeff Kirsher struct sge_txq q; 893f7917c00SJeff Kirsher struct adapter *adap; 894f7917c00SJeff Kirsher struct sk_buff_head sendq; /* list of backpressured packets */ 895f7917c00SJeff Kirsher struct tasklet_struct qresume_tsk; /* restarts the queue */ 896f7917c00SJeff Kirsher u8 full; /* the Tx ring is full */ 897f7917c00SJeff Kirsher } ____cacheline_aligned_in_smp; 898f7917c00SJeff Kirsher 89994cdb8bbSHariprasad Shenai struct sge_uld_rxq_info { 90094cdb8bbSHariprasad Shenai char name[IFNAMSIZ]; /* name of ULD driver */ 90194cdb8bbSHariprasad Shenai struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */ 90294cdb8bbSHariprasad Shenai u16 *rspq_id; /* response queue id's of rxq */ 90394cdb8bbSHariprasad Shenai u16 nrxq; /* # of ingress uld queues */ 90494cdb8bbSHariprasad Shenai u16 nciq; /* # of completion queues */ 90594cdb8bbSHariprasad Shenai u8 uld; /* uld type */ 90694cdb8bbSHariprasad Shenai }; 90794cdb8bbSHariprasad Shenai 908ab677ff4SHariprasad Shenai struct sge_uld_txq_info { 909ab677ff4SHariprasad Shenai struct sge_uld_txq *uldtxq; /* Txq's for ULD */ 910ab677ff4SHariprasad Shenai atomic_t users; /* num users */ 911ab677ff4SHariprasad Shenai u16 ntxq; /* # of egress uld queues */ 912ab677ff4SHariprasad Shenai }; 913ab677ff4SHariprasad Shenai 91493a09e74SPotnuri Bharat Teja /* struct to maintain ULD list to reallocate ULD resources on hotplug */ 91593a09e74SPotnuri Bharat Teja struct cxgb4_uld_list { 91693a09e74SPotnuri Bharat Teja struct cxgb4_uld_info uld_info; 91793a09e74SPotnuri Bharat Teja struct list_head list_node; 91893a09e74SPotnuri Bharat Teja enum cxgb4_uld uld_type; 91993a09e74SPotnuri Bharat Teja }; 92093a09e74SPotnuri Bharat Teja 921b1396c2bSRahul Lakkireddy enum sge_eosw_state { 922b1396c2bSRahul Lakkireddy CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */ 9230e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */ 9240e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */ 9254846d533SRahul Lakkireddy CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */ 9260e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */ 9270e395b3cSRahul Lakkireddy CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */ 928b1396c2bSRahul Lakkireddy }; 929b1396c2bSRahul Lakkireddy 930b1396c2bSRahul Lakkireddy struct sge_eosw_txq { 931b1396c2bSRahul Lakkireddy spinlock_t lock; /* Per queue lock to synchronize completions */ 932b1396c2bSRahul Lakkireddy enum sge_eosw_state state; /* Current ETHOFLD State */ 9330ed96b46SRahul Lakkireddy struct tx_sw_desc *desc; /* Descriptor ring to hold packets */ 934b1396c2bSRahul Lakkireddy u32 ndesc; /* Number of descriptors */ 935b1396c2bSRahul Lakkireddy u32 pidx; /* Current Producer Index */ 936b1396c2bSRahul Lakkireddy u32 last_pidx; /* Last successfully transmitted Producer Index */ 937b1396c2bSRahul Lakkireddy u32 cidx; /* Current Consumer Index */ 938b1396c2bSRahul Lakkireddy u32 last_cidx; /* Last successfully reclaimed Consumer Index */ 9390e395b3cSRahul Lakkireddy u32 flowc_idx; /* Descriptor containing a FLOWC request */ 940b1396c2bSRahul Lakkireddy u32 inuse; /* Number of packets held in ring */ 941b1396c2bSRahul Lakkireddy 942b1396c2bSRahul Lakkireddy u32 cred; /* Current available credits */ 943b1396c2bSRahul Lakkireddy u32 ncompl; /* # of completions posted */ 944b1396c2bSRahul Lakkireddy u32 last_compl; /* # of credits consumed since last completion req */ 945b1396c2bSRahul Lakkireddy 946b1396c2bSRahul Lakkireddy u32 eotid; /* Index into EOTID table in software */ 947b1396c2bSRahul Lakkireddy u32 hwtid; /* Hardware EOTID index */ 948b1396c2bSRahul Lakkireddy 949b1396c2bSRahul Lakkireddy u32 hwqid; /* Underlying hardware queue index */ 950b1396c2bSRahul Lakkireddy struct net_device *netdev; /* Pointer to netdevice */ 951b1396c2bSRahul Lakkireddy struct tasklet_struct qresume_tsk; /* Restarts the queue */ 9520e395b3cSRahul Lakkireddy struct completion completion; /* completion for FLOWC rendezvous */ 953b1396c2bSRahul Lakkireddy }; 954b1396c2bSRahul Lakkireddy 9552d0cb84dSRahul Lakkireddy struct sge_eohw_txq { 9562d0cb84dSRahul Lakkireddy spinlock_t lock; /* Per queue lock */ 9572d0cb84dSRahul Lakkireddy struct sge_txq q; /* HW Txq */ 9582d0cb84dSRahul Lakkireddy struct adapter *adap; /* Backpointer to adapter */ 9592d0cb84dSRahul Lakkireddy unsigned long tso; /* # of TSO requests */ 9608311f0beSRahul Lakkireddy unsigned long uso; /* # of USO requests */ 9612d0cb84dSRahul Lakkireddy unsigned long tx_cso; /* # of Tx checksum offloads */ 9622d0cb84dSRahul Lakkireddy unsigned long vlan_ins; /* # of Tx VLAN insertions */ 9632d0cb84dSRahul Lakkireddy unsigned long mapping_err; /* # of I/O MMU packet mapping errors */ 9642d0cb84dSRahul Lakkireddy }; 9652d0cb84dSRahul Lakkireddy 966f7917c00SJeff Kirsher struct sge { 967f7917c00SJeff Kirsher struct sge_eth_txq ethtxq[MAX_ETH_QSETS]; 968a4569504SAtul Gupta struct sge_eth_txq ptptxq; 969f7917c00SJeff Kirsher struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 970f7917c00SJeff Kirsher 971f7917c00SJeff Kirsher struct sge_eth_rxq ethrxq[MAX_ETH_QSETS]; 972f7917c00SJeff Kirsher struct sge_rspq fw_evtq ____cacheline_aligned_in_smp; 97394cdb8bbSHariprasad Shenai struct sge_uld_rxq_info **uld_rxq_info; 974ab677ff4SHariprasad Shenai struct sge_uld_txq_info **uld_txq_info; 975f7917c00SJeff Kirsher 976f7917c00SJeff Kirsher struct sge_rspq intrq ____cacheline_aligned_in_smp; 977f7917c00SJeff Kirsher spinlock_t intrq_lock; 978f7917c00SJeff Kirsher 9792d0cb84dSRahul Lakkireddy struct sge_eohw_txq *eohw_txq; 9802d0cb84dSRahul Lakkireddy struct sge_ofld_rxq *eohw_rxq; 9812d0cb84dSRahul Lakkireddy 9822b465ed0SRahul Lakkireddy struct sge_eth_rxq *mirror_rxq[NCHAN]; 9832b465ed0SRahul Lakkireddy 984f7917c00SJeff Kirsher u16 max_ethqsets; /* # of available Ethernet queue sets */ 985f7917c00SJeff Kirsher u16 ethqsets; /* # of active Ethernet queue sets */ 986f7917c00SJeff Kirsher u16 ethtxq_rover; /* Tx queue to clean up next */ 9870fbc81b3SHariprasad Shenai u16 ofldqsets; /* # of active ofld queue sets */ 98894cdb8bbSHariprasad Shenai u16 nqs_per_uld; /* # of Rx queues per ULD */ 9892d0cb84dSRahul Lakkireddy u16 eoqsets; /* # of ETHOFLD queues */ 990fd2261d8SRahul Lakkireddy u16 mirrorqsets; /* # of Mirror queues */ 9912d0cb84dSRahul Lakkireddy 992f7917c00SJeff Kirsher u16 timer_val[SGE_NTIMERS]; 993f7917c00SJeff Kirsher u8 counter_val[SGE_NCOUNTERS]; 994543a1b85SVishal Kulkarni u16 dbqtimer_tick; 995d429005fSVishal Kulkarni u16 dbqtimer_val[SGE_NDBQTIMERS]; 99652367a76SVipul Pandya u32 fl_pg_order; /* large page allocation size */ 99752367a76SVipul Pandya u32 stat_len; /* length of status page at ring end */ 99852367a76SVipul Pandya u32 pktshift; /* padding between CPL & packet data */ 99952367a76SVipul Pandya u32 fl_align; /* response queue message alignment */ 100052367a76SVipul Pandya u32 fl_starve_thres; /* Free List starvation threshold */ 10010f4d201fSKumar Sanghvi 1002a3bfb617SHariprasad Shenai struct sge_idma_monitor_state idma_monitor; 1003f7917c00SJeff Kirsher unsigned int egr_start; 10044b8e27a8SHariprasad Shenai unsigned int egr_sz; 1005f7917c00SJeff Kirsher unsigned int ingr_start; 10064b8e27a8SHariprasad Shenai unsigned int ingr_sz; 10074b8e27a8SHariprasad Shenai void **egr_map; /* qid->queue egress queue map */ 10084b8e27a8SHariprasad Shenai struct sge_rspq **ingr_map; /* qid->queue ingress queue map */ 10094b8e27a8SHariprasad Shenai unsigned long *starving_fl; 10104b8e27a8SHariprasad Shenai unsigned long *txq_maperr; 10115b377d11SHariprasad Shenai unsigned long *blocked_fl; 1012f7917c00SJeff Kirsher struct timer_list rx_timer; /* refills starving FLs */ 1013f7917c00SJeff Kirsher struct timer_list tx_timer; /* checks Tx queues */ 101476c3a552SRahul Lakkireddy 101576c3a552SRahul Lakkireddy int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */ 101676c3a552SRahul Lakkireddy int nd_msix_idx; /* Index to non-data interrupts MSI-X info */ 1017f7917c00SJeff Kirsher }; 1018f7917c00SJeff Kirsher 1019f7917c00SJeff Kirsher #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++) 10200fbc81b3SHariprasad Shenai #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++) 1021f7917c00SJeff Kirsher 1022f7917c00SJeff Kirsher struct l2t_data; 1023f7917c00SJeff Kirsher 10242422d9a3SSantosh Rastapur #ifdef CONFIG_PCI_IOV 10252422d9a3SSantosh Rastapur 10267d6727cfSSantosh Rastapur /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial 10277d6727cfSSantosh Rastapur * Configuration initialization for T5 only has SR-IOV functionality enabled 10287d6727cfSSantosh Rastapur * on PF0-3 in order to simplify everything. 10292422d9a3SSantosh Rastapur */ 10307d6727cfSSantosh Rastapur #define NUM_OF_PF_WITH_SRIOV 4 10312422d9a3SSantosh Rastapur 10322422d9a3SSantosh Rastapur #endif 10332422d9a3SSantosh Rastapur 1034a4cfd929SHariprasad Shenai struct doorbell_stats { 1035a4cfd929SHariprasad Shenai u32 db_drop; 1036a4cfd929SHariprasad Shenai u32 db_empty; 1037a4cfd929SHariprasad Shenai u32 db_full; 1038a4cfd929SHariprasad Shenai }; 1039a4cfd929SHariprasad Shenai 1040fc08a01aSHariprasad Shenai struct hash_mac_addr { 1041fc08a01aSHariprasad Shenai struct list_head list; 1042fc08a01aSHariprasad Shenai u8 addr[ETH_ALEN]; 10433f8cfd0dSArjun Vynipadath unsigned int iface_mac; 1044fc08a01aSHariprasad Shenai }; 1045fc08a01aSHariprasad Shenai 104676c3a552SRahul Lakkireddy struct msix_bmap { 104794cdb8bbSHariprasad Shenai unsigned long *msix_bmap; 104894cdb8bbSHariprasad Shenai unsigned int mapsize; 104994cdb8bbSHariprasad Shenai spinlock_t lock; /* lock for acquiring bitmap */ 105094cdb8bbSHariprasad Shenai }; 105194cdb8bbSHariprasad Shenai 105276c3a552SRahul Lakkireddy struct msix_info { 105394cdb8bbSHariprasad Shenai unsigned short vec; 105494cdb8bbSHariprasad Shenai char desc[IFNAMSIZ + 10]; 10550fbc81b3SHariprasad Shenai unsigned int idx; 1056c9765074SNirranjan Kirubaharan cpumask_var_t aff_mask; 105794cdb8bbSHariprasad Shenai }; 105894cdb8bbSHariprasad Shenai 1059661dbeb9SHariprasad Shenai struct vf_info { 1060661dbeb9SHariprasad Shenai unsigned char vf_mac_addr[ETH_ALEN]; 10618ea4fae9SGanesh Goudar unsigned int tx_rate; 1062661dbeb9SHariprasad Shenai bool pf_set_mac; 10639d5fd927SGanesh Goudar u16 vlan; 10648b965f3fSArjun Vynipadath int link_state; 1065661dbeb9SHariprasad Shenai }; 1066661dbeb9SHariprasad Shenai 10678b4e6b3cSArjun Vynipadath enum { 10688b4e6b3cSArjun Vynipadath HMA_DMA_MAPPED_FLAG = 1 10698b4e6b3cSArjun Vynipadath }; 10708b4e6b3cSArjun Vynipadath 10718b4e6b3cSArjun Vynipadath struct hma_data { 10728b4e6b3cSArjun Vynipadath unsigned char flags; 10738b4e6b3cSArjun Vynipadath struct sg_table *sgt; 10748b4e6b3cSArjun Vynipadath dma_addr_t *phy_addr; /* physical address of the page */ 10758b4e6b3cSArjun Vynipadath }; 10768b4e6b3cSArjun Vynipadath 10774055ae5eSHariprasad Shenai struct mbox_list { 10784055ae5eSHariprasad Shenai struct list_head list; 10794055ae5eSHariprasad Shenai }; 10804055ae5eSHariprasad Shenai 1081e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 1082b1871915SGanesh Goudar struct ch_thermal { 1083b1871915SGanesh Goudar struct thermal_zone_device *tzdev; 1084b1871915SGanesh Goudar int trip_temp; 1085b1871915SGanesh Goudar int trip_type; 1086b1871915SGanesh Goudar }; 1087b1871915SGanesh Goudar #endif 1088b1871915SGanesh Goudar 108928b38705SRaju Rangoju struct mps_entries_ref { 109028b38705SRaju Rangoju struct list_head list; 109128b38705SRaju Rangoju u8 addr[ETH_ALEN]; 109228b38705SRaju Rangoju u8 mask[ETH_ALEN]; 109328b38705SRaju Rangoju u16 idx; 109428b38705SRaju Rangoju refcount_t refcnt; 109528b38705SRaju Rangoju }; 109628b38705SRaju Rangoju 1097d915c299SVishal Kulkarni struct cxgb4_ethtool_filter_info { 1098d915c299SVishal Kulkarni u32 *loc_array; /* Array holding the actual TIDs set to filters */ 1099d915c299SVishal Kulkarni unsigned long *bmap; /* Bitmap for managing filters in use */ 1100d915c299SVishal Kulkarni u32 in_use; /* # of filters in use */ 1101d915c299SVishal Kulkarni }; 1102d915c299SVishal Kulkarni 1103d915c299SVishal Kulkarni struct cxgb4_ethtool_filter { 1104d915c299SVishal Kulkarni u32 nentries; /* Adapter wide number of supported filters */ 1105d915c299SVishal Kulkarni struct cxgb4_ethtool_filter_info *port; /* Per port entry */ 1106d915c299SVishal Kulkarni }; 1107d915c299SVishal Kulkarni 1108f7917c00SJeff Kirsher struct adapter { 1109f7917c00SJeff Kirsher void __iomem *regs; 111022adfe0aSSantosh Rastapur void __iomem *bar2; 11110abfd152SHariprasad Shenai u32 t4_bar0; 1112f7917c00SJeff Kirsher struct pci_dev *pdev; 1113f7917c00SJeff Kirsher struct device *pdev_dev; 11140de72738SHariprasad Shenai const char *name; 11153069ee9bSVipul Pandya unsigned int mbox; 1116b2612722SHariprasad Shenai unsigned int pf; 1117f7917c00SJeff Kirsher unsigned int flags; 1118e7b48a32SHariprasad Shenai unsigned int adap_idx; 11192422d9a3SSantosh Rastapur enum chip_type chip; 1120d5fbda61SArjun Vynipadath u32 eth_flags; 1121f7917c00SJeff Kirsher 1122f7917c00SJeff Kirsher int msg_enable; 1123846eac3fSGanesh Goudar __be16 vxlan_port; 1124c746fc0eSGanesh Goudar __be16 geneve_port; 1125f7917c00SJeff Kirsher 1126f7917c00SJeff Kirsher struct adapter_params params; 1127f7917c00SJeff Kirsher struct cxgb4_virt_res vres; 1128f7917c00SJeff Kirsher unsigned int swintr; 1129f7917c00SJeff Kirsher 113076c3a552SRahul Lakkireddy /* MSI-X Info for NIC and OFLD queues */ 113176c3a552SRahul Lakkireddy struct msix_info *msix_info; 113276c3a552SRahul Lakkireddy struct msix_bmap msix_bmap; 1133f7917c00SJeff Kirsher 1134a4cfd929SHariprasad Shenai struct doorbell_stats db_stats; 1135f7917c00SJeff Kirsher struct sge sge; 1136f7917c00SJeff Kirsher 1137f7917c00SJeff Kirsher struct net_device *port[MAX_NPORTS]; 1138f7917c00SJeff Kirsher u8 chan_map[NCHAN]; /* channel -> port map */ 1139f7917c00SJeff Kirsher 1140661dbeb9SHariprasad Shenai struct vf_info *vfinfo; 1141661dbeb9SHariprasad Shenai u8 num_vfs; 1142661dbeb9SHariprasad Shenai 1143793dad94SVipul Pandya u32 filter_mode; 1144636f9d37SVipul Pandya unsigned int l2t_start; 1145636f9d37SVipul Pandya unsigned int l2t_end; 1146f7917c00SJeff Kirsher struct l2t_data *l2t; 1147b5a02f50SAnish Bhatt unsigned int clipt_start; 1148b5a02f50SAnish Bhatt unsigned int clipt_end; 1149b5a02f50SAnish Bhatt struct clip_tbl *clipt; 1150846eac3fSGanesh Goudar unsigned int rawf_start; 1151846eac3fSGanesh Goudar unsigned int rawf_cnt; 11523bdb376eSKumar Sanghvi struct smt_data *smt; 11530fbc81b3SHariprasad Shenai struct cxgb4_uld_info *uld; 1154f7917c00SJeff Kirsher void *uld_handle[CXGB4_ULD_MAX]; 115594cdb8bbSHariprasad Shenai unsigned int num_uld; 11560fbc81b3SHariprasad Shenai unsigned int num_ofld_uld; 1157f7917c00SJeff Kirsher struct list_head list_node; 115801bcca68SVipul Pandya struct list_head rcu_node; 1159fc08a01aSHariprasad Shenai struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */ 116028b38705SRaju Rangoju struct list_head mps_ref; 116128b38705SRaju Rangoju spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */ 1162f7917c00SJeff Kirsher 11637714cb9eSVarun Prakash void *iscsi_ppm; 11647714cb9eSVarun Prakash 1165f7917c00SJeff Kirsher struct tid_info tids; 1166f7917c00SJeff Kirsher void **tid_release_head; 1167f7917c00SJeff Kirsher spinlock_t tid_release_lock; 116829aaee65SAnish Bhatt struct workqueue_struct *workq; 1169f7917c00SJeff Kirsher struct work_struct tid_release_task; 1170881806bcSVipul Pandya struct work_struct db_full_task; 1171881806bcSVipul Pandya struct work_struct db_drop_task; 11728b7372c1SGanesh Goudar struct work_struct fatal_err_notify_task; 1173f7917c00SJeff Kirsher bool tid_release_task_busy; 1174f7917c00SJeff Kirsher 11754055ae5eSHariprasad Shenai /* lock for mailbox cmd list */ 11764055ae5eSHariprasad Shenai spinlock_t mbox_lock; 11774055ae5eSHariprasad Shenai struct mbox_list mlist; 11784055ae5eSHariprasad Shenai 11797f080c3fSHariprasad Shenai /* support for mailbox command/reply logging */ 11807f080c3fSHariprasad Shenai #define T4_OS_LOG_MBOX_CMDS 256 11817f080c3fSHariprasad Shenai struct mbox_cmd_log *mbox_log; 11827f080c3fSHariprasad Shenai 11830fbc81b3SHariprasad Shenai struct mutex uld_mutex; 11840fbc81b3SHariprasad Shenai 1185f7917c00SJeff Kirsher struct dentry *debugfs_root; 1186621a5f7aSViresh Kumar bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */ 1187621a5f7aSViresh Kumar bool trace_rss; /* 1 implies that different RSS flit per filter is 11888e3d04fdSHariprasad Shenai * used per filter else if 0 default RSS flit is 11898e3d04fdSHariprasad Shenai * used for all 4 filters. 11908e3d04fdSHariprasad Shenai */ 1191f7917c00SJeff Kirsher 1192a4569504SAtul Gupta struct ptp_clock *ptp_clock; 1193a4569504SAtul Gupta struct ptp_clock_info ptp_clock_info; 1194a4569504SAtul Gupta struct sk_buff *ptp_tx_skb; 1195a4569504SAtul Gupta /* ptp lock */ 1196a4569504SAtul Gupta spinlock_t ptp_lock; 1197f7917c00SJeff Kirsher spinlock_t stats_lock; 1198fc5ab020SHariprasad Shenai spinlock_t win0_lock ____cacheline_aligned_in_smp; 1199d8931847SRahul Lakkireddy 1200d8931847SRahul Lakkireddy /* TC u32 offload */ 1201d8931847SRahul Lakkireddy struct cxgb4_tc_u32_table *tc_u32; 1202a3ac249aSRohit Maheshwari struct chcr_ktls chcr_ktls; 1203ee0863baSHarsh Jain struct chcr_stats_debug chcr_stats; 1204a8c16e8eSRohit Maheshwari #if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE) 1205a8c16e8eSRohit Maheshwari struct ch_ktls_stats_debug ch_ktls_stats; 1206a8c16e8eSRohit Maheshwari #endif 12071b77be46SVinay Kumar Yadav #if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE) 12081b77be46SVinay Kumar Yadav struct ch_ipsec_stats_debug ch_ipsec_stats; 12091b77be46SVinay Kumar Yadav #endif 121062488e4bSKumar Sanghvi 121162488e4bSKumar Sanghvi /* TC flower offload */ 1212a081e115SCasey Leedom bool tc_flower_initialized; 121379e6d46aSKumar Sanghvi struct rhashtable flower_tbl; 121479e6d46aSKumar Sanghvi struct rhashtable_params flower_ht_params; 1215e0f911c8SKumar Sanghvi struct timer_list flower_stats_timer; 121679e6d46aSKumar Sanghvi struct work_struct flower_stats_work; 1217ad75b7d3SRahul Lakkireddy 1218ad75b7d3SRahul Lakkireddy /* Ethtool Dump */ 1219ad75b7d3SRahul Lakkireddy struct ethtool_dump eth_dump; 12208b4e6b3cSArjun Vynipadath 12218b4e6b3cSArjun Vynipadath /* HMA */ 12228b4e6b3cSArjun Vynipadath struct hma_data hma; 1223e4709475SRaju Rangoju 1224e4709475SRaju Rangoju struct srq_data *srq; 12251dde532dSRahul Lakkireddy 12261dde532dSRahul Lakkireddy /* Dump buffer for collecting logs in kdump kernel */ 12271dde532dSRahul Lakkireddy struct vmcoredd_data vmcoredd; 1228e70a57faSArnd Bergmann #if IS_ENABLED(CONFIG_THERMAL) 1229b1871915SGanesh Goudar struct ch_thermal ch_thermal; 1230b1871915SGanesh Goudar #endif 1231b1396c2bSRahul Lakkireddy 1232b1396c2bSRahul Lakkireddy /* TC MQPRIO offload */ 1233b1396c2bSRahul Lakkireddy struct cxgb4_tc_mqprio *tc_mqprio; 12344ec4762dSRahul Lakkireddy 12354ec4762dSRahul Lakkireddy /* TC MATCHALL classifier offload */ 12364ec4762dSRahul Lakkireddy struct cxgb4_tc_matchall *tc_matchall; 1237d915c299SVishal Kulkarni 1238d915c299SVishal Kulkarni /* Ethtool n-tuple */ 1239d915c299SVishal Kulkarni struct cxgb4_ethtool_filter *ethtool_filters; 1240f7917c00SJeff Kirsher }; 1241f7917c00SJeff Kirsher 1242b72a32daSRahul Lakkireddy /* Support for "sched-class" command to allow a TX Scheduling Class to be 1243b72a32daSRahul Lakkireddy * programmed with various parameters. 1244b72a32daSRahul Lakkireddy */ 1245b72a32daSRahul Lakkireddy struct ch_sched_params { 12464bccfc03SRahul Lakkireddy u8 type; /* packet or flow */ 1247b72a32daSRahul Lakkireddy union { 1248b72a32daSRahul Lakkireddy struct { 12494bccfc03SRahul Lakkireddy u8 level; /* scheduler hierarchy level */ 12504bccfc03SRahul Lakkireddy u8 mode; /* per-class or per-flow */ 12514bccfc03SRahul Lakkireddy u8 rateunit; /* bit or packet rate */ 12524bccfc03SRahul Lakkireddy u8 ratemode; /* %port relative or kbps absolute */ 12534bccfc03SRahul Lakkireddy u8 channel; /* scheduler channel [0..N] */ 12544bccfc03SRahul Lakkireddy u8 class; /* scheduler class [0..N] */ 12554bccfc03SRahul Lakkireddy u32 minrate; /* minimum rate */ 12564bccfc03SRahul Lakkireddy u32 maxrate; /* maximum rate */ 12574bccfc03SRahul Lakkireddy u16 weight; /* percent weight */ 12584bccfc03SRahul Lakkireddy u16 pktsize; /* average packet size */ 12594bccfc03SRahul Lakkireddy u16 burstsize; /* burst buffer size */ 1260b72a32daSRahul Lakkireddy } params; 1261b72a32daSRahul Lakkireddy } u; 1262b72a32daSRahul Lakkireddy }; 1263b72a32daSRahul Lakkireddy 126410a2604eSRahul Lakkireddy enum { 126510a2604eSRahul Lakkireddy SCHED_CLASS_TYPE_PACKET = 0, /* class type */ 126610a2604eSRahul Lakkireddy }; 126710a2604eSRahul Lakkireddy 126810a2604eSRahul Lakkireddy enum { 126910a2604eSRahul Lakkireddy SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */ 12704ec4762dSRahul Lakkireddy SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */ 127110a2604eSRahul Lakkireddy }; 127210a2604eSRahul Lakkireddy 127310a2604eSRahul Lakkireddy enum { 127410a2604eSRahul Lakkireddy SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */ 12750e395b3cSRahul Lakkireddy SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 127610a2604eSRahul Lakkireddy }; 127710a2604eSRahul Lakkireddy 127810a2604eSRahul Lakkireddy enum { 127910a2604eSRahul Lakkireddy SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */ 128010a2604eSRahul Lakkireddy }; 128110a2604eSRahul Lakkireddy 128210a2604eSRahul Lakkireddy enum { 128310a2604eSRahul Lakkireddy SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */ 128410a2604eSRahul Lakkireddy }; 128510a2604eSRahul Lakkireddy 12866cede1f1SRahul Lakkireddy /* Support for "sched_queue" command to allow one or more NIC TX Queues 12876cede1f1SRahul Lakkireddy * to be bound to a TX Scheduling Class. 12886cede1f1SRahul Lakkireddy */ 12896cede1f1SRahul Lakkireddy struct ch_sched_queue { 12906cede1f1SRahul Lakkireddy s8 queue; /* queue index */ 12916cede1f1SRahul Lakkireddy s8 class; /* class index */ 12926cede1f1SRahul Lakkireddy }; 12936cede1f1SRahul Lakkireddy 12940e395b3cSRahul Lakkireddy /* Support for "sched_flowc" command to allow one or more FLOWC 12950e395b3cSRahul Lakkireddy * to be bound to a TX Scheduling Class. 12960e395b3cSRahul Lakkireddy */ 12970e395b3cSRahul Lakkireddy struct ch_sched_flowc { 12980e395b3cSRahul Lakkireddy s32 tid; /* TID to bind */ 12990e395b3cSRahul Lakkireddy s8 class; /* class index */ 13000e395b3cSRahul Lakkireddy }; 13010e395b3cSRahul Lakkireddy 1302f2b7e78dSVipul Pandya /* Defined bit width of user definable filter tuples 1303f2b7e78dSVipul Pandya */ 1304f2b7e78dSVipul Pandya #define ETHTYPE_BITWIDTH 16 1305f2b7e78dSVipul Pandya #define FRAG_BITWIDTH 1 1306f2b7e78dSVipul Pandya #define MACIDX_BITWIDTH 9 1307f2b7e78dSVipul Pandya #define FCOE_BITWIDTH 1 1308f2b7e78dSVipul Pandya #define IPORT_BITWIDTH 3 1309f2b7e78dSVipul Pandya #define MATCHTYPE_BITWIDTH 3 1310f2b7e78dSVipul Pandya #define PROTO_BITWIDTH 8 1311f2b7e78dSVipul Pandya #define TOS_BITWIDTH 8 1312f2b7e78dSVipul Pandya #define PF_BITWIDTH 8 1313f2b7e78dSVipul Pandya #define VF_BITWIDTH 8 1314f2b7e78dSVipul Pandya #define IVLAN_BITWIDTH 16 1315f2b7e78dSVipul Pandya #define OVLAN_BITWIDTH 16 131698f3697fSKumar Sanghvi #define ENCAP_VNI_BITWIDTH 24 1317f2b7e78dSVipul Pandya 1318f2b7e78dSVipul Pandya /* Filter matching rules. These consist of a set of ingress packet field 1319f2b7e78dSVipul Pandya * (value, mask) tuples. The associated ingress packet field matches the 1320f2b7e78dSVipul Pandya * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field 1321f2b7e78dSVipul Pandya * rule can be constructed by specifying a tuple of (0, 0).) A filter rule 1322f2b7e78dSVipul Pandya * matches an ingress packet when all of the individual individual field 1323f2b7e78dSVipul Pandya * matching rules are true. 1324f2b7e78dSVipul Pandya * 1325f2b7e78dSVipul Pandya * Partial field masks are always valid, however, while it may be easy to 1326f2b7e78dSVipul Pandya * understand their meanings for some fields (e.g. IP address to match a 1327f2b7e78dSVipul Pandya * subnet), for others making sensible partial masks is less intuitive (e.g. 1328f2b7e78dSVipul Pandya * MPS match type) ... 1329f2b7e78dSVipul Pandya * 1330f2b7e78dSVipul Pandya * Most of the following data structures are modeled on T4 capabilities. 1331f2b7e78dSVipul Pandya * Drivers for earlier chips use the subsets which make sense for those chips. 1332f2b7e78dSVipul Pandya * We really need to come up with a hardware-independent mechanism to 1333f2b7e78dSVipul Pandya * represent hardware filter capabilities ... 1334f2b7e78dSVipul Pandya */ 1335f2b7e78dSVipul Pandya struct ch_filter_tuple { 1336f2b7e78dSVipul Pandya /* Compressed header matching field rules. The TP_VLAN_PRI_MAP 1337f2b7e78dSVipul Pandya * register selects which of these fields will participate in the 1338f2b7e78dSVipul Pandya * filter match rules -- up to a maximum of 36 bits. Because 1339f2b7e78dSVipul Pandya * TP_VLAN_PRI_MAP is a global register, all filters must use the same 1340f2b7e78dSVipul Pandya * set of fields. 1341f2b7e78dSVipul Pandya */ 1342f2b7e78dSVipul Pandya uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */ 1343f2b7e78dSVipul Pandya uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */ 1344f2b7e78dSVipul Pandya uint32_t ivlan_vld:1; /* inner VLAN valid */ 1345f2b7e78dSVipul Pandya uint32_t ovlan_vld:1; /* outer VLAN valid */ 1346f2b7e78dSVipul Pandya uint32_t pfvf_vld:1; /* PF/VF valid */ 134798f3697fSKumar Sanghvi uint32_t encap_vld:1; /* Encapsulation valid */ 1348f2b7e78dSVipul Pandya uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */ 1349f2b7e78dSVipul Pandya uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */ 1350f2b7e78dSVipul Pandya uint32_t iport:IPORT_BITWIDTH; /* ingress port */ 1351f2b7e78dSVipul Pandya uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */ 1352f2b7e78dSVipul Pandya uint32_t proto:PROTO_BITWIDTH; /* protocol type */ 1353f2b7e78dSVipul Pandya uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */ 1354f2b7e78dSVipul Pandya uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */ 1355f2b7e78dSVipul Pandya uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */ 1356f2b7e78dSVipul Pandya uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */ 1357f2b7e78dSVipul Pandya uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */ 135898f3697fSKumar Sanghvi uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */ 1359f2b7e78dSVipul Pandya 1360f2b7e78dSVipul Pandya /* Uncompressed header matching field rules. These are always 1361f2b7e78dSVipul Pandya * available for field rules. 1362f2b7e78dSVipul Pandya */ 1363f2b7e78dSVipul Pandya uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */ 1364f2b7e78dSVipul Pandya uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */ 1365f2b7e78dSVipul Pandya uint16_t lport; /* local port */ 1366f2b7e78dSVipul Pandya uint16_t fport; /* foreign port */ 1367f2b7e78dSVipul Pandya }; 1368f2b7e78dSVipul Pandya 1369f2b7e78dSVipul Pandya /* A filter ioctl command. 1370f2b7e78dSVipul Pandya */ 1371f2b7e78dSVipul Pandya struct ch_filter_specification { 1372f2b7e78dSVipul Pandya /* Administrative fields for filter. 1373f2b7e78dSVipul Pandya */ 1374f2b7e78dSVipul Pandya uint32_t hitcnts:1; /* count filter hits in TCB */ 1375f2b7e78dSVipul Pandya uint32_t prio:1; /* filter has priority over active/server */ 1376f2b7e78dSVipul Pandya 1377f2b7e78dSVipul Pandya /* Fundamental filter typing. This is the one element of filter 1378f2b7e78dSVipul Pandya * matching that doesn't exist as a (value, mask) tuple. 1379f2b7e78dSVipul Pandya */ 1380f2b7e78dSVipul Pandya uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 138112b276fbSKumar Sanghvi u32 hash:1; /* 0 => wild-card, 1 => exact-match */ 1382f2b7e78dSVipul Pandya 1383f2b7e78dSVipul Pandya /* Packet dispatch information. Ingress packets which match the 1384f2b7e78dSVipul Pandya * filter rules will be dropped, passed to the host or switched back 1385f2b7e78dSVipul Pandya * out as egress packets. 1386f2b7e78dSVipul Pandya */ 1387f2b7e78dSVipul Pandya uint32_t action:2; /* drop, pass, switch */ 1388f2b7e78dSVipul Pandya 1389f2b7e78dSVipul Pandya uint32_t rpttid:1; /* report TID in RSS hash field */ 1390f2b7e78dSVipul Pandya 1391f2b7e78dSVipul Pandya uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 1392f2b7e78dSVipul Pandya uint32_t iq:10; /* ingress queue */ 1393f2b7e78dSVipul Pandya 1394f2b7e78dSVipul Pandya uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 1395f2b7e78dSVipul Pandya uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 1396f2b7e78dSVipul Pandya /* 1 => TCB contains IQ ID */ 1397f2b7e78dSVipul Pandya 1398f2b7e78dSVipul Pandya /* Switch proxy/rewrite fields. An ingress packet which matches a 1399f2b7e78dSVipul Pandya * filter with "switch" set will be looped back out as an egress 1400f2b7e78dSVipul Pandya * packet -- potentially with some Ethernet header rewriting. 1401f2b7e78dSVipul Pandya */ 1402f2b7e78dSVipul Pandya uint32_t eport:2; /* egress port to switch packet out */ 1403f2b7e78dSVipul Pandya uint32_t newdmac:1; /* rewrite destination MAC address */ 1404f2b7e78dSVipul Pandya uint32_t newsmac:1; /* rewrite source MAC address */ 1405f2b7e78dSVipul Pandya uint32_t newvlan:2; /* rewrite VLAN Tag */ 14060ff90994SKumar Sanghvi uint32_t nat_mode:3; /* specify NAT operation mode */ 1407f2b7e78dSVipul Pandya uint8_t dmac[ETH_ALEN]; /* new destination MAC address */ 1408f2b7e78dSVipul Pandya uint8_t smac[ETH_ALEN]; /* new source MAC address */ 1409f2b7e78dSVipul Pandya uint16_t vlan; /* VLAN Tag to insert */ 1410f2b7e78dSVipul Pandya 14110ff90994SKumar Sanghvi u8 nat_lip[16]; /* local IP to use after NAT'ing */ 14120ff90994SKumar Sanghvi u8 nat_fip[16]; /* foreign IP to use after NAT'ing */ 14130ff90994SKumar Sanghvi u16 nat_lport; /* local port to use after NAT'ing */ 14140ff90994SKumar Sanghvi u16 nat_fport; /* foreign port to use after NAT'ing */ 14150ff90994SKumar Sanghvi 141641ec03e5SRahul Lakkireddy u32 tc_prio; /* TC's filter priority index */ 141741ec03e5SRahul Lakkireddy u64 tc_cookie; /* Unique cookie identifying TC rules */ 141841ec03e5SRahul Lakkireddy 14190ff90994SKumar Sanghvi /* reservation for future additions */ 142041ec03e5SRahul Lakkireddy u8 rsvd[12]; 14210ff90994SKumar Sanghvi 1422f2b7e78dSVipul Pandya /* Filter rule value/mask pairs. 1423f2b7e78dSVipul Pandya */ 1424f2b7e78dSVipul Pandya struct ch_filter_tuple val; 1425f2b7e78dSVipul Pandya struct ch_filter_tuple mask; 1426f2b7e78dSVipul Pandya }; 1427f2b7e78dSVipul Pandya 1428f2b7e78dSVipul Pandya enum { 1429f2b7e78dSVipul Pandya FILTER_PASS = 0, /* default */ 1430f2b7e78dSVipul Pandya FILTER_DROP, 1431f2b7e78dSVipul Pandya FILTER_SWITCH 1432f2b7e78dSVipul Pandya }; 1433f2b7e78dSVipul Pandya 1434f2b7e78dSVipul Pandya enum { 1435f2b7e78dSVipul Pandya VLAN_NOCHANGE = 0, /* default */ 1436f2b7e78dSVipul Pandya VLAN_REMOVE, 1437f2b7e78dSVipul Pandya VLAN_INSERT, 1438f2b7e78dSVipul Pandya VLAN_REWRITE 1439f2b7e78dSVipul Pandya }; 1440f2b7e78dSVipul Pandya 1441557ccbf9SKumar Sanghvi enum { 144212b276fbSKumar Sanghvi NAT_MODE_NONE = 0, /* No NAT performed */ 144312b276fbSKumar Sanghvi NAT_MODE_DIP, /* NAT on Dst IP */ 144412b276fbSKumar Sanghvi NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */ 144512b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */ 144612b276fbSKumar Sanghvi NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */ 144712b276fbSKumar Sanghvi NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */ 144812b276fbSKumar Sanghvi NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */ 144912b276fbSKumar Sanghvi NAT_MODE_ALL /* NAT on entire 4-tuple */ 1450557ccbf9SKumar Sanghvi }; 1451557ccbf9SKumar Sanghvi 145259b328cfSRahul Lakkireddy #define CXGB4_FILTER_TYPE_MAX 2 145359b328cfSRahul Lakkireddy 1454d57fd6caSRahul Lakkireddy /* Host shadow copy of ingress filter entry. This is in host native format 1455d57fd6caSRahul Lakkireddy * and doesn't match the ordering or bit order, etc. of the hardware of the 1456d57fd6caSRahul Lakkireddy * firmware command. The use of bit-field structure elements is purely to 1457d57fd6caSRahul Lakkireddy * remind ourselves of the field size limitations and save memory in the case 1458d57fd6caSRahul Lakkireddy * where the filter table is large. 1459d57fd6caSRahul Lakkireddy */ 1460d57fd6caSRahul Lakkireddy struct filter_entry { 1461d57fd6caSRahul Lakkireddy /* Administrative fields for filter. */ 1462d57fd6caSRahul Lakkireddy u32 valid:1; /* filter allocated and valid */ 1463d57fd6caSRahul Lakkireddy u32 locked:1; /* filter is administratively locked */ 1464d57fd6caSRahul Lakkireddy 1465d57fd6caSRahul Lakkireddy u32 pending:1; /* filter action is pending firmware reply */ 1466578b46b9SRahul Lakkireddy struct filter_ctx *ctx; /* Caller's completion hook */ 1467d57fd6caSRahul Lakkireddy struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 14683bdb376eSKumar Sanghvi struct smt_entry *smt; /* Source Mac Table entry for smac */ 1469578b46b9SRahul Lakkireddy struct net_device *dev; /* Associated net device */ 1470578b46b9SRahul Lakkireddy u32 tid; /* This will store the actual tid */ 1471d57fd6caSRahul Lakkireddy 1472d57fd6caSRahul Lakkireddy /* The filter itself. Most of this is a straight copy of information 1473d57fd6caSRahul Lakkireddy * provided by the extended ioctl(). Some fields are translated to 1474d57fd6caSRahul Lakkireddy * internal forms -- for instance the Ingress Queue ID passed in from 1475d57fd6caSRahul Lakkireddy * the ioctl() is translated into the Absolute Ingress Queue ID. 1476d57fd6caSRahul Lakkireddy */ 1477d57fd6caSRahul Lakkireddy struct ch_filter_specification fs; 1478d57fd6caSRahul Lakkireddy }; 1479d57fd6caSRahul Lakkireddy 1480a4cfd929SHariprasad Shenai static inline int is_offload(const struct adapter *adap) 1481a4cfd929SHariprasad Shenai { 1482a4cfd929SHariprasad Shenai return adap->params.offload; 1483a4cfd929SHariprasad Shenai } 1484a4cfd929SHariprasad Shenai 14855c31254eSKumar Sanghvi static inline int is_hashfilter(const struct adapter *adap) 14865c31254eSKumar Sanghvi { 14875c31254eSKumar Sanghvi return adap->params.hash_filter; 14885c31254eSKumar Sanghvi } 14895c31254eSKumar Sanghvi 149094cdb8bbSHariprasad Shenai static inline int is_pci_uld(const struct adapter *adap) 149194cdb8bbSHariprasad Shenai { 149294cdb8bbSHariprasad Shenai return adap->params.crypto; 149394cdb8bbSHariprasad Shenai } 149494cdb8bbSHariprasad Shenai 14950fbc81b3SHariprasad Shenai static inline int is_uld(const struct adapter *adap) 14960fbc81b3SHariprasad Shenai { 14970fbc81b3SHariprasad Shenai return (adap->params.offload || adap->params.crypto); 14980fbc81b3SHariprasad Shenai } 14990fbc81b3SHariprasad Shenai 1500ab0367eaSRahul Lakkireddy static inline int is_ethofld(const struct adapter *adap) 1501ab0367eaSRahul Lakkireddy { 1502ab0367eaSRahul Lakkireddy return adap->params.ethofld; 1503ab0367eaSRahul Lakkireddy } 1504ab0367eaSRahul Lakkireddy 1505f7917c00SJeff Kirsher static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) 1506f7917c00SJeff Kirsher { 1507f7917c00SJeff Kirsher return readl(adap->regs + reg_addr); 1508f7917c00SJeff Kirsher } 1509f7917c00SJeff Kirsher 1510f7917c00SJeff Kirsher static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val) 1511f7917c00SJeff Kirsher { 1512f7917c00SJeff Kirsher writel(val, adap->regs + reg_addr); 1513f7917c00SJeff Kirsher } 1514f7917c00SJeff Kirsher 1515f7917c00SJeff Kirsher #ifndef readq 1516f7917c00SJeff Kirsher static inline u64 readq(const volatile void __iomem *addr) 1517f7917c00SJeff Kirsher { 1518f7917c00SJeff Kirsher return readl(addr) + ((u64)readl(addr + 4) << 32); 1519f7917c00SJeff Kirsher } 1520f7917c00SJeff Kirsher 1521f7917c00SJeff Kirsher static inline void writeq(u64 val, volatile void __iomem *addr) 1522f7917c00SJeff Kirsher { 1523f7917c00SJeff Kirsher writel(val, addr); 1524f7917c00SJeff Kirsher writel(val >> 32, addr + 4); 1525f7917c00SJeff Kirsher } 1526f7917c00SJeff Kirsher #endif 1527f7917c00SJeff Kirsher 1528f7917c00SJeff Kirsher static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr) 1529f7917c00SJeff Kirsher { 1530f7917c00SJeff Kirsher return readq(adap->regs + reg_addr); 1531f7917c00SJeff Kirsher } 1532f7917c00SJeff Kirsher 1533f7917c00SJeff Kirsher static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val) 1534f7917c00SJeff Kirsher { 1535f7917c00SJeff Kirsher writeq(val, adap->regs + reg_addr); 1536f7917c00SJeff Kirsher } 1537f7917c00SJeff Kirsher 1538f7917c00SJeff Kirsher /** 1539098ef6c2SHariprasad Shenai * t4_set_hw_addr - store a port's MAC address in SW 1540098ef6c2SHariprasad Shenai * @adapter: the adapter 1541098ef6c2SHariprasad Shenai * @port_idx: the port index 1542098ef6c2SHariprasad Shenai * @hw_addr: the Ethernet address 1543098ef6c2SHariprasad Shenai * 1544098ef6c2SHariprasad Shenai * Store the Ethernet address of the given port in SW. Called by the common 1545098ef6c2SHariprasad Shenai * code when it retrieves a port's Ethernet address from EEPROM. 1546098ef6c2SHariprasad Shenai */ 1547098ef6c2SHariprasad Shenai static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx, 1548098ef6c2SHariprasad Shenai u8 hw_addr[]) 1549098ef6c2SHariprasad Shenai { 1550098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr); 1551098ef6c2SHariprasad Shenai ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr); 1552098ef6c2SHariprasad Shenai } 1553098ef6c2SHariprasad Shenai 1554098ef6c2SHariprasad Shenai /** 1555f7917c00SJeff Kirsher * netdev2pinfo - return the port_info structure associated with a net_device 1556f7917c00SJeff Kirsher * @dev: the netdev 1557f7917c00SJeff Kirsher * 1558f7917c00SJeff Kirsher * Return the struct port_info associated with a net_device 1559f7917c00SJeff Kirsher */ 1560f7917c00SJeff Kirsher static inline struct port_info *netdev2pinfo(const struct net_device *dev) 1561f7917c00SJeff Kirsher { 1562f7917c00SJeff Kirsher return netdev_priv(dev); 1563f7917c00SJeff Kirsher } 1564f7917c00SJeff Kirsher 1565f7917c00SJeff Kirsher /** 1566f7917c00SJeff Kirsher * adap2pinfo - return the port_info of a port 1567f7917c00SJeff Kirsher * @adap: the adapter 1568f7917c00SJeff Kirsher * @idx: the port index 1569f7917c00SJeff Kirsher * 1570f7917c00SJeff Kirsher * Return the port_info structure for the port of the given index. 1571f7917c00SJeff Kirsher */ 1572f7917c00SJeff Kirsher static inline struct port_info *adap2pinfo(struct adapter *adap, int idx) 1573f7917c00SJeff Kirsher { 1574f7917c00SJeff Kirsher return netdev_priv(adap->port[idx]); 1575f7917c00SJeff Kirsher } 1576f7917c00SJeff Kirsher 1577f7917c00SJeff Kirsher /** 1578f7917c00SJeff Kirsher * netdev2adap - return the adapter structure associated with a net_device 1579f7917c00SJeff Kirsher * @dev: the netdev 1580f7917c00SJeff Kirsher * 1581f7917c00SJeff Kirsher * Return the struct adapter associated with a net_device 1582f7917c00SJeff Kirsher */ 1583f7917c00SJeff Kirsher static inline struct adapter *netdev2adap(const struct net_device *dev) 1584f7917c00SJeff Kirsher { 1585f7917c00SJeff Kirsher return netdev2pinfo(dev)->adapter; 1586f7917c00SJeff Kirsher } 1587f7917c00SJeff Kirsher 1588812034f1SHariprasad Shenai /* Return a version number to identify the type of adapter. The scheme is: 1589812034f1SHariprasad Shenai * - bits 0..9: chip version 1590812034f1SHariprasad Shenai * - bits 10..15: chip revision 1591812034f1SHariprasad Shenai * - bits 16..23: register dump version 1592812034f1SHariprasad Shenai */ 1593812034f1SHariprasad Shenai static inline unsigned int mk_adap_vers(struct adapter *ap) 1594812034f1SHariprasad Shenai { 1595812034f1SHariprasad Shenai return CHELSIO_CHIP_VERSION(ap->params.chip) | 1596812034f1SHariprasad Shenai (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16); 1597812034f1SHariprasad Shenai } 1598812034f1SHariprasad Shenai 1599812034f1SHariprasad Shenai /* Return a queue's interrupt hold-off time in us. 0 means no timer. */ 1600812034f1SHariprasad Shenai static inline unsigned int qtimer_val(const struct adapter *adap, 1601812034f1SHariprasad Shenai const struct sge_rspq *q) 1602812034f1SHariprasad Shenai { 1603812034f1SHariprasad Shenai unsigned int idx = q->intr_params >> 1; 1604812034f1SHariprasad Shenai 1605812034f1SHariprasad Shenai return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0; 1606812034f1SHariprasad Shenai } 1607812034f1SHariprasad Shenai 160801e392aaSLeon Romanovsky /* driver name used for ethtool_drvinfo */ 1609812034f1SHariprasad Shenai extern char cxgb4_driver_name[]; 1610812034f1SHariprasad Shenai 16118156b0baSGanesh Goudar void t4_os_portmod_changed(struct adapter *adap, int port_id); 1612f7917c00SJeff Kirsher void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat); 1613f7917c00SJeff Kirsher 1614f7917c00SJeff Kirsher void t4_free_sge_resources(struct adapter *adap); 16155fa76694SHariprasad Shenai void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q); 1616f7917c00SJeff Kirsher irq_handler_t t4_intr_handler(struct adapter *adap); 1617d5fbda61SArjun Vynipadath netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev); 16187235ffaeSVishal Kulkarni int cxgb4_selftest_lb_pkt(struct net_device *netdev); 1619f7917c00SJeff Kirsher int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, 1620f7917c00SJeff Kirsher const struct pkt_gl *gl); 1621f7917c00SJeff Kirsher int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb); 1622f7917c00SJeff Kirsher int t4_ofld_send(struct adapter *adap, struct sk_buff *skb); 1623f7917c00SJeff Kirsher int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, 1624f7917c00SJeff Kirsher struct net_device *dev, int intr_idx, 16252337ba42SVarun Prakash struct sge_fl *fl, rspq_handler_t hnd, 16262337ba42SVarun Prakash rspq_flush_handler_t flush_handler, int cong); 1627f7917c00SJeff Kirsher int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 1628f7917c00SJeff Kirsher struct net_device *dev, struct netdev_queue *netdevq, 1629d429005fSVishal Kulkarni unsigned int iqid, u8 dbqt); 1630f7917c00SJeff Kirsher int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 1631f7917c00SJeff Kirsher struct net_device *dev, unsigned int iqid, 1632f7917c00SJeff Kirsher unsigned int cmplqid); 16330fbc81b3SHariprasad Shenai int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, 16340fbc81b3SHariprasad Shenai unsigned int cmplqid); 1635ab677ff4SHariprasad Shenai int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, 1636ab677ff4SHariprasad Shenai struct net_device *dev, unsigned int iqid, 1637ab677ff4SHariprasad Shenai unsigned int uld_type); 16382d0cb84dSRahul Lakkireddy int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, 16392d0cb84dSRahul Lakkireddy struct net_device *dev, u32 iqid); 16402d0cb84dSRahul Lakkireddy void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq); 1641f7917c00SJeff Kirsher irqreturn_t t4_sge_intr_msix(int irq, void *cookie); 164252367a76SVipul Pandya int t4_sge_init(struct adapter *adap); 1643f7917c00SJeff Kirsher void t4_sge_start(struct adapter *adap); 1644f7917c00SJeff Kirsher void t4_sge_stop(struct adapter *adap); 1645d429005fSVishal Kulkarni int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q, 1646d429005fSVishal Kulkarni int maxreclaim); 1647812034f1SHariprasad Shenai void cxgb4_set_ethtool_ops(struct net_device *netdev); 1648812034f1SHariprasad Shenai int cxgb4_write_rss(const struct port_info *pi, const u16 *queues); 1649d0a1299cSGanesh Goudar enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb); 16503069ee9bSVipul Pandya extern int dbfifo_int_thresh; 1651f7917c00SJeff Kirsher 1652f7917c00SJeff Kirsher #define for_each_port(adapter, iter) \ 1653f7917c00SJeff Kirsher for (iter = 0; iter < (adapter)->params.nports; ++iter) 1654f7917c00SJeff Kirsher 16559a4da2cdSVipul Pandya static inline int is_bypass(struct adapter *adap) 16569a4da2cdSVipul Pandya { 16579a4da2cdSVipul Pandya return adap->params.bypass; 16589a4da2cdSVipul Pandya } 16599a4da2cdSVipul Pandya 16609a4da2cdSVipul Pandya static inline int is_bypass_device(int device) 16619a4da2cdSVipul Pandya { 16629a4da2cdSVipul Pandya /* this should be set based upon device capabilities */ 16639a4da2cdSVipul Pandya switch (device) { 16649a4da2cdSVipul Pandya case 0x440b: 16659a4da2cdSVipul Pandya case 0x440c: 16669a4da2cdSVipul Pandya return 1; 16679a4da2cdSVipul Pandya default: 16689a4da2cdSVipul Pandya return 0; 16699a4da2cdSVipul Pandya } 16709a4da2cdSVipul Pandya } 16719a4da2cdSVipul Pandya 167201b69614SHariprasad Shenai static inline int is_10gbt_device(int device) 167301b69614SHariprasad Shenai { 167401b69614SHariprasad Shenai /* this should be set based upon device capabilities */ 167501b69614SHariprasad Shenai switch (device) { 167601b69614SHariprasad Shenai case 0x4409: 167701b69614SHariprasad Shenai case 0x4486: 167801b69614SHariprasad Shenai return 1; 167901b69614SHariprasad Shenai 168001b69614SHariprasad Shenai default: 168101b69614SHariprasad Shenai return 0; 168201b69614SHariprasad Shenai } 168301b69614SHariprasad Shenai } 168401b69614SHariprasad Shenai 1685f7917c00SJeff Kirsher static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 1686f7917c00SJeff Kirsher { 1687f7917c00SJeff Kirsher return adap->params.vpd.cclk / 1000; 1688f7917c00SJeff Kirsher } 1689f7917c00SJeff Kirsher 1690f7917c00SJeff Kirsher static inline unsigned int us_to_core_ticks(const struct adapter *adap, 1691f7917c00SJeff Kirsher unsigned int us) 1692f7917c00SJeff Kirsher { 1693f7917c00SJeff Kirsher return (us * adap->params.vpd.cclk) / 1000; 1694f7917c00SJeff Kirsher } 1695f7917c00SJeff Kirsher 169652367a76SVipul Pandya static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 169752367a76SVipul Pandya unsigned int ticks) 169852367a76SVipul Pandya { 169952367a76SVipul Pandya /* add Core Clock / 2 to round ticks to nearest uS */ 170052367a76SVipul Pandya return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 170152367a76SVipul Pandya adapter->params.vpd.cclk); 170252367a76SVipul Pandya } 170352367a76SVipul Pandya 170408c4901bSRahul Lakkireddy static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 170508c4901bSRahul Lakkireddy unsigned int ticks) 170608c4901bSRahul Lakkireddy { 170708c4901bSRahul Lakkireddy return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 170808c4901bSRahul Lakkireddy } 170908c4901bSRahul Lakkireddy 1710f7917c00SJeff Kirsher void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 1711f7917c00SJeff Kirsher u32 val); 1712f7917c00SJeff Kirsher 171301b69614SHariprasad Shenai int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 171401b69614SHariprasad Shenai int size, void *rpl, bool sleep_ok, int timeout); 1715f7917c00SJeff Kirsher int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 1716f7917c00SJeff Kirsher void *rpl, bool sleep_ok); 1717f7917c00SJeff Kirsher 171801b69614SHariprasad Shenai static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 171901b69614SHariprasad Shenai const void *cmd, int size, void *rpl, 172001b69614SHariprasad Shenai int timeout) 172101b69614SHariprasad Shenai { 172201b69614SHariprasad Shenai return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 172301b69614SHariprasad Shenai timeout); 172401b69614SHariprasad Shenai } 172501b69614SHariprasad Shenai 1726f7917c00SJeff Kirsher static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 1727f7917c00SJeff Kirsher int size, void *rpl) 1728f7917c00SJeff Kirsher { 1729f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 1730f7917c00SJeff Kirsher } 1731f7917c00SJeff Kirsher 1732f7917c00SJeff Kirsher static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 1733f7917c00SJeff Kirsher int size, void *rpl) 1734f7917c00SJeff Kirsher { 1735f7917c00SJeff Kirsher return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 1736f7917c00SJeff Kirsher } 1737f7917c00SJeff Kirsher 1738fc08a01aSHariprasad Shenai /** 1739fc08a01aSHariprasad Shenai * hash_mac_addr - return the hash value of a MAC address 1740fc08a01aSHariprasad Shenai * @addr: the 48-bit Ethernet MAC address 1741fc08a01aSHariprasad Shenai * 1742fc08a01aSHariprasad Shenai * Hashes a MAC address according to the hash function used by HW inexact 1743fc08a01aSHariprasad Shenai * (hash) address matching. 1744fc08a01aSHariprasad Shenai */ 1745fc08a01aSHariprasad Shenai static inline int hash_mac_addr(const u8 *addr) 1746fc08a01aSHariprasad Shenai { 1747fc08a01aSHariprasad Shenai u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 1748fc08a01aSHariprasad Shenai u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 1749fc08a01aSHariprasad Shenai 1750fc08a01aSHariprasad Shenai a ^= b; 1751fc08a01aSHariprasad Shenai a ^= (a >> 12); 1752fc08a01aSHariprasad Shenai a ^= (a >> 6); 1753fc08a01aSHariprasad Shenai return a & 0x3f; 1754fc08a01aSHariprasad Shenai } 1755fc08a01aSHariprasad Shenai 175694cdb8bbSHariprasad Shenai int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 175794cdb8bbSHariprasad Shenai unsigned int cnt); 175894cdb8bbSHariprasad Shenai static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 175994cdb8bbSHariprasad Shenai unsigned int us, unsigned int cnt, 176094cdb8bbSHariprasad Shenai unsigned int size, unsigned int iqe_size) 176194cdb8bbSHariprasad Shenai { 176294cdb8bbSHariprasad Shenai q->adap = adap; 176394cdb8bbSHariprasad Shenai cxgb4_set_rspq_intr_params(q, us, cnt); 176494cdb8bbSHariprasad Shenai q->iqe_len = iqe_size; 176594cdb8bbSHariprasad Shenai q->size = size; 176694cdb8bbSHariprasad Shenai } 176794cdb8bbSHariprasad Shenai 1768f56ec676SArjun Vynipadath /** 1769f56ec676SArjun Vynipadath * t4_is_inserted_mod_type - is a plugged in Firmware Module Type 1770f56ec676SArjun Vynipadath * @fw_mod_type: the Firmware Mofule Type 1771f56ec676SArjun Vynipadath * 1772f56ec676SArjun Vynipadath * Return whether the Firmware Module Type represents a real Transceiver 1773f56ec676SArjun Vynipadath * Module/Cable Module Type which has been inserted. 1774f56ec676SArjun Vynipadath */ 1775f56ec676SArjun Vynipadath static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type) 1776f56ec676SArjun Vynipadath { 1777f56ec676SArjun Vynipadath return (fw_mod_type != FW_PORT_MOD_TYPE_NONE && 1778f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED && 1779f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN && 1780f56ec676SArjun Vynipadath fw_mod_type != FW_PORT_MOD_TYPE_ERROR); 1781f56ec676SArjun Vynipadath } 1782f56ec676SArjun Vynipadath 178313ee15d3SVipul Pandya void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 178413ee15d3SVipul Pandya unsigned int data_reg, const u32 *vals, 178513ee15d3SVipul Pandya unsigned int nregs, unsigned int start_idx); 1786f2b7e78dSVipul Pandya void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 1787f2b7e78dSVipul Pandya unsigned int data_reg, u32 *vals, unsigned int nregs, 1788f2b7e78dSVipul Pandya unsigned int start_idx); 17890abfd152SHariprasad Shenai void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); 1790f2b7e78dSVipul Pandya 1791f2b7e78dSVipul Pandya struct fw_filter_wr; 1792f2b7e78dSVipul Pandya 1793f7917c00SJeff Kirsher void t4_intr_enable(struct adapter *adapter); 1794f7917c00SJeff Kirsher void t4_intr_disable(struct adapter *adapter); 1795f7917c00SJeff Kirsher int t4_slow_intr_handler(struct adapter *adapter); 1796f7917c00SJeff Kirsher 17978203b509SHariprasad Shenai int t4_wait_dev_ready(void __iomem *regs); 17988156b0baSGanesh Goudar 17999f764898SVishal Kulkarni fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port, 18009f764898SVishal Kulkarni struct link_config *lc); 18018156b0baSGanesh Goudar int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox, 18028156b0baSGanesh Goudar unsigned int port, struct link_config *lc, 18039f764898SVishal Kulkarni u8 sleep_ok, int timeout); 18048156b0baSGanesh Goudar 18058156b0baSGanesh Goudar static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox, 18068156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 18078156b0baSGanesh Goudar { 18088156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 18098156b0baSGanesh Goudar true, FW_CMD_MAX_TIMEOUT); 18108156b0baSGanesh Goudar } 18118156b0baSGanesh Goudar 18128156b0baSGanesh Goudar static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox, 18138156b0baSGanesh Goudar unsigned int port, struct link_config *lc) 18148156b0baSGanesh Goudar { 18158156b0baSGanesh Goudar return t4_link_l1cfg_core(adapter, mbox, port, lc, 18168156b0baSGanesh Goudar false, FW_CMD_MAX_TIMEOUT); 18178156b0baSGanesh Goudar } 18188156b0baSGanesh Goudar 1819f7917c00SJeff Kirsher int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 1820fc5ab020SHariprasad Shenai 1821b562fc37SHariprasad Shenai u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); 1822b562fc37SHariprasad Shenai u32 t4_get_util_window(struct adapter *adap); 1823b562fc37SHariprasad Shenai void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window); 1824b562fc37SHariprasad Shenai 18251a4330cdSRahul Lakkireddy int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off, 18261a4330cdSRahul Lakkireddy u32 *mem_base, u32 *mem_aperture); 18271a4330cdSRahul Lakkireddy void t4_memory_update_win(struct adapter *adap, int win, u32 addr); 18281a4330cdSRahul Lakkireddy void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf, 18291a4330cdSRahul Lakkireddy int dir); 1830fc5ab020SHariprasad Shenai #define T4_MEMORY_WRITE 0 1831fc5ab020SHariprasad Shenai #define T4_MEMORY_READ 1 1832fc5ab020SHariprasad Shenai int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len, 1833f01aa633SHariprasad Shenai void *buf, int dir); 1834fc5ab020SHariprasad Shenai static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr, 1835fc5ab020SHariprasad Shenai u32 len, __be32 *buf) 1836fc5ab020SHariprasad Shenai { 1837fc5ab020SHariprasad Shenai return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0); 1838fc5ab020SHariprasad Shenai } 1839fc5ab020SHariprasad Shenai 1840812034f1SHariprasad Shenai unsigned int t4_get_regs_len(struct adapter *adapter); 1841812034f1SHariprasad Shenai void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); 1842812034f1SHariprasad Shenai 1843940c9c45SRahul Lakkireddy int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 1844f7917c00SJeff Kirsher int t4_seeprom_wp(struct adapter *adapter, bool enable); 1845098ef6c2SHariprasad Shenai int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p); 1846098ef6c2SHariprasad Shenai int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p); 18470eaec62aSCasey Leedom int t4_get_pfres(struct adapter *adapter); 184849216c1cSHariprasad Shenai int t4_read_flash(struct adapter *adapter, unsigned int addr, 184949216c1cSHariprasad Shenai unsigned int nwords, u32 *data, int byte_oriented); 1850f7917c00SJeff Kirsher int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 18515fff701cSRahul Lakkireddy int t4_load_phy_fw(struct adapter *adap, int win, 185201b69614SHariprasad Shenai int (*phy_fw_version)(const u8 *, size_t), 185301b69614SHariprasad Shenai const u8 *phy_fw_data, size_t phy_fw_size); 185401b69614SHariprasad Shenai int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver); 185549216c1cSHariprasad Shenai int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 185622c0b963SHariprasad Shenai int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 185722c0b963SHariprasad Shenai const u8 *fw_data, unsigned int size, int force); 1858acac5962SHariprasad Shenai int t4_fl_pkt_align(struct adapter *adap); 1859636f9d37SVipul Pandya unsigned int t4_flash_cfg_addr(struct adapter *adapter); 1860a69265e9SHariprasad Shenai int t4_check_fw_version(struct adapter *adap); 18614da18741SArjun Vynipadath int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 186216e47624SHariprasad Shenai int t4_get_fw_version(struct adapter *adapter, u32 *vers); 18630de72738SHariprasad Shenai int t4_get_bs_version(struct adapter *adapter, u32 *vers); 186416e47624SHariprasad Shenai int t4_get_tp_version(struct adapter *adapter, u32 *vers); 1865ba3f8cd5SHariprasad Shenai int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 1866760446f9SGanesh Goudar int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 1867760446f9SGanesh Goudar int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 1868760446f9SGanesh Goudar int t4_get_version_info(struct adapter *adapter); 1869760446f9SGanesh Goudar void t4_dump_version_info(struct adapter *adapter); 187016e47624SHariprasad Shenai int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, 187116e47624SHariprasad Shenai const u8 *fw_data, unsigned int fw_size, 187216e47624SHariprasad Shenai struct fw_hdr *card_fw, enum dev_state state, int *reset); 1873f7917c00SJeff Kirsher int t4_prep_adapter(struct adapter *adapter); 18743be0679bSHariprasad Shenai int t4_shutdown_adapter(struct adapter *adapter); 1875e85c9a7aSHariprasad Shenai 1876e85c9a7aSHariprasad Shenai enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 1877b2612722SHariprasad Shenai int t4_bar2_sge_qregs(struct adapter *adapter, 1878e85c9a7aSHariprasad Shenai unsigned int qid, 1879e85c9a7aSHariprasad Shenai enum t4_bar2_qtype qtype, 188066cf188eSHariprasad S int user, 1881e85c9a7aSHariprasad Shenai u64 *pbar2_qoffset, 1882e85c9a7aSHariprasad Shenai unsigned int *pbar2_qid); 1883e85c9a7aSHariprasad Shenai 1884dc9daab2SHariprasad Shenai unsigned int qtimer_val(const struct adapter *adap, 1885dc9daab2SHariprasad Shenai const struct sge_rspq *q); 1886ae469b68SHariprasad Shenai 1887ae469b68SHariprasad Shenai int t4_init_devlog_params(struct adapter *adapter); 1888e85c9a7aSHariprasad Shenai int t4_init_sge_params(struct adapter *adapter); 18895ccf9d04SRahul Lakkireddy int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 1890dcf7b6f5SKumar Sanghvi int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 1891c035e183SHariprasad Shenai int t4_init_rss_mode(struct adapter *adap, int mbox); 1892c3e324e3SHariprasad Shenai int t4_init_portinfo(struct port_info *pi, int mbox, 1893c3e324e3SHariprasad Shenai int port, int pf, int vf, u8 mac[]); 1894f7917c00SJeff Kirsher int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); 1895fd2261d8SRahul Lakkireddy int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf, 1896fd2261d8SRahul Lakkireddy u16 *mirror_viid); 1897f7917c00SJeff Kirsher void t4_fatal_err(struct adapter *adapter); 1898f988008aSGanesh Goudar unsigned int t4_chip_rss_size(struct adapter *adapter); 1899f7917c00SJeff Kirsher int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 1900f7917c00SJeff Kirsher int start, int n, const u16 *rspq, unsigned int nrspq); 1901f7917c00SJeff Kirsher int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 1902f7917c00SJeff Kirsher unsigned int flags); 1903c035e183SHariprasad Shenai int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 1904c035e183SHariprasad Shenai unsigned int flags, unsigned int defq); 1905688ea5feSHariprasad Shenai int t4_read_rss(struct adapter *adapter, u16 *entries); 19065ccf9d04SRahul Lakkireddy void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 19075ccf9d04SRahul Lakkireddy void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 19085ccf9d04SRahul Lakkireddy bool sleep_ok); 1909688ea5feSHariprasad Shenai void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 19105ccf9d04SRahul Lakkireddy u32 *valp, bool sleep_ok); 1911688ea5feSHariprasad Shenai void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 19125ccf9d04SRahul Lakkireddy u32 *vfl, u32 *vfh, bool sleep_ok); 19135ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 19145ccf9d04SRahul Lakkireddy u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 1915688ea5feSHariprasad Shenai 1916193c4c28SArjun Vynipadath unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx); 1917193c4c28SArjun Vynipadath unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx); 1918b3bbe36aSHariprasad Shenai void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1919b3bbe36aSHariprasad Shenai void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 1920e5f0e43bSHariprasad Shenai int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 1921e5f0e43bSHariprasad Shenai size_t n); 1922c778af7dSHariprasad Shenai int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 1923c778af7dSHariprasad Shenai size_t n); 1924f1ff24aaSHariprasad Shenai int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1925f1ff24aaSHariprasad Shenai unsigned int *valp); 1926f1ff24aaSHariprasad Shenai int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1927f1ff24aaSHariprasad Shenai const unsigned int *valp); 1928f1ff24aaSHariprasad Shenai int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 192919689609SHariprasad Shenai void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 193019689609SHariprasad Shenai unsigned int *pif_req_wrptr, 193119689609SHariprasad Shenai unsigned int *pif_rsp_wrptr); 193226fae93fSHariprasad Shenai void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 193374b3092cSHariprasad Shenai void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 193472aca4bfSKumar Sanghvi const char *t4_get_port_type_description(enum fw_port_type port_type); 1935f7917c00SJeff Kirsher void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1936a4cfd929SHariprasad Shenai void t4_get_port_stats_offset(struct adapter *adap, int idx, 1937a4cfd929SHariprasad Shenai struct port_stats *stats, 1938a4cfd929SHariprasad Shenai struct port_stats *offset); 193965046e84SHariprasad Shenai void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 1940f7917c00SJeff Kirsher void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1941bad43792SHariprasad Shenai void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 1942636f9d37SVipul Pandya void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 1943636f9d37SVipul Pandya unsigned int mask, unsigned int val); 19442d277b3bSHariprasad Shenai void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 19455ccf9d04SRahul Lakkireddy void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 19465ccf9d04SRahul Lakkireddy bool sleep_ok); 19475ccf9d04SRahul Lakkireddy void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 19485ccf9d04SRahul Lakkireddy bool sleep_ok); 19495ccf9d04SRahul Lakkireddy void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 19505ccf9d04SRahul Lakkireddy bool sleep_ok); 19515ccf9d04SRahul Lakkireddy void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 19525ccf9d04SRahul Lakkireddy bool sleep_ok); 1953f7917c00SJeff Kirsher void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 19545ccf9d04SRahul Lakkireddy struct tp_tcp_stats *v6, bool sleep_ok); 1955a6222975SHariprasad Shenai void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 19565ccf9d04SRahul Lakkireddy struct tp_fcoe_stats *st, bool sleep_ok); 1957f7917c00SJeff Kirsher void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 1958f7917c00SJeff Kirsher const unsigned short *alpha, const unsigned short *beta); 1959f7917c00SJeff Kirsher 1960797ff0f5SHariprasad Shenai void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 1961797ff0f5SHariprasad Shenai 19627864026bSHariprasad Shenai void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 1963f2b7e78dSVipul Pandya void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 1964f2b7e78dSVipul Pandya 1965f7917c00SJeff Kirsher void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 1966f7917c00SJeff Kirsher const u8 *addr); 1967f7917c00SJeff Kirsher int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 1968f7917c00SJeff Kirsher u64 mask0, u64 mask1, unsigned int crc, bool enable); 1969f7917c00SJeff Kirsher 1970f7917c00SJeff Kirsher int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 1971f7917c00SJeff Kirsher enum dev_master master, enum dev_state *state); 1972f7917c00SJeff Kirsher int t4_fw_bye(struct adapter *adap, unsigned int mbox); 1973f7917c00SJeff Kirsher int t4_early_init(struct adapter *adap, unsigned int mbox); 1974f7917c00SJeff Kirsher int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 1975636f9d37SVipul Pandya int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, 1976636f9d37SVipul Pandya unsigned int cache_line_size); 1977636f9d37SVipul Pandya int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 1978f7917c00SJeff Kirsher int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 1979f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 1980f7917c00SJeff Kirsher u32 *val); 19818f46d467SArjun Vynipadath int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, 19828f46d467SArjun Vynipadath unsigned int vf, unsigned int nparams, const u32 *params, 19838f46d467SArjun Vynipadath u32 *val); 198401b69614SHariprasad Shenai int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 1985f7917c00SJeff Kirsher unsigned int vf, unsigned int nparams, const u32 *params, 19868f46d467SArjun Vynipadath u32 *val, int rw, bool sleep_ok); 198701b69614SHariprasad Shenai int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 1988688848b1SAnish Bhatt unsigned int pf, unsigned int vf, 1989688848b1SAnish Bhatt unsigned int nparams, const u32 *params, 199001b69614SHariprasad Shenai const u32 *val, int timeout); 199101b69614SHariprasad Shenai int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 199201b69614SHariprasad Shenai unsigned int vf, unsigned int nparams, const u32 *params, 1993688848b1SAnish Bhatt const u32 *val); 1994f7917c00SJeff Kirsher int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 1995f7917c00SJeff Kirsher unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 1996f7917c00SJeff Kirsher unsigned int rxqi, unsigned int rxq, unsigned int tc, 1997f7917c00SJeff Kirsher unsigned int vi, unsigned int cmask, unsigned int pmask, 1998f7917c00SJeff Kirsher unsigned int nexact, unsigned int rcaps, unsigned int wxcaps); 1999f7917c00SJeff Kirsher int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 2000f7917c00SJeff Kirsher unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 200102d805dcSSantosh Rastapur unsigned int *rss_size, u8 *vivld, u8 *vin); 20024f3a0fcfSHariprasad Shenai int t4_free_vi(struct adapter *adap, unsigned int mbox, 20034f3a0fcfSHariprasad Shenai unsigned int pf, unsigned int vf, 20044f3a0fcfSHariprasad Shenai unsigned int viid); 2005f7917c00SJeff Kirsher int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 2006696c278fSRahul Lakkireddy unsigned int viid_mirror, int mtu, int promisc, int all_multi, 2007696c278fSRahul Lakkireddy int bcast, int vlanex, bool sleep_ok); 2008846eac3fSGanesh Goudar int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 2009846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 2010846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 201198f3697fSKumar Sanghvi int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx, 201298f3697fSKumar Sanghvi bool sleep_ok); 201398f3697fSKumar Sanghvi int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 201498f3697fSKumar Sanghvi const u8 *addr, const u8 *mask, unsigned int vni, 201598f3697fSKumar Sanghvi unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 201698f3697fSKumar Sanghvi bool sleep_ok); 2017846eac3fSGanesh Goudar int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 2018846eac3fSGanesh Goudar const u8 *addr, const u8 *mask, unsigned int idx, 2019846eac3fSGanesh Goudar u8 lookup_type, u8 port_id, bool sleep_ok); 2020f7917c00SJeff Kirsher int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 2021f7917c00SJeff Kirsher unsigned int viid, bool free, unsigned int naddr, 2022f7917c00SJeff Kirsher const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); 2023fc08a01aSHariprasad Shenai int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 2024fc08a01aSHariprasad Shenai unsigned int viid, unsigned int naddr, 2025fc08a01aSHariprasad Shenai const u8 **addr, bool sleep_ok); 2026f7917c00SJeff Kirsher int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 202702d805dcSSantosh Rastapur int idx, const u8 *addr, bool persist, u8 *smt_idx); 2028f7917c00SJeff Kirsher int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 2029f7917c00SJeff Kirsher bool ucast, u64 vec, bool sleep_ok); 2030688848b1SAnish Bhatt int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 2031688848b1SAnish Bhatt unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 2032e2f4f4e9SArjun Vynipadath int t4_enable_pi_params(struct adapter *adap, unsigned int mbox, 2033e2f4f4e9SArjun Vynipadath struct port_info *pi, 2034e2f4f4e9SArjun Vynipadath bool rx_en, bool tx_en, bool dcb_en); 2035f7917c00SJeff Kirsher int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 2036f7917c00SJeff Kirsher bool rx_en, bool tx_en); 2037f7917c00SJeff Kirsher int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 2038f7917c00SJeff Kirsher unsigned int nblinks); 2039f7917c00SJeff Kirsher int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 2040f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 *valp); 2041f7917c00SJeff Kirsher int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 2042f7917c00SJeff Kirsher unsigned int mmd, unsigned int reg, u16 val); 2043ebf4dc2bSHariprasad Shenai int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 2044ebf4dc2bSHariprasad Shenai unsigned int vf, unsigned int iqtype, unsigned int iqid, 2045ebf4dc2bSHariprasad Shenai unsigned int fl0id, unsigned int fl1id); 2046f7917c00SJeff Kirsher int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2047f7917c00SJeff Kirsher unsigned int vf, unsigned int iqtype, unsigned int iqid, 2048f7917c00SJeff Kirsher unsigned int fl0id, unsigned int fl1id); 2049f7917c00SJeff Kirsher int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2050f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 2051f7917c00SJeff Kirsher int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2052f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 2053f7917c00SJeff Kirsher int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 2054f7917c00SJeff Kirsher unsigned int vf, unsigned int eqid); 2055736c3b94SRahul Lakkireddy int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type); 2056d429005fSVishal Kulkarni int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers, 2057d429005fSVishal Kulkarni u16 *dbqtimers); 205823853a0aSHariprasad Shenai void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl); 20592061ec3fSGanesh Goudar int t4_update_port_info(struct port_info *pi); 2060c3168cabSGanesh Goudar int t4_get_link_params(struct port_info *pi, unsigned int *link_okp, 2061c3168cabSGanesh Goudar unsigned int *speedp, unsigned int *mtup); 2062f7917c00SJeff Kirsher int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 2063881806bcSVipul Pandya void t4_db_full(struct adapter *adapter); 2064881806bcSVipul Pandya void t4_db_dropped(struct adapter *adapter); 20658e3d04fdSHariprasad Shenai int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 20668e3d04fdSHariprasad Shenai int filter_index, int enable); 20678e3d04fdSHariprasad Shenai void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 20688e3d04fdSHariprasad Shenai int filter_index, int *enabled); 20698caa1e84SVipul Pandya int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 20708caa1e84SVipul Pandya u32 addr, u32 val); 207108c4901bSRahul Lakkireddy void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 207208c4901bSRahul Lakkireddy void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 207308c4901bSRahul Lakkireddy unsigned int *kbps, unsigned int *ipg, bool sleep_ok); 20749e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 20759e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 20769e5c598cSRahul Lakkireddy int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 20779e5c598cSRahul Lakkireddy enum ctxt_type ctype, u32 *data); 20784bccfc03SRahul Lakkireddy int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode, 20794bccfc03SRahul Lakkireddy u8 rateunit, u8 ratemode, u8 channel, u8 class, 20804bccfc03SRahul Lakkireddy u32 minrate, u32 maxrate, u16 weight, u16 pktsize, 20814bccfc03SRahul Lakkireddy u16 burstsize); 208268bce192SKumar Sanghvi void t4_sge_decode_idma_state(struct adapter *adapter, int state); 2083a3bfb617SHariprasad Shenai void t4_idma_monitor_init(struct adapter *adapter, 2084a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma); 2085a3bfb617SHariprasad Shenai void t4_idma_monitor(struct adapter *adapter, 2086a3bfb617SHariprasad Shenai struct sge_idma_monitor_state *idma, 2087a3bfb617SHariprasad Shenai int hz, int ticks); 2088858aa65cSHariprasad Shenai int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf, 2089858aa65cSHariprasad Shenai unsigned int naddr, u8 *addr); 20905ccf9d04SRahul Lakkireddy void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 20915ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 20924359cf33SRahul Lakkireddy void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 20934359cf33SRahul Lakkireddy u32 start_index, bool sleep_ok); 20945ccf9d04SRahul Lakkireddy void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 20955ccf9d04SRahul Lakkireddy u32 start_index, bool sleep_ok); 20965ccf9d04SRahul Lakkireddy 20970fbc81b3SHariprasad Shenai void t4_uld_mem_free(struct adapter *adap); 20980fbc81b3SHariprasad Shenai int t4_uld_mem_alloc(struct adapter *adap); 20990fbc81b3SHariprasad Shenai void t4_uld_clean_up(struct adapter *adap); 21000fbc81b3SHariprasad Shenai void t4_register_netevent_notifier(void); 2101f56ec676SArjun Vynipadath int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port, 2102f56ec676SArjun Vynipadath unsigned int devid, unsigned int offset, 2103f56ec676SArjun Vynipadath unsigned int len, u8 *buf); 210455088355SVishal Kulkarni int t4_load_boot(struct adapter *adap, u8 *boot_data, 210555088355SVishal Kulkarni unsigned int boot_addr, unsigned int size); 2106d5002c9aSVishal Kulkarni int t4_load_bootcfg(struct adapter *adap, 2107d5002c9aSVishal Kulkarni const u8 *cfg_data, unsigned int size); 210894cdb8bbSHariprasad Shenai void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl); 2109ab677ff4SHariprasad Shenai void free_tx_desc(struct adapter *adap, struct sge_txq *q, 2110ab677ff4SHariprasad Shenai unsigned int n, bool unmap); 2111b1396c2bSRahul Lakkireddy void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq, 2112b1396c2bSRahul Lakkireddy u32 ndesc); 21130e395b3cSRahul Lakkireddy int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc); 21140eb484eeSAllen Pais void cxgb4_ethofld_restart(struct tasklet_struct *t); 21154846d533SRahul Lakkireddy int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, 21164846d533SRahul Lakkireddy const struct pkt_gl *si); 2117ab677ff4SHariprasad Shenai void free_txq(struct adapter *adap, struct sge_txq *q); 2118a6ec572bSAtul Gupta void cxgb4_reclaim_completed_tx(struct adapter *adap, 2119a6ec572bSAtul Gupta struct sge_txq *q, bool unmap); 2120a6ec572bSAtul Gupta int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, 2121a6ec572bSAtul Gupta dma_addr_t *addr); 2122a6ec572bSAtul Gupta void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q, 2123a6ec572bSAtul Gupta void *pos); 2124a6ec572bSAtul Gupta void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, 2125a6ec572bSAtul Gupta struct ulptx_sgl *sgl, u64 *end, unsigned int start, 2126a6ec572bSAtul Gupta const dma_addr_t *addr); 2127a6ec572bSAtul Gupta void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n); 21289d5fd927SGanesh Goudar int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 21299d5fd927SGanesh Goudar u16 vlan); 2130ebddd97aSGanesh Goudar int cxgb4_dcb_enabled(const struct net_device *dev); 2131b1871915SGanesh Goudar 2132b1871915SGanesh Goudar int cxgb4_thermal_init(struct adapter *adap); 2133b1871915SGanesh Goudar int cxgb4_thermal_remove(struct adapter *adap); 2134c9765074SNirranjan Kirubaharan int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 2135c9765074SNirranjan Kirubaharan cpumask_var_t *aff_mask, int idx); 2136c9765074SNirranjan Kirubaharan void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask); 2137b1871915SGanesh Goudar 21382f0b9406SRaju Rangoju int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 21392f0b9406SRaju Rangoju int *tcam_idx, const u8 *addr, 21402f0b9406SRaju Rangoju bool persistent, u8 *smt_idx); 21412f0b9406SRaju Rangoju 2142f9f329adSRaju Rangoju int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid, 2143f9f329adSRaju Rangoju bool free, unsigned int naddr, 2144f9f329adSRaju Rangoju const u8 **addr, u16 *idx, 2145f9f329adSRaju Rangoju u64 *hash, bool sleep_ok); 2146f9f329adSRaju Rangoju int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid, 2147f9f329adSRaju Rangoju unsigned int naddr, const u8 **addr, bool sleep_ok); 214828b38705SRaju Rangoju int cxgb4_init_mps_ref_entries(struct adapter *adap); 214928b38705SRaju Rangoju void cxgb4_free_mps_ref_entries(struct adapter *adap); 215028b38705SRaju Rangoju int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 215128b38705SRaju Rangoju const u8 *addr, const u8 *mask, 215228b38705SRaju Rangoju unsigned int vni, unsigned int vni_mask, 215328b38705SRaju Rangoju u8 dip_hit, u8 lookup_type, bool sleep_ok); 215428b38705SRaju Rangoju int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 215528b38705SRaju Rangoju int idx, bool sleep_ok); 21565fab5158SRaju Rangoju int cxgb4_free_raw_mac_filt(struct adapter *adap, 21575fab5158SRaju Rangoju unsigned int viid, 21585fab5158SRaju Rangoju const u8 *addr, 21595fab5158SRaju Rangoju const u8 *mask, 21605fab5158SRaju Rangoju unsigned int idx, 21615fab5158SRaju Rangoju u8 lookup_type, 21625fab5158SRaju Rangoju u8 port_id, 21635fab5158SRaju Rangoju bool sleep_ok); 21645fab5158SRaju Rangoju int cxgb4_alloc_raw_mac_filt(struct adapter *adap, 21655fab5158SRaju Rangoju unsigned int viid, 21665fab5158SRaju Rangoju const u8 *addr, 21675fab5158SRaju Rangoju const u8 *mask, 21685fab5158SRaju Rangoju unsigned int idx, 21695fab5158SRaju Rangoju u8 lookup_type, 21705fab5158SRaju Rangoju u8 port_id, 21715fab5158SRaju Rangoju bool sleep_ok); 21722f0b9406SRaju Rangoju int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid, 21732f0b9406SRaju Rangoju int *tcam_idx, const u8 *addr, 21742f0b9406SRaju Rangoju bool persistent, u8 *smt_idx); 217576c3a552SRahul Lakkireddy int cxgb4_get_msix_idx_from_bmap(struct adapter *adap); 217676c3a552SRahul Lakkireddy void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx); 2177b1396c2bSRahul Lakkireddy int cxgb_open(struct net_device *dev); 2178b1396c2bSRahul Lakkireddy int cxgb_close(struct net_device *dev); 21792d0cb84dSRahul Lakkireddy void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q); 21802d0cb84dSRahul Lakkireddy void cxgb4_quiesce_rx(struct sge_rspq *q); 2181fd2261d8SRahul Lakkireddy int cxgb4_port_mirror_alloc(struct net_device *dev); 2182fd2261d8SRahul Lakkireddy void cxgb4_port_mirror_free(struct net_device *dev); 2183a8c16e8eSRohit Maheshwari #if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE) 2184a3ac249aSRohit Maheshwari int cxgb4_set_ktls_feature(struct adapter *adap, bool enable); 2185a3ac249aSRohit Maheshwari #endif 2186f7917c00SJeff Kirsher #endif /* __CXGB4_H__ */ 2187